Pixel circuit and electroluminescent display device including same

Abstract

The invention relates to a pixel circuit and an electroluminescent display device. The pixel circuit includes: a driving transistor including a gate electrode connected to a gate node and a source electrode connected to a source node, and thereby generating a driving current; a first light emitting device including a first anode electrode and emitting light with the driving current; a second light emitting device including a second anode electrode and emitting light with the driving current; a first emission transistor that, in response to a first emission signal, connects the source node to the first anode electrode in an odd frame, and disconnects the source node from the first anode electrode during an even frame; and a second transmission transistor that, in response to a second transmission signal, connects the source node to the second anode electrode in an even frame, and disconnects the source node from the second anode electrode during an odd frame.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0025778, filed on February 22, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a pixel circuit and an electroluminescent display device including the pixel circuit. Background Art

[0004] The electroluminescent display device includes pixels arranged in a matrix type, and image data is supplied to the pixels in synchronization with a scan signal, and thus brightness corresponding to the image data is achieved in the pixels.

[0005] Each pixel includes a driving element that generates a driving current corresponding to image data and a light-emitting device that emits light with a brightness corresponding to the driving current. The level of the driving current is proportional to the grayscale level of the image data, and as the driving current increases, the amount of light emitted by the light-emitting device, which contributes to the brightness, increases.

[0006] However, when the grayscale level of image data applied to a pixel changes from black to white and then remains at the white grayscale level for several frames, a luminance deviation occurs between the first frame immediately after the change to white grayscale and the remaining frames in which the white grayscale level remains. The grayscale level of the image data remains white in the remaining frames, and in the first frame, the grayscale level of the image data changes from black to white. Due to this, a charging delay occurs in the light-emitting device of the corresponding pixel in the first frame, resulting in luminance lower than the target luminance. Summary of the Invention

[0007] To overcome the above-mentioned problems of the related art, the present disclosure may provide a pixel circuit and an electroluminescent display device including the pixel circuit, which may reduce luminance deviation occurring in a pixel at a moment when the grayscale level of image data changes from black to white.

[0008] To achieve these objectives and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a pixel circuit includes: a driving transistor configured to include a gate electrode connected to a gate node and a source electrode connected to a source node, and to generate a driving current; a first light-emitting device configured to include a first anode electrode and to emit light in response to the driving current; a second light-emitting device configured to include a second anode electrode and to emit light in response to the driving current; a first emission transistor that connects the source node to the first anode electrode in odd frames in response to a first emission signal and disconnects the source node from the first anode electrode during even frames; and a second emission transistor that connects the source node to the second anode electrode in even frames in response to a second emission signal and disconnects the source node from the second anode electrode during odd frames. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0010] Figure 1 is a diagram showing an electroluminescent display device according to the present disclosure;

[0011] Figure 2 is a schematic diagram showing the arrangement of Figure 1 A diagram showing a configuration of a pixel circuit in a display panel;

[0012] Figure 3 A graph used to describe the brightness deviation that occurs when the grayscale level of image data changes from black to white.

[0013] Figure 4A In odd frames Figure 2 A schematic driving waveform diagram of a pixel circuit;

[0014] Figure 4B In even frames Figure 2 A schematic driving waveform diagram of a pixel circuit;

[0015] Figure 5 is a diagram showing an example of reducing a luminance deviation occurring at a moment when the grayscale level of image data changes from black to white by applying the present disclosure;

[0016] Figure 6 is a diagram showing a configuration of a pixel circuit according to the present disclosure;

[0017] Figure 7 In odd frames Figure 6 A driving waveform diagram of a pixel circuit;

[0018] Figure 8A is a diagram showing the operation of a pixel circuit in a first initialization period of an odd-numbered frame;

[0019] Figure 8B is a diagram showing the operation of a pixel circuit in a threshold voltage sampling period of an odd-numbered frame;

[0020] Figure 8C is a diagram showing the operation of the pixel circuit in the data writing period of an odd-numbered frame;

[0021] Figure 8D is a diagram showing the operation of the pixel circuit in the second initialization period of the odd-numbered frame;

[0022] Figure 8E is a diagram showing the operation of a pixel circuit in an emission period of an odd-numbered frame;

[0023] Figure 9 In even frames Figure 6 A driving waveform diagram of a pixel circuit;

[0024] Figure 10A is a diagram showing the operation of a pixel circuit in a first initialization period of an even-numbered frame;

[0025] Figure 10B is a diagram showing the operation of a pixel circuit in a threshold voltage sampling period of an even-numbered frame;

[0026] Figure 10C is a diagram showing the operation of a pixel circuit in a data writing period of an even-numbered frame;

[0027] Figure 10D is a diagram showing the operation of the pixel circuit in the second initialization period of the even frame; and

[0028] Figure 10E is a diagram showing the operation of a pixel circuit in an emission period of an even-numbered frame. DETAILED DESCRIPTION

[0029] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments of the present disclosure. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0030] The advantages and features of the present disclosure and their implementation methods will be illustrated by the embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0031] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing various embodiments of the present disclosure are merely exemplary, and the present disclosure is not limited thereto. The same reference numerals always refer to the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, unless the term "only" is used, the terms "including," "having," "comprising," etc. imply that other parts may be added. As used herein, unless the context clearly indicates otherwise, the singular forms "one," "an," and "the" are intended to also include the plural forms.

[0032] Even if not explicitly stated, the elements in the various embodiments of the present disclosure should be interpreted as including an error margin.

[0033] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "below", and "beside", unless "exactly" or "directly" is used, one or more other parts may be provided between the two parts.

[0034] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, an organic light-emitting display device including an organic light-emitting material will be mainly described as an example of an electroluminescent display device. However, the present invention is not limited to organic light-emitting display devices and can also be applied to inorganic light-emitting display devices including inorganic light-emitting materials.

[0036] Figure 1 is a diagram illustrating an electroluminescent display device according to the present disclosure.

[0037] Reference Figure 1, the electroluminescent display device may include a display panel 10, a timing controller 11, a data driver 12, a gate driver 13 and a power circuit.

[0038] The plurality of pixels PXL included in the display panel 10 can be arranged in a matrix type to configure a pixel array. In the pixel array, each of the plurality of pixels PXL can be connected to a data line 14, a gate line 15, a reset voltage power line, a reference voltage power line, a high-level power line, and a low-level power line. Here, the gate line 15 connected to one pixel PXL may include a plurality of scan lines and a plurality of emission lines. Each pixel PXL may be supplied with a data voltage through the data line 14, a plurality of scan signals with different phases through the plurality of scan lines, a plurality of emission signals with different phases through the plurality of emission lines, a reset voltage Var through the reset voltage power line, a reference voltage Vref through the reference voltage power line, a high-level pixel source electrode EVDD through the high-level power line, and a low-level pixel source electrode EVSS through the low-level power line.

[0039] The reset voltage power line, the reference voltage power line, the high level power line and the low level power line can be connected to the power circuit. The power circuit can output the reset voltage Var, the reference voltage Vref, the high level pixel source electrode EVDD and the low level pixel source electrode EVSS.

[0040] The pixel circuit included in each pixel PXL may include a driving transistor and two light-emitting devices. The driving transistor may generate a driving current to be supplied to the light-emitting devices based on image data DATA. The two light-emitting devices may be alternately connected to the driving transistor during a certain period of time and, therefore, may alternately emit light during a certain period of time. When one of the two light-emitting devices emits light, the other light-emitting device may not emit light. The driving transistor included in each pixel PXL may be implemented as an oxide transistor with good leakage current characteristics, but the present disclosure is not limited to this.

[0041] The timing controller 11 may receive image data DATA and timing control information Vsync, Hsync, DCLK and DE from the host system. The timing control information Vsync, Hsync, DCLK and DE may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock DCLK and a data enable signal DE.

[0042] The timing controller 11 may generate a source control signal DDC for controlling the operation timing of the data driver 12 and a gate control signal GDC for controlling the operation timing of the gate driver 13 based on the timing control information Vsync, Hsync, DCLK, and DE.

[0043] The timing controller 11 may supply a source control signal DDC and image data DATA to the data driver 12 . The timing controller 11 may supply a gate control signal GDC to the gate driver 13 .

[0044] The data driver 12 may convert the image data DATA from a digital format to an analog format based on the source control signal DDC to generate a data voltage corresponding to the image data DATA. The data voltage may be generated to have a level that varies based on the grayscale of the image data DATA within a predetermined voltage range. The lower limit voltage value of the voltage range may correspond to a data voltage representing a black grayscale. The upper limit voltage value of the voltage range may correspond to a data voltage representing a white grayscale.

[0045] The data driver 12 may output data voltages to the data lines 14 of the display panel 10 .

[0046] The gate driver 13 can generate multiple scan signals and multiple emission signals with different phases based on the gate control signal GDC. The gate driver 13 can output multiple scan signals to multiple scan lines and multiple emission signals to multiple emission lines, and thus can select a pixel row to be written. Here, a pixel row can refer to a group of pixels PXL adjacent to each other in the horizontal direction. The pixels PXL constituting a pixel row can be connected to the data driver 12 via multiple data lines, and can be connected to the gate driver 13 via multiple scan lines and multiple emission lines.

[0047] Based on the gate driver in panel (GIP) type, the gate driver 13 can be directly formed in the bezel area of ​​the display panel 10. Here, the bezel area may correspond to a non-display area outside the screen area configured with the pixel array. The bezel area may not display an image.

[0048] Figure 2 is a schematic diagram showing the arrangement of Figure 1 Diagram of the configuration of a pixel circuit in a display panel. Figure 3 A diagram for describing the luminance deviation that occurs when the grayscale level of image data changes from black to white. Figure 4A In odd frames Figure 2 Schematic driving waveform diagram of the pixel circuit.

[0049] Figure 4B In even frames Figure 2 Schematic driving waveform diagram of the pixel circuit. Figure 5 is a diagram illustrating an example in which a luminance deviation occurring at a point in time when the grayscale level of image data changes from black to white is reduced by applying the present disclosure.

[0050] Reference Figure 2, shows one pixel PXL arranged in one pixel row.

[0051] The pixel PXL according to the present disclosure can be used to reduce the brightness deviation that occurs in the first frame in which the gray level of the data voltage Vdata changes from black to white. Figure 3 shown.

[0052] Since the brightness of the first frame (hereinafter referred to as the nth frame) immediately after the black gray level is changed to the white gray level is lower than the brightness of the next frame (hereinafter referred to as the n+1th frame) maintaining the white gray level, brightness deviation may occur. In other words, since the level of the driving current IEL of the nth frame for achieving the same white gray level is lower than the level of the driving current IEL of the n+1th frame, brightness deviation may occur.

[0053] The degree of charging delay of the internal capacitor of the light-emitting device may vary based on the grayscale of the previous frame, and due to this, a deviation may occur in the driving current IEL and the anode voltage of the light-emitting device. The data voltage representing the white grayscale may be greater than the data voltage representing the black grayscale. Therefore, as in the embodiment, when the grayscale of the n-1th frame is black and the grayscale of each of the nth frame and the n+1th frame is white, the charging delay may be relatively large in the nth frame when the black grayscale changes to the white grayscale, and the charging delay may be relatively small in the n+1th frame when the white grayscale is maintained.

[0054] This brightness deviation is referred to as the Shooting Amount Ratio (SAR). The SAR may be maximum in the nth frame, including the moment when the grayscale changes from black to white, and may gradually decrease in the nth frame, including the next frame where the grayscale remains white. It may approach almost zero starting from a specific next frame. For example, the SAR of the nth frame may be 54% smaller than that of the specific next frame.

[0055] SAR may be a concept that includes not only the recognition deviation of the black grayscale but also the recognition deviation of the white grayscale. However, the recognition deviation of the black grayscale can be ignored because the recognition deviation of the black grayscale is much smaller than that of the white grayscale.

[0056] In other words, when the grayscale of the previous frame is black and the grayscale of the current frame is white, SAR can be easily recognized. However, in the opposite case, that is, when the grayscale of the previous frame is white and the grayscale of the current frame is black, SAR may not be easily recognized. Therefore, in the following description, only the recognition deviation of the white grayscale will be described as an example of SAR.

[0057] Figure 2The illustrated pixel PXL of the present disclosure may be used to reduce SAR, and may have a feature in which the anode voltage of the light emitting device is initialized equally in all frames regardless of the grayscale level of the previous frame.

[0058] Such a feature can be based on the on-off alternating driving using two light emitting devices and the discharge driving performed in the light emitting device driven in the off state. This will be described in detail below.

[0059] The pixel PXL according to the present disclosure may include a first light emitting device OLED1 , a second light emitting device OLED2 , a driving transistor DR, and first and second emission transistors ET1 and ET2 for on-off alternating driving and discharge driving.

[0060] The driving transistor DR may generate a driving current to be supplied to the first light emitting device OLED1 or the second light emitting device OLED2. The gate electrode of the driving transistor DR may be connected to the gate node DTG, and the source electrode of the driving transistor DR may be connected to the source node DTS. The driving current may be proportional to the square of the voltage difference between the gate node DTG and the source node DTS.

[0061] The first light emitting device OLED1 may include a first anode electrode, a first cathode electrode, and a first emission layer disposed between the first anode electrode and the first cathode electrode. The low-level pixel source electrode EVSS may be supplied to the first cathode electrode, and the first anode electrode may be coupled to the first cathode electrode through an internal capacitor and an internal resistor.

[0062] The second light-emitting device OLED2 may include a second anode electrode, a second cathode electrode, and a second emission layer disposed between the second anode electrode and the second cathode electrode. The low-level pixel source electrode EVSS may be supplied to the second cathode electrode, and the second anode electrode may be coupled to the second cathode electrode via an internal capacitor and an internal resistor. The second light-emitting device OLED2 may emit light using a driving current supplied from the driving transistor DR.

[0063] The first light emitting device OLED1 may be turned on (i.e., emit light) using a driving current supplied from the driving transistor DR during odd frames, and may be turned off (i.e., may not emit light) during even frames. The anode voltage of the first light emitting device OLED1 may be discharged through an internal resistor using a low-level pixel source electrode EVSS during even frames.

[0064] The second light emitting device OLED2 can be turned on (i.e., emit light) using the driving current supplied from the driving transistor DR during even frames, and can be turned off (i.e., may not emit light) during odd frames. The anode voltage of the second light emitting device OLED2 can be discharged through the internal resistor using the low-level pixel source electrode EVSS during odd frames.

[0065] The first emission transistor ET1 and the second emission transistor ET2 may be used for on-off alternating driving of the first light emitting device OLED1 and the second light emitting device OLED2 .

[0066] In response to the first emission signal EM1, the first emission transistor ET1 can connect the first anode electrode of the first light-emitting device OLED1 to the source node DTS during odd frames, and can disconnect the first anode electrode of the first light-emitting device OLED1 from the source node DTS during even frames. The first emission transistor ET1 may include a gate electrode connected to the first emission line EL1, a drain electrode connected to the source node DTS, and a source electrode connected to the first anode electrode of the first light-emitting device OLED1.

[0067] In response to the second emission signal EM2, the second emission transistor ET2 can connect the second anode electrode of the second light-emitting device OLED2 to the source node DTS during even frames, and can disconnect the second anode electrode of the second light-emitting device OLED2 from the source node DTS during odd frames. The second emission transistor ET2 may include a gate electrode connected to the second emission line EL2, a drain electrode connected to the source node DTS, and a source electrode connected to the second anode electrode of the second light-emitting device OLED2.

[0068] Reference Figure 4A and Figure 4B , one frame may include a first initialization period X1 and Y1, a threshold voltage sampling period X2 and Y2, a data writing period X3 and Y3, a second initialization period X4 and Y4, and an emission period X5 and Y5.

[0069] The first emission signal EM1 may be input at an on-level Lon in the first initialization period X1 and the emission period X5 of the odd frame, and may be input at an off-level Loff in the threshold voltage sampling period X2, the data writing period X3, and the second initialization period X4 of the odd frame. The first emission signal EM1 may be input at an off-level Loff during all periods Y1 to Y5 including the emission period Y5 of the even frame.

[0070] In response to the first emission signal EM1 , the first emission transistor ET1 may be powered on during the first initialization period X1 and the emission period X5 of the odd frame, and may be powered off during all periods Y1 to Y5 of the even frame.

[0071] Therefore, the first light emitting device OLED1 may be turned on and driven during the emission period X5 of the odd-numbered frame, and may be turned off and driven during all periods Y1 to Y5 of the even-numbered frame.

[0072] The second emission signal EM2 may be input at the on-level Lon in the first initialization period Y1 and the emission period Y5 of the even frame, and may be input at the off-level Loff in the threshold voltage sampling period Y2, the data writing period Y3, and the second initialization period Y4 of the even frame. The second light-emitting signal EM2 may be input at the off-level Loff during all periods X1 to X5 including the emission period X5 of the odd frame.

[0073] In response to the second emission signal EM2 , the second emission transistor ET2 may be powered on during the first initialization period Y1 and the emission period Y5 of the even frame, and may be powered off during all periods X1 to X5 of the odd frame.

[0074] Therefore, the second light emitting device OLED2 may be turned on and driven during the emission period Y5 of the even-numbered frame, and may be turned off and driven during all periods X1 to X5 of the odd-numbered frame.

[0075] Further references Figure 2 The pixel PXL according to the present disclosure may also supply an external reset voltage Var to the anode electrode of the corresponding light-emitting device in the off-drive state, so as to more effectively initialize the light-emitting device before turning on the drive. To this end, the pixel PXL according to the present disclosure may further include a first scanning transistor ST1 and a second scanning transistor ST2.

[0076] The first scan transistor ST1 may also supply a reset voltage Var to the first anode electrode of the first light emitting device OLED1 based on the first scan signal SCAN1. The first scan transistor ST1 may include a gate electrode connected to the first scan line SL1, a drain electrode connected to an input terminal of the reset voltage Var, and a source electrode connected to the first anode electrode of the first light emitting device OLED1.

[0077] The second scan transistor ST2 may also supply a reset voltage Var to the second anode electrode of the second light emitting device OLED2 based on the second scan signal SCAN2. The second scan transistor ST2 may include a gate electrode connected to the second scan line SL2, a drain electrode connected to an input terminal of the reset voltage Var, and a source electrode connected to the second anode electrode of the second light emitting device OLED2.

[0078] Further references Figure 4A and Figure 4B , the first scan signal SCAN1 may be input at the on-level Lon in the other periods X1 to X4 except the emission period X5 of the odd-numbered frame and in all periods Y1 to Y5 including the emission period Y5 of the even-numbered frame. On the other hand, the second scan signal SCAN2 may be input at the on-level Lon in the other periods Y1 to Y4 except the emission period Y5 of the even-numbered frame and in all periods X1 to X5 including the emission period X5 of the odd-numbered frame.

[0079] In response to the first scan signal SCAN1, the first scan transistor ST1 may be turned on during all periods Y1 to Y5 of the even-numbered frame and may initialize the first anode electrode of the first light-emitting device OLED1 to the reset voltage Var. In addition, in response to the second scan signal SCAN2, the second scan transistor ST2 may be turned on during all periods X1 to X5 of the odd-numbered frame and may initialize the second anode electrode of the second light-emitting device OLED2 to the reset voltage Var.

[0080] Here, the reset voltage Var may be smaller than the data voltage representing the black gray level for stable off-driving. For example, when the data voltage representing the black gray level is 0.5V, the reset voltage Var may be set to -3V.

[0081] As described above, according to the present disclosure, the anode voltage of the light emitting device can be initialized equally in all frames regardless of the grayscale level of the previous frame. Figure 5 As shown, the brightness of the first frame immediately after the change from black gray level to white gray level may be substantially the same as the brightness of the next frame maintaining the white gray level. This may indicate that the SAR is reduced to 0%.

[0082] Further references Figure 2 The pixel PXL according to the present disclosure may further include a node control circuit CPG for programming a voltage difference (hereinafter referred to as Vgs) between the gate node DTG and the source node DTS before the first light-emitting device OLED1 or the second light-emitting device OLED2 in each of odd and even frames. The configuration of the node control circuit CPG may be variously modified.

[0083] For example, the node control circuit CPG can be connected to the data line 14 to receive the data voltage Vdata, and can also be connected to the third scan line SL3 and the fourth scan line SL4 to further receive the third scan signal SCAN3 and the fourth scan signal SCAN4, and can also be connected to the third emission line EL3 to further receive the third emission signal EM3, and can be connected to the reference voltage power line to receive the reference voltage Vref, and can be connected to the high-level power line to receive the high-level pixel source electrode EVDD.

[0084] exist Figure 6 , a configuration of a pixel circuit including a configuration of a node control circuit CPG according to an embodiment is shown in FIG. Figure 6 In addition to the node control circuit CPG, other components can be Figure 2 same.

[0085] Reference Figure 6 The node control circuit CPG may include: a third scanning transistor ST3 for supplying a data voltage Vdata to the gate node DTG; a fourth scanning transistor ST4 for supplying a reference voltage Vref to the gate node DTG; a third emission transistor ET3 for supplying a high-level pixel source electrode EVDD to the driving transistor DR; a first capacitor Cst; and a second capacitor CA.

[0086] The third scan transistor ST3 may include a gate electrode connected to the third scan line SL3 , a drain electrode connected to the data line 14 , and a source electrode connected to the gate node DTG.

[0087] The fourth scan transistor ST4 may include a gate electrode connected to the fourth scan line SL4 , a drain electrode connected to the reference voltage power line, and a source electrode connected to the gate node DTG.

[0088] The third emission transistor ET3 may include a gate electrode connected to the third emission line EL3 , a drain electrode connected to the input terminal of the high-level pixel source electrode EVDD, and a source electrode connected to the drain electrode of the driving transistor DR.

[0089] One electrode of the first capacitor Cst may be connected to the gate node DTG, and the other electrode of the first capacitor Cst may be connected to the source node DTS.

[0090] One electrode of the second capacitor CA may be connected to the input terminal of the high-level pixel source electrode EVDD, and the other electrode of the second capacitor CA may be connected to the source node DTS.

[0091] Figure 7 In odd frames Figure 6 Driving waveform diagram of the pixel circuit. Figure 8Ais a diagram illustrating the operation of a pixel circuit in a first initialization period of an odd-numbered frame. Figure 8B is a diagram showing the operation of the pixel circuit in the threshold voltage sampling period of an odd-numbered frame. Figure 8C is a diagram showing the operation of the pixel circuit in the data writing period of an odd-numbered frame. Figure 8D is a diagram illustrating the operation of the pixel circuit in the second initialization period of the odd-numbered frame. Figure 8E is a diagram showing the operation of the pixel circuit in the emission period of an odd-numbered frame.

[0092] Reference Figure 7 and Figure 8A In the first initialization period X1 of the odd frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon, the fourth scan transistor ST4 may be powered on based on the fourth scan signal SCAN4 of the conduction level Lon, and the first emission transistor ET1 may be powered on based on the first emission signal EM1 of the conduction level Lon. In addition, the other transistors DR, ST3, ET2, and ET3 may be powered off.

[0093] Therefore, in the first initialization period X1 of the odd frame, the gate node DTG may be initialized to the reference voltage Vref, and the source node DTS may be initialized to the reset voltage Var. For operational stability, the reference voltage Vref may be set to be greater than the data voltage representing the black grayscale, and the reset voltage Var may be set to be less than the data voltage representing the black grayscale. For example, when the data voltage representing the black grayscale is 0.5V, the reset voltage Var may be set to -3V, and the reference voltage Vref may be set to 1.5V.

[0094] Reference Figure 7 and Figure 8B In the threshold voltage sampling period X2 of the odd frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon, the fourth scan transistor ST4 may be powered on based on the fourth scan signal SCAN4 of the conduction level Lon, the third emission transistor ET3 may be powered on based on the third emission signal EM3 of the conduction level Lon, and the drive transistor DR may be powered on. In addition, the other transistors ST3, ET1, and ET2 may be powered off.

[0095] Therefore, in the threshold voltage sampling period X2 of the odd frame, the threshold voltage of the driving transistor DR can be sampled and stored in the first capacitor Cst. In the threshold voltage sampling period X2 of the odd frame, the potential of the gate node DTG can be the reference voltage Vref, and the potential of the source node DTS can be "Vref-Vth". Here, Vth can represent the threshold voltage of the driving transistor DR.

[0096] Reference Figure 7 and Figure 8C In the data writing period X3 of the odd frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon, and the third scan transistor ST3 may be powered on based on the third scan signal SCAN3 of the conduction level Lon. In addition, the other transistors DR, ST4, ET1, ET2, and ET3 may be powered off.

[0097] Therefore, in the data writing period X3 of the odd frame, the data voltage Vdata representing the white grayscale may be supplied to the gate node DTG. In the data writing period X3 of the odd frame, the potential of the gate node DTG may be the data voltage Vdata, and the potential of the source node DTS may be "Vref-Vth+C(Vdata-Vref)". Here, C may represent a value obtained by dividing the capacitance of the first capacitor Cst by the sum of the capacitance of the first capacitor Cst and the capacitance of the second capacitor CA.

[0098] In addition, the third scan signal SCAN3 can be delayed by a specific time Td from the start timing T0 of the data write period X3, and can then be converted to the on-level Lon, thereby preventing an abnormal short circuit between the data line DL and the input terminal of the reference voltage Vref due to the fact that the third scan transistor ST3 and the fourth scan transistor ST4 are simultaneously powered on at the moment (i.e., T0) when the threshold voltage sampling period X2 becomes the data write period X3.

[0099] Reference Figure 7 and Figure 8D In the second initialization period X4 of the odd frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, and the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon. In addition, the other transistors DR, ST3, ST4, ET1, ET2, and ET3 may be powered off.

[0100] Therefore, the reset voltage Var may be supplied to the first anode electrode of the first light emitting device OLED1 and the second anode electrode of the second light emitting device OLED2. The potential of the first anode electrode and the second anode electrode may continuously maintain the reset voltage Var from the first initialization period X1 to the second initialization period X4.

[0101] Based on the reset voltage Var maintained by the first and second anode electrodes from the first initialization period X1 until the second initialization period X4, the first anode electrode of the first light emitting device OLED1 and the second anode electrode of the second light emitting device OLED2 may be equally initialized (or discharged) regardless of the grayscale of the previous frame.

[0102] The first and second light emitting devices OLED1 and OLED2 may be powered off (or may not emit light) from the first initialization period X1 until the second initialization period X4 , and thus, a black grayscale image may be implemented.

[0103] Reference Figure 7 and Figure 8E In the emission period X5 of the odd frame, the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon, the first emission transistor ET1 may be powered on based on the first emission signal EM1 of the conduction level Lon, the third emission transistor ET3 may be powered on based on the third emission signal EM3 of the conduction level Lon, and the drive transistor DR may be powered on. In addition, the other transistors ST1, ST3, ST4, and ET2 may be powered off.

[0104] In the emission period X5 of the odd frame, the potential of the gate node DTG may be “Vdata+Voled”, and the potential of the source node DTS may be “Vref-Vth+C(Vdata-Vref)+Voled”. Here, Voled may be the turn-on voltage (or operating point voltage) of the first light emitting device OLED1.

[0105] A potential difference between the gate node DTG and the source node DTS, which determines the level of the driving current, may be “Vdata−Vref−C(Vdata−Vref)+Vth.” Therefore, the driving current Ioled may be expressed as the following Equation 1.

[0106] [Formula 1]

[0107] Ioled=k / 2{(1-C)*(Vdata-Vref)} 2

[0108] As shown in Equation 1, the driving current Ioled can be compensated regardless of the threshold voltage Vth offset of the driving transistor DR, and the first light emitting device OLED1 can be powered (or emit light) by the driving current Ioled during the emission period X5 of the odd frame, thereby realizing a white grayscale image.

[0109] On the other hand, the second light emitting device OLED2 may maintain a turn-off state during the entire period of the odd-numbered frame, and thus may be initially driven (or discharged).

[0110] Figure 9 In even frames Figure 6 Driving waveform diagram of the pixel circuit. Figure 10A is a diagram illustrating the operation of a pixel circuit in a first initialization period of an even-numbered frame. Figure 10B is a diagram showing the operation of a pixel circuit in a threshold voltage sampling period of an even-numbered frame. Figure 10C is a diagram showing the operation of the pixel circuit in the data writing period of an even-numbered frame. Figure 10D is a diagram illustrating the operation of the pixel circuit in the second initialization period of the even-numbered frame. Figure 10E is a diagram showing the operation of a pixel circuit in an emission period of an even-numbered frame.

[0111] Reference Figure 9 and Figure 10A In the first initialization period Y1 of the even frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon, the fourth scan transistor ST4 may be powered on based on the fourth scan signal SCAN4 of the conduction level Lon, and the second emission transistor ET2 may be powered on based on the second emission signal EM2 of the conduction level Lon. In addition, the other transistors DR, ST3, ET1, and ET3 may be powered off.

[0112] Therefore, in the first initialization period Y1 of the even frame, the gate node DTG may be initialized to the reference voltage Vref, and the source node DTS may be initialized to the reset voltage Var.

[0113] Reference Figure 9 and Figure 10BIn the threshold voltage sampling period Y2 of an even frame, the first scanning transistor ST1 may be powered on based on the first scanning signal SCAN1 of the conduction level Lon, the second scanning transistor ST2 may be powered on based on the second scanning signal SCAN2 of the conduction level Lon, the fourth scanning transistor ST4 may be powered on based on the fourth scanning signal SCAN4 of the conduction level Lon, the third emission transistor ET3 may be powered on based on the third emission signal EM3 of the conduction level Lon, and the driving transistor DR may be powered on. In addition, the other transistors ST3, ET1, and ET2 may be powered off.

[0114] Therefore, in the threshold voltage sampling period Y2 of the even frame, the threshold voltage of the driving transistor DR can be sampled and stored in the first capacitor Cst. In the threshold voltage sampling period Y2 of the even frame, the potential of the gate node DTG can be the reference voltage Vref, and the potential of the source node DTS can be "Vref-Vth". Here, Vth can represent the threshold voltage of the driving transistor DR.

[0115] Reference Figure 9 and Figure 10C In the data writing period Y3 of the even frame, the first scanning transistor ST1 may be powered on based on the first scanning signal SCAN1 of the conduction level Lon, the second scanning transistor ST2 may be powered on based on the second scanning signal SCAN2 of the conduction level Lon, and the third scanning transistor ST3 may be powered on based on the third scanning signal SCAN3 of the conduction level Lon. In addition, the other transistors DR, ST4, ET1, ET2, and ET3 may be powered off.

[0116] Therefore, in the data writing period Y3 of the even frame, the data voltage Vdata representing the white grayscale may be supplied to the gate node DTG. In the data writing period Y3 of the even frame, the potential of the gate node DTG may be the data voltage Vdata, and the potential of the source node DTS may be "Vref-Vth+C(Vdata-Vref)". Here, C may represent a value obtained by dividing the capacitance of the first capacitor Cst by the sum of the capacitance of the first capacitor Cst and the capacitance of the second capacitor CA.

[0117] In addition, the third scan signal SCAN3 can be delayed by a specific time Td from the start timing T0 of the data write period Y3, and can then be converted to the on-level Lon, thereby preventing an abnormal short circuit between the data line DL and the input terminal of the reference voltage Vref due to the fact that the third scan transistor ST3 and the fourth scan transistor ST4 are simultaneously powered on at the moment (i.e., T0) when the threshold voltage sampling period Y2 becomes the data write period Y3.

[0118] Reference Figure 9 and Figure 10D In the second initialization period Y4 of the even frame, the first scan transistor ST1 may be powered on based on the first scan signal SCAN1 of the conduction level Lon, and the second scan transistor ST2 may be powered on based on the second scan signal SCAN2 of the conduction level Lon. In addition, the other transistors DR, ST3, ST4, ET1, ET2, and ET3 may be powered off.

[0119] Therefore, the reset voltage Var may be supplied to the first anode electrode of the first light emitting device OLED1 and the second anode electrode of the second light emitting device OLED2. The potential of the first anode electrode and the second anode electrode may continuously maintain the reset voltage Var from the first initialization period Y1 to the second initialization period Y4.

[0120] Based on the reset voltage Var maintained by the first and second anode electrodes from the first initialization period Y1 until the second initialization period Y4, the first anode electrode of the first light emitting device OLED1 and the second anode electrode of the second light emitting device OLED2 may be equally initialized (or discharged) regardless of the grayscale level of the previous frame.

[0121] The first and second light emitting devices OLED1 and OLED2 may be powered off (or may not emit light) from the first initialization period Y1 until the second initialization period Y4 , and thus, a black grayscale image may be implemented.

[0122] Reference Figure 9 and Figure 10E In the emission period Y5 of the even frame, the first scanning transistor ST1 may be powered on based on the first scanning signal SCAN1 of the conduction level Lon, the second emission transistor ET2 may be powered on based on the second emission signal EM2 of the conduction level Lon, the third emission transistor ET3 may be powered on based on the third emission signal EM3 of the conduction level Lon, and the driving transistor DR may be powered on. In addition, the other transistors ST2, ST3, ST4, and ET1 may be powered off.

[0123] In the emission period Y5 of the even frame, the potential of the gate node DTG may be “Vdata+Voled”, and the potential of the source node DTS may be “Vref-Vth+C(Vdata-Vref)+Voled”. Here, Voled may be the turn-on voltage (or operating point voltage) of the second light emitting device OLED2.

[0124] A potential difference Vgs between the gate node DTG and the source node DTS, which determines the level of the driving current, may be “Vdata−Vref−C(Vdata−Vref)+Vth.” Therefore, the driving current Ioled may be expressed as Equation 1.

[0125] As shown in Equation 1, the driving current Ioled can be compensated regardless of the threshold voltage Vth offset of the driving transistor DR, and the second light emitting device OLED2 can be powered (or emit light) by the driving current Ioled during the emission period Y5 of the even frame, thereby realizing a white grayscale image.

[0126] On the other hand, the second light emitting device OLED2 may maintain a turn-off state during the entire period of the even-numbered frame, and thus may be initially driven (or discharged).

[0127] As described above, in a case where the grayscale level of image data applied to a pixel changes from black to white and then maintains the white grayscale level during several frames, the present invention can reduce the brightness deviation between the first frame immediately after changing to the white grayscale level and the other frames maintaining the white grayscale level, thereby improving the display quality.

[0128] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0129] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A pixel circuit, comprising: a driving transistor configured to include a gate electrode connected to a gate node and a source electrode connected to a source node, and to generate a driving current; a first light emitting device configured to include a first anode electrode and emit light in response to the driving current; a second light emitting device configured to include a second anode electrode and emit light in response to the driving current; a first emission transistor that connects the source node to the first anode electrode during odd frames and disconnects the source node from the first anode electrode during even frames in response to a first emission signal; as well as A second emission transistor connects the source node to the second anode electrode in the even frames and disconnects the source node from the second anode electrode during the odd frames in response to a second emission signal.

2. The pixel circuit according to claim 1, wherein: The first emission transistor is turned on during an emission period of the odd-numbered frame and is turned off during all periods of the even-numbered frame, and The second emission transistor is turned on during an emission period of the even-numbered frame, and is turned off during all periods of the odd-numbered frame.

3. The pixel circuit according to claim 1, wherein: The first light emitting device is turned on during the emission period of the odd-numbered frames and remains in an off state during the even-numbered frames, and The second light emitting device is turned on during an emission period of the even-numbered frame and maintains an off state during the odd-numbered frame.

4. The pixel circuit according to claim 3, further comprising: a first scanning transistor that supplies a reset voltage to the first anode electrode based on a first scanning signal; as well as A second scanning transistor that supplies the reset voltage to the second anode electrode based on a second scanning signal.

5. The pixel circuit according to claim 4, wherein: The first scanning transistor is turned on in the other periods of the odd frame except the emission period, and is turned on in all periods of the even frame, and The second scanning transistor is turned on in other periods of the even frame except the emission period, and is turned on in all periods of the odd frame. The pixel circuit according to claim 4 , wherein: In a data writing period before the emission period of the odd-numbered frame or a data writing period before the emission period of the even-numbered frame, A data voltage included in a predetermined voltage range is applied to the gate node to implement a gray scale, and The reset voltage is lower than a lower limit voltage value of the predetermined voltage range.

7. An electroluminescent display device comprising: A display panel, the display panel comprising a plurality of pixels; a gate driver that drives scan lines and emission lines connected to the plurality of pixels; as well as a data driver that drives data lines connected to the plurality of pixels, The pixel circuit of each pixel in the plurality of pixels includes: a driving transistor configured to include a gate electrode connected to a gate node and a source electrode connected to a source node, and to generate a driving current; a first light emitting device configured to include a first anode electrode and emit light in response to the driving current; a second light emitting device configured to include a second anode electrode and emit light in response to the driving current; a first emission transistor that connects the source node to the first anode electrode in odd frames and disconnects the source node from the first anode electrode during even frames in response to a first emission signal supplied through a first emission line; and a second emission transistor that connects the source node to the second anode electrode in the even frames and disconnects the source node from the second anode electrode during the odd frames in response to a second emission signal supplied through a second emission line.

8. The electroluminescent display device according to claim 7, wherein: The first emission transistor is turned on during an emission period of the odd-numbered frame and is turned off during all periods of the even-numbered frame, and The second emission transistor is turned on during an emission period of the even-numbered frame, and is turned off during all periods of the odd-numbered frame.

9. The electroluminescent display device according to claim 7, wherein: The first light emitting device is turned on during the emission period of the odd-numbered frames and remains in an off state during the even-numbered frames, and The second light emitting device is turned on during an emission period of the even-numbered frame and maintains an off state during the odd-numbered frame.

10. The electroluminescent display device of claim 9, further comprising: a first scanning transistor that supplies a reset voltage to the first anode electrode based on a first scanning signal supplied through a first scanning line; as well as a second scanning transistor that supplies the reset voltage to the second anode electrode based on a second scanning signal supplied through a second scanning line.

11. The electroluminescent display device according to claim 10, wherein: The first scanning transistor is turned on in the other periods of the odd frame except the emission period, and is turned on in all periods of the even frame, and The second scanning transistor is turned on in other periods of the even frame except the emission period, and is turned on in all periods of the odd frame.

12. The electroluminescent display device according to claim 10, wherein: In a data writing period before the emission period of the odd-numbered frame or a data writing period before the emission period of the even-numbered frame, A data voltage included in a predetermined voltage range is applied to the gate node to implement a gray scale, and The reset voltage is lower than a lower limit voltage value of the predetermined voltage range.

13. The electroluminescent display device according to claim 7, wherein: The pixel circuit is configured to: During the odd-numbered frame, a reset voltage is supplied to the first anode electrode and the second anode electrode in a period before an emission period of the odd-numbered frame, and During the even-numbered frame, the reset voltage is supplied to the first anode electrode and the second anode electrode in a period before an emission period of the even-numbered frame.

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