A semiconductor structure of a driving chip

Abstract

The application relates to the technical field of semiconductor chips, in particular to a semiconductor structure of a driving chip. The semiconductor structure of the driving chip comprises a substrate, at least one first type of isolation layer, the first type of isolation layer being formed on the substrate, and at least one body region being formed on the first isolation layer; semiconductor devices are respectively formed on the substrate and the body region; wherein the first type of isolation layer is configured in a suspended state or a high resistance state. The semiconductor structure of the driving chip can avoid that a load draws current from a chip power supply when driving the load.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chips, in particular to a semiconductor structure of a driving chip. BACKGROUND

[0002] In applications such as DC-DC power supply, relay driving, motor driving, etc., a driving chip is often used for driving, and an isolation region is often arranged between different devices in the driving chip for isolation, and the isolation region is often configured to be connected with a VDD potential or a specific bias.

[0003] When the load of the driving chip contains a large inductive component, the N-type isolation of the power device inside the driving chip for driving the load is often designed to be connected to the load output end together with the device drain, and the N-type isolation of other regions is designed to be connected to the VDD or the specific bias. However, when the output of the driving chip is in a high resistance state, due to the freewheeling effect of the inductance, the current on the inductance will not immediately decay to zero, causing the load to draw current from the driving chip for a long time, which will cause the N-type isolation of the power device inside the driving chip, the P-type substrate and other N-type isolation to form a parasitic NPN triode to conduct, directly drawing current from the VDD, and when the current drawn from the VDD exceeds its power supply capability, it will pull the VDD to near ground voltage, affecting the stability of the chip operation, and even causing the chip logic to be chaotic, resulting in unpredictable results. SUMMARY

[0004] In order to solve the problems existing in the prior art, the purpose of the present application is to provide a semiconductor structure of a driving chip, which avoids the load from drawing current from the chip power supply when driving the load.

[0005] To achieve the above purpose, the present application provides a semiconductor structure of a driving chip, comprising:

[0006] a substrate,

[0007] at least one first type of isolation layer formed on the substrate, at least one body region being formed on the first isolation layer;

[0008] semiconductor devices are respectively formed on the substrate and the body region;

[0009] wherein the first type of isolation layer is configured to be in a suspended state or in a high resistance state.

[0010] Further, at least two of the first type of isolation layers are connected to each other.

[0011] Further, each of the first type of isolation layers is separated by the substrate.

[0012] Further, the substrate is a P-type substrate, each of the first type isolation layers is an N-type isolation layer, and the body region is a P-type body region.

[0013] Further, the semiconductor structure further comprises: a second type isolation layer, the second type isolation layer is formed on the substrate and is in ohmic connection with the first isolation layer.

[0014] Further, each of the first type isolation layers comprises any one or a combination of a buried layer, a deep well and a well.

[0015] To achieve the above object, the application further provides a driving chip and a semiconductor structure of the driving chip.

[0016] The semiconductor structure of the driving chip provided by the application configures the first isolation layer as a suspended state or a high resistance state, so that when a load extracts current from the semiconductor structure of the driving chip, the voltage of the first type isolation layer will not be affected before the reverse breakdown voltage of the parasitic diode is reached, thereby avoiding the problem that the load extracts current from VDD due to the connection of the isolation layer and VDD, affecting the working of the semiconductor structure of the driving chip, and improving the robustness of the semiconductor structure of the driving chip.

[0017] Other features and advantages of the application will be described in the following description, and some will become apparent from the description, or will be learned from the practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, and are used to explain the application together with the embodiments of the application, and do not constitute a limitation on the application. In the drawings:

[0019] Figure 1 is a structural schematic diagram of a conventional semiconductor structure of a driving chip;

[0020] Figure 2 is a structural schematic diagram of a semiconductor structure of a driving chip of Embodiment 1 of the application;

[0021] Figure 3 is a structural schematic diagram of a semiconductor structure of a driving chip of Embodiment 2 of the application;

[0022] Figure 4 is a structural schematic diagram of a semiconductor structure of a driving chip of Embodiment 3 of the application;

[0023] Figure 5 is a structural schematic diagram of a semiconductor structure of a driving chip of Embodiment 4 of the application;

[0024] Reference numerals: 100 - substrate, 101 - first type of isolation layer, 1011 - first first type of isolation layer, 1012 - second first type of isolation layer, 102 - body region, 103 - well, 104 - semiconductor device, 105 - parasitic triode, 106 - wire, 108 - second type of isolation layer. DETAILED DESCRIPTION

[0025] Embodiments of the present application will be described below in greater detail. While certain embodiments of the present application are shown in the drawings, it is understood that the present application can be practiced by various means, and should not be construed as being limited to the embodiments shown herein, but rather the embodiments are provided for more thorough and complete understanding of the present application. It is understood that the drawings and embodiments of the present application are for illustrative purposes only, and should not be construed as limiting the scope of the present application.

[0026] It is understood that each of the steps recited in the method embodiments of the present application can be performed in different orders, and / or in parallel. In addition, the method embodiments can include additional steps and / or omit performing the steps shown. The scope of the present application is not limited in this regard.

[0027] The term "comprising" and variations thereof as used herein are open-ended, and mean "including but not limited to". The term "based on" means "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related terms shall be construed accordingly.

[0028] It is noted that the use of "a", "an", "the" and similar referents in the application are intended to be illustrative of the application and are not intended to be limiting. It will be understood by those skilled in the art that, although the present application has been described in relation to the foregoing description, modification and / or additions can be made thereto without departing from the scope of the application.

[0029] Figure 1 A schematic diagram of a semiconductor structure of a conventional driver chip is shown in Figure 1The device includes a substrate 100, a first type-1 isolation region 1011 and a second type-1 isolation region 1012, a well 103, and a semiconductor device 104. The first type-1 isolation region 1011 is configured to connect to the drain of the semiconductor device formed thereon and to the inductor L1 and the load. The second type-1 isolation region 1012 is configured to connect to the VDD power supply. When the semiconductor structure of the driver chip is in a high-impedance state, due to the freewheeling effect of the inductor L1, the current in the inductor L1 does not immediately decay to zero. This causes the load to draw current from the semiconductor structure of the driver chip for a prolonged period. This results in the first type-1 isolation region 1011, the second type-1 isolation region 1012, and the substrate 100 within the semiconductor structure of the driver chip forming a parasitic transistor that directly draws current from the VDD power supply. When the current drawn from the VDD power supply exceeds its power supply capacity, it pulls the VDD power supply close to ground, affecting the operational stability of the semiconductor structure of the driver chip and potentially causing logic corruption and unpredictable results.

[0030] To address the aforementioned issues, this application provides a semiconductor structure for a driver chip that avoids the formation of parasitic transistors within the device structure when driving inductive loads, thereby preventing the load from drawing current from the power supply VDD of the driver chip's semiconductor structure.

[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0032] Example 1

[0033] One embodiment of this application provides a semiconductor structure for a driver chip. Figure 2 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 1 of this application. The following will refer to... Figure 2 The semiconductor structure of the driver chip in this application is described in detail, including:

[0034] Substrate 100,

[0035] In this embodiment, the substrate 100 is a P-type substrate.

[0036] A first type of isolation layer 101 is formed on the substrate 100;

[0037] In this embodiment, the first type of isolation layer 101 is an N-type isolation layer;

[0038] In this embodiment, the first type of isolation layer 101 includes a burial layer and a well.

[0039] In other embodiments, the first type of isolation layer 101 may also be a combination of any N-type doped structure, for example, a combination of N-type deep wells and N-type wells.

[0040] As can be understood, a buried layer refers to a region with a high doping concentration formed on a substrate through high-energy ion implantation or diffusion, which is then covered and buried by an epitaxial layer grown on top of it. A well refers to a region with a certain depth and doping concentration formed through ion implantation, high-temperature propulsion (annealing), or diffusion. Wells of different depths are used to meet different isolation and device fabrication requirements.

[0041] Body region 102 is a P-type body region, and two of them are formed on the first type of isolation layer 101.

[0042] Semiconductor devices 104 are formed on substrate 100 and body region 102, respectively.

[0043] In this configuration, the P-type semiconductor device 104 is indirectly formed on the substrate 100 or the body region 102 through the N-type well 103, while the N-type semiconductor is directly formed on the substrate 100 or the body region 102.

[0044] In some other embodiments, the substrate is an N-type substrate, the first type of isolation layer 101 is a P-type isolation layer, and the body region 102 is an N-type body region.

[0045] It is understandable that different body regions 102 can correspond to different operating voltage domains, and the semiconductor device 104 can be formed in the corresponding body region 102 according to the required operating voltage domain.

[0046] It is understandable that the number of body regions, the type and number of semiconductor devices, etc., can be adaptively set on the substrate 100 and the first type of isolation layer 101 according to the actual circuit requirements of the driver chip.

[0047] In this embodiment, the first type of isolation layer 101 is configured to be in a floating state, which means that the driver chip is not directly connected to an external potential when in use.

[0048] In this embodiment, the voltage of the first type of isolation layer 101 is determined by the body region with the highest potential connected to it. When the voltage of the body region decreases, the first type of isolation layer 101 will maintain the previous voltage and will not form a parasitic transistor conduction until the reverse bias breakdown voltage of the parasitic diode between the first type of isolation layer 101 and the body region is reached. Only then will the charge of the first type of isolation layer 101 be discharged and the voltage of the first type of isolation layer 101 decrease.

[0049] Example 2

[0050] One embodiment of this application provides a semiconductor structure for a driver chip. Figure 3 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 2 of this application. The following will refer to... Figure 3The semiconductor structure of the driver chip in Embodiment 2 of this application is described in detail below:

[0051] The difference between Embodiment 2 and Embodiment 1 of this application is as follows:

[0052] In this embodiment, two first-type isolation layers are disposed at intervals on the substrate 100, namely a first first-type isolation region 1011 and a second first-type isolation region 1012, which are connected by a wire 106 ohms.

[0053] In some other embodiments, multiple first-type isolation layers may be provided on the substrate 100 at intervals according to the circuit requirements of the semiconductor structure of the actual driver chip, and two or more of the first-type isolation layers are connected by wires 106 ohms.

[0054] In other embodiments, as long as each of the first type of isolation layers is configured to be in a floating or high-resistance state, it is not necessary to connect it via the wire 106 ohms, but simply to be isolated by the substrate 100.

[0055] Example 3

[0056] One embodiment of this application provides a semiconductor structure for a driver chip. Figure 4 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 3 of this application. The following will refer to... Figure 4 The semiconductor structure of the driver chip in Embodiment 3 of this application is described in detail below:

[0057] The difference between Embodiment 3 and Embodiment 1 of this application is as follows:

[0058] In this embodiment, a second type of isolation layer 108 is also provided on the substrate 100. No bulk region or semiconductor device is formed on the second type of isolation layer 108. The second type of isolation layer 108 is ohm connected to the first type of isolation layer 101 through a wire 106.

[0059] Example 4

[0060] One embodiment of this application provides a semiconductor structure for a driver chip. Figure 5 This is a schematic diagram of the semiconductor structure of the driver chip in Embodiment 4 of this application. The following will refer to... Figure 5 The semiconductor structure of the driver chip in Embodiment 4 of this application is described in detail below:

[0061] The difference between Embodiment 4 and Embodiment 1 in this application is as follows:

[0062] In this embodiment, the first type of isolation layer 101 is in a high-resistance state after being connected to the bias voltage VB via resistor Rh.

[0063] Understandably, since the first type of isolation layer 101 is configured in a high-impedance state, the connected bias voltage VB does not need to be driven.

[0064] Example 5

[0065] One embodiment of this application provides a driver chip that employs the semiconductor structure described above.

[0066] The above description is merely a partial embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0067] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0068] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A semiconductor structure for a driver chip, characterized in that, include: Substrate, At least one type of isolation layer is formed on the substrate, and at least one bulk region is formed on the type of isolation layer; Semiconductor devices are formed on the substrate and the body region, respectively; The first type of isolation layer is configured to be in a floating state or in a high-resistivity state; The first type of isolation layer includes any one or a combination of buried layers, deep wells, and wells.

2. The semiconductor structure of the driver chip according to claim 1, characterized in that, At least two of the first type of isolation layers are interconnected.

3. The semiconductor structure of the driver chip according to claim 1, characterized in that, Each of the first type of isolation layers is separated by the substrate.

4. The semiconductor structure of the driver chip according to claim 1, characterized in that, The substrate is a P-type substrate, each of the first type of isolation layers is an N-type isolation layer, and the body region is a P-type body region.

5. The semiconductor structure of the driver chip according to claim 1, characterized in that, Also includes: A second type of isolation layer is formed on the substrate and is ohmically connected to the first type of isolation layer.

6. A driver chip, characterized in that, The semiconductor structure of the driver chip described in any one of claims 1-5 is adopted.

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