Semiconductor package

Abstract

A semiconductor package is provided that includes a redistribution layer having a first surface and a second surface opposite the first surface in a first direction. The first heat dissipation layer is embedded in the redistribution layer and exposed at the first surface and the second surface. A semiconductor die is disposed on the redistribution layer and the first heat dissipation layer, the semiconductor die including a die body and a die pad between the die body and the redistribution layer and electrically connected to the redistribution layer. The molding layer is disposed at least on the redistribution layer and surrounds the semiconductor die. The connection terminal is disposed under the redistribution layer, and is electrically connected to the redistribution layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a bare die. Background Art

[0002] Typically, a bare die (also known as a "semiconductor die") having a predetermined function can be manufactured by performing semiconductor processes on a wafer. However, the manufactured bare die is susceptible to damage because its functional structure is exposed to the outside. In order to improve the reliability of the bare die, semiconductor packaging technology has been proposed. In semiconductor packaging technology, the bare die can be placed on a packaging substrate such as a printed circuit board (PCB), and a mold layer is formed on the packaging substrate to encapsulate the bare die, thereby protecting the bare die. For example, a semiconductor package including a bare die can be used as a chip in electronic devices such as smartphones, tablet computers, portable multimedia players, personal digital assistants, e-books, and similar devices.

[0003] As electronic devices become more multifunctional, the demand for dies with higher operating performance continues to grow. This higher operating performance can increase the heat generated by the die during operation. If the semiconductor package containing the die is unable to effectively dissipate the heat generated by the die, thermal failure of the die can occur.

[0004] Furthermore, with the miniaturization of electronic devices, the demand for smaller semiconductor packages continues to grow. However, conventional semiconductor packaging technologies, such as package substrates, molding layers, and / or heat dissipation components, may have limitations in size reduction (e.g., material limitations and / or process limitations), which may restrict the miniaturization of semiconductor packages. Summary of the Invention

[0005] The present disclosure provides a semiconductor package with improved reliability.

[0006] The present disclosure provides a semiconductor package with improved heat dissipation and / or reduced size.

[0007] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a redistribution layer having a first surface and a second surface opposite to the first surface in a first direction; a first heat dissipation layer within the redistribution layer and exposed from the first and second surfaces of the redistribution layer; a semiconductor die on the redistribution layer and the first heat dissipation layer and comprising a die body and a die pad between the die body and the redistribution layer, the semiconductor die being electrically connected to the redistribution layer via the die pad; a molding layer at least on the redistribution layer and surrounding the semiconductor die; and a connection terminal below the redistribution layer and electrically connected to the redistribution layer.

[0008] In an embodiment, the semiconductor die may have an active surface, the die pad is disposed on the active surface, the redistribution layer may cover a portion of the active surface where the die pad is disposed, and the first heat dissipation layer may cover a portion of the active surface where the die pad is not disposed.

[0009] In an embodiment, when viewed along the first direction, the entire first heat dissipation layer may overlap with the semiconductor die.

[0010] In an embodiment, a side surface of the semiconductor die may be located on the redistribution layer in the first direction.

[0011] In an embodiment, a portion of a side surface of the semiconductor die may be located on the redistribution layer in the first direction, and another portion of the side surface of the semiconductor die may be located on the first heat dissipation layer in the first direction.

[0012] In an embodiment, the first heat dissipation layer may have a first portion located within the redistribution layer and a second portion extending from the first portion to the second surface of the redistribution layer, and the second portion of the first heat dissipation layer may be spaced apart from the connection terminal.

[0013] In an embodiment, the semiconductor package may further include: a second heat dissipation layer located between the semiconductor die and the mold layer and extending above the semiconductor die to cover the semiconductor die. In the first direction, the mold layer may not overlap with the second heat dissipation layer.

[0014] In an embodiment, the entire first heat dissipation layer may overlap the semiconductor die in the first direction, and the second heat dissipation layer may be located on the redistribution layer between the semiconductor die and the mold layer.

[0015] In an embodiment, the first heat dissipation layer may have a portion extending beyond a side surface of the semiconductor die. A portion of the second heat dissipation layer located between the semiconductor die and the mold layer may be on the redistribution layer, and another portion of the second heat dissipation layer located between the semiconductor die and the mold layer may be on the portion of the first heat dissipation layer.

[0016] In an embodiment, the first heat dissipation layer may include or have a first exposed surface exposed toward the outside of the semiconductor package in the first direction.

[0017] In an embodiment, the second heat dissipation layer may include or have a second exposed surface exposed toward the outside of the semiconductor package in the first direction.

[0018] In an embodiment, at least one of the first heat dissipation layer and the second heat dissipation layer may include or have at least one groove formed on a corresponding exposed surface of the first exposed surface and the second exposed surface.

[0019] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a redistribution layer having a first surface and a second surface, the second surface being opposite to the first surface in a first direction; a first heat dissipation layer embedded in the redistribution layer and exposed at the first surface and the second surface of the redistribution layer; a semiconductor die disposed on the redistribution layer and the first heat dissipation layer, the semiconductor die comprising a die body and a die pad, the die pad being disposed between the die body and the redistribution layer, wherein the semiconductor die is electrically connected to the redistribution layer through the die pad; a second heat dissipation layer disposed above the semiconductor die, wherein the second heat dissipation layer is bonded to the semiconductor die; a molding layer disposed at least on the redistribution layer and surrounding the semiconductor die and the second heat dissipation layer; and a connection terminal disposed below the redistribution layer and electrically connected to the redistribution layer.

[0020] In an embodiment, the first heat dissipation layer and the second heat dissipation layer may be formed of different thermally conductive materials.

[0021] In an embodiment, the second heat dissipation layer may have grooves on an exposed surface thereof.

[0022] In an embodiment, the molding layer may be formed of epoxy molding compound.

[0023] In an embodiment, the second heat dissipation layer may extend laterally beyond the semiconductor die and may at least partially overlap the first heat dissipation layer.

[0024] According to one aspect of the present disclosure, a semiconductor package is provided, comprising: a redistribution layer having a first surface and a second surface, the second surface being opposite to the first surface in a first direction; a first heat dissipation layer penetrating the entire redistribution layer and exposed at the first surface and the second surface of the redistribution layer; a semiconductor die disposed on the redistribution layer and the first heat dissipation layer, the semiconductor die comprising a die body and a die pad, the die pad being disposed between the die body and the redistribution layer, wherein the semiconductor die is electrically connected to the redistribution layer through the die pad; a second heat dissipation layer disposed to surround the upper surface and side surfaces of the semiconductor die; a molding layer disposed at least on the redistribution layer and surrounding the semiconductor die and the second heat dissipation layer; and a connection terminal disposed below the redistribution layer and electrically connected to the redistribution layer.

[0025] In an embodiment, an upper surface of the first heat dissipation layer may be substantially coplanar with the first surface of the redistribution layer. A lower surface of the first heat dissipation layer may be substantially coplanar with the second surface of the redistribution layer.

[0026] In an embodiment, the redistribution layer may include an insulating layer and a plurality of conductive paths within the insulating layer, with both ends of each conductive path exposed on the first surface and the second surface, respectively. A side surface of the first heat dissipation layer may contact a side surface of the redistribution layer, and the first heat dissipation layer may be electrically insulated from the plurality of conductive paths of the redistribution layer.

[0027] In an embodiment, the side surface of the first heat dissipation layer may be spaced apart from the inner side surface of the redistribution layer. An additional insulating layer may be further interposed between the side surface of the first heat dissipation layer and the inner side surface of the redistribution layer.

[0028] In an embodiment, the die pad may be provided on the die body, and may be arranged to be spaced apart from the first heat dissipation layer in a direction perpendicular to the first direction.

[0029] According to one aspect of the present disclosure, a method for forming a semiconductor package is provided, the method comprising: forming a redistribution layer, the redistribution layer having a first surface and a second surface, the second surface being opposite to the first surface in a first direction; forming a first heat dissipation layer in the redistribution layer, the first heat dissipation layer having a first exposed surface exposed at the second surface of the redistribution layer; disposing a semiconductor die on the redistribution layer and the first heat dissipation layer, the semiconductor die comprising a die body and a die pad, the die pad being located between the die body and the redistribution layer, wherein the semiconductor die is electrically connected to the redistribution layer through the die pad; forming a second heat dissipation layer above the semiconductor die, the second heat dissipation layer being thermally bonded to the semiconductor die; forming a mold layer, the mold layer being at least on the redistribution layer and surrounding the semiconductor die and the second heat dissipation layer; and forming at least one groove in the second heat dissipation layer.

[0030] In an embodiment, the second heat dissipation layer may be formed of a material having a different thermal conductivity than that of the first heat dissipation layer.

[0031] In an embodiment, the grooves on the second heat dissipation layer may be formed by a laser cutting process.

[0032] In an embodiment, the molding layer may be formed of epoxy molding compound.

[0033] In an embodiment, the second heat dissipation layer may be deposited using a sputtering process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other aspects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings.

[0035] Figure 1 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0036] Figure 2 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0037] Figure 3 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0038] Figure 4 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0039] Figure 5 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0040] Figure 6is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0041] Figures 7 to 9 are cross-sectional views schematically illustrating stages of a method of manufacturing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0042] Example embodiments will be described more fully with reference to the accompanying drawings showing example embodiments. The embodiments described herein are provided as examples and, therefore, the present disclosure is not limited thereto but may be implemented in various forms. Each embodiment provided in the following description does not exclude association with another example or another embodiment that is also provided herein or not provided herein but is consistent with the present disclosure. In the accompanying drawings, various elements, components, layers, regions, etc. may not be drawn to scale for the sake of clarity. In the accompanying drawings, the same or similar reference numerals represent the same or similar components.

[0043] For descriptive purposes, spatially relative terms such as "below," "lower," "bottom," "above," "upper," "top," etc. may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "below" another element or feature would then be positioned "above" the other element or feature. Thus, the exemplary term "below" can include both an above and a below orientation. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0044] Hereinafter, some example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0046] Reference Figure 1 The semiconductor package 1 according to some embodiments may include a redistribution layer 100 , a first heat dissipation layer 200 , a semiconductor die 400 , a molding layer 500 , and a connection terminal 600 .

[0047] The redistribution layer 100 may have a first surface 100a (e.g., an upper surface or top surface) and a second surface 100b (e.g., a lower surface and a bottom surface). The first surface 100a and the second surface 100b may be opposite to each other in a first direction Z and may each extend in a second direction X and / or a third direction Y. As used herein, the first direction Z, the second direction X, and the third direction Y may be directions that intersect (e.g., are orthogonal to) each other. For example, the first direction Z may be a direction parallel to the thickness direction of the redistribution layer 100, and the second direction X and the third direction Y may be directions that intersect (e.g., are orthogonal to) the thickness direction of the redistribution layer 100. For example, the first direction Z may also be referred to as a vertical direction, the second direction X may also be referred to as a first horizontal direction, and the third direction Y may also be referred to as a second horizontal direction.

[0048] In the semiconductor package 1, the redistribution layer 100 may be a wiring layer used to electrically connect internal components (e.g., semiconductor die 400) of the semiconductor package 1 to an external device (e.g., an external circuit board). In other words, the internal components (e.g., semiconductor die 400) of the semiconductor package 1 can be electrically connected to the external device (e.g., an external circuit board) via the redistribution layer 100, rather than a conventional package substrate (such as a printed circuit board (PCB), glass substrate, ceramic substrate, semiconductor material substrate, etc.). Conventional package substrates may be relatively difficult to minimize in size (e.g., thickness) due to limitations in materials and / or processes, which limits the minimization of the size (e.g., thickness) of the semiconductor package. In contrast, the redistribution layer 100 can generally be formed to have smaller dimensions (e.g., thickness). Therefore, the semiconductor package 1 including the redistribution layer 100 can have dimensions (e.g., thickness) that are easily reduced (e.g., minimized).

[0049] In an embodiment, the redistribution layer 100 may include one or more wirings and one or more vias. Figure 1As shown in FIG, the redistribution layer 100 may include a plurality of wirings and a plurality of vias formed at multiple levels. The plurality of wirings and the plurality of vias of the redistribution layer 100 may be connected to each other, so that the redistribution layer 100 may include a plurality of independent conductive paths CP. The plurality of conductive paths CP may extend in the redistribution layer 100 in a first direction Z, a second direction X, and / or a third direction Y. Both ends of each conductive path CP may be exposed at the first surface 100a and the second surface 100b of the redistribution layer 100, respectively, for connection (e.g., electrical connection or electrical bonding) with components disposed on corresponding surfaces of the first surface 100a and the second surface 100b of the redistribution layer 100. In the semiconductor package 1, the conductive paths CP of the redistribution layer 100 may provide electrical paths for communication (e.g., power transmission, signal transmission, etc.) between internal components of the semiconductor package 1 (e.g., the semiconductor die 400) and the outside (e.g., an external circuit board). In an embodiment, each wiring and via in the redistribution layer 100 may be formed of a conductive material (such as metal, metal nitride, and / or metal silicide). In an embodiment, each wiring and via in the redistribution layer 100 may have a single-layer structure or a multi-layer structure composed of at least one of the above conductive materials, but is not limited thereto.

[0050] The redistribution layer 100 may further include an insulating layer BL (eg, a solder resist layer) covering the wirings and vias. Figure 1 As shown in , the insulating layer BL may surround and / or bury the conductive paths CP to electrically insulate and / or isolate the conductive paths CP from each other. In other words, in the redistribution layer 100, the conductive paths CP may extend within the insulating layer BL and be separated from each other by the insulating layer BL therebetween, thereby being electrically insulated / isolated from each other. In an embodiment, the insulating layer BL may be formed of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In an embodiment, the insulating layer BL may have a multilayer structure including at least one of the above insulating materials, but is not limited thereto.

[0051] In an embodiment, the conductive paths CP and the insulating layer BL of the redistribution layer 100 may be integrated with each other. For example, the redistribution layer 100 including the conductive paths CP and the insulating layer BL (eg, integrated with each other) may be formed by a series of processes such as deposition, patterning, and / or planarization.

[0052] In addition, in the redistribution layer 100, the number and structure of the conductive paths CP, the number and structure of the wirings and vias constituting the conductive paths CP, etc. may not be limited to Figure 1 The number and structure shown in FIG. 1 are different from those shown in FIG. 1 , but may be variously changed according to requirements (eg, requirements for wiring connections between internal components of the semiconductor package 1 and the outside).

[0053] like Figure 1 As shown in FIG, the first heat dissipation layer 200 may be disposed within the redistribution layer 100. For example, the first heat dissipation layer 200 may be disposed at the same level (e.g., horizontal level) as the redistribution layer 100. For example, in the horizontal direction (e.g., the second direction X and / or the third direction Y), the first heat dissipation layer 200 may be surrounded by the redistribution layer 100, and in the vertical direction (e.g., the first direction Z), the first heat dissipation layer 200 may not be covered by the redistribution layer 100. For example, the first heat dissipation layer 200 may penetrate the entire redistribution layer 100 in the thickness direction of the redistribution layer 100.

[0054] like Figure 1 As shown in , the first heat dissipation layer 200 may be exposed at the first surface 100a and the second surface 100b of the redistribution layer 100. For example, the first heat dissipation layer 200 may have a first surface (e.g., an upper surface or top surface) and a second surface (e.g., a lower surface or bottom surface) that are opposite to each other in the first direction Z. The upper surface of the first heat dissipation layer 200 may be exposed from the first surface 100a of the redistribution layer 100, and the lower surface of the first heat dissipation layer 200 may be exposed from the second surface 100b of the redistribution layer 100. In an embodiment, as Figure 1 As shown in FIG, the upper surface of the first heat dissipation layer 200 may be substantially coplanar with the first surface 100a of the redistribution layer 100, and the lower surface of the first heat dissipation layer 200 may be substantially coplanar with the second surface 100b of the redistribution layer 100. However, these embodiments are not limited thereto. In some embodiments, the lower surface of the first heat dissipation layer 200 may extend below the second surface 100b of the redistribution layer 100 in the first direction (Z).

[0055] According to embodiments of the present disclosure, the first heat dissipation layer 200 can have high heat dissipation properties. For example, the first heat dissipation layer 200 can be formed from a material having high thermal conductivity. For example, the first heat dissipation layer 200 can be made from a metal material. For example, the metal material can include at least one of metals such as copper (Cu), iron (Fe), cobalt (Co), nickel (Ni), and alloys thereof.

[0056] The first heat dissipation layer 200 may be electrically insulated and / or isolated from the conductive path CP of the redistribution layer 100. In an embodiment, the first heat dissipation layer 200 may be in contact with the redistribution layer 100 but electrically insulated and / or isolated from the conductive path CP. Figure 1As shown in FIG, the side surfaces (e.g., outer surfaces) of the first heat dissipation layer 200 and the side surfaces (e.g., inner surfaces) of the redistribution layer 100 may be in contact with each other, while a portion of the insulating layer BL of the redistribution layer 100 may be positioned between the first heat dissipation layer 200 and the conductive path CP to electrically insulate and / or isolate the first heat dissipation layer 200 from the conductive path CP. However, embodiments are not limited thereto. In some other embodiments, for example, the first heat dissipation layer 200 and the redistribution layer 100 may be spaced apart from each other (e.g., in the second direction X and / or the third direction Y), while an additional insulating layer may be positioned between the first heat dissipation layer 200 and the redistribution layer 100 to electrically insulate and / or isolate the first heat dissipation layer 200 and the redistribution layer 100 from each other. The additional insulating layer may be formed of an insulating material (e.g., silicon oxide or silicon nitride). Furthermore, the additional insulating layer may include a material that is the same as or different from the insulating layer BL of the redistribution layer 100.

[0057] In the semiconductor package 1, the semiconductor die 400 may be an unpackaged die obtained through a wafer-level semiconductor process. The semiconductor die 400 may be configured to implement a predetermined or set function (e.g., logic processing, data storage, etc.). For example, the semiconductor die 400 may function as a logic die, a memory die, or both a logic die and a memory die. However, the embodiment is not limited thereto, and as required, the semiconductor die 400 may be designed and manufactured to implement various suitable or desired functions.

[0058] like Figure 1 As shown in , a semiconductor die 400 may have a first surface 400a (e.g., an upper surface or top surface) and a second surface 400b (a lower surface or bottom surface). The first surface 400a and the second surface 400b may be opposite to each other in a vertical direction (e.g., a first direction Z) and may each extend in a horizontal direction (e.g., a second direction X and / or a third direction Y). Furthermore, the semiconductor die 400 may further have a third surface 400s (e.g., a side surface) between the first and second surfaces 400a, 400b that are opposite to each other. In the semiconductor die 400, the third surface 400s may extend in a vertical direction (e.g., the first direction Z) to connect the first and second surfaces 400a, 400b. In addition, in the semiconductor die 400, the third surface 400s extending in the vertical direction (e.g., the first direction Z) may also extend in the horizontal direction (e.g., the second direction X and / or the third direction Y) to constitute the outer contour of the semiconductor die 400 together with the first surface 400a and the second surface 400b.

[0059] like Figure 1 As shown in FIG, a semiconductor die 400 may include a die body 410 and a die pad 420 .

[0060] The die body 410 may include a semiconductor material (such as silicon, germanium, or silicon germanium). The die body 410 may include a circuit structure (also referred to as a functional circuit layer; not shown) for implementing a predetermined or set function. In an embodiment, the circuit structure within the die body 410 may be composed of transistors, interconnects, and other components, but is not limited thereto. In an embodiment, the die body 410 including the circuit structure or functional circuit layer may be manufactured by performing semiconductor processes such as implantation, deposition, masking, etching, and planarization on a wafer, but is not limited thereto.

[0061] The die pad 420 may be disposed on the second surface 400b of the semiconductor die 400. For example, the die pad 420 may be disposed on the die body 410 at the second surface 400b of the semiconductor die 400. Figure 1 As shown in , the die pad 420 can be provided to protrude below the die body 410, for example, protruding from the lower surface or bottom surface of the die body 410. However, embodiments are not limited thereto. In some other embodiments, the die pad 420 can be provided in a portion of the die body 410 adjacent to the second surface 400 b and can be exposed from the second surface 400 b of the semiconductor die 400. In embodiments, the die pad 420 can be formed of a conductive material (such as a metal, an alloy, a metal nitride, and / or a metal silicide). In embodiments, the die pad 420 can have a single-layer structure or a multi-layer structure composed of at least one of the above-mentioned conductive materials.

[0062] The die pad 420 can connect the die body 410 and the redistribution layer 100 to each other, so that the circuit structure in the die body 410 can be electrically connected to the conductive path CP of the redistribution layer 100 via the die pad 420. As such, the second surface 400b of the semiconductor die 400 on which the die pad 420 is disposed can be referred to as an "active surface." Furthermore, the first surface 400a of the semiconductor die 400, which is opposite to the second surface 400b, can be referred to as an "inactive surface."

[0063] In the semiconductor package 1, as Figure 1 As shown in FIG, the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 provided with the die pad 420 may face the redistribution layer 100. That is, in the semiconductor package 1, the semiconductor die 400 may be flip-chip bonded to the redistribution layer 100. As a result, the space required for electrical connection between the semiconductor die 400 and the redistribution layer 100 may be minimized.

[0064] Reference Figure 1The semiconductor die 400 may be disposed on the redistribution layer 100 and the first heat dissipation layer 200. For example, the semiconductor die 400 may be partially disposed on the redistribution layer 100 and partially disposed on the first heat dissipation layer 200. For example, the semiconductor die 400 may overlap both the redistribution layer 100 and the first heat dissipation layer 200 in the first direction Z. As a result, the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 may face both the redistribution layer 100 and the first heat dissipation layer 200. A portion of the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 may be covered by the redistribution layer 100, and another portion (e.g., the remaining portion) of the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 may be covered by the first heat dissipation layer 200. In embodiments, the semiconductor die 400 may be disposed directly on the redistribution layer 100 and the first heat dissipation layer 200. In this case, the semiconductor die 400 may be electrically connected only to the conductive path CP of the redistribution layer 100 and may be electrically insulated from the first heat dissipation layer 200 .

[0065] In an embodiment, the die pad 420 of the semiconductor die 400 may be between the die body 410 and the redistribution layer 100 of the semiconductor die 400, but not between the die body 410 and the first heat dissipation layer 200. For example, the die pad 420 may be disposed between portions of the die body 410 and the redistribution layer 100 that overlap each other in the first direction Z, but not between portions of the die body 410 and the first heat dissipation layer 200 that overlap each other in the first direction Z. In this manner, the redistribution layer 100 may cover the portion of the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 where the die pad 420 is disposed, and the first heat dissipation layer 200 may cover the portion of the active surface (i.e., the second surface 400 b ) of the semiconductor die 400 where the die pad 420 is not disposed.

[0066] The die pad 420 may be electrically insulated and / or isolated from the first heat dissipation layer 200. For example, the die pad 420 may be spaced apart (e.g., physically spaced apart) from the first heat dissipation layer 200. For example, the die pad 420 may be spaced apart from the first heat dissipation layer 200 in a horizontal direction (e.g., the second direction X and / or the third direction Y). For example, the die pad 420 may be spaced apart from the first heat dissipation layer 200 on the second surface 400 b of the semiconductor die 400. In embodiments, a portion of insulating material or insulating layer included in the semiconductor die 400 and / or the redistribution layer 100, and / or an additional insulating layer may be disposed between the die pad 420 and the first heat dissipation layer 200 to electrically insulate and / or isolate the die pad 420 and the first heat dissipation layer 200 from each other. For example, the additional insulating layer may be composed of an insulating material (e.g., silicon oxide or silicon nitride) and may include the same or different insulating material as the insulating material of the semiconductor die 400 or the redistribution layer 100.

[0067] exist Figure 1 In the embodiment shown in FIG, the entire first heat dissipation layer 200 may overlap the semiconductor die 400 in the first direction Z. In other words, the entire first heat dissipation layer 200 may be on the second surface 400b of the semiconductor die 400. For example, the first heat dissipation layer 200 may extend on the second surface 400b of the semiconductor die 400, and the redistribution layer 100 may surround the first heat dissipation layer 200 on the second surface 400b of the semiconductor die 400. For example, the third surface 400s (e.g., a side surface) of the semiconductor die 400 may be positioned on the redistribution layer 100 in the vertical direction (e.g., the first direction Z) (e.g., entirely positioned on the redistribution layer 100). In other words, the semiconductor die 400 may extend beyond the first heat dissipation layer 200 in the horizontal direction (e.g., the second direction X and the third direction Y) and onto the first surface 100a of the redistribution layer 100. In this case, when viewed in plan, the die pad 420 may surround the first heat dissipation layer 200 and be spaced apart from the first heat dissipation layer 200. However, the embodiment is not limited thereto. In some embodiments, the first heat dissipation layer 200 may also extend beyond the semiconductor die 400 (e.g., a portion of the third surface 400s of the semiconductor die 400) in a horizontal plane (e.g., in the second direction X and / or the third direction Y). In this case, the redistribution layer 100 may partially surround the first heat dissipation layer 200 on the second surface 400b of the semiconductor die 400, or the redistribution layer 100 may be disposed on one side of the first heat dissipation layer 200.

[0068] In the semiconductor package 1 , the mold layer 500 may be at least on the redistribution layer 100 and may surround the semiconductor die 400 . Figure 1 In the embodiment shown in FIG, the mold layer 500 may cover the semiconductor die 400 on the redistribution layer 100. For example, the mold layer 500 may be formed on the first surface 400a and the third surface 400s of the semiconductor die 400, as well as the first surface 100a of the redistribution layer 100. For example, the mold layer 500 may be in contact with the semiconductor die 400 and the redistribution layer 100, and may not be in contact with the first heat dissipation layer 200. However, embodiments are not limited thereto. In some example embodiments, when the first heat dissipation layer 200 extends beyond the semiconductor die 400 in a horizontal direction (e.g., the second direction X and / or the third direction Y) as described above, the mold layer 500 may also be positioned on portions of each of the redistribution layer 100 and the first heat dissipation layer 200 that extend beyond the semiconductor die 400.

[0069] In an embodiment, the molding layer 500 may include a molding material having high thermal conductivity. For example, the molding material having high thermal conductivity may include epoxy molding compound and an inorganic filler dispersed in the epoxy molding compound. For example, the inorganic filler may be composed of aluminum oxide, boron nitride, graphene, carbon nanotubes, or the like.

[0070] Although not shown, a conductive member (e.g., a conductive plug, a conductive pillar, or a conductive interconnection line) may be further formed in a portion of the mold layer 500 on the redistribution layer 100. Both ends of the conductive member may be exposed at the upper and lower surfaces, respectively, of the mold layer 500. One end of the conductive member may be connected to the conductive path CP of the redistribution layer 100, and the other end of the conductive member may be exposed from the upper surface of the mold layer 500 for electrical connection with an external component (e.g., to serve as a contact).

[0071] In the semiconductor package 1, the connection terminals 600 may be below the redistribution layer 100 and may be electrically connected to the redistribution layer 100. For example, the connection terminals 600 may be disposed on the second surface 100b of the redistribution layer 100. For example, the connection terminals 600 may be electrically connected to the conductive paths CP of the redistribution layer 100. For example, the connection terminals 600 may directly contact one end of the conductive paths CP on the second surface 100b of the redistribution layer 100. Each of the connection terminals 600 may have a configuration such as a conductive bump or a solder ball, but is not limited thereto. The connection terminals 600 may be formed of a conductive material such as a metal or an alloy. Furthermore, although not shown, the connection terminals 600 may be disposed on the second surface 100b of the redistribution layer 100 in various suitable planar arrangements depending on the connection specifications between the semiconductor package 1 and an external component (e.g., an external circuit board).

[0072] In an embodiment, at least some of the connection terminals 600 may be electrically connected to the die pad 420 via a conductive path CP, and thus electrically connected to the functional circuit layer of the die body 410. In an embodiment, when a conductive member is formed in the mold layer 500, some of the connection terminals 600 may also be electrically connected to the conductive member in the mold layer 500 via the conductive path CP. In these embodiments, the connection terminals 600 may be electrical connection members in the semiconductor package 1 for connecting to an external component (e.g., an external circuit board).

[0073] In an embodiment, some of the connection terminals 600 (e.g., the connection terminals 600 at the edge region of the redistribution layer 100) may also be electrically floating. In such an embodiment, the connection terminals 600 may be support members for supporting the semiconductor package 1 when the semiconductor package 1 is coupled or mounted to an external component (e.g., an external circuit board).

[0074] The connection terminal 600 may be electrically insulated or isolated from the first heat dissipation layer 200. For example, Figure 1 As shown in , the connection terminal 600 may be spaced apart from the first heat dissipation layer 200 exposed at the second surface 100b of the redistribution layer 100. For example, Figure 1 As shown in , the first heat dissipation layer 200 may not overlap the connection terminal 600 in a vertical direction (eg, first direction Z) and be spaced apart from the connection terminal 600 in horizontal directions (eg, second direction X and third direction Y).

[0075] As described above, in the semiconductor die 400, circuit structures or functional circuit layers (not shown) may generally be formed on the active surface (e.g., the second surface 400 b ) of the semiconductor die 400, for example, in a portion of the die body 410 adjacent to the active surface (e.g., the second surface 400 b ). As a result, during operation, heat generated by the semiconductor die 400 may be primarily concentrated on the active surface of the semiconductor die 400. In the semiconductor package 1 according to an embodiment of the present disclosure, the semiconductor die 400 may be disposed on the first heat dissipation layer 200 with its active surface facing the first heat dissipation layer 200. This allows heat concentrated on the active surface (e.g., the second surface 400 b ) of the semiconductor die 400 to be efficiently dissipated via the first heat dissipation layer 200. Consequently, the semiconductor package 1 may have improved heat dissipation. Consequently, thermal failure of the die may be prevented or reduced in the semiconductor package 1, resulting in improved reliability of the semiconductor package 1.

[0076] Furthermore, when the first heat dissipation layer 200 is disposed on the active surface (e.g., the second surface 400 b ) of the semiconductor die 400 and can be formed of a metal material having high thermal conductivity, the first heat dissipation layer 200 can be formed with a relatively thin thickness. Therefore, both the redistribution layer 100 and the first heat dissipation layer 200 embedded in the redistribution layer 100 can be implemented with a smaller size (e.g., thickness). As a result, the semiconductor package 1 can have a further reduced size (e.g., thickness) while having improved heat dissipation performance.

[0077] Figure 2 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0078] According to an embodiment of the present disclosure, in addition to the semiconductor package 2 further comprising the second heat dissipation layer 300 , Figure 2 The semiconductor package 2 shown in FIG. Figure 1 The semiconductor package 1 described is substantially the same or similar to that of FIG. Figure 1 The differences between the described embodiments.

[0079] Reference Figure 2 The semiconductor package 2 according to an embodiment of the present disclosure may include a redistribution layer 100, a first heat dissipation layer 200 in the redistribution layer 100, a semiconductor die 400 on the redistribution layer 100 and the first heat dissipation layer 200, and a mold layer 500' surrounding the semiconductor die 400 on the redistribution layer 100.

[0080] like Figure 2 As shown in , the mold layer 500' may be spaced apart from the semiconductor die 400 in the horizontal direction (e.g., the second direction X and the third direction Y) and may not overlap the semiconductor die 400 in the vertical direction (e.g., the first direction Z). In an embodiment, the mold layer 500' may have a thickness greater than that of the semiconductor die 400 in the vertical direction (e.g., the first direction Z). For example, the upper surface of the mold layer 500' may be at a height higher than the first surface 400a of the semiconductor die 400. In an embodiment, the mold layer 500' may include an epoxy molding compound. For example, as with reference Figure 1 Unlike the mold layer 500 described above, the mold layer 500' may not include an inorganic filler for increasing thermal conductivity. Figure 1 Compared to the mold layer 500 described in , it may be easier to reduce the size (eg, thickness) of the mold layer 500 ′.

[0081] Reference Figure 2 The semiconductor package 2 may further include a second heat dissipation layer 300. The second heat dissipation layer 300 may be positioned between the semiconductor die 400 and the mold layer 500' and extend above the semiconductor die 400. For example, the second heat dissipation layer 300 may partially extend over the first surface 400a (e.g., an inactive surface) of the semiconductor die 400. The second heat dissipation layer 300 may cover the semiconductor die 400. The second heat dissipation layer 300 may fill the interior space of the mold layer 500' and cover the first surface 400a and third surface 400s of the semiconductor die 400 as well as the inner surface of the mold layer 500'.

[0082] For example, in the horizontal direction (e.g., the second direction X and the third direction Y), the second heat dissipation layer 300 may surround the semiconductor die 400, and the mold layer 500' may surround the second heat dissipation layer 300. For example, in the vertical direction (e.g., the first direction Z), the second heat dissipation layer 300 may partially overlap the semiconductor die 400, the first heat dissipation layer 200, and the redistribution layer 100. For example, in the vertical direction (e.g., the first direction Z), the second heat dissipation layer 300 may not overlap the mold layer 500'. For example, the top surface of the second heat dissipation layer 300 may be exposed from the mold layer 500' toward the outside of the semiconductor package 2. For example, the top surface of the second heat dissipation layer 300 may be substantially coplanar with the top surface of the mold layer 500'.

[0083] The second heat dissipation layer 300 can have high heat dissipation properties. For example, the second heat dissipation layer 300 can be formed from a material with high thermal conductivity. For example, the second heat dissipation layer 300 can be formed from a metal material. For example, the metal material can include at least one of metals such as copper (Cu), iron (Fe), cobalt (Co), nickel (Ni), and alloys thereof. In embodiments, the second heat dissipation layer 300 can be made of a material that is the same as or different from that of the first heat dissipation layer 200.

[0084] exist Figure 2 In the embodiment shown in FIG, the entire first heat dissipation layer 200 may overlap the semiconductor die 400 in the vertical direction (e.g., the first direction Z). In other words, the entire first heat dissipation layer 200 may be on the second surface 400b of the semiconductor die 400. In this case, the second heat dissipation layer 300 may be located (e.g., entirely) on the redistribution layer 100 between the semiconductor die 400 and the mold layer 500'. For example, the portion of the second heat dissipation layer 300 between the semiconductor die 400 and the mold layer 500' may not overlap the first heat dissipation layer 200 in the vertical direction (e.g., the first direction Z). However, embodiments are not limited thereto. In some other embodiments, when the first heat dissipation layer 200 extends beyond the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y), a portion of the second heat dissipation layer 300 between the semiconductor die 400 and the mold layer 500′ may be disposed on (e.g., in contact with) the portion of the first heat dissipation layer 200 extending beyond the semiconductor die 400, and another portion of the second heat dissipation layer 300 between the semiconductor die 400 and the mold layer 500′ may be disposed on the redistribution layer 100. In addition, depending on the distance that the first heat dissipation layer 200 extends beyond the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y), the first heat dissipation layer 200 may also extend beyond the second heat dissipation layer 300 (e.g., the outer surface of the second heat dissipation layer 300) in the horizontal direction (e.g., the second direction X and / or the third direction Y), so that a portion of the mold layer 500' may be disposed on the portion of the first heat dissipation layer 200 extending beyond the second heat dissipation layer 300, and another portion of the mold layer 500' may be disposed on the redistribution layer 100.

[0085] In the semiconductor package 2, the second heat dissipation layer 300 can cover the semiconductor die 400 inside the mold layer 500' and be exposed to the outside from the mold layer 500'. As a result, an additional heat dissipation path can be provided for the semiconductor die 400. Therefore, the semiconductor package 2 can have further improved heat dissipation.

[0086] Furthermore, the second heat dissipation layer 300 can cover the semiconductor die 400 and can be formed from a metal material with high thermal conductivity. In this case, the second heat dissipation layer 300 can be formed with a relatively thin thickness. Furthermore, the mold layer 500' can serve as a frame surrounding the second heat dissipation layer 300 and the semiconductor die 400 covered by the second heat dissipation layer 300, eliminating the need for the mold layer 500' to include a material with high thermal conductivity and, therefore, can also be formed with a relatively thin thickness. As a result, the semiconductor package 2 can have a further reduced size (e.g., thickness) while maintaining enhanced heat dissipation.

[0087] Figure 3 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments.

[0088] According to an embodiment of the present disclosure, in addition to at least one of the first heat dissipation layer 200' and the second heat dissipation layer 300' having at least one groove formed on the exposed surface thereof, Figure 3 The semiconductor package 2a shown in FIG. Figure 2 Therefore, the following description will focus on the embodiment of the reference Figure 2 The differences between the described embodiments.

[0089] Reference Figure 3 The semiconductor package 2a according to an embodiment of the present disclosure may include a redistribution layer 100, a first heat dissipation layer 200' in the redistribution layer 100, a semiconductor die 400 on the redistribution layer 100 and the first heat dissipation layer 200', a mold layer 500' surrounding the semiconductor die 400 on the redistribution layer 100, and a second heat dissipation layer 300' between the semiconductor die 400 and the mold layer 500' and covering the semiconductor die 400.

[0090] like Figure 3 As shown in , the first heat dissipation layer 200 ′ may have a first exposed surface 200 e exposed toward the outside of the semiconductor package 2 a (eg, exposed downward). Figure 3 In the embodiment shown in , since the first heat dissipation layer 200′ is disposed in the redistribution layer 100 and is exposed from the second surface 100b (e.g., the lower surface or bottom surface) of the redistribution layer 100, the first exposed surface 200e of the first heat dissipation layer 200′ may be the lower surface or bottom surface of the first heat dissipation layer 200′ that is located at a height substantially the same as or higher than the second surface 100b of the redistribution layer 100 in the vertical direction (e.g., the first direction Z).

[0091] like Figure 3As shown in FIG, at least one first groove G1 may be formed on the first exposed surface 200e of the first heat dissipation layer 200'. The first groove G1 may extend from the first exposed surface 200e of the first heat dissipation layer 200' toward the interior of the first heat dissipation layer 200' in a vertical direction (e.g., a first direction Z). In embodiments, a plurality of first grooves G1 may be present. The plurality of first grooves G1 may be arranged in a specific or predetermined pattern on the first exposed surface 200e of the first heat dissipation layer 200' in a horizontal direction (e.g., a second direction X and / or a third direction Y).

[0092] The first trench G1 may have various shapes in a cross section taken along a vertical direction (eg, a first direction Z). Figure 3 As shown in FIG, the first groove G1 may have a rectangular shape in a cross-section taken along a vertical direction (e.g., the first direction Z). However, example embodiments are not limited thereto. In some other embodiments, the vertical cross-section of the first groove G1 may also have a tapered, trapezoidal, semicircular, or the like shape, with its width decreasing in the vertical direction toward the interior of the first heat dissipation layer 200', but is not limited thereto. For example, the first groove G1 may be created on the first exposed surface 200e of the first heat dissipation layer 200' by a process such as etching, stamping, or laser cutting, but is not limited thereto. Furthermore, the first groove G1 may extend inward from the first exposed surface 200e of the first heat dissipation layer 200' to any suitable depth, without particular limitation.

[0093] Due to the first trench G1, the first exposed surface 200e of the first heat dissipation layer 200' can have an increased area. Therefore, the first heat dissipation layer 200' can have an increased heat dissipation area. Therefore, the semiconductor package 2a can have further improved heat dissipation performance.

[0094] Additionally or alternatively, such as Figure 3 As shown in , the second heat dissipation layer 300 ′ may have a second exposed surface 300 e exposed toward the outside of the semiconductor package 2 a (eg, exposed upward). Figure 3 In the embodiment, since the second heat dissipation layer 300' is disposed inside the mold layer 500' and is exposed from the upper surface or top surface of the mold layer 500', the second exposed surface 300e of the second heat dissipation layer 300' may be an upper surface or top surface of the second heat dissipation layer 300' that is located at a height substantially the same as or higher than the upper surface of the mold layer 500' in the vertical direction (e.g., the first direction Z).

[0095] like Figure 3As shown in FIG, at least one second groove G2 may be formed on the second exposed surface 300e of the second heat dissipation layer 300'. The second groove G2 may extend from the second exposed surface 300e of the second heat dissipation layer 300' toward the interior of the second heat dissipation layer 300' in a vertical direction (e.g., the first direction Z). In an embodiment, a plurality of second grooves G2 may be provided. The plurality of second grooves G2 may be arranged in a specific or predetermined pattern on the second exposed surface 300e of the second heat dissipation layer 300' in a horizontal direction (e.g., the second direction X and / or the third direction Y).

[0096] The second trench G2 may have various shapes in a cross section taken along a vertical direction (eg, a first direction Z). Figure 3 As shown in FIG, the second trench G2 may have a rectangular shape in a cross-section taken along a vertical direction (e.g., the first direction Z). However, example embodiments are not limited thereto. In some other embodiments, the second trench G2 may have a vertical cross-section having a shape such as an inverted cone, an inverted trapezoid, an inverted semicircle, or the like, with its width decreasing in the vertical direction toward the interior of the second heat dissipation layer 300', but is not limited thereto. For example, the second trench G2 may be formed on the second exposed surface 300e of the second heat dissipation layer 300' by performing a process such as etching, stamping, or laser cutting on the second exposed surface 300e of the second heat dissipation layer 300', but is not limited thereto. Furthermore, the second trench G2 may extend inward from the second exposed surface 300e of the second heat dissipation layer 300' to any suitable depth, without particular limitation.

[0097] Due to the second trench G2, the second exposed surface 300e of the second heat dissipation layer 300' can have an increased area. Therefore, the second heat dissipation layer 300' can have an increased heat dissipation area. Therefore, the semiconductor package 2a can have further improved heat dissipation performance.

[0098] Although not shown, Figure 3 The first heat dissipation layer 200' having grooves on the exposed surface shown in FIG can also be applied to the reference Figure 1 The semiconductor package 1 (specifically, the first heat dissipation layer 200 of the semiconductor package 1 ) is described.

[0099] Figure 4 is a schematic cross-sectional view illustrating a semiconductor package according to some embodiments.

[0100] According to an embodiment of the present disclosure, in addition to the first heat dissipation layer 200 ″ including the first portion 210 in the redistribution layer 100 and the second portion 220 below the redistribution layer 100, Figure 4 The semiconductor package 2b shown in FIG. Figure 2Therefore, the following description will focus on the embodiment of the reference Figure 2 The differences between the described embodiments.

[0101] Reference Figure 4 The semiconductor package 2b according to an embodiment of the present disclosure may include a redistribution layer 100, a first heat dissipation layer 200" penetrating the redistribution layer 100, a semiconductor die 400 on the redistribution layer 100 and the first heat dissipation layer 200", a mold layer 500' surrounding the semiconductor die 400 on the redistribution layer 100, and a second heat dissipation layer 300 between the semiconductor die 400 and the mold layer 500' and covering the semiconductor die 400.

[0102] Reference Figure 4 The first heat dissipation layer 200" may include a first portion 210 in the redistribution layer 100 and a second portion 220 extending to the second surface 100b (eg, lower surface or bottom surface) of the redistribution layer 100. For ease of description and illustration, Figure 4 An imaginary dividing line between the first portion 210 and the second portion 220 of the first heat dissipation layer 200 ″ is shown in dashed lines. However, it should be understood that the first portion 210 and the second portion 220 of the first heat dissipation layer 200 ″ may be continuous without an interface therebetween.

[0103] like Figure 4 As shown in , the first portion 210 of the first heat dissipation layer 200" may penetrate the redistribution layer 100. The first portion 210 of the first heat dissipation layer 200" may be exposed at the first surface 100a (e.g., the upper surface or the top surface) of the redistribution layer 100. In an embodiment, the surface (e.g., the upper surface or the top surface) of the first portion 210 of the first heat dissipation layer 200" exposed at the first surface 100a of the redistribution layer 100 may be substantially coplanar with the first surface 100a of the redistribution layer 100. In an embodiment, the semiconductor die 400 may be disposed on the first portion 210 of the first heat dissipation layer 200" and the redistribution layer 100. For example, the semiconductor die 400 may be disposed on the upper surface of the first portion 210 of the first heat dissipation layer 200" and the first surface 100a of the redistribution layer 100. In addition to these features or aspects, the first portion 210 of the first heat dissipation layer 200" may have the same characteristics as those of the reference numerals. Figure 2The configuration of the first heat dissipation layer 200 described above is substantially the same as or similar to that described above. For example, the first portion 210 of the first heat dissipation layer 200 ″ may be surrounded by the redistribution layer 100 in the horizontal direction (e.g., the second direction X and / or the third direction Y) and may not overlap with the redistribution layer 100 in the vertical direction (e.g., the first direction Z). For example, in the vertical direction (e.g., the first direction Z), the first portion 210 of the first heat dissipation layer 200 ″ may have substantially the same size (e.g., thickness) as the size (e.g., thickness) of the redistribution layer 100.

[0104] like Figure 4 As shown in , the second portion 220 of the first heat dissipation layer 200" may extend downward from the second surface 100b of the redistribution layer 100 in the first direction Z. For example, the second portion 220 of the first heat dissipation layer 200" may extend from the first portion 210 of the first heat dissipation layer 200" in the vertical direction (e.g., the first direction Z) to be positioned at a height lower than the second surface 100b of the redistribution layer 100 in the vertical direction (e.g., the first direction Z). In addition, the second portion 220 may extend in the horizontal direction (e.g., the second direction X and / or the third direction Y) so as to partially position itself under a portion of the redistribution layer 100 and cover the portion of the redistribution layer 100. In an embodiment, on the second surface 100b of the redistribution layer 100, the second portion 220 of the first heat dissipation layer 200" may be spaced apart from and electrically insulated and / or isolated from the connection terminal 600. In an embodiment, on the second surface 100 b of the redistribution layer 100 , the connection terminal 600 may be disposed around the second portion 220 of the first heat dissipation layer 200 ″ to partially or completely surround the second portion 220 of the first heat dissipation layer 200 ″. In an embodiment, in a vertical direction (e.g., a first direction Z), the second portion 220 of the first heat dissipation layer 200 ″ may have a size (e.g., thickness) smaller than a size (e.g., thickness) of the connection terminal 600 .

[0105] In the semiconductor package 2 b, the second portion 220 of the first heat dissipation layer 200 ″ may extend onto the second surface 100 b of the redistribution layer 100 and thus may have an expanded planar area. In this case, since the first exposed surface 200 e of the first heat dissipation layer 200 ″, which is exposed toward the outside of the semiconductor package 2 b in the vertical direction (e.g., the first direction Z), is provided by the second portion 220 whose planar area is expanded, the first heat dissipation layer 200 ″ may have an increased heat dissipation area. Therefore, the semiconductor package 2 b may have further improved heat dissipation performance.

[0106] Furthermore, since the second portion 220 of the first heat dissipation layer 200″ may have a size (e.g., thickness) smaller than that of the connection terminal 600 (e.g., thickness), the second portion 220 of the first heat dissipation layer 200″ may not occupy additional arrangement space and thus may not result in an increase in the size (e.g., thickness) of the semiconductor package 2b. Therefore, the semiconductor package 2b may have a reduced size (e.g., thickness) while having further improved heat dissipation performance.

[0107] Although not shown, Figure 4 The first heat dissipation layer 200 including the first portion 210 and the second portion 220 shown in FIG. 2 can also be applied to the reference Figure 1 The semiconductor package 1 (specifically, the first heat dissipation layer 200 of the semiconductor package 1 ) is described.

[0108] Figure 5 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0109] According to an embodiment of the present disclosure, in addition to at least one of the first heat dissipation layer 200_1 and the second heat dissipation layer 300_1 having at least one groove formed on an exposed surface thereof, Figure 5 The semiconductor package 2c shown in FIG. Figure 4 Therefore, the following description will focus on the embodiment of the reference Figure 4 The differences between the described embodiments.

[0110] The semiconductor package 2c according to an embodiment of the present disclosure may include a redistribution layer 100, a first heat dissipation layer 200_1 penetrating the redistribution layer 100 and extending below the redistribution layer 100, a semiconductor die 400 on the redistribution layer 100 and the first heat dissipation layer 200_1, a mold layer 500' surrounding the semiconductor die 400 on the redistribution layer 100, and a second heat dissipation layer 300_1 between the semiconductor die 400 and the mold layer 500' and covering the semiconductor die 400.

[0111] like Figure 5 As shown in FIG, the first heat dissipation layer 200_1 and the first portion 210_1 and the second portion 220_1 may have the same Figure 4 The first heat dissipation layer 200 ″ and the first portion 210 and the second portion 220 are similarly constructed.

[0112] The first heat dissipation layer 200_1 may further include at least one first trench G1_1 on a first exposed surface 220e_1 provided by its second portion 220_1 and exposed toward the outside of the semiconductor package 2c (e.g., exposed downward). The first trench G1_1 may extend from the first exposed surface 220e_1 toward the interior of the first heat dissipation layer 200_1 in a vertical direction (e.g., a first direction Z). For example, in a region where the first portion 210_1 and the second portion 220_1 of the first heat dissipation layer 200_1 overlap each other, the first trench G1_1 may penetrate the second portion 220_1 in a vertical direction (e.g., a first direction Z) and extend into the first portion 210_1. Furthermore, although not shown, in a region where the second portion 220_1 of the first heat dissipation layer 200_1 overlaps the redistribution layer 100, the first trench G1_1 may extend from the first exposed surface 220e_1 toward the interior of the second portion 220_1. In addition to these features or aspects, the first trench G1_1 may have the same characteristics as those described in reference to FIG. Figure 3 The configuration of the first trench G1 described above is substantially the same or similar, and therefore, redundant description thereof is omitted here.

[0113] Due to the first trench G1_1, the first exposed surface 220e_1 of the first heat dissipation layer 200_1 can have an increased area. Therefore, the first heat dissipation layer 200_1 can have an increased heat dissipation area. Therefore, the semiconductor package 2c can have further improved heat dissipation performance.

[0114] Additionally or alternatively, such as Figure 5 As shown in FIG, the second heat dissipation layer 300_1 may have a second exposed surface 300e_1 exposed toward the outside of the semiconductor package 2c (e.g., exposed upward), and at least one second trench G2_1 may be formed on the second exposed surface 300e_1 of the second heat dissipation layer 300_1. The second heat dissipation layer 300_1 and its second exposed surface 300e_1, as well as the second trench G2_1 formed on the second exposed surface 300e_1, may have the same Figure 3 The described second heat dissipation layer 300 ′ and the second exposed surface 300 e thereof, and the second trench G2 formed on the second exposed surface 300 e are substantially the same or similar, and therefore, redundant descriptions thereof are omitted herein.

[0115] Due to the second trench G2_1, the second exposed surface 300e_1 of the second heat dissipation layer 300_1 can have an increased area. Therefore, the second heat dissipation layer 300_1 can have an increased heat dissipation area. Therefore, the semiconductor package 2c can have further improved heat dissipation performance.

[0116] Although not shown, Figure 5The first heat dissipation layer 200_1 having grooves on the exposed surface shown in FIG can also be applied to the reference Figure 1 The semiconductor package 1 (specifically, the first heat dissipation layer 200 of the semiconductor package 1 ) is described.

[0117] Figure 6 is a cross-sectional view schematically illustrating a semiconductor package according to some embodiments.

[0118] According to an embodiment of the present disclosure, in addition to the first heat dissipation layer 200_2 extending beyond the semiconductor die 400 in the horizontal direction, Figure 6 The semiconductor package 3 shown in FIG. Figure 2 Therefore, the following description will focus on the embodiment with reference to Figure 2 The differences between the described embodiments.

[0119] Reference Figure 6 The semiconductor package 3 according to an embodiment of the present disclosure may include a redistribution layer 100, a first heat dissipation layer 200_2 in the redistribution layer 100, a semiconductor die 400 on the redistribution layer 100 and the first heat dissipation layer 200_2, a mold layer 500' surrounding the semiconductor die 400 on the redistribution layer 100, and a second heat dissipation layer 300 between the semiconductor die 400 and the mold layer 500' and covering the semiconductor die 400.

[0120] like Figure 6 As shown in FIG, the first heat dissipation layer 200_2 extends beyond the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y). For example, the first heat dissipation layer 200_2 may extend beyond a portion (e.g., the second direction X and / or the third direction Y) of the third surface 400s of the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y). Figure 6 The first portion 400s1 of the third surface 400s of the semiconductor die 400 is formed so that the portion of the third surface 400s of the semiconductor die 400 can be positioned on the first heat dissipation layer 200_2, and another portion of the third surface 400s of the semiconductor die 400 different from the portion (or the remaining portion except the portion) (for example, Figure 6 The second portion 400 s 2 ) may be positioned on the redistribution layer 100 .

[0121] In such an embodiment, for the semiconductor die 400, the die pad 420 can be disposed on the second surface 400b of the semiconductor die 400 relative to the second portion 400s2 of the third surface 400s of the semiconductor die 400, and overlap with the redistribution layer 100 in a vertical direction (e.g., the first direction Z) to be electrically connected to the conductive path CP of the redistribution layer 100.

[0122] In such an embodiment, a portion of the second heat dissipation layer 300 between the mold layer 500 ′ and the first portion 400s1 of the third surface 400s of the semiconductor die 400 may contact (eg, directly contact) the first heat dissipation layer 200_2 (eg, in a vertical direction (eg, first direction Z)).

[0123] In an embodiment, the first heat dissipation layer 200_2 may extend beyond the first portion 400s1 of the third surface 400s of the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y), but may not extend beyond the side surface 300s of the second heat dissipation layer 300. In this case, the second heat dissipation layer 300 may overlap the first heat dissipation layer 200_2 and the redistribution layer 100 in the vertical direction (e.g., the first direction Z) between the mold layer 500′ and the first portion 400s1 of the third surface 400s of the semiconductor die 400.

[0124] In an embodiment, the first heat dissipation layer 200_2 may extend horizontally (e.g., the second direction X and / or the third direction Y) beyond the first portion 400s1 of the third surface 400s of the semiconductor die 400, and further extend beyond a portion of the side surface 300s of the second heat dissipation layer 300 adjacent to or opposite to the first portion 400s1. In this case, the first heat dissipation layer 200_2 may overlap the semiconductor die 400, the second heat dissipation layer 300, and the mold layer 500' in the vertical direction (e.g., the first direction Z). In this case, the portion of the mold layer 500' adjacent to or opposite to the first portion 400s1 of the third surface 400s of the semiconductor die 400 may be located on both the first heat dissipation layer 200_2 and the redistribution layer 100 in the vertical direction (e.g., the first direction Z).

[0125] In an embodiment, the first heat dissipation layer 200_2 and the second heat dissipation layer 300 may each include at least one of the aforementioned metal materials having high thermal conductivity. In an embodiment, the first heat dissipation layer 200_2 and the second heat dissipation layer 300 may include the same or different materials. When the first heat dissipation layer 200_2 and the second heat dissipation layer 300 include the same material, the interface between the first heat dissipation layer 200_2 and the second heat dissipation layer 300, which are in contact (e.g., direct contact), may not be distinct. For example, the first heat dissipation layer 200_2 and the second heat dissipation layer 300 may be integrated at the contact point. For example, the first heat dissipation layer 200_2 and the second heat dissipation layer 300 may be formed together as a single unitary member that fills the space surrounding the semiconductor die 400 and exposes only the portion of the second surface 400 b (e.g., the active surface) of the semiconductor die 400 where the die pad 420 is located (e.g., only the die pad 420 of the semiconductor die 400 is exposed).

[0126] In the semiconductor package 3 described above, the first heat dissipation layer 200_2 can extend beyond the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y). Therefore, the first heat dissipation layer 200_2 can easily have an increased planar area, and thus, an increased heat dissipation area. As a result, the semiconductor package 3 can further improve heat dissipation.

[0127] Furthermore, because the first heat dissipation layer 200_2 can extend beyond the semiconductor die 400 in the horizontal direction (e.g., the second direction X and / or the third direction Y), even when the die pad 420 is relatively concentrated on a specific portion of the second surface 400 b (e.g., the active surface) of the semiconductor die 400, the first heat dissipation layer 200_2 can still have a sufficient planar surface area or heat dissipation area. As a result, the die pad 420 of the semiconductor die 400 can be arranged in various configurations. Therefore, the semiconductor package 3 can also have improved heat dissipation while also offering increased design freedom.

[0128] Furthermore, since the first heat dissipation layer 200_2 and the second heat dissipation layer 300 can be in contact with each other (e.g., integrated with each other), a continuous and extended heat dissipation path can be formed around the semiconductor die 400, significantly improving heat dissipation efficiency. Consequently, the semiconductor package 3 can have further improved heat dissipation (e.g., while having a reduced size).

[0129] Although not shown, according to the arrangement of the die pad of the semiconductor die on the active surface of the semiconductor die, the reference Figure 6 The first heat dissipation layer 200_2 extending beyond the semiconductor die described above can be applied to the reference Figure 1 The first heat dissipation layer 200 described, or referring to Figure 6 The first heat dissipation layer 200_2 and the second heat dissipation layer 300 described as being in contact with each other at the side of the semiconductor die may be applied to the embodiment of the present invention with reference to FIG. Figures 2 to 5 The first heat dissipation layers 200, 200', 200", 200_1 and the second heat dissipation layers 300, 300', 300_1 are described.

[0130] In the foregoing, an example of a semiconductor package according to an embodiment of the present disclosure has been described with reference to the accompanying drawings. Hereinafter, an example of a method of manufacturing a semiconductor package according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0131] Figures 7 to 9 are cross-sectional views schematically illustrating stages of a method of manufacturing a semiconductor package according to some embodiments.

[0132] Reference Figure 7, a semiconductor die 400 may be prepared. As described above, the semiconductor die 400 may be an unpackaged die manufactured by a semiconductor process, and may be designed and manufactured to perform a predetermined or set function.

[0133] like Figure 7 As shown in , a semiconductor die 400 can be disposed on a carrier substrate SUB. In an embodiment, the carrier substrate SUB can be a rigid substrate for support, and there may be no particular limitation on the type. The semiconductor die 400 may have a first surface 400a (e.g., an inactive surface) and a second surface 400b (e.g., an active surface) opposite the first surface 400a. The semiconductor die 400 may include a die pad (not shown) disposed on the second surface 400b (e.g., an active surface). The semiconductor die 400 may be placed on the carrier substrate SUB with the second surface 400b facing the carrier substrate SUB and the first surface 400a facing away from the carrier substrate SUB. In addition, the semiconductor die 400 may be attached and fixed to the carrier substrate SUB using an adhesive layer (not shown) such as a die attach film (DAF), a pressure-sensitive adhesive film, etc., but is not limited thereto.

[0134] Next, refer to Figure 8 A second heat dissipation layer 300 may be formed on the carrier substrate SUB to cover the semiconductor die 400. The second heat dissipation layer 300 may cover the inactive surface (e.g., the first surface 400a) and side surfaces (e.g., the third surface 400s) of the semiconductor die 400. In embodiments, the second heat dissipation layer 300 may be formed by depositing, spraying, sputtering, or printing a material having high thermal conductivity. For example, the second heat dissipation layer 300 may be formed using a metal material. For example, the metal material may include at least one of copper (Cu), iron (Fe), cobalt (Co), nickel (Ni), and alloys thereof.

[0135] Then, a mold layer 500' can be formed on the carrier substrate SUB to surround the second heat dissipation layer 300 and the semiconductor die 400 covered by the second heat dissipation layer 300. The mold layer 500' can be in contact with the side surface of the second heat dissipation layer 300 and can expose the upper surface or top surface of the second heat dissipation layer 300. The mold layer 500' can be formed to have a frame structure and can be used to increase the rigidity of the semiconductor package. In an embodiment, the mold layer 500' can be formed by depositing or spin-coating an epoxy molding compound, curing the epoxy molding compound, and then planarizing the epoxy molding compound to expose the second heat dissipation layer 300, but is not limited thereto.

[0136] In some other embodiments (e.g., Figure 1 Refer to it together Figure 8 ), the step of forming the second heat dissipation layer 300 can be omitted. In this way, a reference Figure 1 A molding layer 500 is depicted covering the semiconductor die 400. For example, the molding layer 500 may be formed using an epoxy molding compound having high thermal conductivity.

[0137] In other embodiments, Figure 3 Refer to it together Figure 8 After forming the mold layer 500', a process such as etching, stamping, or laser cutting may be performed on the exposed surface of the second heat dissipation layer 300 to create one or more grooves. Figure 3 The second heat dissipation layer 300 ′ is depicted as having second grooves G2 formed on the exposed surface thereof.

[0138] Afterwards, refer to Figure 9 , you can pass from Figure 8 The resulting structure obtained by removing the carrier substrate SUB is flipped over so that the second surface 400 b (eg, active surface) of the semiconductor die 400 faces upward, thereby exposing the die pad 420 of the semiconductor die 400 .

[0139] Subsequently, a redistribution layer 100 having an opening OP may be formed on the semiconductor die 400 and the mold layer 500′. The redistribution layer 100 having the opening OP may cover the portion of the second surface 400b (e.g., the active surface) of the semiconductor die 400 where the die pad 420 is provided, and may not cover the portion of the second surface 400b (e.g., the active surface) of the semiconductor die 400 where the die pad 420 is not provided. The redistribution layer 100 may include an insulating layer BL and a conductive path CP extending within the insulating layer BL. In an embodiment, the conductive path CP may be composed of one or more wirings and one or more vias. Both ends of the conductive path CP may be exposed from opposing surfaces of the redistribution layer 100, respectively. At least a portion of the conductive path CP may be connected to the die pad 420 of the semiconductor die 400.

[0140] In an embodiment, the redistribution layer 100 can be formed by a continuous process such as deposition, patterning and / or planarization. For example, the first level of the redistribution layer 100 is created by depositing a portion of the insulating layer BL on the semiconductor die 400 and the mold layer 500', patterning the portion of the insulating layer BL to form a via hole, depositing a conductive material and planarizing it to fill the via hole, and then depositing additional conductive material and patterning the additional conductive material to form wiring connected to the via hole. If necessary, the remaining levels of the redistribution layer 100 can be formed by repeating some or all of the aforementioned processes. Thus, the redistribution layer 100 including the conductive path CP and the insulating layer BL as described above can be manufactured. However, the embodiment is not limited thereto. In some other embodiments, the vias and wiring at the same level of the redistribution layer 100 can be formed in an order opposite to the order described herein, or can also be formed simultaneously in the same process. In addition, the process for forming the redistribution layer 100 may not be limited to the above process, but can be appropriately selected and adjusted according to the embodiment.

[0141] Then, an opening OP may be formed in the redistribution layer 100 formed as described above. The opening OP may be formed to expose at least a portion of the second surface 400b of the semiconductor die 400 where the die pad 420 is not provided. For example, the opening OP may be formed by performing a process such as etching or laser cutting on the redistribution layer 100. As a result, the redistribution layer 100 having the opening OP may be formed.

[0142] exist Figure 9 In the embodiment shown in FIG, the die pad 420 may be provided along the peripheral portion of the second surface 400b of the semiconductor die 400. Therefore, in a plan view (not shown), the portion of the second surface 400b of the semiconductor die 400 where the die pad 420 is not provided may be surrounded by the die pad 420. Therefore, in a plan view (not shown), the opening OP may be formed in the inner region defined by the die pad 420. However, example embodiments are not limited thereto. In some other embodiments (e.g., Figure 6 Refer to it together Figure 9 ), the die pad 420 may also be relatively concentratedly disposed in a specific region of the second surface 400b of the semiconductor die 400. In this case, the opening OP may be formed to expose a portion of the second surface 400b of the semiconductor die 400 where the die pad 420 is not disposed, and to expose a portion of the second heat dissipation layer 300 (optionally, the second heat dissipation layer 300 and the mold layer 500′) that is not adjacent to the die pad 420.

[0143] Next, the first heat dissipation layer 200 may be formed. For example, the first heat dissipation layer 200 may be formed by depositing, spraying, sputtering, or printing a material having high thermal conductivity to cover (e.g., fill) the opening OP of the redistribution layer 100. For example, the first heat dissipation layer 200 may be formed using a metal material. For example, the metal material may include at least one of metals such as copper (Cu), iron (Fe), cobalt (Co), nickel (Ni), and alloys thereof.

[0144] When the opening OP formed in the previous process exposes only a portion of the second surface 400 b of the semiconductor die 400, the first heat dissipation layer 200 may be formed entirely on the portion of the second surface 400 b of the semiconductor die 400. When the opening OP formed in the previous process exposes not only a portion of the second surface 400 b of the semiconductor die 400 but also a portion of the second heat dissipation layer 300 and / or the mold layer 500 ′ adjacent to the portion of the second surface 400 b of the semiconductor die 400, the first heat dissipation layer 200 may be formed on the portion of the semiconductor die 400 and the portion of the second heat dissipation layer 300 (alternatively, the second heat dissipation layer 300 and the mold layer 500 ′), wherein the portion of the first heat dissipation layer 200 on the second heat dissipation layer 300 may be in contact with (e.g., in direct contact with) the second heat dissipation layer 300.

[0145] In some other embodiments (e.g., Figure 4 Refer to it together Figure 9 ), a first heat dissipation layer 200 ″ may be formed in the opening OP and on a portion of the redistribution layer 100 adjacent to the opening OP, such that the first heat dissipation layer 200 ″ may include a first portion 210 in the redistribution layer 100 and a second portion 220 extending onto the redistribution layer 100. For example, in a plan view (not shown), the second portion 220 of the first heat dissipation layer 200 ″ may be positioned between the conductive paths CP of the redistribution layer 100 and spaced apart from the conductive paths CP of the redistribution layer 100.

[0146] In still other embodiments (e.g., Figure 3 Refer to it together Figure 9 ), after forming the first heat dissipation layer 200, a process such as etching, stamping, laser cutting, etc. may be performed on the exposed surface of the first heat dissipation layer 200 to form a groove on the exposed surface of the first heat dissipation layer 200. Figure 3 The first heat dissipation layer 200 ′ is described as having the first groove G1 formed on the exposed surface thereof.

[0147] Afterwards, return to the reference Figures 1 to 6, a connection terminal 600 can be formed on the redistribution layer 100 of the structure obtained through the above process. For example, the connection terminal 600 can be formed on the exposed end of the conductive path CP of the redistribution layer 100. In an embodiment, the connection terminal 600 can be a conductive member such as a conductive bump or a solder ball. In an embodiment, the connection terminal 600 can be fixed to the end of the conductive path CP in the redistribution layer 100 using a surface attachment process or a ball planting process, but other methods can also be used.

[0148] By using the above process steps or their appropriate combination, reference Figure 1 The semiconductor package 1 described in Figure 2 The semiconductor package 2 described in reference Figure 3 The semiconductor package 2a described Figure 4 The semiconductor package 2b described, referring to Figure 5 The semiconductor package 2c described or referring to Figure 6 The semiconductor package 3 is described. However, the embodiment is not limited thereto. Other semiconductor packages having any one or more of the above features or aspects according to the embodiments of the present disclosure may be manufactured by other suitable combinations of the above process steps.

[0149] According to an exemplary embodiment of the present disclosure, a semiconductor package may include a first heat dissipation layer disposed on an active surface of a semiconductor die. This allows heat generated by a functional circuit layer of the semiconductor die to be efficiently dissipated via the first heat dissipation layer. Consequently, the heat dissipation performance of the semiconductor package can be improved, and thermal failure of the semiconductor die can be prevented or reduced. Consequently, the reliability of the semiconductor package can be improved.

[0150] According to example embodiments of the present disclosure, a semiconductor package may include a first heat dissipation layer and a redistribution layer at the same level, and each of the first heat dissipation layer and the redistribution layer may be formed with a relatively small size (e.g., thickness). Therefore, compared to conventional semiconductor packages, the semiconductor package may have a reduced size (e.g., thickness) while having improved heat dissipation.

[0151] According to example embodiments of the present disclosure, a semiconductor package can include a second heat dissipation layer covering a semiconductor die and a mold layer surrounding both the semiconductor die and the second heat dissipation layer as a frame. The second heat dissipation layer can be formed with a relatively small size (e.g., thickness), while the mold layer can be formed of conventional mold plastic rather than a high-thermal-conductivity mold plastic and thus can also be formed with a relatively small size (e.g., thickness). Consequently, compared to conventional semiconductor packages, the semiconductor package can have a further reduced size (e.g., thickness) while having improved heat dissipation.

[0152] According to example embodiments of the present disclosure, a semiconductor package may include a (e.g., integral) heat dissipation member (e.g., including a first heat dissipation layer covering a portion of the active surface, the passive surface, and the side surface of a semiconductor die) (e.g., including a first heat dissipation layer covering a portion of the active surface, and a second heat dissipation layer covering the passive surface and the side surface and in contact with the first heat dissipation layer). Consequently, a coherent and extended heat dissipation path may be formed around the semiconductor die, significantly improving heat dissipation efficiency. Consequently, the semiconductor package may have further reduced size (e.g., thickness) while still achieving further improved heat dissipation.

[0153] Although specific details of some example embodiments are described in this specification, these specific details should not be construed as limitations on the scope of any claimed subject matter, but rather as descriptions of features specific to specific embodiments. Some features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. On the other hand, different features described in this specification in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable subcombination.

[0154] While aspects of the example embodiments have been particularly shown and described, it will be understood by those skilled in the art that various changes and substitutions in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: a redistribution layer having a first surface and a second surface opposite to the first surface in a first direction; a first heat dissipation layer located within the redistribution layer and exposed at the first surface and the second surface of the redistribution layer; a semiconductor die located on the redistribution layer and the first heat dissipation layer, and comprising a die body and a die pad located between the die body and the redistribution layer, the semiconductor die being electrically connected to the redistribution layer through the die pad; a molding layer disposed on the redistribution layer and surrounding the semiconductor die; as well as The connection terminal is disposed under the redistribution layer and electrically connected to the redistribution layer.

2. The semiconductor package according to claim 1, in, The semiconductor die has an active surface, the die pad is disposed on the active surface, and The redistribution layer covers a portion of the active surface where the die pad is provided, and the first heat dissipation layer covers a portion of the active surface where the die pad is not provided.

3. The semiconductor package according to claim 1, wherein When viewed along the first direction, the entire first heat dissipation layer overlaps the semiconductor die.

4. The semiconductor package according to claim 3, wherein A side surface of the semiconductor die is located on the redistribution layer in the first direction.

5. The semiconductor package according to claim 1, wherein A portion of the side surface of the semiconductor die is located on the redistribution layer in the first direction, and Another portion of the side surface of the semiconductor die is located on the first heat dissipation layer in the first direction. The semiconductor package according to claim 1 , wherein: The first heat dissipation layer has a first portion located within the redistribution layer and a second portion extending from the first portion to the second surface of the redistribution layer, and The second portion of the first heat dissipation layer is spaced apart from the connection terminal.

7. The semiconductor package according to claim 1, in, The semiconductor package further includes a second heat dissipation layer located between the semiconductor die and the molding layer and extending above the semiconductor die to cover the semiconductor die, and Wherein, in the first direction, the molding layer does not overlap with the second heat dissipation layer.

8. The semiconductor package according to claim 7, in, The entire first heat dissipation layer overlaps the semiconductor die in the first direction, and The second heat dissipation layer is located on the redistribution layer between the semiconductor die and the molding layer.

9. The semiconductor package according to claim 7, in, The first heat dissipation layer has a portion extending beyond a side surface of the semiconductor die, and A portion of the second heat dissipation layer located between the semiconductor die and the molding layer is on the redistribution layer, and another portion of the second heat dissipation layer located between the semiconductor die and the molding layer is on the portion of the first heat dissipation layer.

10. The semiconductor package according to claim 7, in, The first heat dissipation layer includes a first exposed surface exposed toward the outside of the semiconductor package in the first direction, wherein the second heat dissipation layer includes a second exposed surface exposed toward the outside of the semiconductor package in the first direction, and At least one of the first heat dissipation layer and the second heat dissipation layer includes at least one groove formed on a corresponding exposed surface of the first exposed surface and the second exposed surface.

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