Energy feedback type electronic load circuit and control method thereof

Abstract

The invention provides an energy feedback type electronic load circuit and a control method thereof, and the circuit comprises a pre-stage circuit which is composed of N phases of Boost converters in staggered parallel connection, each phase of Boost converter comprises an inductance element, an IGBT switch tube and a diode, and the pre-stage circuit is used for boosting an input DC voltage to a preset bus voltage; the post-stage circuit is composed of an LCL type NPC grid-connected inverter, comprises an NPC three-level inverter topology and an LCL filter, and is used for inverting the boosted direct-current voltage into alternating current and feeding the alternating current back to a power grid; the signal acquisition module is configured to acquire the input voltage, the inductive current of each phase and the bus voltage of the pre-stage circuit, and the inverter side current, the filter capacitor voltage, the network side current and the network side voltage of the post-stage circuit; the control module comprises a pre-stage continuous control set model prediction unit which is connected to a pre-stage circuit and is used for optimizing the switch duty ratio of the Boost converter in real time; and the post-stage linear active disturbance rejection and sliding mode fusion control unit is connected to a post-stage circuit and is used for generating a switch modulation signal of the NPC inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of energy-feedback electronic loads, and in particular relates to an energy-feedback electronic load circuit and a control method thereof. Background Art

[0002] Traditional energy-consuming electronic loads simulate loads by dissipating energy through resistors. These loads suffer from bulk, excessive heat generation, insufficient accuracy, and slow response speeds. These factors make them particularly difficult to meet the high-dynamic simulation requirements for large, transient loads required for high-altitude testing of aircraft engines. While energy-feedback electronic loads improve energy consumption through energy feedback technology, their application in high-power scenarios still faces significant bottlenecks: existing topologies are often based on single-transistor or simple parallel designs, leading to current stress concentration, large input ripple, and poor power quality on the grid-connected inverter side, which can easily cause grid harmonic pollution and voltage fluctuations.

[0003] For the transient power rapid switching scenarios that need to be simulated in high-altitude platform testing, the dynamic performance of existing energy-fed electronic loads is insufficient, and the limitations of control strategies are particularly prominent. Traditional control methods (such as PI and PR control) rely on linearized models, which have a delayed response to sudden load changes or grid disturbances, weak anti-interference capabilities, and difficulty in balancing dynamic response speed and system stability. In addition, existing solutions lack the coordinated design of front-stage power conversion and back-stage energy feedback, resulting in a disconnect between the topology and control strategy, making it impossible to effectively suppress grid-connected transient shocks, and affecting system reliability.

[0004] The lack of synergy between topology innovation and control optimization in current technologies is a key constraint on the performance of energy-fed electronic loads. Most solutions rely on complex hardware compensation or redundant circuits, which, while partially alleviating the problem, increase system cost and design complexity. Therefore, an integrated solution that balances efficient power processing, fast dynamic response, and high grid connection quality is urgently needed. By deeply integrating structural innovation with advanced control strategies, this solution can overcome the technical bottlenecks of high-power energy-fed electronic loads. Summary of the Invention

[0005] In response to the defects and shortcomings of existing technologies, the present invention provides a feed-back electronic load circuit and control method thereof. By deeply integrating topological innovation with control strategies, the present invention solves the problems of slow dynamic response, large grid connection impact, and poor harmonic suppression capability in high-power scenarios. The core innovation of the solution lies in:

[0006] Front-end topology and control innovation: The use of multi-phase interleaved parallel boost converters, combined with a phase-by-phase discrete prediction model and dynamic cost function optimization, achieves fast and balanced current tracking for each phase, significantly reducing input ripple and device stress.

[0007] Innovation in downstream topology and control: Design of an LCL-type NPC three-level inverter, using sliding-mode active disturbance rejection fusion control to compensate for disturbances in real time, combined with an SVPWM modulation strategy with zero-sequence component superposition to suppress grid-connected harmonics and neutral-point potential fluctuations;

[0008] Collaborative control mechanism: Establish dynamic linkage logic between the front-stage current reference value and the back-stage disturbance observation, and optimize the global performance through the feedforward-feedback dual-channel collaborative optimization, taking into account the transient load simulation accuracy and grid-connected power quality.

[0009] This solution breaks through the limitations of the traditional separation of energy-feed load topology and control, and is particularly suitable for high-dynamic, high-power scenarios such as aircraft engine high-altitude test benches, providing an integrated solution for complex load simulation and efficient energy feedback.

[0010] The technical solution specifically adopted by the present invention to solve the technical problem is:

[0011] An energy-fed electronic load circuit, comprising:

[0012] The front-stage circuit consists of N-phase Boost converters connected in parallel. Each phase Boost converter includes an inductor, an IGBT switch tube, and a diode, which is used to boost the input DC voltage to a preset bus voltage.

[0013] The subsequent circuit consists of an LCL-type NPC grid-connected inverter, including an NPC three-level inverter topology and an LCL filter, which is used to invert the boosted DC voltage into AC power and feed it back to the grid;

[0014] A signal acquisition module is configured to collect the input voltage, each phase inductor current, and bus voltage of the front-stage circuit, as well as the inverter-side current, filter capacitor voltage, grid-side current, and grid-side voltage of the back-stage circuit;

[0015] Control module, including:

[0016] a front-stage continuous control set model prediction unit, connected to the front-stage circuit, for optimizing the switching duty cycle of the Boost converter in real time;

[0017] The post-stage linear active disturbance rejection + sliding mode fusion control unit is connected to the post-stage circuit and is used to generate a switching modulation signal for the NPC inverter.

[0018] Furthermore, the boost target value of the front-stage interleaved parallel Boost converter is 800V, and the parameters of the inductance of each phase are 1.5mH, the resistance is 0.1Ω, the bus capacitance is 0.1F, and the switching frequency is 20kHz.

[0019] Furthermore, the parameters of the post-stage LCL filter satisfy: the inverter side inductor L f =2mH, grid-side inductance Lg =0.4mH, filter capacitor C f =50μF, through asymmetric inductance distribution and capacitance optimization, the total harmonic distortion of the grid-connected current is achieved to be less than 1%.

[0020] Furthermore, the preceding continuous control set model prediction unit is configured to perform phase optimization, wherein the phase optimization generates a phase-staggered PWM signal, including:

[0021] Establish discrete dynamic equations for each phase inductor current independently;

[0022] The phase cost function is constructed by the sum of squares of the errors between the predicted current value of each phase and the reference value;

[0023] The duty cycle that minimizes the phase-splitting cost function is solved and output to the switch tube of the corresponding phase of the previous-stage Boost converter.

[0024] And, a control method for the energy-fed electronic load circuit described above, comprising:

[0025] Pre-stage control:

[0026] Based on the preceding continuous control set model prediction unit, the dynamic value of each phase inductor current is solved in real time through a discrete prediction model;

[0027] The duty cycle is optimized independently for each phase current error to generate a phase-staggered PWM signal to drive the switch tube;

[0028] Post-stage control:

[0029] The bus voltage disturbance is estimated and compensated in real time through the post-stage linear active disturbance rejection + sliding mode fusion control unit;

[0030] The inverter switching signal is generated by forcing current tracking on the sliding surface and combining it with SVPWM modulation;

[0031] Collaborative control: Current reference value I predicted by the previous model ref Dynamic adjustment is made based on the disturbance observation results of the subsequent stage, linking the strategies of the previous and subsequent stages to achieve dynamic load simulation and harmonic suppression.

[0032] Furthermore, in the pre-stage control, the discrete prediction model is constructed by the following steps:

[0033] Based on the state space averaging method, the continuous state equation of the interleaved parallel Boost converter is established;

[0034] The continuous model is discretized by first-order forward difference to obtain the dynamic equation of the inductor current of each phase;

[0035] Predict the inductor current value at the next moment based on the current input voltage, bus voltage and duty cycle;

[0036] The independently optimizing duty cycle for each phase current error includes:

[0037] Design a cost function for each phase inductor current independently and calculate the square of its error with the reference value;

[0038] By minimizing the total cost function, the optimal duty cycle of each phase is solved and multi-phase current balanced tracking is achieved.

[0039] Furthermore, in the latter stage control, the implementation of the linear expansion observer includes:

[0040] The first state variable of the observer is defined as the estimated value of the bus voltage, and the second state variable is defined as the estimated value of the bus voltage disturbance;

[0041] According to the deviation between the actual bus voltage value and the estimated bus voltage value, the state variables are dynamically updated:

[0042] The update rate of the first state variable is determined by the linear compensation term of the deviation and the second state variable;

[0043] The update rate of the second state variable is determined only by the linear compensation term of the deviation;

[0044] The estimated value of the bus voltage disturbance is feed-forwarded to the input of the sliding mode controller to improve the system's anti-disturbance capability.

[0045] Furthermore, the sliding mode surface is designed as an integral form of the inverter side current error:

[0046] The steady-state error is eliminated by introducing the integral term to enhance the tracking accuracy;

[0047] Combined with the saturation function to limit the sudden change amplitude of the control quantity to suppress system chattering;

[0048] By adjusting the convergence coefficient, the response speed and stability can be balanced.

[0049] Furthermore, in the SVPWM modulation, midpoint potential balancing is achieved through the following steps:

[0050] Calculate the zero-sequence component of the three-phase modulation signal of the NPC inverter;

[0051] The zero-sequence component is added to the original modulation signal to balance the upper and lower bus capacitor voltages;

[0052] A switching sequence is generated according to the superimposed modulation signal to ensure that the midpoint potential fluctuation is less than a preset threshold.

[0053] Furthermore, in the collaborative control, the current reference value I predicted by the previous model ref The logic of dynamic adjustment includes:

[0054] The disturbance estimation value based on the output of the subsequent LESO reflects the sudden change in load or the intensity of grid fluctuation;

[0055] Set the initial current reference value I ref0 The disturbance estimate is calculated by the feedforward gain coefficient K p Weighted superposition to generate dynamically adjusted reference value I ref (k);

[0056] Through the feedforward-feedback dual channel, real-time coordination of the front-stage and back-stage control strategies is achieved, balancing the dynamic response speed and system stability.

[0057] Compared with the prior art, the present invention and its preferred embodiments have at least the following beneficial effects:

[0058] Improved dynamic response capability: Through phase modeling and dynamic optimization control of the front-stage multi-phase interleaved Boost converter, rapid and balanced current tracking of each phase is achieved, significantly improving the response speed and tracking accuracy in load mutation scenarios;

[0059] Enhanced system immunity: Based on the fusion strategy of post-stage sliding mode control and linear active disturbance rejection, it observes and compensates for bus voltage disturbances in real time, effectively suppressing transient shocks caused by grid fluctuations and load switching;

[0060] Optimize grid-connected power quality: LCL filters are designed in conjunction with NPC three-level inverters, combined with a zero-sequence component superposition modulation strategy to reduce grid-connected current harmonic content and improve energy feedback stability.

[0061] Simplified hardware structure: Through the coordinated optimization of control strategies, the use of additional voltage-sharing circuits or redundant compensation modules is reduced, thus reducing system complexity and cost.

[0062] Expanded application scenarios: Adapt to the testing needs of high-power, high-dynamic aircraft engines, realize the integrated integration of transient load simulation and efficient energy feedback, and fill the technological gap in this field.

[0063] The above effects are derived from the deep integration of topology architecture and control logic, especially reflected in core innovative designs such as front-stage phase control, rear-stage anti-interference-tracking coordination and global strategy linkage. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0065] Figure 1 This is a circuit diagram of an energy-fed electronic load according to an embodiment of the present invention;

[0066] Figure 2 This is an overall control block diagram of the energy-fed electronic load according to an embodiment of the present invention;

[0067] Figure 3 This is a block diagram of the continuous control set model predictive control according to an embodiment of the present invention;

[0068] Figure 4 This is a block diagram of linear active disturbance rejection and sliding mode fusion control according to an embodiment of the present invention;

[0069] Figure 5 : This is an equivalent circuit diagram of an LCL filter according to an embodiment of the present invention;

[0070] Figure 6 1 is a six-phase inductor current waveform diagram according to an embodiment of the present invention;

[0071] Figure 7 This is a busbar capacitor voltage waveform diagram according to an embodiment of the present invention;

[0072] Figure 8 This is a three-phase grid-side current waveform diagram of an embodiment of the present invention;

[0073] Figure 9 This is an FFT spectrum analysis diagram of the grid-side current of phase A in an embodiment of the present invention;

[0074] Figure 10 This is an input power waveform diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0075] In order to make the features and advantages of the present invention more clearly understood, the following embodiments are given for detailed description:

[0076] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this application belongs.

[0077] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0078] The circuit diagram of the energy-feedback electronic load proposed in the embodiment of the present invention is as follows: Figure 1 As shown, it includes a front-stage six-phase interleaved parallel Boost converter and a rear-stage LCL-type NPC grid-connected inverter. The front-stage interleaved parallel Boost converter completes fast and accurate current tracking to achieve high response speed of the electronic load, and the rear-stage LCL-type NPC inverter completes the energy feedback function to achieve energy recycling.

[0079] The overall control block diagram of the system is as follows: Figure 2 As shown in the figure, continuous control set model prediction is applied in the front-stage converter, and PWM is used as the modulator; linear active disturbance rejection + sliding mode fusion control is adopted in the rear-stage inverter, and SVPWMM is used as the modulation method.

[0080] Specifically:

[0081] The system consists of two main circuit modules: a front-stage interleaved parallel Boost converter and a rear-stage LCL-type NPC grid-connected inverter. The front-stage interleaved parallel Boost converter performs fast and accurate current tracking, enabling high response speed of the electronic load, while the rear-stage LCL-type NPC inverter performs energy feedback and realizes energy recycling.

[0082] Also includes:

[0083] Signal acquisition module, sampling key system parameters;

[0084] The continuous control set model predictive control module accurately and quickly tracks the reference current of the previous converter;

[0085] The first-order linear active disturbance rejection + sliding mode fusion control module optimizes the grid-side current and bus voltage of the subsequent inverter.

[0086] In this embodiment, by cascading an interleaved parallel Boost converter with an LCL-type NPC grid-connected inverter, it is suitable for high-power applications and has the advantages of high precision, low heat generation, and the ability to promptly reflect load changes. In particular, in high-altitude platform testing of space shuttle engines, it can accurately and quickly simulate the rapid loading and unloading conditions of aircraft engines during flight operations.

[0087] In this embodiment, the front-stage interleaved parallel boost converter contains N inductors, N IGBTs, and N diodes. It is constructed by connecting N single-phase boost converters in parallel using interleaved parallel technology, where N is the number of phases in the interleaved parallel connection. This not only reduces the current stress in each phase of the converter, but also reduces heat generation in electronic components, thereby lowering losses and improving efficiency. Furthermore, the interleaved and superimposed inductor currents in each phase significantly reduces input current ripple. Compared to a single-transistor boost circuit, a single-transistor boost converter can handle smaller voltage and current levels, making it unsuitable for high-power applications. A multi-transistor interleaved parallel boost converter is a more suitable solution for high-power applications.

[0088] The front-stage interleaved parallel Boost converter controls the duty cycle of N switching devices to boost the input DC voltage to 800V bus capacitor voltage.

[0089] The post-stage LCL type NPC grid-connected inverter includes an NPC grid-connected inverter and an LCL filter.

[0090] Compared with two-level inverters, the LCL-type NPC grid-connected inverter has the following advantages:

[0091] (1) Low voltage stress and low switching power loss: The power device stress of the NPC grid-connected inverter is half of the bus voltage, and its voltage stress and switching power loss are relatively low;

[0092] (2) Small output voltage and current harmonics and low EMI: The output waveform of the NPC grid-connected inverter is three-level, which is closer to a sine wave. The total harmonic distortion (THD) of its output current is low, which helps to reduce the impact on the power grid and harmonic pollution;

[0093] (3) High efficiency and large capacity: Due to the reduced voltage stress and switching loss of switching devices, NPC grid-connected inverters have higher efficiency and can achieve larger capacity power conversion;

[0094] Therefore, it is feasible and has outstanding advantages to use NPC grid-connected inverter as the back-end topology of energy-feeding electronic load in high-power occasions.

[0095] The subsequent LCL-type NPC grid-connected inverter inverts the 800V bus capacitor voltage into a square wave voltage containing harmonics, and then filters out most of the harmonics through the LCL filter, converting it into a grid-side current in phase with the grid voltage to achieve energy feedback.

[0096] The LCL-type NPC grid-connected inverter converts the 800V bus capacitor voltage into a high-quality grid-side current with the same frequency and phase as the grid voltage, thus achieving energy feedback.

[0097] In this embodiment, the signal acquisition module samples the input voltage, inductor current and bus voltage in the front-stage circuit, and samples the inverter side current, filter capacitor voltage, grid side current and grid side voltage in the back-stage circuit.

[0098] In this embodiment, the continuous control set model predictive control module includes discrete prediction model establishment, cost function minimization and PWM modulator, wherein:

[0099] Discrete prediction model establishment: First, the KCL and KVL equations are formulated for the front-stage interleaved parallel boost converter. Then, the state-space averaging method is used to obtain the average model of the interleaved parallel boost converter. The average model is then subjected to first-order forward differencing. Finally, the average model is converted into a discrete prediction model containing the switch duty cycle function.

[0100] Cost function minimization: First, establish a cost function. The cost function is calculated by square the difference between the reference and predicted inductor currents at the next moment. Then, the partial derivative of the duty cycle in the cost function is taken and set equal to zero. This gives the required duty cycle for the interleaved parallel boost converter to switch on and off at the next moment.

[0101] PWM modulator: Since the previous stage circuit uses interleaved parallel technology, the PWM carrier needs to be phase-staggered with a phase shift angle of 2π / N, where N is the number of interleaved parallel phases. The duty cycle obtained in the cost function minimization step is then compared with the carrier to output the converter's switching signal.

[0102] In this embodiment, the first-order linear active disturbance rejection + sliding mode fusion control module controls the subsequent LCL-type NPC grid-connected inverter by combining linear active disturbance rejection as the voltage outer loop, sliding mode control as the current inner loop, and SVPWM as the switching modulation strategy.

[0103] The first-order linear active disturbance rejection + sliding mode fusion control module includes a linear active disturbance rejection module, a sliding mode control module, and an SVPWM module, among which:

[0104] Linear Active Disturbance Rejection Module: This module uses the bus voltage as input, estimates it through an internal observer, and uses compensation to eliminate disturbances from outside the system, enabling rapid response of the bus voltage to disturbances.

[0105] Sliding mode control module: By introducing a sliding surface, ignoring external disturbances and uncertain parameters, it forces the system to slide quickly on and along the sliding surface, thereby achieving stable control of the system;

[0106] SVPWM module: The modulation signal obtained by sliding mode control is modulated by horn wave, and the voltage balance of the two bus capacitors of the NPC grid-connected inverter is achieved by superimposing the zero-sequence component. Finally, it is compared with the triangular carrier to obtain the switching signal of each switch of the subsequent LCL type NPC grid-connected inverter.

[0107] The continuous control set model predictive control block diagram is as follows Figure 3 As shown, the specific control steps are as follows:

[0108] For the interleaved parallel Boost converter, when S n =1(n=1,2,…,6), according to KCL and KVL, we can get:

[0109]

[0110] When S n =0(n=1,2,…,6), we have:

[0111]

[0112] Where V in is the input voltage, L n is the inductance of each phase, R n is the resistance on the inductor, V bus is the bus capacitor voltage.

[0113] Assume that the duty cycle of each phase switch is d n (t), n=1,2,…,6, the system average model can be obtained by the state space averaging method as follows:

[0114]

[0115] Performing first-order forward difference on equations (3) and (4), we can get the discrete prediction model as follows:

[0116]

[0117] In the formula, k refers to the current moment, k+1 refers to the next moment, T s is the switching period, n=1,2,…,6.

[0118] Make each phase inductor current i Ln Tracking current reference value I ref The cost function J is designed as follows:

[0119]

[0120] Among them, i Ln (k+1) is calculated according to formula (5), I ref is the current reference value given by the aircraft engine;

[0121] Substitute equation (5) into equation (7), and the duty cycle d in the cost function J is n (k) Find the partial derivative and make At this point, the duty cycle required by the interleaved parallel Boost converter at the next moment can be obtained as:

[0122]

[0123] In the PWM modulator, since the previous stage circuit uses the staggered parallel technology and the number of staggered parallel phases is 6, the PWM carrier needs to be phase-staggered, and the phase-stagger angle is 2π / 6. Then, the duty cycle of each phase switch obtained in formula (8) is compared with the PWM carrier, and the switching signal of each phase is output to the previous stage staggered parallel Boost converter to drive the switch tube of each phase.

[0124] At the next moment, the input voltage, the inductor current of each phase, and the bus capacitor voltage are sampled, and the above steps are repeated to perform feedback correction to achieve rolling optimization of the switching signals of each phase.

[0125] In the control strategy of the downstream LCL-type NPC grid-connected inverter, the first-order linear active disturbance rejection (ADR) module uses the bus voltage as the module input. After estimation by an internal observer, it eliminates external disturbances from the system through compensation, achieving a rapid bus voltage response under disturbances. At the same time, its output control variable serves as the reference value for the grid-side current in the sliding mode control. In this case, the sliding mode control module uses the grid-side current reference value obtained from the ADR as the control input. By introducing a sliding mode surface, it ignores external disturbances and uncertain parameters, forcing the system to slide rapidly on and along the sliding mode surface, thereby achieving stable control of the system. SVPWMM, as the switching signal modulation control, modulates the modulation signal obtained by the sliding mode control with a ram-horn wave. By superimposing the zero-sequence component, the voltages of the two bus capacitors of the NPC grid-connected inverter are balanced. Finally, the switching signal is compared with the triangular carrier to obtain the switching signal for each switch of the downstream LCL-type NPC grid-connected inverter.

[0126] The control block diagram of linear active disturbance rejection and sliding mode fusion control is as follows: Figure 4 As shown, the control steps are as follows:

[0127] A first-order system with perturbations can be expressed as:

[0128]

[0129] In the formula, b is the gain of the control system, which shows a proportional relationship between the controller input and output control quantity. It is the main part of the controller, and f1 is the unknown system disturbance that is independent of the input u.

[0130] Since the exact proportional relationship b between input and output is usually complicated to calculate, and the controller is not highly dependent on parameters, b can be approximated by a constant b0, and the inaccurate part can be treated as a disturbance and combined with f1 to form f. Then Equation (9) becomes:

[0131]

[0132] Next, the bus capacitor voltage outer loop linear extended observer (LESO) is constructed, and the input signal is the bus capacitor voltage V bus and grid-side current reference value i 2d * , the output signal is the observed value z1 of the bus capacitor voltage and the observed value z2 of the total system disturbance. Therefore, the constructed LESO is:

[0133]

[0134] Where V bus *is the bus capacitor voltage reference value, u is the grid side current reference value i 2d * , β1 and β2 are two adjustable parameters inside LESO, which determine the dynamic performance of the observer, and e is the observation error.

[0135] Convert Equation (11) into the corresponding state space equation:

[0136]

[0137] in, C=[1 0], V bus estimated value of;

[0138] By transforming Equation (12), we can obtain the characteristic polynomial of LESO:

[0139] λ(s)=|sI-(A-LC)|=s 2 +β1s+β2 (13)

[0140] According to the bandwidth theory, the two poles of LESO are configured at -ω0, so that the parameter to be adjusted is reduced to one, at this time β1=2ω0, β2=ω0 2 .

[0141] In order to make the observer output z1 and z2 quickly track the system output y and the total disturbance f respectively, the control quantity u is calculated as follows:

[0142]

[0143] Where, ω c is the bandwidth of the controller;

[0144] Through the above steps, the bus capacitor voltage V can be quickly tracked bus , and output the reference value of the grid-side current.

[0145] Next, Figure 5 The equivalent circuit of the LCL filter is listed in KCL and KVL equations:

[0146]

[0147] Where i 1k is the inverter side current, i 2k is the grid-side current, V ck is the filter capacitor voltage, u k is the inverter output voltage, e k is the grid-side voltage;

[0148] After dq transformation of the above formula, we have:

[0149]

[0150] Under power frequency conditions, without considering the influence of higher harmonics, i 2dq and V cdq It can be regarded as a fixed constant. The reference value of the grid-side current i obtained by formula (14) is 2d * , we can get the filter capacitor voltage reference value and the inverter side current reference value:

[0151]

[0152] The selection of the sliding surface must ensure the stability and good dynamic quality of the sliding motion. The following sliding surface is selected:

[0153]

[0154] When the system reaches the sliding surface after the approaching stage, s = 0, thus achieving the inverter side current i 1d 、i 1q Tracking compensation;

[0155] Simplify formula (18) as follows:

[0156] s=xx * (19)

[0157] In order to make the system state approach the sliding surface and maintain it on the sliding surface, it is necessary to design the control rate u:

[0158] u=u sw +u eq (20)

[0159] Where u sw is the switching control rate, which ensures that the system state can reach the sliding surface within a finite time, and is determined by the reaching law; u eq is the equivalent control rate. To keep the system state on the sliding surface, when u=u eq hour,

[0160] The first equation in equation (16) is converted into the state equation:

[0161]

[0162] In the formula, x=[i 1d i 1q ] T ; u=[u d u q ] T ;

[0163] By derivatizing formula (19) and inserting it into formula (21), we can obtain:

[0164]

[0165] From this we can get u eq :

[0166]

[0167] After the sliding mode surface is determined, the equivalent control rate of the LCL-type NPC grid-connected inverter will not change, while the switching control rate will show different results according to the different reaching laws.

[0168] To suppress system chattering, a boundary layer Δ is added so that the system motion state is confined to a certain Δ neighborhood of the sliding surface rather than the sliding surface. Outside the boundary layer, switching control is adopted. Inside the boundary layer, continuous state linearized feedback control is adopted, thereby avoiding or weakening the chattering problem caused by switching the control structure on the sliding surface. The expression of the saturation function is as follows:

[0169]

[0170] At this time, the switching control rate u sw for:

[0171]

[0172] Then the total control rate u is:

[0173]

[0174] The total control rate u is input into the SVPWM modulator as a modulation signal to modulate the switching signal;

[0175] In the device solution provided in this embodiment, since S a , S b , S c Each value has three output states, so the NPC grid-connected inverter has a total of 27 switching states for the three phases. Each switching state corresponds to a voltage vector, among which there are some redundant vectors. There are 19 actual voltage vectors, including one zero vector, six small vectors, six medium vectors, and six large vectors. The switching states corresponding to the specific vectors are shown in Table 1.

[0176] Table 1 Voltage vectors corresponding to different switch states

[0177]

[0178]

[0179] The total control rate obtained by equation (26) is converted to the αβ axis, and the corresponding switching signal of each phase is output to the LCL type NPC grid-connected inverter according to the position of the voltage vector.

[0180] Through the above steps, linear anti-disturbance control and sliding mode fusion control can be realized to complete the control of the subsequent grid-connected inverter.

[0181] The circuit parameters of the energy-fed electronic load in this embodiment are shown in Table 2:

[0182] Table 2 Energy-feedback electronic load circuit parameters

[0183] parameter name Numerical <![CDATA[V in ]]> Input voltage 540V <![CDATA[V bus ]]> Bus capacitor voltage 800V e Grid-side voltage 220V <![CDATA[f s ]]> Switching frequency 20kHz <![CDATA[L1,L2,…,L6]]> Interleaved Boost Inductors 1.5mH <![CDATA[R1,R2,…,R6]]> Interleaved Boost Inductor Internal Resistance 0.1Ω <![CDATA[C1,C2]]> Bus capacitance 0.1F <![CDATA[L f ]]> Inverter side inductor 2mH <![CDATA[L g ]]> Grid-side inductor 0.4mH <![CDATA[C f ]]> LCL filter capacitor 50μF

[0184] The simulation results are as follows:

[0185] The six-phase inductor current waveforms of this embodiment are shown in FIG. Figure 6 As shown in the figure, it can be seen that the inductor currents of each phase are evenly staggered, realizing the phase interleaving of the inductor currents, and when the average value of the inductor current jumps from 5A to 40A, the inductor current reaches a new stable state in only 0.2ms, indicating that the system tracks the current reference value accurately and quickly, achieving high dynamic performance of the system.

[0186] The busbar capacitor voltage waveform of this embodiment is as follows: Figure 7 As shown in the figure, by using the fusion control of linear anti-disturbance control and sliding mode, the bus capacitor voltage has no overshoot voltage at startup and reaches the preset value of 800V quickly and smoothly; at 0.3s, a disturbance occurs in the system, at this time the bus capacitor voltage overshoots only 7.5V, and reaches a stable state after 40ms, indicating that the fusion control proposed in the present invention has strong resistance to external disturbances, good system robustness, and good dynamic response speed.

[0187] The grid-connected current waveform of this embodiment is as follows: Figure 8 As shown, the three-phase grid-connected current of the system presents a sine wave, and the FFT spectrum analysis of phase A is as follows Figure 9 As shown in Figure 2, the grid-side current THD of phase A is only 0.73%, indicating that the grid-connected quality of the system is good. Figure 10 It can be seen that the system power jumps from 16kW to 130kW at 0.3s, which verifies that the energy-fed electronic load of the present invention can be applied to high-power occasions. In addition, the proposed integrated control strategy enables the energy-fed electronic load to have better dynamic response and robustness.

[0188] It should be noted that, unless otherwise defined, the technical or scientific terms used in the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0189] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other manner. Any person skilled in the art may utilize the above-disclosed technical content to modify or modify the present invention into equivalent embodiments. However, any simple modifications, equivalent variations, and modifications to the above embodiments that do not depart from the technical content of the present invention and are based on the technical essence of the present invention remain within the scope of protection of the present invention.

[0190] The present invention is not limited to the above-mentioned preferred embodiment. Anyone can derive various other forms of a feed-back electronic load circuit and its control method based on the inspiration of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A power-feed electronic load circuit, characterized in that: include: The front-stage circuit consists of N-phase Boost converters connected in parallel. Each phase Boost converter includes an inductor, an IGBT switch tube, and a diode, which is used to boost the input DC voltage to a preset bus voltage. The subsequent circuit consists of an LCL-type NPC grid-connected inverter, including an NPC three-level inverter topology and an LCL filter, which is used to invert the boosted DC voltage into AC power and feed it back to the grid; A signal acquisition module is configured to collect the input voltage, each phase inductor current, and bus voltage of the front-stage circuit, as well as the inverter-side current, filter capacitor voltage, grid-side current, and grid-side voltage of the back-stage circuit; Control module, including: a front-stage continuous control set model prediction unit, connected to the front-stage circuit, for optimizing the switching duty cycle of the Boost converter in real time; The post-stage linear active disturbance rejection + sliding mode fusion control unit is connected to the post-stage circuit and is used to generate a switching modulation signal for the NPC inverter.

2. The energy-fed electronic load circuit according to claim 1, characterized in that: The boost target value of the front-stage interleaved parallel Boost converter is 800V, and the parameters of the inductance of each phase are 1.5mH, the resistance is 0.1Ω, the bus capacitance is 0.1F, and the switching frequency is 20kHz.

3. The energy-fed electronic load circuit according to claim 1, characterized in that: The parameters of the post-stage LCL filter meet the following requirements: the inverter side inductor L f =2mH, grid-side inductance L g =0.4mH, filter capacitor C f =50μF, and through asymmetric inductance distribution and capacitance optimization, the total harmonic distortion of the grid-connected current is achieved to be less than 1%.

4. The energy-fed electronic load circuit according to claim 1, characterized in that: The preceding continuous control set model prediction unit is configured to perform phase optimization, wherein the phase optimization generates a phase-staggered PWM signal, including: Establish discrete dynamic equations for each phase inductor current independently; The phase cost function is constructed by the sum of squares of the errors between the predicted current value of each phase and the reference value; The duty cycle that minimizes the phase-splitting cost function is solved and output to the switch tube of the corresponding phase of the previous-stage Boost converter.

5. A control method for the energy-fed electronic load circuit according to claim 1, characterized in that: include: Pre-stage control: Based on the preceding continuous control set model prediction unit, the dynamic value of each phase inductor current is solved in real time through a discrete prediction model; The duty cycle is optimized independently for each phase current error to generate a phase-staggered PWM signal to drive the switch tube; Post-stage control: The bus voltage disturbance is estimated and compensated in real time through the post-stage linear active disturbance rejection + sliding mode fusion control unit; The inverter switching signal is generated by forcing current tracking on the sliding surface and combining it with SVPWM modulation; Collaborative control: Current reference value I predicted by the previous model ref Dynamic adjustment is made based on the disturbance observation results of the subsequent stage, linking the strategies of the previous and subsequent stages to achieve dynamic load simulation and harmonic suppression.

6. The control method according to claim 5, characterized in that: In the pre-stage control, the discrete prediction model is constructed by the following steps: Based on the state space averaging method, the continuous state equation of the interleaved parallel Boost converter is established; The continuous model is discretized by first-order forward difference to obtain the dynamic equation of the inductor current of each phase; Predict the inductor current value at the next moment based on the current input voltage, bus voltage and duty cycle; The independently optimizing duty cycle for each phase current error includes: Design a cost function for each phase inductor current independently and calculate the square of its error with the reference value; By minimizing the total cost function, the optimal duty cycle of each phase is solved and multi-phase current balanced tracking is achieved.

7. The control method according to claim 5, characterized in that: In the latter stage control, the implementation of the linear expansion observer includes: The first state variable of the observer is defined as the estimated value of the bus voltage, and the second state variable is defined as the estimated value of the bus voltage disturbance; According to the deviation between the actual bus voltage value and the estimated bus voltage value, the state variables are dynamically updated: The update rate of the first state variable is determined by the linear compensation term of the deviation and the second state variable; The update rate of the second state variable is determined only by the linear compensation term of the deviation; The estimated value of the bus voltage disturbance is feed-forwarded to the input of the sliding mode controller to improve the system's anti-disturbance capability.

8. The control method according to claim 5, characterized in that: The sliding surface is designed as the integral form of the inverter side current error: The steady-state error is eliminated by introducing the integral term to enhance the tracking accuracy; Combined with the saturation function to limit the sudden change amplitude of the control quantity to suppress system chattering; By adjusting the convergence coefficient, the response speed and stability can be balanced.

9. The control method according to claim 5, characterized in that: In the SVPWM modulation, midpoint potential equalization is achieved through the following steps: Calculate the zero-sequence component of the three-phase modulation signal of the NPC inverter; The zero-sequence component is added to the original modulation signal to balance the upper and lower bus capacitor voltages; A switching sequence is generated according to the superimposed modulation signal to ensure that the midpoint potential fluctuation is less than a preset threshold.

10. The control method according to claim 5, characterized in that: In the collaborative control, the current reference value I predicted by the previous model ref The logic of dynamic adjustment includes: The disturbance estimation value based on the output of the subsequent LESO reflects the sudden change in load or the intensity of grid fluctuation; Set the initial current reference value I ref0 The disturbance estimate is calculated by the feedforward gain coefficient K p Weighted superposition to generate dynamically adjusted reference value I ref (k); Through the feedforward-feedback dual channel, real-time coordination of the front-stage and back-stage control strategies is achieved, balancing the dynamic response speed and system stability.

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