Converter with zero current detection, corresponding apparatus and method

Abstract

The invention relates to a converter with zero current detection, a corresponding device and a method. A buck, boost, or inverted topology converter includes a high-side power stage and a low-side power stage between which a coil is coupled at a current supply node. A zero-cross detection (ZCD) circuit includes a comparator that generates a detection signal when a coil current has a zero-cross event. Threshold tuning circuitry selectively changes a threshold of the comparator in a first direction or a second direction based on a feedback signal provided by voltage detection circuitry coupled to the voltage detection node at the coil. The presence or absence of a voltage transition at the voltage detection node indicates whether a zero-crossing event of the detection signal with respect to the coil current is advanced or delayed.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102024000003991, filed on February 26, 2024, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The description relates to a converter including a zero current detector (ZCD) circuit.

[0004] Aspects of the present description are applicable to, for example, a DC-DC converter including a ZCD comparator.

[0005] In theory, aspects of the present description can be used in all kinds of applications where a DC-DC converter is used. Background Art

[0006] Detecting the zero current condition of the current flowing through the coil (coil current) is a feature of a DC-DC converter that facilitates managing the transition from a continuous mode of operation (called continuous current mode - CCM) to a discontinuous mode of operation (called discontinuous current mode - DCM).

[0007] A zero current detector (ZCD) is a circuit block configured to detect a zero current condition in a coil in a converter. Such a converter typically includes a low-side (LS) switch and a high-side (HS) switch.

[0008] The ZCD unit can be designed in different ways, depending on the DC-DC converter topology and the shape (waveform) of the coil current.

[0009] Conventional solutions for implementing a ZCD unit involve monitoring the operation of the half-bridge power section of the converter.

[0010] The phase (positive / negative slope) of the coil current used to determine the conditions for zero detection is a factor worth considering for this purpose.

[0011] For example, current sensing can be done at T OFF The current sensing element is “on” (i.e., conducting) during the selected phase. ON ” is achieved by a power switch. Detection involves monitoring the voltage drop across a sense element.

[0012] Figure 1This is an example of such a solution used in a "buck" converter, where zero-crossing detection (ZCD) involves monitoring the voltage at node SW between the high-side power stage HS Power (which includes the HS switching transistor) and the low-side power stage LS Power (which includes the LS switching transistor) of the converter. The low-side power stage LS Power is arranged between node SW and ground GND.

[0013] Node SW is coupled to coil L in the converter, and current Icoil passes through coil L.

[0014] The ZCD unit 10 compares the voltage at node SW with a reference to generate an output signal ZCD_OUT, and this output signal ZCD_OUT can be gated at an AND gate via a gating signal Gate_LS to generate a gated ZCD signal ZCD_OUT_MASK.

[0015] As Figure 1A shown in the figure: When the transistor of the low-side power stage LS Power is in the "on" (conducting - LS ON) state, Icoil > 0, VSW < GND, and the ZCD unit output is low; and when LS ON, Icoil < 0, VSW > GND, and the ZCD output is high.

[0016] Figure 2 The figure illustrates the case of a "boost" converter, where zero-current detection ZCD involves monitoring the voltage (VOUT - SW) across the transistor of the high-side power stage HS Power of the converter. In Figure 2 it, for simplicity, the same reference symbols as Figure 1 are used.

[0017] As Figure 2A shown in the figure, in the case of the arrangement of Figure 2 : When the transistor of the high-side power stage HS Power is in the "on" (conducting - HS ON) state, Icoil > 0, VSW > VOUT, and the ZCD output is low; and when HS ON, Icoil < 0, VSW < VOUT, and the ZCD output is high.

[0018] Figure 3 The figure illustrates the (inverting) "buck-boost" case, where ZCD detection involves monitoring the voltage (VOUT - SW) across the transistor of the low-side power stage LS Power of the converter. In Figure 3 it, for simplicity, the same reference symbols as Figure 1 and Figure 2 are used.

[0019] As Figure 3A shown in the figure, in the case of Figure 3In the case of the arrangement: When the transistor of the low-side power stage LS Power is "on" (conducting - LS ON), Icoil > 0, VSW < VOUT, and the ZCD output is low; and when LS ON, Icoil < 0, VSW > VOUT, and the ZCD output is high.

[0020] Figure 1 , Figure 2 and Figure 3 are all examples of converters, including: a high-side power stage HS Power and a low-side power stage LS Power, with a coil L coupled therebetween at a current supply node, where the coil is configured to be traversed by a coil current Icoil in response to the transistors of the high-side power stage HS Power and the low-side power stage LS Power turning on and off (not necessarily in an alternating manner); and a zero-crossing detection (ZCD) circuit 10, configured to detect zero-crossing events of the coil current Icoil, where the ZCD circuit 10 includes a voltage detection node SW configured to be coupled to the coil L at the current supply node.

[0021] Figure 4 In an exemplary case of a buck configuration and for a common (abscissa) time scale t, the possible time behaviors are illustrated, from top to bottom: the current Icoil, the voltage at the sensing node SW between the high-side power transistor stage and the low-side power transistor stage, and the ZCD detection signal ZCD_OUT.

[0022] It is noted that, with the necessary corrections, the following discussion related to Figure 4 applies to Figure 1 , Figure 2 and Figure 3 all the topologies shown in. Moreover, the value of a minimum of 250 nS is of course purely exemplary and not restrictive.

[0023] By using a (very) fast zero-crossing comparator, the zero-crossing detection efficiency is promoted: In fact, any long delay time of the comparator will result in a system response that is likely to occur when the current passing through the coil L has reversed.

[0024] The effective total delay consists of the comparator delay depending on the supply voltage and the slope of the signal at the SW node as a function of the voltage V OUT and the inductance value of the (external) coil L.

[0025] By showing that the comparator delay and offset (essentially the intervention threshold of the comparator) may cause the first problem, Figure 5A the graph of Figure 4 is developed on the graph of

[0026] Figure 5AIt is highlighted that without a fast comparator response, the coil current Icoil may respond delayed by time t when the current Icoil has reversed. Delay The ZCD detection signal is detected and the controller is stopped (turned off).

[0027] The delay should desirably be compatible with the maximum switching frequency. (Very) low offset and fast reaction time (low delay) are rarely compatible unless very complex circuit arrangements are employed.

[0028] Figure 5B The graph shows that the Vout voltage and coil current overlay may cause a second problem.

[0029] In fact, the slope of the coil current during the Toff phase ( Figure 5B The possible time behavior of the coil L (referred to as "coil" for short) with different slopes is shown by way of example in FIG. 1 , where the impedance of the coil L (referred to as "coil") depends on the (regulated) output voltage and the type of coil used according to the following equation:

[0030] dI / dT=V OUT / Coil

[0031] The design of the ZCD comparator can take the maximum allowable coil current slope into consideration as a design parameter to reduce detection errors. This may lead to an over-design that is optimized for a single application case.

[0032] Figure 5C The figure shows that temperature and angle compensation may cause further problems.

[0033] In fact, the “on” resistance Ron of the sensing element plus the reaction time and offset of the comparator can vary with temperature (see Figure 5C "Hot" and "Cold" conditions indicated at the bottom) and angular expansion.

[0034] As a result, the accuracy of the ZCD detection threshold will vary with the variation of the power MOS Ron, the offset of the comparator and T Delay changes with the changes.

[0035] Possible solutions to these problems could involve: dynamic offset cancellation in the comparator; dedicated design options for dedicated application cases; or static fine-tuning of the ZCD threshold and T Delay .

[0036] The disadvantage of dynamic offset cancellation is that it is inefficient with respect to comparator delay times and may ultimately result in a complex implementation.

[0037] Dedicated design options for specialized application cases may not provide the desired complete use case coverage and may also involve the use of different part numbers for different use cases.

[0038] The ZCD threshold can be statically trimmed using a slow ramp during final testing. In functional mode, the situation is different if the pre-trimming dependencies are not taken into account.

[0039] There is a need in the art for contributions that address the various issues discussed above. Summary of the Invention

[0040] One or more embodiments relate to a converter.

[0041] One or more embodiments are directed to corresponding devices (any device using a DC-DC converter can be taken as an example of such a device).

[0042] One or more embodiments are directed to corresponding methods.

[0043] The solution as described herein provides one or more of the following advantages: low footprint compared to accurate but complex comparators; compensation for comparator delays; and flexibility with respect to application use cases.

[0044] The solution as described herein facilitates providing a zero current detector for various types of DC-DC converters.

[0045] The solution as described herein may be optimized for buck converters, but is equally applicable to boost converters and inverting ("buck-boost") topologies: see, for example, the topologies discussed in the introductory part of this description.

[0046] That is, the solution as described herein is generally applicable to a zero-crossing detection circuit configured to be coupled to a coil coupled to a current supply node between a high-side power stage HS Power and a low-side power stage LS Power, wherein the coil current Icoil (negative or positive: see, for example, Figure 24B , as discussed below) through the coil.

[0047] Throughout this description, for simplicity, the same name (i.e., SW) will be used to denote nodes intended to serve the following roles: a current supply node between the high-side power stage HS Power and the low-side power stage LS Power, wherein the coil is coupled to the power stages HS Power and LS Power so as to be passed through by a current exhibiting a zero crossing point (i.e., a point at which the current intensity has a zero value); and a voltage detection node of the ZCD circuit described herein, for detecting voltage changes occurring at this node, with the purpose of identifying (via voltage detection) the zero crossing point of the current Icoil passing through the coil L.

[0048] The solution as described herein involves on-the-fly calibration, which facilitates the use of simple comparators that do not require accurate and very fast comparator performance. On-the-fly calibration (for other parameters, known per se in the art) has been found to be used in a particularly advantageous manner in the case of voltage-based zero crossing detection (ZCD).

[0049] The solution described in this article employs continuous “on-the-fly” calibration and can optimize the ZCD threshold (thus improving system efficiency), focusing primarily on comparator delay.

[0050] The solution as described herein can cover a wide variety of application cases without using complex structures, while also mitigating undesired production proliferation. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0052] As discussed above Figure 1-1A 、 Figure 2-2A 、 Figure 3-Figure 3A 、 Figure 4 and Figures 5A-5C , to present the relevant technologies and the shortcomings encountered;

[0053] Figure 6 schematically represents the principles on which the embodiments of the present description are based;

[0054] Figure 7A and Figure 7B 、 Figure 8A and Figure 8B as well as Figure 9A and Figure 9B further details the principles upon which the embodiments of this description are based;

[0055] Figure 10 、 Figure 11 and Figure 12 is an example of a timing diagram of signals that may occur in embodiments of the present description;

[0056] Figure 13 and Figure 14 Details certain possible features of embodiments of this description;

[0057] Figure 15 is a circuit diagram of an embodiment of the present description;

[0058] Figure 16 illustrates the principles upon which embodiments of the present description may be based;

[0059] Figure 17 is realized Figure 16 A circuit diagram of an embodiment of the present description illustrating the principles;

[0060] Figure 18 illustrates possible operations of embodiments of the present description;

[0061] Figure 19 and Figure 20 further details possible operations of embodiments of the present description;

[0062] Figure 21A 、 Figure 21B and Figure 21C illustrates possible operations of embodiments of the present description;

[0063] Figure 22A 、 Figure 22B and Figure 23 further details possible operations of embodiments of the present description;

[0064] Figure 24A and Figure 24B Detailed description of zero current diode detection in embodiments of the present description;

[0065] Figure 25 and Figure 26 Further details zero current diode detection in embodiments of the present description;

[0066] Figure 27 is a circuit diagram of an embodiment of the present description;

[0067] Figure 28 Illustrated Figure 27 The possible operations of the circuit;

[0068] Figure 29 is a block diagram of exemplary circuitry configured to test a self-calibration loop, wherein a unit hosts a calibration process and has associated circuitry to facilitate Figure 30A 、 Figure 30B 、 Figure 31 and Figure 32A 、 Figure 32B Test bench for testing circuit behavior;

[0069] Figure 30A and Figure 30BIllustrated Figure 29 The possible operations of the circuit;

[0070] Figure 31 is a timing diagram illustrating possible advantageous features of embodiments of the present description; and

[0071] Figure 32A and Figure 32B Illustrated Figure 31 The possible effects of the characteristics. DETAILED DESCRIPTION

[0072] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0073] The edges of a feature drawn in a figure do not necessarily indicate the end of the extent of that feature.

[0074] In the following description, one or more specific details are provided to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0075] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more places in this description do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0076] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0077] Throughout the drawings appended hereto, similar parts or elements are indicated with similar references / numerals unless the context indicates otherwise, and the corresponding descriptions will not be repeated for the sake of brevity.

[0078] Moreover, for the sake of brevity and ease of explanation, the same name may be used throughout this description to represent: a node or line and a signal appearing at the node or line (the node SW mentioned throughout this description is an example); and / or a component (such as an inductor of a capacitor, a resistor, or a coil) and its electrical parameters: the name "coil" used for the inductor L and its inductance (impedance) value is an example.

[0079] Throughout this description, when referring to zero-crossing detection or a detector configured to detect a zero-crossing condition, the abbreviation ZCD will be used, where the intensity of the current flowing through an inductor reaches (and crosses) a zero value.

[0080] As discussed in the introductory part of this description, a zero-crossing detection comparator should desirably be able to monitor the voltage at the coil (such as the voltage at node SW discussed previously) and, based on this, identify the condition where the current flowing in the coil is zero.

[0081] To keep this detailed description from being overly long and cumbersome, the accompanying drawings starting from Figure 6 will describe as much as possible in reference to the previously provided description in conjunction with Figures 1 to 5A - Figure 5C provided.

[0082] Therefore, in the accompanying drawings starting from Figure 6 the parts, components, and entities introduced in conjunction with Figures 1 to 5A - Figure 5C will be indicated by similar names / reference marks and will not be described in detail again for the sake of brevity.

[0083] As Figure 6 depicted (and by way of example referring to the circuit layout according to the buck configuration discussed previously), during the conduction phase of the low-side power stage LS, the current through the coil L, i.e., Icoil, can be expressed as: Icoil = Vds / Ron, where Vds and Ron indicate the drain-to-source voltage drop across the low-side power stage (e.g., a MOSFET transistor)—which is the voltage at node SW—and its "on" resistance.

[0084] Once again, the solution described herein aims to facilitate: zero-crossing detection in the current (Icoil); based on: voltage-based sensing of the voltage (e.g., at node SW).

[0085] If it is assumed that the comparator (see reference numeral 10 in the previous drawings) has an x% offset: in the case of a first value Ron1 for the resistance Ron, a Y% uncertainty will result in the coil current Icoil; and in the case of a second, lower value Ron2 < Ron1 for the resistance Ron, a much larger error Y1% may result in determining the current Icoil.

[0086] Therefore, the larger the transistor of the power stage LS Power (the smaller Ron), the more accurate the comparator (the smaller the offset) will be involved. This will result in (further) larger area and higher complexity, and almost inevitably involve fine-tuning.

[0087] Therefore, the possibility of correcting the comparator offset (essentially the intervention threshold of the comparator) and the ability to account for possible errors due to the comparator's delay may represent a point worth further investigation, considering different use cases.

[0088] Figure 7A 、 Figure 7B and Figure 8A 、 Figure 8B Representing a possible operation of a ZCD comparator (with reference to a buck configuration by way of example), the following possible temporal behaviors (waveforms) are illustrated (from top to bottom) relative to a common time (abscissa) scale t: the current through the coil Icoil; the voltage at the node SW; and the output signal ZCD_COMP from the comparator.

[0089] Note that for simplicity and ease of understanding, buck configurations are primarily mentioned throughout this description. The same underlying principles apply to other types of configurations, with the circuit arrangements being adapted accordingly, and such adaptations are within the capabilities of those skilled in the art.

[0090] Figure 7A 、 Figure 7B and Figure 8A 、 Figure 8B The effect of the ZCD comparator output signal ZCD_COMP switching to "1" to turn off the transistor of the low-side power stage LS Power is shown under the following conditions: the current Icoil has a first sign or direction (positive - Icoil>0) - Figure 7A and Figure 7B ; or the current Icoil has a second sign or direction (negative - Icoil < 0) - Figure 8A and Figure 8B .

[0091] Specifically, Figure 7A and Figure 8A Shown is a possible temporal behavior of a (forward biased) voltage applied to the body diode D1 of the low-side MOSFET in the low-side power stage LS Power and the body diode D2 of the high-side MOSFET in the transistors of the high-side power stage HS Power.

[0092] Figure 7A 、 Figure 7B and Figure 8A 、 Figure 8B The time delay between when the ZCD comparator commands LS to turn off (making the transistor of the low-side power stage LS Power non-conductive) and when the associated bridge actually operates (body diode D1 or D2 turns on, i.e. becomes conductive) is shown. The zero-crossing monitoring window will include this delay.

[0093] Figure 9A and Figure 9B is an example method where the signal SW (essentially the voltage Vds across the transistor of the low side power stage LS Power (hereinafter LS)) is monitored after the ZCD comparator turns off the LS Power transistor by rendering it non-conductive.

[0094] For example, this can be achieved via a monitoring device such as a voltage sampler or via a comparator (and in a manner known per se to those skilled in the art).The information obtained from this device can be used to correct the offset of the main ZCD comparator (essentially the intervention threshold).

[0095] Figure 9A and Figure 9B Illustrated on a common time (abscissa) scale are—from top to bottom—the possible time behavior of: the coil current Icoil; the output signal ZCD_COMP from the ZCD comparator; and the signal SW, ie the signal at the node SW.

[0096] Figure 9A and Figure 9B The diagram can be viewed as a time sequence including stages or regions I to V, namely: I - ZCD comparator operating region (Toff phase); II - Vds monitoring region; III - high impedance (HZ) region; IV - offset correction region (Ton phase); and V - additional ZCD comparator operating region after offset correction.

[0097] The effect of the offset correction on the signal Icoil is illustrated at the right end of the correlation curve: In the case where the offset correction starts with Icoil>0 ( Figure 9A ); and in the case where the offset correction starts from Icoil<0 ( Figure 9B ).

[0098] In fact, in this latter case, Vds monitoring information indicating conduction of the (body) diode is awaited in order to be able to “dribble” with the previous state.

[0099] Thus, the approach as contemplated herein would benefit from: a ZCD comparator, which itself does not need to be highly accurate since the associated offset will be corrected, which in turn would facilitate a reduced area footprint; circuitry for generating a (variable) offset to apply to the ZCD comparator, having features that facilitate changing the offset in both directions and understanding when the added offset is too high or too low; and logic circuitry configured to determine whether offset correction is desired.

[0100] Note again that changing the offset of a comparator as discussed throughout is exemplary and indicative of the act of changing the intervention threshold of the comparator.

[0101] In the solution as described herein, an "adaptive" generator is implemented, which operates cycle by cycle, correcting the ZCD comparator threshold based on a feedback signal.

[0102] For example, when the device starts up, the comparator may be unbalanced, in such a way that the ZCD thresholding action is anticipated (or delayed): this unbalanced condition can be selected and varied as needed.

[0103] Based on the feedback signal, the ZCD comparator threshold can be adjusted cycle by cycle until an "optimal" condition is achieved. This condition can be represented by a coil current Icoil that is as close to zero as possible (even if not exactly zero).

[0104] For example (as described in further detail below), the comparator offset may be adapted via an up / down counter. At each clock pulse, the offset value may be increased or decreased (e.g., one count step at a time) under the control of control logic operating one step at a time.

[0105] A desired (optimal) offset or threshold is maintained in response to the control logic being in a condition to command an opposite offset adjustment at a subsequent clock pulse, for example, increasing (respectively decreasing) the comparator offset value at one clock pulse and then decreasing (respectively increasing) the comparator offset value at the next clock pulse.

[0106] In that way, the system will "dribble" around the optimal zero-crossing threshold detected.

[0107] Figure 10 and Figure 12 Again, a possible time behavior of the coil current Icoil and the signal SW relative to the common abscissa time scale t is represented, and Figure 11 The following possible "UP" and "DOWN" offset / threshold corrections are illustrated, resulting in Figure 12 The behavior exemplified in .

[0108] In a possible implementation of the solution described herein, the drain-to-source voltage drop Vds across the transistors of the low-side power stage LS Power can be sensed during the “off” condition (e.g. at the node SW). As long as the behavior of the low-side power stage LS Power is sensed immediately after the ZCD comparator switches the stage LS Power off (non-conducting) (i.e. the SW signal, which is the Vds across the MOSFET transistors in the low-side power stage LS Power), it is possible to determine that the current Icoil circulating in the coil L at this moment is still positive (switching on the “low-side” body diode BD D1 - see Figure 7A and Figure 7B ) or negative (turning on the "high side" body diode BD D2 - see Figure 8A and Figure 8B ).

[0109] Figure 13 and Figure 14 This is illustrated in , showing the operation in response to the signal ZCD_COMP=1, where the transistors of the power stage LS Power are switched off (become non-conducting), and a different time behavior of the current Icoil at the start of the “switch-off” condition.

[0110] Figure 15 is a circuit diagram of an embodiment of the present description, which is adapted to be applied to the beginning of the present description in conjunction with Figures 1 to 5A to Figure 5C The present invention is discussed in the general context (ie, not necessarily restricted to the buck configuration considered herein as an example).

[0111] That is, Figure 15 The circuit illustrated in the figure can generally be applied to a converter, which includes: a high-side power stage HSPower and a low-side power stage LSPower, with a coil L coupled therebetween at a current supply node, wherein the coil is configured to be passed through by a coil current Icoil in response to the transistors of the high-side power stage HSPower and the transistors of the low-side power stage LSPower being turned on and off (not necessarily in an alternating manner); a zero-crossing detection (ZCD) circuit 10, configured to issue a ZCD detection signal ZCD_COMP indicative of a zero-crossing event of the coil current Icoil, wherein the ZCD circuit 10 includes: a voltage detection node (SW), configured to be coupled to the coil L at the current supply node; and a ZCD comparator, having a ZCD input node coupled to the voltage detection node SW, and configured to issue a ZCD detection signal in response to the voltage at the voltage detection node SW crossing a selectively tunable ZCD comparator threshold (offset).

[0112] exist Figure 15 In the circuit diagram of FIG. 1 , a “predictive” ZCD comparator circuit system is illustrated comprising a comparator 100 which should, for any condition and extended processing, switch as soon as the current Icoil in the coil L reaches (in the Toff phase) zero value as expected.

[0113] To this end, the comparator 100 may be configured (in a manner known per se) such that it is capable of adapting its threshold voltage to meet desired specifications, having an internal offset that is tunable via an offset generator 100A.

[0114] Note again that, as discussed throughout, changing the offset of the comparator is exemplary and indicates the act of changing the intervention threshold of the comparator (even in Figure 15For simplicity, the comparator 100 is illustrated as referenced to ground, which also applies).

[0115] exist Figure 15 In the circuit diagram of: reference numeral 102 denotes an up / down (sequential) counter configured to increase or decrease the internal offset of the comparator 100 (in fact, the threshold at which the comparator 100 “trips” or switches) via the offset generator 100A; reference numeral 103 denotes a Vds monitoring level circuit system configured to detect the SW signal, i.e., the Vds voltage drop across the transistors of the low-side power stage LS Power; and reference numeral 104 denotes a logic circuit system configured to manage the “adaptive” or adjustable evolution of the offset of the comparator 100 according to the desired operating conditions.

[0116] It is worth noting that Figure 15 The arrangement illustrated in does more than simply “move” accuracy-related issues from the ZCD comparator 100 to the Vds monitor level circuitry 103 .

[0117] like Figure 15 The arrangement illustrated in FIG is simple to implement and takes up little space: the additional area for the logic circuitry 104 and the offset generator 100A is largely outweighed by the possibility of obtaining a system that is more accurate than a single ZCD comparator and more versatile in terms of possible different applications, with the additional advantage of avoiding fine-tuning.

[0118] As mentioned, high accuracy is not necessary for the ZCD_COMP signal: therefore a comparator 100 with a simple structure can be used.

[0119] The offset generator 100A is actually able to recover the inaccuracies of the ZCD comparator 100 with a desired granularity (resolution).

[0120] Likewise, high accuracy is not necessary for the Vds monitor level circuitry 103 .

[0121] Advantageous features of such circuitry can involve being able to "feel" (sense) fast enough for rapid changes at its input, and being sensitive enough for the smallest voltage drop that is desired to be detected. In fact, even relatively inaccurate Vds monitoring can sense changes at its input as desired and provide correct sensing at the minimum sensitivity current.

[0122] That is, the Vds monitor level circuitry 103 is configured to quickly sense the voltage drop before the monitoring window closes and before the current changes sign / direction (ie, becomes negative and the body diode no longer conducts).

[0123] Figure 16 The illustration shows the fact that the offset value generated via a digital counter, such as counter 102, has a wider range (coverage) of comparator offset CO than the range applicable to comparator 100 via generator 100A. The "rest" of the coverage facilitates correction of other phenomena, such as time delays, adverse effects on Ron, etc.

[0124] Possible options to allow different functional conditions during startup may include: starting from the top offset value and decreasing it until the desired threshold is captured; starting from the bottom offset value and increasing it until the threshold is captured; or starting from the middle offset value and increasing / decreasing it until the threshold is captured.

[0125] As described, at each clock pulse, the counter value (and thus the offset / threshold of comparator 100 ) may be increased or decreased (eg, one count step at a time).

[0126] Thus, the desired offset (threshold) can be maintained in response to an opposite offset adjustment generated at a subsequent clock pulse, for example, increasing (respectively, decreasing) the comparator offset value at a certain clock pulse and then decreasing (respectively, increasing) the comparator offset value at the next clock pulse.

[0127] Various solutions / implementations of comparators with tunable offset known to those skilled in the art may be used in the arrangement as discussed herein.

[0128] Figure 17 is an example of a possible comparator solution (ZCD comparator 100) with current offset resolution = 1 / 4I, so the ZCD coil current resolution = ( 1 / 4I*gmCOMP) / RonLS, where: gmCOMP represents the transconductance of the comparator 100; and RonLS represents the “on” resistance of the MOSFET transistor in the low-side power stage LS Power.

[0129] For example, Figure 17 A comparator 100 is illustrated in FIG. 1 , with its associated offset generator 100A driven by a (eg, 6-bit) counter 102, wherein an AND gate 105 (see FIG. Figure 1 、 Figure 2 and Figure 3 A gate 12 in FIG. 1 is coupled to an output terminal of the comparator 100 to provide an output signal ZCD_COMP gated by a gate signal Gate LS.

[0130] A current digital-to-analog converter (DAC) can be designed to tune possible imbalances in circuits designed to calibrate positive and negative offset values. The solution provides a fast and small tunable current offset for the ZCD comparator.

[0131] Figure 18 The diagram in shows (again scaled against a common time abscissa t) possible time waveforms—from top to bottom: coil current Icoil; ZCD comparator output signal ZCD_COMP; and ZCD comparator quiescent current IQ_ZCD.

[0132] Figure 18 The graph shows that when operating in discontinuous current mode (DCM) at very light loads, the impact of the ZCD comparator quiescent current on the overall efficiency of the converter may not be negligible.

[0133] The system can thus be configured such that, when in ULP (ultra low power) mode, the ZCD converter can be switched off during the high impedance phase (HZ phase), leaving only the mirror bias prepolarization with very low current.

[0134] In fact, the ZCD converter can be switched at a time “t” after the ZCD edge. HOLD " and then shuts down completely. This time is found to be useful for low-side Vds detection.

[0135] Advantageously, Figure 15 and Figure 17 The counter 102 may be a synchronous up / down (UP / DWN) counter based on a flip-flop.

[0136] It can be configured (e.g. via an output multiplexer) to start up from a semi-dynamic state, with clamps (top and bottom - see Figure 16 ) can be used to combat unwanted periodic rotation of the count.

[0137] Various solutions can be implemented to measure the voltage Vds on the low side (node ​​SW).

[0138] Figure 19 An advantageous solution for low-side Vds sensing is detailed using a simple current comparator 200 coupled at node N to the current line from a current generator 202 to a MOSFET transistor 204 to "copy" (i.e., provide a copy of) the MOSFET transistor in the low-side stage LS Power.

[0139] The thresholds of comparator 200 (not to be confused with comparator 100) are not explicitly represented because the switching of comparator 200 can be determined by the turn-on threshold voltage Vth of the "body-drain" diode D1' of MOSFET transistor 204, which is of the same type (a "copy") as the MOSFET transistor of the low-side power stage LS Power (and therefore experiences the same temperature-induced variations).

[0140] like Figure 19 As shown in FIG, a MOSFET 206 (discussed further below) may be arranged between the node N and the replica MOSFET 204 to provide a voltage drop Vcas of, for example, 0.6V.

[0141] It is reasonable to expect that the replica sense transistor 204 (here implemented as a MOSFET transistor near the MOSFET transistor in the power stage LS Power) exhibits the same temperature\process variations as the threshold voltage of the body diode of the MOSFET transistor in the power stage LS Power.

[0142] like Figure 19 As shown in , when the voltage of the node SW is lower than the threshold voltage Vth of the body diode D1 of the replica MOSFET 204 (e.g., diode-connected via source-gate coupling), the body diode D1 therein is turned on and the current flowing therethrough is higher than the current from the current generator 202.

[0143] The sensitivity of the comparator 200 can be tuned according to the LS body diode characterization so that the output DIODE_ON from the comparator 200 will switch, giving the desired information. Furthermore, a latch can be provided to save the switching condition.

[0144] Once the ZCD comparator 100 switches, the power stage LS Power turns off (becomes non-conductive) and the node SW becomes a high impedance node.

[0145] This can generate spurious oscillations that can cause the diode comparator 200 to switch. Thus, the diode comparator can switch a short time (eg, less than 20 ns - see Figure 20 ) is activated and is shorted to ground GND via switch 208 (configured to be controlled via signal T1, as discussed below) when not activated.

[0146] Figure 21A 、 Figure 21B and Figure 21C Provided Figure 19, wherein transistor 206 is represented as transistor M2 in a current mirror arrangement including a mirror transistor M1 configured to be coupled to a supply rail Vpre (e.g., at 1.8V) and configured to be passed through by a current flowing through transistor M1 and mirrored into generator 202.

[0147] Run through Figure 21A 、 Figure 21B and Figure 21C , the gate-source voltages (ie, Vgs1 and Vgs2 ) of the transistors M1 and M2 (reference numeral 206 ) are maintained to satisfy the condition Vgs1 > Vgs2 .

[0148] Resistor R208 is also shown in series with switch 208 .

[0149] Figure 21A 、 Figure 21B and Figure 21C Refer to low-side Vds detection by considering three possible conditions:

[0150] SW>0( Figure 21A ): This is the Ton phase, in which the switch 208 (switch T1) is closed and the node N (OUTint) is “high”, and the signal DIODE_ON from the comparator 200 is equal to “0” (low).

[0151] SW<0( Figure 21B ): This is the Toff phase, where the switch 208 (switch T1) is open and the node N (OUTint) is “high”, and the signal DIODE_ON from the comparator 200 is equal to “0” (low).

[0152] SW<<0( Figure 21C ): This is the monitoring phase, where switch 208 (switch T1) is open and node N (OUTint) is "low", and the signal DIODE_ON from comparator 200 is equal to "1" (high). If SW>0 (negative coil current), then OUTint remains high.

[0153] exist Figure 21A During the Ton phase, the bias current is diverted to ground GND via resistor R208 through switch 208 (closed and therefore conducting) to obtain Vgs1>Vgs2; voltage SW>0 keeps diode D1 off (non-conducting) and signal Outint=high.

[0154] exist Figure 21B During the Toff phase, SW < 0, but has not yet reached a level sufficient to turn on the diode. A small portion of the associated bias current can begin to flow through the diode. The condition Vgs1 > Vgs2 results in the signal OUTint = high.

[0155] Note that once the Toff phase is entered, the (temporary) turn-on of the low-side diode is "masked" by the delayed signal from the delay circuit system. In fact, when entering the Toff phase, masking is provided at the end of the Ton phase: in that case, the diode is temporarily turned on (the low-side switch is turned on with positive current, and the small delay avoids undesired high-side and low-side cross-conduction between HS and LS: this has no specific motivation for the purpose of this article). Similarly, masking is provided at the end of the Toff phase, that is, when the diode is monitored: the former masking is used to ignore the start of the Toff phase, the latter masking is used for the purpose of monitoring at the end of the Toff phase.

[0156] Note further that the monitoring phase starts immediately after the low-side switch is turned off, which occurs (slightly) after the ZCD comparator trips (due to the propagation time of the ZCD trip information throughout the device frame). If the ZCD comparator does not trip (in the case of high currents), then monitoring will start anyway with the information related to the low-side shutdown, which is synchronized with the PWM signal from the bridge.

[0157] The drop in voltage SW - the current in the coil is still positive - causes signal DIODE_ON to switch from 0 to 1 (DIODE_ON=1). Signal OUTint is an analog signal that changes from a maximum value (eg, Vdd=1.8) to a low value, such as to cause switching of logic circuitry arranged downstream.

[0158] The failure of the voltage at node SW to drop or surge upwards indicates that the current has gone negative, so signal SW is not low enough, or even positive, so that switching of signal DIODE_ON from 0 to 1 does not occur. There is a slight uncertainty around zero, but this is not significant.

[0159] To summarize, in the embodiment as discussed herein: if the coil current is (still) positive, it pulls down the OUTint signal, which causes the comparator 200 to trip, i.e., DIODE_ON=1; conversely, if the signal SW does not drop or "bursts" upwards, then a coil current close to zero or negative must be handled, and the OUTint signal remains high.

[0160] Switch 208 remains open (non-conducting) throughout the monitoring phase and is closed again immediately after the monitoring phase ends.

[0161] Figure 22A and Figure 22B as well as Figure 23 This possible behavior is further illustrated in .

[0162] These figures show (again for a common abscissa time scale t) possible waveforms - Figure 22A and Figure 22B From top to bottom: the voltage at the node SW; the comparator output signal ZCD_Comp; and the signal OUTint entering the comparator 200;

[0163] These figures also show (again for a common abscissa time scale t) possible waveforms - Figure 23 From top to bottom in the figure: coil current Icoil (Icoil>0); comparator output signal ZCD_Comp; diode detection signal at node SW affected by pseudo oscillation (which may cause diode comparator 200 to switch); signal OUTint entering comparator 200; and DIODE_ON signal from comparator 200.

[0164] By highlighting the turning on (becoming conductive) of the diode in the transistor of the power stage LS Power during the Toff phase, masked via the inner mask, Figure 22A and Figure 22B The sequence of Ton, Toff and monitoring phases is depicted.

[0165] To further explain the ZCD detection in the solution as described in this article, by highlighting the high impedance phase HZ and the presence of masking and detection events, Figure 24A and Figure 24B Possible waveforms of the coil current Icoil (top) and the voltage at the node SW are shown (as before, for a common abscissa time scale t).

[0166] Again, review the quantitative data presented throughout the figures to support the description (such as Figure 24A The time durations of 50 nS and 200 nS shown in ) are merely exemplary and non-limiting.

[0167] Figure 24B Possible different signs (directions) of the current Icoil through the coil L are shown, such as for example being considered “negative” when the current Icoil flows from the inductor L into the power stage HS Power and being considered “positive” when the current Icoil flows from the power stage LS Power into the inductor L.

[0168] consider Figure 24A Based on the temporal behavior of the signal in , it is possible to keep the circuit active (biased or polarized and its output masked) during the Ton phase, while changing the circuit (making it operational) and ready to trigger (its output no longer regulated) during the Toff phase.

[0169] As discussed previously, the dead time introduced when the low side is turned on (the beginning of the Toff phase) to avoid unwanted cross-conduction between the high side and the low side is masked, while the dead time introduced when the low side is turned off (the end of the Toff phase) represents the correct detection phase of the diode comparator 200.

[0170] Based on the offset of the ZCD comparator, it is possible to detect whether the “zero” (actually non-zero) current in the power stage LS Power is positive or negative.

[0171] When the ZCD comparator 100 switches: in case of a positive coil current Icoil, the diode of the power stage LS Power will turn on (become conductive) and the voltage at the node SW will drop; and in case of a negative coil current Icoil, the diode of the power stage HS Power will turn on (become conductive) and the voltage at the node SW will remain positive (higher than Vin).

[0172] Thus, activation of the diode in the power stage LS Power (or the absence of such activation) can be used to check whether the ZCD comparator 100 switches early, late or “exactly” (in fact approximately) when the coil current Icoil is zero.

[0173] Therefore, this information can be found in Figure 15 , is used in the circuit topology represented in , as a feedback signal provided by Vds monitor block 103 to logic circuitry 104 to modulate (eg, via counter 102 and offset generator 100A) the offset of ZCD comparator 100 .

[0174] Note that real-time monitoring facilitates taking into account changes in external conditions, including temperature etc.: for this purpose, offset modulation can be applied in both directions.

[0175] Figure 25 and Figure 26 A possible implementation of the ZCD diode comparator 200 and associated circuitry is detailed, wherein the ZCD diode comparator 200 and associated circuitry are combined. Figure 19 Parts or components that have been described are denoted by the same reference symbols.

[0176] exist Figure 25 , transistor 208 is shown as being controllable via signal T1 ctrl to activate / deactivate the “replica” MOSFET transistor 204 . Figure 25 Reference numeral 210 in FIG. 2 indicates an output flip-flop associated with the comparator 200 to generate the signal DIODE_ON.

[0177] exist Figure 263 (wherein the individual curves in the figure share a common abscissa time scale), the top curve represents a possible time behavior of the voltage at the node SW (top curve) plus a possible corresponding time behavior of the signal ZCD_COMP (middle curve) and a delayed version thereof, which is marked ZCD_del (bottom curve) delayed by a monitoring time MT.

[0178] The signal labeled ZCD_del can in fact be considered as a "nominal" copy of the signal ZCD_COMP, whose switching time (rising edge) is delayed (eg, by a few nanoseconds) relative to the switching time (rising edge) of the signal ZCD_COMP.

[0179] It is intended to emphasize that the monitoring time MT corresponds to a time window that is synchronized with the switch-off time of the low-side power stage LS Power.

[0180] Thus, the low-side power stage LS Power can be turned off in response to the ZCD comparator 100 switching (when switching) or in response to the pulse width modulation signal (PWM) when the ZCD comparator 100 is not switching (see below in conjunction with Figure 29 Multiplexer circuit 304 described above).

[0181] Figure 27 is a functional block diagram (with Figure 15 and Figure 17 Considered in conjunction with FIG. 1 ), possible connections of the ZCD logic control circuitry 104 to the ZCD comparator 100 and the diode comparator 200 (in the Vds monitor level block 103) providing the signal ZCD_Comp (delayed as previously discussed during monitoring) are shown.

[0182] like Figure 27 As shown in , the logic circuit system 104 can be configured (in a manner known per se to those skilled in the art) to generate an add / subtract signal and a clock signal CLK_int to drive a counter 102, which changes (via an offset generator 100A) the offset of the ZCD comparator 100 based on the DIODE_ON signal from the diode comparator 200 and taking into account the ZCD_COMP signal.

[0183] like Figure 27 As shown in , in order to avoid undesirable calibration loss during detection of valley mode (highest peak current in the coil) and OVP (overvoltage protection on Vout) operating conditions, sufficient signals are processed by combinational logic to block the CLK_int signal and prevent the counter from changing.

[0184] Advantageously, logic circuitry 104 may be configured to implement an adaptive evolution of the ZCD comparator offset as a function of operating conditions according to the following Table 1, which illustrates “Adaptive Evolution of the ZCD Comparator Offset”:

[0185] ZCD_Comp DIODE_ON CLK_int UP_DOWN 0 0 run 1 0 1 stop not give a damn about 1 0 run 1 1 1 run 0

[0186] The first row of the table refers to the condition where the "native" offset of the ZCD comparator 100 is so negative that no tripping will occur (at least not during the entire Toff period). At the same time, the coil current becomes negative, so the diode comparator 200 cannot provide any useful information: this is Figure 28 The third time behavior shown in (starting from the left).

[0187] The second row in the table refers to continuous current mode (CCM), where the ZCD comparator 100 does not trip when the coil current is positive (DIODE_ON=0) and far from zero. When this condition is detected, the signal CLK_int stops and the most recently calibrated offset is stored to prevent undesired loss of calibration of the counter. Figure 28 The last, rightmost temporal behavior shown in .

[0188] The third row in the table refers to the conditions under which zero crossing detection will correspond to negative coil current. Figure 28 The first, leftmost temporal behavior shown in .

[0189] The fourth row in the table refers to the conditions under which zero-crossing detection will correspond to a positive coil current. Figure 28 The second time behavior shown in (starting from the left).

[0190] Figure 28 The horizontal solid line in represents the ideal zero line of the coil current (Icoil=0).

[0191] The first row in the table ( Figure 28 ) identifies a condition where the ZCD comparator 100 does not switch (eg, for some reason, it has a very high negative offset).

[0192] Therefore, the shutdown of the low-side power stage LS Power (and the consequent start of the Ton phase) when the current Icoil is already negative responds to the following in conjunction with Figure 29 Pulse Width Modulated Signal (PWM) described: As illustrated herein, the system can be configured as a synchronous system, wherein the ZCD comparator 100 is configured to (only) anticipate a possible shutdown of the low side power stage LS Power before commanding a shutdown of the low side power stage LS Power by a subsequent edge of the PWM signal.

[0193] In that case (the ZCD comparator is more unbalanced than in the case of negative coil current, which means that the "natural" offset is higher than the negative peak of the current ripple), the diode comparator 200 does not switch (negative current), and the ZCD comparator 100 also does not switch (with a rather negative natural offset). Under these conditions, the system will try to change the comparator offset (i.e., the comparator threshold) in order to make the comparator 100 trigger or switch before the subsequent edge of the PWM signal turns off the low-side power stage LS Power, i.e., to make the comparator 100 trigger or switch so that the negative current is closer to zero.

[0194] Therefore, a situation will arise where the ZCD comparator will start toggling or switching, reaching the condition in the third row of the table ( Figure 28 If the counter 102 still has a "word available", it will cause the comparator 100 to trigger or switch earlier than the Icoil current crosses zero, until it is as close to the optimal threshold as possible (this "ideal" condition is shown in the second and third rows of the table). Figure 28 (depicted in the rightmost temporal behavior shown in ).

[0195] As previously discussed, the offset (threshold) correction action performed at each pulse of the clock signal CLK_int will cause the ZCD comparator 100 to trigger or switch, reaching the condition in the fourth row of the table ( Figure 28 ), so that the comparator 100 triggers or switches later than the Icoil current crosses zero.

[0196] Figure 29 is a block diagram of exemplary circuitry configured to test a self-calibration loop, wherein block 1000 hosts a calibration process with associated circuitry to provide a test bench that facilitates testing according to Figure 30A 、 Figure 30B 、 Figure 31 and Figure 32A 、 Figure 32B The test circuit behavior.

[0197] Note that, Figure 29 The block 1000 in FIG. 1 represents the entire system, which includes a ZCD comparator, a diode comparator, and an offset generator with an UP / DWN counter.

[0198] exist Figure 29 In FIG, the load driven via the coil L is represented by a capacitor C referenced to the ground GND, which has a voltage Vout applied via the coil L.

[0199] exist Figure 29In operation of the arrangement shown in , in response to the unit 1000 providing the signal ZCD_COMP having a “high” value, this is used to start a new Ton phase (given by the astable block 300) of constant duration and enter a Toff phase while waiting for the self-calibrating ZCD circuit to trip at the subsequently newly calibrated threshold.

[0200] During the initial simulation phase, the current through the coil is loaded by the multiplexer 304. For example, the multiplexer 304 is configured to apply a pulse width modulated signal PWM to the drivers 302A and 302B, the pulse width modulated signal PWM being derived from the clock signal CLK_CP received at the input terminal labeled 0 of the multiplexer 304 (generated in a manner known per se to those skilled in the art, which also facilitates coil pre-charging).

[0201] After a period of time (e.g., allowing the coil current to increase to 10A), the multiplexer 304 switches to the input marked 1 and the loop begins normal operation, aiming to achieve the calibrated threshold, with system control handed over to the ZCD comparator 100, as previously discussed.

[0202] like Figure 29 As shown in , the control terminals (gates in the case of field effect transistors such as MOSFET transistors) in the power stage HS Power and the power stage LS Power are driven via respective drivers 302A and 302B, wherein a multiplexer 304 may be arranged between the oscillator 300 and the drivers 302A, 302B.

[0203] exist Figure 29 , the dashed line between block 1000 and the low-side driver 302B illustrates the low-side shutdown, followed (immediately) by the high-impedance (HZ) phase. After a short delay (the duration of the HZ phase), the signal PWM_COMP causes the Ton portion of the PWM signal to be applied. Note that this delay should not be confused with the masking during the monitoring period discussed previously: As previously mentioned, Figure 29 The block 1000 in FIG. 1 represents the entire system, which includes a ZCD comparator, a diode comparator, and an offset generator with an UP / DWN counter.

[0204] Figure 30A 、 Figure 30B 、 Figure 31 、 Figure 32A and Figure 32B As shown, the calibration process described herein results in Figure 30A 、 Figure 30B 、 Figure 31 、 Figure 32A and Figure 32B Expected behavior presented in .

[0205] Figure 30A and Figure 30B The case without calibration (without offset tuning) is compared with the case with offset tuning as disclosed herein by the delay t Delay The possible comparisons affect the operation of the ZCD comparator.

[0206] As discussed in the introductory part of this description, without calibration, based on the relationship dI / dT=V OUT / Coil, the decrease in Vout results in a decrease in the slope of Icoil during Toff.

[0207] Two possible temporal behaviors of Icoil (marked as Icoil@Vout1 - dashed line - and Icoil@Vout2 - continuous line) lead to ZCD detection errors, as shown in Figure 30A depicted at the far right end of .

[0208] Figure 30A and Figure 30B To facilitate understanding, for the same time delay of the ZCD comparator, this results in two different current thresholds for two different Vout values: this is visible at the far right of the diagram.

[0209] In the case of calibration with Vout1, the circuit will add and offset in such a way as to anticipate comparator tripping (which causes the ZCD comparator to trigger earlier - see arrow marked 1) and provide relevant information after a delay time so that the current will be (very close to) zero at this time.

[0210] If the output voltage changes from Vout1 to Vout2, the same offset will no longer apply and the circuit will correct the offset in such a way that it provides relevant information after a delay time so that the current will be (very close to) zero again at this time and compensate for the comparator delay with a lower slope.

[0211] In both cases, for both Icoil@Vout1 and Icoil@Vout2, the zero crossing is detected at zero value to combat the negative effects, while the delay t delay Not relevant.

[0212] In various applications, reducing the size (area) of the power stage can be beneficial to improve efficiency when the load is low.

[0213] like Figure 31 As shown in , this can have an impact on the ZCD threshold.

[0214] exist Figure 31, illustrated from top to bottom are possible time behaviors (for a common abscissa time scale): current Icoil; two possible outputs (Vds monitoring levels) from the SW detector circuitry SW_1module - dashed line and SW_2module - continuous line; and the ZCD_Comp signal.

[0215] In the case where only one power module's load is required, the size (area) of the power stage can be reduced accordingly, so that the ZCD threshold can be located at point A for a small offset of the ZCD comparator 100 .

[0216] If a larger load is to be considered, the size of the power stage is increased to improve efficiency. The device may still be in discontinuous current mode (DCM), and the ZCD threshold may be located at point B, which is different from point A.

[0217] like Figure 32A As depicted in , without calibration, the ZCD threshold changes from A to B when the power stage size changes.

[0218] In contrast, Figure 32A The beneficial effect calibration (offset adjustment) is shown with the ZCD threshold increasing (steps marked 1 ) and with the ZCD threshold decreasing (steps marked 1 ).

[0219] In both cases, for both Icoil@Vout1 and Icoil@Vout2, the zero crossing is detected at zero value to combat the negative effects regardless of load and power module changes.

[0220] The effect of a change in the number of modules (in the example considered here, from one to two modules, resulting in a decrease in Ron) after the first calibration has been achieved (see point A) is a recalibration of the counter word in such a way that the new calibration point B is close to point A (by lowering it).

[0221] In a solution as disclosed herein, the logic circuitry 104 may be configured to operate in such a manner (see also Table 1 above) that the ZCD comparator 100 begins operating uncalibrated and is then calibrated using the ZCD calibration stored by the counter 102 as it evolves and responds to a transition from continuous current mode to discontinuous current mode (CCM to DCM) operation.

[0222] The solutions described herein provide, for example, a zero current detector (ZCD) circuit for a DC-DC converter. Although these solutions are advantageously applied to buck converters, they can also be applied to boost converters and inverting ("buck-boost") topologies.

[0223] The solution as described herein employs a continuous “on-the-fly” offset (threshold) calibration that facilitates optimizing the ZCD threshold (and therefore system efficiency) for different application scenarios, primarily with respect to comparator delays.

[0224] The solution as described herein avoids complex structures, thereby mitigating the effects of possible production proliferation.

[0225] The solution as described herein involves a ZCD threshold that has a small periodic variation in steady state (a possible effect of cycle-by-cycle calibration). Changes in the input voltage Vin and the output voltage Vout can trigger a temporary change in the ZCD threshold that is corrected within a few clock cycles.

[0226] In the exemplary case disclosed herein, adjusting the offset of the comparator 100 involves increasing the offset (by increasing the comparator threshold) in response to finding that the voltage at the node SW drops to indicate a negative current Icoil through the coil L when the low-side power stage LS Power is turned off; and decreasing the offset (by decreasing the comparator threshold) in response to finding that the voltage at the node SW remains stable or increases to indicate a near-zero or positive current Icoil through the coil L when the low-side power stage LS Power is turned off.

[0227] Those skilled in the art will readily appreciate that the embodiments described and illustrated herein relate to possible signal / component polarities (positive / negative) and relative relationships (higher / lower, earlier / later) that are purely exemplary and not in themselves binding.

[0228] For example, increasing / decreasing the comparator offset (comparator threshold) may occur in a manner complementary to the exemplary embodiments shown herein: to name just one possible example, such as Figure 11 and Figure 28 The offset (threshold) correction actions marked UP and DOWN in the figures such as are suitable for implementing them with opposite signs, while still aiming to adapt the thresholds (offsets) of the ZCD comparator 100 so that the tripping or switching time of the voltage comparator 100 matches the actual zero-crossing level of the current through the coil L (i.e., Icoil) as closely as possible.

[0229] Moreover, in various embodiments, the high-side power stage HS Power and the low-side power stage LS Power may be interchanged and / or have different polarities, with the positive and negative directions of the current correspondingly reversed as shown in FIG. 24 .

[0230] Regardless of the specific details of the converter / ZCD detector implementation, the various solutions discussed herein contemplate zero-crossing detection, with the ZCD circuit 10 configured to issue a ZCD detection signal ZCD_COMP indicative of a zero-crossing event of the coil current Icoil through the converter coil L by detecting the voltage at a voltage detection node (Vds of the low-side power stage LS Power), such as a node SW configured to be coupled to the coil L at a current supply node for the coil L.

[0231] Regardless of the specific details of the converter / ZCD detector implementation, the various solutions discussed herein include a ZCD comparator 100 having a ZCD input node coupled to a voltage sense node SW and configured to issue a ZCD detection signal ZCD_COMP in response to the voltage at the voltage sense node SW crossing a threshold of the ZCD (voltage) comparator, which threshold is selectively tunable “on the fly” via, for example, block 100A.

[0232] The threshold tuning circuitry 102 of the ZCD comparator 100 is configured to selectively change the threshold of the ZCD comparator 100: in a first direction (e.g., by increasing the threshold), wherein the voltage at the voltage detection node SW crossing the ZCD comparator threshold is delayed in time; this may be in response to a feedback signal (e.g., Figure 15 The signal UP / DWN in the example 1 has a first value (eg, UP), see for example Figure 9A and in a second direction (eg, by decreasing the threshold), wherein the voltage at the voltage detection node SW crosses the ZCD comparator threshold value is advanced in time; this may be in response to a feedback signal (eg, Figure 15 The signal UP / DWN in the example has a second value (eg, DWN), see for example Figure 9B .

[0233] Such as Figure 19 、 Figure 21A 、 Figure 21B and Figure 21C As illustrated in the figures such as , the voltage detection circuit system 104 can be coupled to the voltage detection node SW to detect the presence (occurrence) of a voltage transition at the voltage detection node SW, which indicates that the ZCD detection signal ZCD_COMP is issued before the zero-crossing event of the coil current Icoil.

[0234] This possible behavior is Figure 7A, where the voltage transition is represented by the turn-on of the body diode BD D1 of the low-side MOSFET transistor LS Power, which indicates the fact that the ZCD detection signal ZCD_COMP is issued before the zero-crossing event of the coil current Icoil: Figure 7A As shown in , the coil current Icoil is (still) positive at the rising edge of the signal ZCD_COMP.

[0235] In this case, the first value may be used to generate a feedback signal through the threshold tuning circuitry 102 of the ZCD comparator to correct the comparator threshold / offset in such a way that the response is delayed in time and, at a subsequent clock cycle, the signal ZCD_COMP is issued at the actual zero crossing of the current Icoil in the coil L (or generally closer to that point) (see Figure 9A on the right-hand side of the ).

[0236] Such as Figure 19 、 Figure 21A 、 Figure 21B and Figure 21C The voltage detection circuit system 104 illustrated in the figures such as can also be coupled to the voltage detection node SW to detect the absence (non-occurrence) of a voltage transition at the voltage detection node SW, which indicates that the ZCD detection signal ZCD_COMP is issued before the zero-crossing event of the coil current Icoil.

[0237] This can be Figure 8A The possible behavior is shown in the case where Figure 7A The voltage transition BD D1 is replaced by the turn-on of the body diode BD D2 of the high-side MOSFET transistor HS Power, which indicates the fact that the ZCD detection signal ZCD_COMP is delayed with respect to the zero-crossing event of the coil current Icoil: Figure 8A As shown in , the coil current Icoil is (already) negative at the rising edge of the signal ZCD_COMP.

[0238] In this case, the feedback signal through the threshold tuning circuitry 102 of the ZCD comparator may be generated with the second value to correct the comparator threshold / offset in such a way that, in response to the advance in time, at a subsequent clock cycle, the signal ZCD_COMP is issued at the actual zero crossing point of the current Icoil in the coil L (or generally closer thereto) (see Figure 9B on the right-hand side of the ).

[0239] In either case, signal ZCD_COMP is issued at a time that more faithfully mirrors the actual zero crossing of current Icoil in coil L.

[0240] Various embodiments may represent standalone components that are intended only to be coupled to an associated load by an end user and / or only during use of the converter.

[0241] Therefore, the associated load (such as Figure 29 ) may not represent part of an embodiment.

[0242] Without affecting the underlying principle, the details and embodiments may vary, even significantly, with respect to what is described merely by way of example, without departing from the scope of protection.

[0243] The claims are an integral part of the technical teaching provided herein with respect to the exemplary embodiments.

[0244] The scope of protection is determined by the appended claims.

Claims

1. A converter, comprising: High-side switching transistor; a low-side switching transistor coupled to the high-side switching transistor at a switching node; a coil having a first terminal coupled to the switch node, wherein the coil is configured to be passed through by a coil current in response to turning on and off the high-side switching transistor and the low-side switching transistor; a current source configured to provide a sensing current to the sensing node; as well as A circuit configured to monitor a voltage drop across the low-side switching transistor, comprising: a first transistor having a drain coupled to the sense node and a source coupled to an intermediate node; a second transistor having a source coupled to the intermediate node and a drain coupled to the switch node, wherein a gate of the second transistor is coupled to the intermediate node; a switch disposed between the intermediate node and a reference node, wherein when the switch is actuated, the sense current flowing through the first transistor flows toward the reference node, and wherein when the switch is de-actuated, the sense current flowing through the first transistor flows toward the switch node through the second transistor; and A sense comparator has an input coupled to the sense node and is configured to generate an output signal having a first logic state in response to a voltage transition at the switch node and a second logic state in response to the absence of a voltage transition at the switch node.

2. The converter according to claim 1, wherein The second transistor is a copy of the low-side switching transistor.

3. The converter according to claim 2, wherein When the replica second transistor is activated, the switch is activated.

4. The converter according to claim 1 further comprises a zero-crossing detection (ZCD) circuit configured to generate a ZCD detection signal indicative of a zero-crossing event of the current flowing through the coil, wherein the output signal of the sense comparator is input to the ZCD circuit, and wherein a ZCD comparator threshold of the ZCD circuit is selectively adjustable in response to the output signal.

5. The converter according to claim 4, wherein The ZCD circuit includes a threshold tuning circuit system, which is configured to selectively change the ZCD comparator threshold in zero crossing detection in a first direction in response to a first logic state of the output signal, and selectively change the ZCD comparator threshold in a second direction in response to a second logic state of the output signal.

6. The converter according to claim 5, wherein The first direction causes the zero-crossing detection of the ZCD circuit to be delayed in time, and wherein the second direction causes the zero-crossing detection of the ZCD circuit to be advanced in time.

7. The converter according to claim 5, wherein The first direction causes the zero-crossing detection of the ZCD circuit to be advanced in time, and wherein the second direction causes the zero-crossing detection of the ZCD circuit to be delayed in time.

8. The converter according to claim 5, wherein The threshold tuning circuitry of the ZCD comparator includes an up / down counter configured to increase and decrease the ZCD comparator threshold in response to a first logic state and a second logic state of the output signal.

9. The converter according to claim 1, wherein When the second transistor is activated, the switch is activated.

10. The converter according to claim 1, wherein The circuit configured to monitor the voltage drop further includes: a further current source configured to supply current to a further intermediate node; and A third transistor has a drain and a gate coupled to the further intermediate node and a source coupled to the reference node.

11. A device comprising: The converter according to claim 1; as well as An electrical load is coupled to the coil.

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