Fast protection switching method and device for short-distance optical network

Abstract

According to an embodiment of the present disclosure, a fast protection switching method and apparatus for a short-distance optical network are provided. The method includes determining whether the state of a received data signal is valid; if the state of the first data signal is invalid, the first clock obtained when the received data signal changes from valid to invalid enters a clock frequency freeze state, and a predetermined sequence is sent to the downstream module with a second clock, the state of the first data signal maintains an invalid stage, and the frequency of the second clock remains unchanged; if the state of the first data signal is valid and the state of the second data signal is invalid, the clock frequency freeze state is entered, and when the state of the first data signal maintains a valid stage, normal service data is sent to the downstream module, and the frequency of the second clock changes according to the input clock frequency of the receiving end. This method can quickly and stably complete service switching when a fiber optic link fault is detected, avoiding the timeout problem in the protection switching process of the short-distance optical network.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to a method and device for fast protection switching in a short-distance optical network. Background Art

[0002] As the current mainstream communication transmission method, fiber-optic communication has been widely adopted in various communication networks, including backbone networks and metropolitan area networks, due to its advantages such as high bandwidth, long distance, low loss, and strong resistance to electromagnetic interference. To ensure the application of optical networks in high-reliability applications and prevent communication interruptions caused by link failures or equipment anomalies, network equipment backup is required to avoid serious economic and social impacts.

[0003] To this end, optical networks can be deployed with protection switching mechanisms. When a fault occurs, these mechanisms, through real-time fault detection, traffic switching, and coordinated processing between source and sink nodes, enable services to be quickly restored by switching from the working channel to the protection channel. Carrier-grade protection switching technology must ensure that service interruption does not exceed 50 milliseconds, minimizing service damage. With the rapid development of services such as 5G communications, high-definition video, big data, and artificial intelligence, the demand for network reliability in short-haul optical communication networks, such as data center networks, edge aggregation access networks, and carrier access layers, is also increasing.

[0004] However, in short-haul optical networks, due to the need to simplify network architecture and control costs, complex dedicated protection switching equipment is often not deployed. This leads to problems such as slow switching response and switching timeouts in the existing protection switching mechanism in actual applications, seriously affecting the network's service quality and user experience. Summary of the Invention

[0005] Currently, there is an urgent need to propose a rapid protection switching method and apparatus for short-haul optical communication networks that can quickly and stably complete service switching when a fiber link failure is detected, thereby improving the service assurance capabilities of data centers and access networks in high-bandwidth, high-reliability scenarios. To address the problems existing in the prior art, embodiments of the present disclosure provide a rapid protection switching method and apparatus for short-haul optical networks, which are applicable to short-haul optical communication networks and can quickly and stably complete service switching when a fiber link failure is detected.

[0006] A first aspect of an embodiment of the present disclosure provides a fast protection switching method for a short-haul optical network. The method includes determining whether the state of a received data signal is valid; if the state of a first data signal is invalid, receiving a first clock obtained when the data signal changes from valid to invalid, entering a clock frequency freeze state, and sending a predetermined sequence to a downstream module using a second clock, wherein the state of the first data signal remains in the invalid phase and the frequency of the second clock remains unchanged; if the state of the first data signal is valid and the state of the second data signal is invalid, entering a clock frequency thaw state, and while the state of the first data signal remains in the valid phase, sending normal service data to the downstream module, wherein the frequency of the second clock changes according to the input clock frequency of the receiving end; wherein the state of the first data signal is the state of the currently received data signal, and the state of the second data signal is the state of the data signal received at the last moment. The short-haul optical communication network in the present disclosure may include a data center network, a carrier access network, etc. The communication distance may be within tens of kilometers, for example, within 20 kilometers. The clock frequency freeze state indicates that the clock frequency remains unchanged, while the clock frequency thaw state indicates that the clock can converge or change as needed.

[0007] Optionally, entering the clock frequency freeze state includes freezing the first frequency deviation between the first clock obtained when the data signal changes from valid to invalid and the local clock of the receiving end to maintain the first frequency deviation unchanged, and thawing the clock frequency freeze state includes thawing the first frequency deviation so that the clock recovery module recovers the clock signal according to the received data signal until it is locked.

[0008] The method disclosed herein continuously monitors the status of the data signal to determine whether a fault has occurred in the working channel and to judge whether to switch from the working channel to the protection channel. Once the current data signal status is invalid, it indicates that the link of the working channel has failed, and protection switching must be performed immediately. The current data signal status is valid and the status of the saved data signal at the previous moment is invalid, indicating that the failed working channel is switching to the protection channel. During this period, the communication device needs to return to the normal working mode. The clock information is frozen when a fault occurs in the working channel, and the clock information is unfrozen when switching to the protection channel. The clock recovery module can converge based on the sum of the local clock and the first frequency deviation (i.e., the frozen clock information), thereby shortening the time required for clock locking.

[0009] Furthermore, when the data signal is invalid, a predetermined sequence is sent to the downstream module using an unchanged clock. This ensures that the data signal sent by the transmitter is not affected by the data signal or its clock received by the receiver, effectively isolating the transmission path from upstream link failures. This allows the downstream module to operate normally, eliminating the need to re-perform recovery processes such as link reestablishment and clock and parameter convergence after service recovery, significantly improving link recovery efficiency and system response speed.

[0010] Optionally, according to the first aspect of the embodiment of the present disclosure, the second clock may be a local clock or a frequency offset adjusted clock, and the frequency offset adjusted clock is the sum of a second frequency offset obtained according to the first frequency offset and the local clock of the transmitting end.

[0011] Optionally, according to the first aspect of the embodiment of the present disclosure, if the status of the first data signal is invalid, entering the clock frequency freeze state also includes the transmitting end freezing the received second frequency offset to maintain the second frequency offset unchanged, the second frequency offset is obtained based on the first frequency offset, and the second clock is equal to the sum of the local clock of the transmitting end and the second frequency offset; if the status of the first data signal is valid and the status of the second data signal is invalid, unfreezing the clock frequency freeze state also includes, after the clock signal is locked, unfreezing the second frequency offset, and the transmitting end sends normal business data to the downstream module with a normally working transmitting clock.

[0012] Freezing the second frequency offset of the transmitting end of the communication device makes the transmitting clock close to the transmitting clock in the normal working state, which can shorten the time required for the communication device to recover the normal working state.

[0013] Optionally, according to the first aspect of the embodiment of the present disclosure, if the state of the first data signal is invalid, one or more parameters of the equalizer are frozen so that the one or more parameters of the equalizer maintain the convergence result when the state of the data signal changes from valid to invalid.

[0014] Optionally, according to the first aspect of the embodiment of the present disclosure, if the state of the first data signal is valid and the state of the second data signal is invalid, the equalizer converges based on the frozen one or more parameters.

[0015] When the difference in channel conditions is not greater than a threshold, the time for equalizer parameter convergence can be significantly shortened by freezing the equalizer parameters.

[0016] Optionally, according to the first aspect of the embodiments of the present disclosure, determining whether the status of the received data signal is valid includes detecting any one of the following or a combination thereof: the power or average power of the data signal, the amplitude or average amplitude of the data signal, the number of symbol transitions of the data signal, a signal loss indication signal, and a phase-locked loop loss indication signal. Optionally, one or more of the power or average power of the data signal, the amplitude or average amplitude of the data signal, and the number of symbol transitions of the data signal can be compared with their respective predetermined thresholds to determine whether a working path has failed. Optionally, the signal loss indication signal and the phase-locked loop loss indication signal can be used separately to determine whether a working path has failed.

[0017] Optionally, according to the first aspect of the embodiment of the present disclosure, the predetermined sequence is a pseudo-random sequence.

[0018] A second aspect of an embodiment of the present disclosure provides a communication device, comprising a receiving end, configured to receive a data signal from a working channel or a protection channel and determine whether the state of the data signal is valid; a clock recovery module, configured to recover a clock signal from the received data signal; and a transmitting end, configured to send data to a downstream device, wherein if the receiving end determines that the state of a first data signal is invalid, the communication device enters a clock frequency freeze state based on a first clock obtained when the data signal changes from valid to invalid, and sends a predetermined sequence to the downstream module using a second clock, wherein the state of the first data signal remains in an invalid stage and the frequency of the second clock remains unchanged; if the receiving end determines that the state of the first data signal is valid and the state of the second data signal is invalid, the communication device enters a thawed clock frequency freeze state, and when the state of the first data signal remains in a valid stage, the transmitting end sends normal service data to the downstream module, and the frequency of the second clock changes according to the input clock frequency of the receiving end, wherein the state of the first data signal is the state of the currently received data signal, and the state of the second data signal is the state of the data signal received at the previous moment.

[0019] Optionally, according to the second aspect of the embodiment of the present disclosure, entering the clock frequency freeze state includes freezing the first frequency deviation between the first clock obtained when the data signal changes from valid to invalid and the local clock of the receiving end to maintain the first frequency deviation unchanged, and thawing the clock frequency freeze state includes thawing the first frequency deviation so that the clock recovery module recovers the clock signal according to the received data signal until it is locked.

[0020] Optionally, according to the second aspect of the embodiment of the present disclosure, if the receiving end determines that the status of the first data signal is invalid, the communication device enters the clock frequency freeze state and also includes the transmitting end freezing the second frequency offset received based on the first frequency offset to maintain the second frequency offset unchanged, the second frequency offset is obtained based on the first frequency offset, and the second clock is equal to the sum of the local clock of the transmitting end and the second frequency offset; if the receiving end determines that the status of the first data signal is valid and the status of the second data signal is invalid, the communication device enters the unfrozen clock frequency freeze state and also includes the transmitting end unfreezing the second frequency offset after the clock signal is locked, so that the transmitting end sends normal business data to the downstream module with a normally working transmitting clock.

[0021] Optionally, according to the second aspect of the embodiment of the present disclosure, the communication device also includes multiple equalizers and an equalizer parameter freezing module, and the equalizer parameter freezing module freezes one or more parameters of the multiple equalizers so that they maintain the convergence result when the data signal changes from valid to invalid; wherein if the receiving end determines that the state of the first data signal is valid and the state of the second data signal is invalid, the equalizer converges based on the frozen parameters.

[0022] According to a third aspect of the present disclosure, a communication device is provided, comprising a processor and a memory, wherein the memory stores program code; the processor is configured to read and execute the program code stored in the memory to implement the method described above.

[0023] The method and apparatus for protection switching provided by the embodiments of the present disclosure can meet the high bandwidth and high reliability requirements of short-distance, high-speed access networks such as data center networks and operators, and can quickly switch to the protection channel when a working channel fails, thereby avoiding timeout of service interruption.

[0024] It is not necessary to achieve all of the advantages described above simultaneously when implementing any device or method of the present disclosure. Other features and advantages of the present disclosure will be described in the following embodiments and will become apparent from the embodiments or learned through practice of the present disclosure. The objectives and advantages of the embodiments of the present disclosure can be achieved and obtained through the structures specified in the description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0026] Figure 1A schematic flow chart of a fast protection switching method for a short-distance optical network according to an embodiment of the present disclosure is shown;

[0027] Figure 2 A schematic flow chart of a fast protection switching method for a short-distance optical network according to another embodiment of the present disclosure is shown;

[0028] Figure 3 A schematic flow chart showing a method for restoring a normal working mode during a fast protection switching process according to an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic flow chart showing a method for restoring a normal working mode during a fast protection switching process according to another embodiment of the present disclosure is shown;

[0030] Figure 5 A schematic structural diagram of a communication device for a short-distance optical network according to an embodiment of the present disclosure is shown;

[0031] Figure 6 A schematic structural diagram of a communication device for a short-distance optical network according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not necessarily indicate a quantity limitation. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] Figure 1 A schematic flow chart illustrates a method 10 for rapid protection switching in a short-haul optical network according to an embodiment of the present disclosure. In step 11, a receiving end of a communication device receives a data signal via the optical network. In step 12, the receiving end of the communication device detects the received data signal to determine whether it is valid. If the data signal is invalid, it indicates a fault in the working path, and the communication device will be switched to the protection path.

[0035] The communication device disclosed herein can be used in high-speed communication systems, particularly short-distance high-speed communication systems, and may include, for example, a SerDes (serializer / deserializer) transceiver, a direct modulation / direct detection DSP (digital signal processing) transceiver, and the like.

[0036] In this embodiment, the detection process for determining whether a data signal is valid may include the following: the receiving end may analyze a segment of the received data signal and determine whether the data signal is valid based on one or more characteristics of the signal. These characteristics may include the power and / or average power, amplitude and / or average amplitude, number of symbol transitions, etc. of the segment. The detection process may include comparing one or more of these characteristics with corresponding thresholds. For example, if the detected average received power is lower than a preset threshold, the data signal is determined to be invalid; if the amplitude is lower than a preset threshold, it may indicate signal attenuation or link interruption, and may also be considered an invalid signal; if the number of symbol transitions is lower than a set threshold (e.g., less than a certain number per unit time), the data may be considered to be in a static or locked state and may also be considered invalid data. Any of these parameters or a combination thereof can be used to determine signal validity to meet the requirements of false alarm rate and switching sensitivity in different scenarios.

[0037] In some optional implementations, the signal validity determination can also be performed in conjunction with status information from upstream modules. For example, the receiving end can detect indication signals output by its upstream receiving module or optical module, such as loss of signal (LOS) or phase-locked loop (PLL) loss of lock (LOL) indicators. If any of these conditions are detected, the currently received data can be directly determined to be invalid.

[0038] The communication device generates signal status information based on the received data signal detection results. The signal status information saved at the previous moment can indicate the status of the data signal at the moment before the current moment. The signal status information indicates whether the currently received signal is valid (for example, signal status information "1" indicates valid, and signal status information "0" indicates invalid). Optionally, the signal status information may also include two flag fields: a signal valid flag and a signal invalid flag. For example, when the signal is valid, the signal valid flag is set to 1, and the signal invalid flag is set to 0; when the signal is invalid, the signal valid flag is set to 0, and the signal invalid flag is set to 1. The communication device saves the signal status information at the previous moment, which indicates the signal status at the previous moment (i.e., the previous detection cycle). Similarly, the single flag or dual flag method described above can be used to indicate the valid and invalid states of the signal. For example, when the dual flag method is used, the signal status information at the previous moment may include the signal valid flag at the previous moment and the signal invalid flag at the previous moment.

[0039] If the signal is determined to be invalid in step 12, i.e., a link problem has occurred and protection switching is required, the process proceeds to step 14. In step 14, since the signal status information indicates an invalid signal, the process enters fast protection switching mode. At this point, at least the clock information is frozen, ensuring that subsequent output clock information remains unchanged.

[0040] Specifically, the receiving end of the communication device freezes the first frequency offset Δf between the clock signal recovered by the clock recovery module (CDR) and the receiving end's local clock signal. This means that the first frequency offset Δf remains unchanged, resulting in a clock signal equal to the sum of the receiving end's local clock and the first frequency offset Δf. In this case, the clock recovery module no longer dynamically adjusts the clock frequency based on the input data, but instead maintains the same clock frequency and phase as when the signal transitions from valid to invalid.

[0041] The first frequency offset after freezing is obtained when the signal transitions from valid to invalid (i.e., immediately after the data signal is detected to be invalid). This represents the output frequency offset during clock lock, and therefore can differ from the frequency offset recovered from received data during normal operation. This offset is typically within a few hundred hertz, well within the acceptable range of system design. Freezing the frequency offset of the receiving clock signal can shorten the time required for clock convergence when the communication device resumes normal operation.

[0042] In a communication device, the clock recovered by the clock recovery module is transmitted to its transmitter. In this embodiment, the first frequency offset can be transmitted to the transmitter. Optionally, in step 15, the transmitter receives a second frequency offset Δf' based on the first frequency offset Δf and freezes the second frequency offset. The second frequency offset of the transmitter is derived based on the first frequency offset, but is not necessarily equal to the first frequency offset. Due to influences such as noise in the transmission channel from the receiver to the transmitter, the first frequency offset may change when it is transmitted to the transmitter. Furthermore, the first frequency offset can be modified based on the needs of the transmit clock when it is transmitted to the transmitter. For example, if the transmit clock frequency of the transmitter is a divided frequency of the clock of the data signal of the receiver, the local clock frequency of the transmitter and the second frequency offset will also be modified accordingly. For example, the local clock of the transmitter can be a corresponding divided frequency of the local clock of the receiver, and the second frequency offset will also be divided based on the first frequency offset. Compared to the local clock of the receiver, freezing the second frequency offset can further shorten the time required for the communication device to resume normal operation.

[0043] The manner of freezing the clock information may include, but is not limited to, storing the clock information to be frozen in a register, maintaining the locked frequency of the clock recovery module, and the like.

[0044] In step 16, the transmitter of the communication device switches the data signal sent to the downstream module to predetermined data. For example, this predetermined data can be a pseudo-random bit sequence (PRBS) or a predetermined specific sequence, and transmits the predetermined sequence to the downstream module at a constant clock frequency. This clock frequency can be a local clock or a frequency offset-adjusted clock. The frequency offset-adjusted clock is equal to the sum of the second frequency offset and the local clock of the transmitter. The data signal sent by the transmitter is not affected by invalid data signals received by the receiver or the clock of the data signal, thus isolating the transmission path from upstream link failures. Furthermore, this process ensures that the physical link between the communication device and the downstream module remains normal during protection switching. This allows the downstream module to operate normally, eliminating the need to re-perform recovery processes such as link reestablishment and clock and parameter convergence after service restoration. This significantly improves link recovery efficiency and system response speed.

[0045] Back to Figure 1 , if the signal status information indicates that the signal is in a valid state, then go to step 13 and continue to determine whether the current state is entering a valid state from an invalid state. In step 13, determine whether the signal status information recorded at the previous moment is valid. If the result is valid, it means that the signal was previously in a valid state, and the communication device remains in normal working mode. If the current signal status information indicates that the signal is valid, and the signal status information at the previous moment indicates that the data signal at the previous moment was in an invalid state, then it means that the signal state is switched from an invalid state to a valid state, that is, from a working path to a protection path, and the communication device will enter a working recovery mode. In this mode, the communication device will release the clock freeze and re-enable clock convergence to restore link synchronization. This process will be referred to below. Figure 3 Provide explanation.

[0046] Figure 2 FIG2 shows a schematic flow chart of a fast protection switching method for a short-distance optical network according to another embodiment of the present disclosure. Figure 1 Compared with the embodiment shown, Figure 2 The embodiment adds a step of freezing the parameters of the equalizer. Figure 2 Steps 21-25 shown in Figure 1 The steps 11-15 are the same or similar to those in the preceding text. Please refer to the description of steps 11-15 above and will not be repeated here.

[0047] While freezing the clock frequency and phase, the communication device also freezes the parameters of various equalizers in step 26. These equalizers may include analog and / or digital equalizers. For example, if the communication device includes a SerDes (serializer / deserializer) device, the equalizers may include one or more of the following: continuous time linear equalization (CTLE), feedforward equalization (FFE), and decision feedback equalization (DFE). The communication device freezes one or more sets of parameters in each equalizer, maintaining the convergence results obtained when the signal transitions from valid to invalid, and discontinuing real-time adaptive updates. The equalizer parameters may include a subset of the equalizer's parameters, particularly key or core parameters, which typically require retraining and convergence during link establishment. Examples include the gain of the CTLE and the tap weights and number of taps for the FFE and DFE. Ways to freeze the parameters of the equalizer may include, but are not limited to, storing the currently converged equalizer coefficients in a register, disabling the adaptive update function of the equalizer and keeping its current equalization parameters unchanged, and the like.

[0048] By freezing the equalizer parameters when the link is interrupted or the signal is invalid, the compensation characteristics of the original channel state can be maintained, preventing the equalizer from incorrectly adjusting parameters due to receiving noise or erroneous information, which would damage the receiving performance. Secondly, equalizer parameter freezing can work synergistically with clock freezing to form a stable transmission link state. In addition, freezing the equalizer parameters and clock information allows the system to quickly complete clock recovery and equalizer parameter convergence after communication is restored or switched to the protection channel, significantly improving the recovery speed of protection switching.

[0049] The steps 24-25 of freezing the clock information and the step 26 of freezing the equalizer parameters may be performed simultaneously or sequentially, and the execution order is not limited here.

[0050] Step 27 is the same as or similar to step 16. The transmitter of the communication device switches the data to be sent to the downstream module to a predetermined sequence. For example, the predetermined sequence can be a pseudo-random bit sequence (PRBS) or a predetermined specific sequence. The predetermined sequence is then sent to the downstream module according to a frequency offset adjustment clock. The frequency offset adjustment clock is equal to the sum of the second frequency offset and the local clock of the transmitter. For more details, see the description of step 16 above.

[0051] Figure 3 Shown with Figure 1 A schematic flowchart of a working recovery mode 30 corresponding to an embodiment of the present invention is provided. In step 31, upon detecting that the received signal state changes from invalid to valid, the first frequency offset frozen at the receiving end is unfrozen. Specifically, the receiving end uses the sum of the previously frozen first frequency offset and the receiving end's local clock as the initial condition. The clock recovery module converges based on this initial condition, tracking the clock information of the data signal. Unfreezing, as used herein, refers to recovery from a frozen state to a dynamic operating state.

[0052] In step 32, a determination is made as to whether the clock recovery module has entered a locked state. If it detects that the clock recovery module has not yet entered a locked state, the module continues to converge (step 31) until the clock is locked. Because the clock recovery module converges not from the local clock but from the local clock plus a first frequency offset, and the first frequency offset is close to the frequency offset recovered from the data signal during normal operation, the frequency deviation is smaller, enabling faster clock lock and shortening clock recovery time. This approach effectively avoids delays associated with re-locking the clock and is particularly suitable for communication systems with high reliability and transmission rate requirements. Clock lock indicates that the recovered clock signal is synchronized with the clock of the data signal in frequency and phase.

[0053] Optionally, when the clock recovery module enters the locked state, the second frequency offset of the transmitter is unfrozen, restoring the transmitter's clock to a normal operating transmit clock. This normal operating transmit clock is related to the frequency offset of the clock recovered from the data signal by the clock recovery module. In step 33, the data (i.e., the predetermined sequence) to be sent to the downstream module is restored to normal service data, and the transmitter uses the normal operating transmit clock for transmission.

[0054] Thus, in step 34, the protection switching recovery mode is complete, and the communication device enters normal operating mode. In normal operating mode, the clock recovery module on the receiving end of the communication device operates according to the normal operating mode, and the data signal and clock on the transmitting end of the communication device also operate according to the normal operating mode. The transmit clock in normal operating mode is determined by the local clock on the transmitting end and the frequency offset received by the transmitting end from the receiving end.

[0055] Optionally, Figure 4 A schematic flow chart of restoring a normal working mode during a fast protection switching process according to another embodiment of the present disclosure is shown, which corresponds to Figure 2 The embodiment shown. Figure 3 Compared with the method Figure 4 Added unfreezing step for equalizer parameters. Figure 4 Steps 41, 42, 44 and 45 are respectively Figure 3 The steps 31-34 are the same or similar to those in the preceding text, and reference may be made to the above description of the steps 31-34.

[0056] While the clock recovery module is converging and locking, the parameters can be unfrozen in step 43, meaning convergence is performed based on the frozen parameters, significantly shortening the convergence time. The order of unfreezing the clock and unfreezing the equalizer parameters is not limited; they can also be performed simultaneously.

[0057] After the clock is locked and the parameters of the equalizer are converged, in step 44 , the data to be sent to the downstream module is restored to normal service data and sent using a sending clock in a normal working state.

[0058] Figure 5 The structure diagram of a communication device for a short-distance optical network according to an embodiment of the present disclosure is shown. The communication device 500 includes a receiving end 501, a transmitting end 502, a clock recovery module 503, an equalizer module 504, and an equalizer parameter freezing module 505. The device in this embodiment can be used to implement the following Figure 1-4 The method of at least one embodiment shown in .

[0059] Specifically, the receiving end 501 is used to receive high-speed data signals from a short-distance optical communication link and convert the received optical signals into electrical signals for subsequent processing. This module may include, for example, optoelectronic conversion devices, amplifiers and other circuits to ensure that the received signal has a stable amplitude and shape. The receiving end can also be used to detect the received data signal to determine whether the data signal is valid and generate signal status information based on the received data signal detection result. For details, please refer to the disclosure of Figure 1 Description of steps 11 and 12.

[0060] When the signal status information indicates that the signal status is invalid, the receiving end 501 freezes the first frequency offset between the clock signal output by the clock recovery module (CDR) and the local clock of the receiving end to maintain the first frequency offset unchanged. In this case, the clock recovery module optionally no longer dynamically adjusts the output frequency based on the input data, but instead maintains its output frequency and phase in a stable locked state from valid to invalid signal. For a more detailed description of freezing the clock signal at the receiving end, please refer to the disclosure of the present invention. Figure 1 When the current data signal is valid and the data signal at the previous moment is invalid, the frozen first frequency offset is unfrozen so that the clock recovery module can converge based on the clock frequency of the sum of the local clock of the receiving end and the first frequency offset, thereby shortening the clock locking time. For a more detailed description of the unfreezing of the clock signal at the receiving end, please refer to the disclosure of the present invention. Figure 3 Description of steps 31-32.

[0061] The transmitting end 502 is used to send data to the downstream device. When it is detected that the current data signal is invalid, the transmitting end sends data to the downstream module at an unchanged transmitting frequency. Optionally, the transmitting end can freeze the second frequency offset received according to the first frequency offset to maintain the second frequency offset unchanged, and send a predetermined sequence to the downstream module with the sum of the frozen second frequency offset and the local clock of the transmitting end. For example, the predetermined sequence can be a pseudo-random sequence (Pseudo-Random Bit Sequence, PRBS) or a predetermined specific data sequence. In the working recovery mode, the transmitting end can send predetermined data to the downstream module with an unchanged clock, such as the sum of the frozen second frequency offset and the local clock of the transmitting end, until the clock recovery module relocks the clock according to the received data. When the clock recovered by the clock recovery module is locked, the second frequency offset is unfrozen. At this time, the transmitting end restores the data sent to the downstream module to normal business data, and uses the transmitting clock in normal working state to send it. For more specific descriptions of freezing and unfreezing the transmitting end clock signal, please refer to the present disclosure for details. Figure 1 Step 15 and Figure 3 Description of step 33.

[0062] The clock recovery module 503 is used to recover the clock signal from the received data signal. This module can be implemented using a phase-locked loop (PLL), delay-locked loop (DLL), or other circuits. It extracts and synchronizes the clock signal, providing a timing reference for subsequent modules. When the data signal is detected to be invalid, the clock recovery module 503 can maintain the clock lock state. In working recovery mode, where the current signal status information indicates a valid signal, while the signal status information at the previous moment indicates an invalid signal, the clock recovery module can converge the clock based on the received data information, using a frozen first frequency offset. If the clock recovery module has not yet reached the locked state, it continues to converge until the clock is locked. Because the clock recovery module converges not from the local clock but from the locked clock when the signal is invalid (i.e., the sum of the local clock and the first frequency offset), which is closer to the clock recovered from the data signal during normal operation, the frequency deviation is smaller, enabling faster clock lock and shortening the clock recovery time. In normal operating mode, the clock recovery module recovers the clock signal under normal operating conditions from the data signal.

[0063] The equalizer module 504 includes multiple equalizers, which may include digital and / or analog equalizers, such as a continuous time linear equalizer (CTLE), a forward equalizer (FFE), and a decision feedback equalizer (DFE). The parameters of the equalizer can be dynamically adjusted through training to cope with different channel conditions. One or more parameters in each equalizer are frozen to maintain the convergence result when the signal changes from valid to invalid, and no further adaptive updates are performed. The method for freezing the equalizer can be referred to in the disclosure of the invention. Figure 2 In the working recovery mode, if the parameters of the equalizer are frozen before, the parameters are unfrozen, that is, convergence is performed based on the frozen parameters, that is, the equalizer adaptive process is started based on the frozen parameters. The above process can be referred to in the present disclosure for Figure 4 The description of step 43 is as follows. If the parameters of the equalizer have not been frozen before, the parameters of the equalizer will be re-converged.

[0064] The equalizer parameter freezing module 505 can freeze the parameters of multiple equalizers. Figure 2 The description of step 26 is as follows, wherein one or more groups of parameters in each equalizer are frozen so that they maintain the convergence result from the time when the signal is valid to the time when the signal is invalid, and the real-time adaptive update is no longer performed.

[0065] Each module in this embodiment can be implemented by hardware, software, or a combination of software and hardware.

[0066] Figure 6FIG. 1 shows a schematic structural diagram of another communication device for a short-distance optical network according to an embodiment of the present disclosure. Figure 6 As shown, the communication device 600 includes a processor 601, a memory 602, a receiving end 603, and a transmitting end 604. The processor 601 is connected to the memory 602, the receiving end 603, and the transmitting end 604 respectively, and the receiving end 603 is connected to the transmitting end 604.

[0067] The processor 601 is used to implement the method steps in the above embodiment except for sending and receiving signals. The program code executed by the processor 601 can be stored in the memory 602. The receiving end 603 is used to receive optical signals, and the transmitting end 604 is used to send signals to downstream modules.

[0068] The processor 601 may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array, or other programmable logic device, and may implement or execute the various method steps in the present disclosure. The methods of the embodiments of the present disclosure may be executed by hardware, or by a combination of hardware and software. The memory 602 may be a non-volatile memory or a volatile memory. The memory 602 may store program code for reading and executing by the processor to implement the above-described methods of the embodiments of the present disclosure.

[0069] In addition, an embodiment of the present disclosure further provides a chip, which includes a processor, configured to implement the functions involved in any one or more of the above embodiments, for example, Figure 1-Figure 4 Optionally, the chip further comprises a memory for storing program instructions and data executed by the processor. The chip may comprise a chip, and optionally, may also comprise other discrete devices.

[0070] The device and method disclosed in the present invention can monitor the link status in real time through real-time signal detection and status analysis. When a link anomaly is detected, the clock locking time in the recovery phase is reduced by a clock freezing mechanism, and the convergence time of the equalizer parameters in the recovery phase can be reduced by freezing some parameters of the equalizer. In addition, when the link is abnormal, the normal operation of the downstream module is guaranteed by sending predetermined data to the downstream with a stable clock, ensuring that the downstream module can communicate normally after the link is restored. The DSP chip implemented using the communication device and communication method disclosed in the present invention can shorten the recovery time in the protection switching process to less than 50ms, or even less than 20ms, and is suitable for high-speed communication environments in short-distance optical networks, thereby improving the overall communication reliability and system robustness.

[0071] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A fast protection switching method for a short-distance optical network, characterized in that: include: determining whether the status of the received data signal is valid; If the state of the first data signal is invalid, a first clock obtained when the data signal changes from valid to invalid is received, the clock frequency is frozen, and a predetermined sequence is sent to the downstream module using a second clock, the state of the first data signal remains in the invalid stage, and the frequency of the second clock remains unchanged; If the state of the first data signal is valid and the state of the second data signal is invalid, entering the thawing clock frequency freezing state, and when the state of the first data signal is in the maintaining valid stage, sending normal service data to the downstream module, and the frequency of the second clock changes according to the input clock frequency of the receiving end; The state of the first data signal is the state of the currently received data signal, and the state of the second data signal is the state of the data signal received at the last moment.

2. The fast protection switching method for a short-distance optical network according to claim 1, characterized in that: Entering the clock frequency freeze state includes freezing the first frequency offset between the first clock obtained when the data signal changes from valid to invalid and the local clock of the receiving end to maintain the first frequency offset unchanged, and thawing the clock frequency freeze state includes thawing the first frequency offset so that the clock recovery module recovers the clock signal according to the received data signal until it is locked.

3. The fast protection switching method for a short-distance optical network according to claim 1, characterized in that: The second clock is a local clock of the transmitting end or a frequency offset adjusted clock, and the frequency offset adjusted clock is the sum of a second frequency offset obtained by the transmitting end according to the first frequency offset and the local clock of the transmitting end.

4. The fast protection switching method for a short-distance optical network according to claim 2, characterized in that: If the state of the first data signal is invalid, entering the clock frequency freeze state further includes the transmitting end freezing a received second frequency offset to maintain the second frequency offset unchanged, where the second frequency offset is obtained based on the first frequency offset, and the second clock is equal to the sum of the local clock of the transmitting end and the second frequency offset; If the state of the first data signal is valid and the state of the second data signal is invalid, the unfreezing clock frequency frozen state also includes unfreezing the second frequency deviation after the clock signal is locked, and the transmitting end sends normal business data to the downstream module with a normally operating transmitting clock.

5. The fast protection switching method for a short-distance optical network according to claim 1, wherein: If the state of the first data signal is invalid, one or more parameters of the equalizer are frozen so that the one or more parameters of the equalizer maintain a convergence result when the state of the data signal changes from valid to invalid.

6. The fast protection switching method for a short-distance optical network according to claim 5, characterized in that: If the state of the first data signal is valid and the state of the second data signal is invalid, the equalizer converges based on the frozen one or more parameters.

7. The fast protection switching method for a short-distance optical network according to claim 1, characterized in that: Determining whether the status of the received data signal is valid includes detecting any one of the following or a combination thereof: the power or average power of the data signal, the amplitude or average amplitude of the data signal, the number of symbol jumps of the data signal, a signal loss indication signal, and a phase-locked loop loss indication signal.

8. A communication device, characterized in that include a receiving end, configured to receive a data signal from a working channel or a protection channel, and determine whether a state of the data signal is valid; A clock recovery module, configured to recover a clock signal from the received data signal; The sending end is used to send data to the downstream device, where If the receiving end determines that the state of the first data signal is invalid, the communication device receives a first clock obtained when the data signal changes from valid to invalid, enters a clock frequency freezing state, and sends a predetermined sequence to the downstream module using a second clock, the state of the first data signal remains in the invalid stage, and the frequency of the second clock remains unchanged; If the receiving end determines that the state of the first data signal is valid and the state of the second data signal is invalid, the communication device enters a thawing clock frequency freezing state, and when the state of the first data signal is in a maintaining valid stage, the transmitting end sends normal service data to the downstream module, and the frequency of the second clock changes according to the input clock frequency of the receiving end. The state of the first data signal is the state of the currently received data signal, and the state of the second data signal is the state of the data signal received at the last moment.

9. The communication device according to claim 8, wherein: Entering the clock frequency freeze state includes freezing the first frequency offset between the first clock obtained when the data signal changes from valid to invalid and the local clock of the receiving end to maintain the first frequency offset unchanged, and thawing the clock frequency freeze state includes thawing the first frequency offset so that the clock recovery module recovers the clock signal according to the received data signal until it is locked.

10. The communication device according to claim 9, wherein: If the receiving end determines that the state of the first data signal is invalid, the communication device entering the clock frequency freeze state further includes the transmitting end freezing the received second frequency offset to maintain the second frequency offset unchanged, where the second frequency offset is obtained based on the first frequency offset, and the second clock is equal to the sum of the local clock of the transmitting end and the second frequency offset; If the receiving end determines that the state of the first data signal is valid and the state of the second data signal is invalid, the communication device enters the unfrozen clock frequency frozen state, which also includes the transmitting end unfreezing the second frequency deviation after the clock signal is locked, so that normal business data is sent to the downstream module with a normally working transmitting clock.

11. The communication device according to claim 8, characterized in that The device further includes a plurality of equalizers and an equalizer parameter freezing module. If the receiving end determines that the state of the first data signal is invalid, the equalizer parameter freezing module freezes one or more parameters of the plurality of equalizers to maintain the convergence result when the data signal changes from valid to invalid; If the receiving end determines that the state of the first data signal is valid and the state of the second data signal is invalid, the equalizer converges based on the frozen one or more parameters.

12. The communication device according to claim 8, characterized in that The receiving end determines whether the status of the data signal is valid by detecting any one or a combination of the following on the received data signal: the power or average power of the data signal, the amplitude or average amplitude of the data signal, the number of symbol jumps of the data signal, a signal loss indication signal, and a phase-locked loop loss indication signal.

Images