An ANPC three-level converter and a narrow pulse elimination method and device thereof

Abstract

The application relates to an ANPC three-level converter and a narrow pulse elimination method and device thereof, and is characterized by comprising the following steps: collecting signal data of a converter to calculate initial comparison values of a pulse modulation module of the converter for generating a pulse width modulation wave; calculating a narrow pulse lower limit value T down and a narrow pulse upper limit value T up according to a clock frequency T clock , a dead time T s , a narrow pulse time T N and a pulse period T PRD of the pulse modulation module; when the initial comparison value is greater than the narrow pulse upper limit value T up , setting a final comparison value as the narrow pulse upper limit value T up ; when the comparison value is less than 0, performing positive processing on the initial comparison value to make the final comparison value a positive value; when the comparison value is less than the narrow pulse lower limit value T down , setting the final comparison value as 0; and generating a pulse width modulation wave for regulating the converter by using the final comparison value. The problem that narrow pulses easily cause damage to power devices in the converter is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics and new energy power generation, and particularly relates to an ANPC three-level converter and a narrow pulse elimination method and device thereof. BACKGROUND

[0002] At present, photovoltaic inverters and energy storage converters all adopt ANPC three-level topology structure, and IGBT modules all need to be provided with pulse interlocking dead zones.

[0003] In the running process of an insulated gate bipolar transistor (IGBT) module, if a narrow pulse occurs, the IGBT will be greatly affected, and even damaged. The main reason is that the internal IGBT or antiparallel diode unit is turned off again under the condition of not being completely turned on, and the di / dt generated in this process is much larger than that in the case of completely turning on and then turning off, thereby a large turn-off voltage spike is generated for the IGBT unit, and a large du / dt and oscillation are generated for the antiparallel diode unit. SUMMARY

[0004] The purpose of the present application is to provide an ANPC three-level converter and a narrow pulse elimination method and device thereof, so as to solve the problem that narrow pulses are easy to cause damage to power devices in the converter.

[0005] To achieve the above-mentioned purpose, the scheme of the present application includes:

[0006] The narrow pulse elimination method of the ANPC three-level converter of the present application includes the following steps:

[0007] (1) collecting signal data of the converter to calculate an initial comparison value of a pulse modulation module of the converter for generating a pulse width modulation wave;

[0008] (2) calculating a narrow pulse lower limit value T down and a narrow pulse upper limit value T up according to a clock frequency T clock , a dead zone time T s , a narrow pulse time T N and a pulse period T FRD of the pulse modulation module;

[0009] (3) when the initial comparison value is greater than the narrow pulse upper limit value T up , setting a final comparison value as the narrow pulse upper limit value T up ; when the comparison value is less than 0, performing positive processing on the initial comparison value to make the final comparison value a positive value; when the comparison value is less than the narrow pulse lower limit value T down , setting the final comparison value as 0; and generating a pulse width modulation wave for regulating and controlling the converter by using the final comparison value.

[0010] The control method is based on the principle of narrow pulse generation, and the comparison value of the converter and the lower limit value T down and the upper limit value T up of the narrow pulse are calculated, and the comparison value is compared with the upper limit value and the lower limit value of the narrow pulse and 0, so that the comparison value generated by the triangular wave and the sine wave in different cases does not have a narrow pulse, which solves the problem of narrow pulse generation of the ANPC and solves the problem that the narrow pulse is easy to damage other devices in the converter.

[0011] Further, in step (1), the signal data includes alternating current voltage, direct current bus voltage, direct current and alternating current.

[0012] Further, the initial comparison value is generated by using a direct current bus voltage outer ring and an alternating current inner ring control strategy.

[0013] The above technical solution has the beneficial effects that the DC side voltage and the AC side voltage are considered, so that the generated comparison value is more accurate, and the modulation of the narrow pulse is more accurate.

[0014] Further, in step (3), the variable positive processing is specifically: setting the final comparison value as the sum of the initial comparison value and 1.

[0015] Further, in step (3), the formula for calculating the lower limit value T down of the narrow pulse is as follows:

[0016] T down =(T s +T B )*T clock ;

[0017] The formula for calculating the upper limit value T up of the narrow pulse is as follows:

[0018] T up =T PRD -T down .

[0019] The narrow pulse elimination device of the ANPC three-level converter of the application comprises a processor and a memory, and the processor is used to execute the computer program instructions stored in the memory to realize the narrow pulse elimination method of the ANPC three-level converter as described above.

[0020] The above technical solution has the beneficial effects that the effective and reliable execution of the narrow pulse elimination method of the ANPC three-level converter is ensured.

[0021] The ANPC three-level converter of the application comprises a plurality of power modules and the device as described above.

[0022] The technical scheme has the beneficial effects that the converter adopts a narrow pulse elimination method of the ANPC three-level converter, the comparison value of the converter is calculated and the lower limit value T down and the upper limit value T up of the narrow pulse are calculated, and then the comparison value is compared with the upper limit value, the lower limit value and 0, so that the comparison value result generated by the triangular wave and the sine wave does not have the narrow pulse in different cases, the problem of the generation of the narrow pulse of the ANPC is solved from the source, the problem that the narrow pulse easily causes damage to other devices in the converter is solved, and the long-life operation of the converter is realized. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is the ANPC three-level topology schematic diagram provided by the application;

[0024] Figure 2 It is the in-phase carrier pulse generation diagram provided by the application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the application more clear and explicit, the application is further described in detail below with reference to the drawings and examples.

[0026] For the elimination of the narrow pulse, the application provides a method for eliminating the narrow pulse of the ANPC three-level. The control method is based on the principle of the generation of the narrow pulse, and the control method generated by the micro-processing chip EPWM solves the problem of the generation of the narrow pulse of the ANPC from the source.

[0027] The method concept comprises the following steps: according to the principle of the generation of the EPWM pulse, the dead time T N and the set value T s of the narrow pulse are combined to calculate the lower limit value T down and the upper limit value T up of the narrow pulse, and then the comparison value of the converter is calculated, when the comparison value is greater than the upper limit value T up of the narrow pulse, the comparison value is equal to the upper limit value T up of the narrow pulse, when the comparison value is less than the lower limit value T down of the narrow pulse, the comparison value is equal to 0, and the narrow pulse elimination control of the ANPC modulation algorithm is realized. Based on the concept, the narrow pulse elimination method of the ANPC three-level converter, the narrow pulse elimination device of the ANPC three-level converter and the ANPC three-level converter of the application can be realized.

[0028] An embodiment of the narrow pulse elimination method of the ANPC three-level converter is as follows:

[0029] The embodiment is directed to an ANPC three-level converter as shown in Figure 1 The pulse generation principle diagram is shown in Figure 2 The ANPC three-level converter adopts a narrow pulse elimination method of the ANPC three-level converter of the application to eliminate narrow pulses, which will be further described in detail in combination with the principle diagram and the in-phase carrier pulse generation diagram.

[0030] (1) The device hardware detection loop collects signal data information of the AC voltage, DC bus voltage, DC current, AC current, etc. of the converter.

[0031] Figure 1 The collected DC voltage is taken as the voltage feedback value of the DC voltage outer loop, and the AC current is taken as the current feedback value of the AC current inner loop. The collected AC voltage is output through software phase locking to output the electrical angle, which is the reference angle for three-phase current transformation. As shown in Figure 2 The output of the double closed loop is transformed to generate a sinusoidal modulation wave.

[0032] (2) The data information is calculated to obtain the initial comparison value for controlling the generation of the pulse width of the modulation converter.

[0033] The comparison value required by the EPWM module is output by the double closed loop control strategy of the DC voltage outer loop and the AC current inner loop, and the pulse principle is compared according to the in-phase carrier layering mode to generate PWM pulses.

[0034] (3) The narrow pulse lower limit value and the narrow pulse upper limit value are calculated according to the clock frequency of the EPMW module, the dead time, the narrow pulse time and the pulse period.

[0035] The clock frequency of the EPMW module is defined as T clock , the dead time is T s , the narrow pulse time is T N , the pulse period is T PRD , the narrow pulse lower limit value is T down , and the narrow pulse upper limit value is T up ,

[0036] The narrow pulse lower limit value is T down The calculation formula is:

[0037] T down =(T s +T N )*T clock ;

[0038] The calculation formula of the narrow pulse upper limit value T up is:

[0039] T up =T PRD-T down .

[0040] (4) When the comparison value of EPWM is greater than 0, and greater than the maximum set threshold value T up of narrow pulse, the comparison value is equal to the upper limit value T up of narrow pulse; when the comparison value of EPWM is less than 0, the comparison value is positive by positive processing, in this embodiment, the comparison value of EPWM is set to 1 and the sum of the comparison value of EPWM, the comparison value is less than the lower limit value T down of narrow pulse, then the comparison value is equal to 0, realizing the narrow pulse elimination control of ANPC modulation algorithm; when the comparison value of EPWM is in the range of the maximum threshold T up and the minimum threshold T down of narrow pulse, the comparison value is normally compared and output.

[0041] Through the above narrow pulse elimination control scheme, the generation of ANPC three-level narrow pulse can be eliminated, the stable operation of energy storage device is realized, and the reliability of new energy device operation is ensured.

[0042] An embodiment of a narrow pulse elimination device of an ANPC three-level converter:

[0043] A narrow pulse elimination device of an ANPC three-level converter, comprising a processor and a memory, the processor is used to execute the computer program instructions stored in the memory to realize the narrow pulse elimination method of the ANPC three-level converter, the narrow pulse elimination method of the ANPC three-level converter has been introduced in the narrow pulse elimination method of the ANPC three-level converter embodiment enough clearly, here will not be repeated.

[0044] An embodiment of an ANPC three-level converter:

[0045] An ANPC three-level converter, comprising a plurality of power modules, further comprising a narrow pulse elimination device of an ANPC three-level converter, the narrow pulse elimination device of an ANPC three-level converter has been introduced in the narrow pulse elimination device of an ANPC three-level converter embodiment enough clearly, here will not be repeated.

Claims

1. A method for narrow pulse elimination of an ANPC three-level converter, characterized in that, The method comprises the following steps: (1) collecting signal data of the converter to calculate initial comparison values of a pulse modulation module of the converter for generating a pulse width modulation wave; (2) According to the clock frequency T of the pulse modulation module clock , Dead time T s , narrow pulse time T N and pulse period T PRD Calculate the narrow pulse lower limit T down and narrow pulse upper limit T up ; and T down =(T s +T N )*T clock , T up =T PRD -T down ; (3) when the initial comparison value is greater than the upper limit value T up for narrow pulses, setting the final comparison value to the upper limit value T up for narrow pulses; when the initial comparison value is less than 0, performing a positive change on the initial comparison value to make a final comparison value a positive value; when the initial comparison value is less than a narrow pulse lower value T down a final comparison value is set to 0; a pulse width modulation wave for regulating the converter is generated using the final comparison value.

2. The method for narrow pulse elimination of an ANPC three-level converter according to claim 1, characterized in that, in step (1), the signal data comprises an alternating voltage, a DC bus voltage, a DC current and an alternating current.

3. The method for narrow pulse elimination of an ANPC three-level converter according to claim 2, characterized in that, The initial comparison values are generated by using a DC bus voltage outer loop and an alternating current inner loop control strategy.

4. The method of narrow pulse elimination for an ANPC three-level converter according to claim 1, characterized in that, in step (3), the positive change is specifically setting the final comparison value as a sum of the initial comparison value and 1.

5. A narrow pulse elimination device for an ANPC three-level converter, characterized in that The device comprises a processor and a memory, the processor is used to execute computer program instructions stored in the memory to realize the narrow pulse elimination method of the ANPC three-level converter as claimed in any one of claims 1-4.

6. An ANPC three-level converter comprising several power modules, characterized in that, The device as claimed in claim 5 is also comprised.

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