Electronic device having a pad offset to a function

Abstract

An electronic device (100) is described, the electronic device (100) comprising: i) a semiconductor element (110) comprising a plurality of connection pads on at least one main surface (111); ii) a redistribution layer structure (120) coupled to the main surface (111) of the semiconductor element (110), where the redistribution layer structure (120) comprises: iia) a first main surface (121) electrically associated with the main surface (111) of the semiconductor element (110), iib) a second main surface (122) opposite the first main surface (121), iii) a plurality of first pads (123) exposed on the first main surface (121) and electrically connected to the plurality of connection pads (112), and iv) a plurality of second pads (124) exposed at the second major surface (122); v) a component carrier (130) coupled to the redistribution layer structure (120), where the component carrier (130) comprises: va) at least one electrically insulating layer structure (132), and vb) at least one electrically conductive layer structure (134), where the at least one electrically conductive layer structure (134) is electrically connected to the plurality of second pads (124); and vi) at least one functional element (140) arranged in / on the component carrier; wherein at least some of the second pads (124) are offset in plan view with respect to a position of the corresponding first pad (123) towards the at least one functional element (140).

Description

Technical Field

[0001] The present invention relates to an electronic device comprising a semiconductor element, a redistribution layer structure, a component carrier and a functional element. Specifically, a lower pad of the redistribution layer structure is offset relative to a corresponding upper pad toward the functional element.

[0002] Thus, the present invention may relate to the technical field of component carriers, such as printed circuit boards or IC substrates, in the context of electrical connections. Background Art

[0003] Against the backdrop of the ever-increasing product functionality of component carriers equipped with one or more electronic components, the increasing miniaturization of such electronic components, and the ever-increasing number of electronic components to be mounted on component carriers, such as printed circuit boards, increasingly powerful array-like components or packages with a plurality of electronic components are being used, which have a plurality of contacts or connections with increasingly smaller spacing between these contacts. Removing the heat generated by these electronic components and the component carriers themselves during operation is becoming an increasingly important problem. Furthermore, effective protection against electromagnetic interference (EMI) is becoming increasingly important. At the same time, component carriers should be mechanically robust and electrically and magnetically reliable in order to be able to operate even under adverse conditions.

[0004] In particular, electrically connecting multiple electronic parts, such as semiconductor components and component carriers, within an assembly, such as an electronic device, can be a challenge. Since semiconductor components (e.g., chips) typically include very small electrical pads (connection terminals), while component carriers (e.g., circuit boards) typically include larger electrical pads (e.g., solder balls), electrical connections between semiconductor components (e.g., chips) and component carriers (e.g., circuit boards) can be particularly problematic.

[0005] In order to "convert" between the small pads of the chip and the large pads of the circuit board, an interposer including a redistribution layer (fan-out structure) can be used. In this document, the term "redistribution layer (RDL)" may particularly refer to an at least partially electrically conductive structure that is designed to convert a small electrical contact located at a first surface into a large electrical contact located at a second surface, in particular, wherein the first surface and the second surface are arranged opposite to each other. To this end, the redistribution layer includes a plurality of vertical structures (vias) and horizontal structures (traces) to expand the size of a small pad (e.g. a pad of a chip) to the scale of a large pad (e.g. a pad of a circuit board).

[0006] Figure 7Figure a shows an example of a conventional arrangement structure of an IC chip 210 and a redistribution layer 220 connected thereto. While first pads 223 on the upper surface 221 of the redistribution layer 220 are electrically connected to pads on the IC chip 210, second pads 224 on the lower surface 222 of the redistribution layer 220 are exposed to be connected to a circuit board (not shown).

[0007] Figure 7 b also shows a plan view (along the z-axis in the xy plane) of the lower surface 222 of the redistribution layer 220. It can be seen that a large number of distributed second pads 224 are provided (see also below). Figure 8 The remaining second pads 124b are depicted in FIG. 2 . The figure shows different functions of the second pads in different schemes, and it can be seen that the distribution of the different pads is completely mixed.

[0008] When placing the lower surface 222 of the redistribution layer 220 onto a circuit board, it can be particularly challenging to achieve effective electrical connection to specific functions of the circuit board in order to establish electrical contact. Summary of the Invention

[0009] It may be desirable to provide electrical connections between various electronic parts of an electronic device in an efficient, reliable, and design-flexible manner.The present invention provides an electronic device.

[0010] According to one aspect of the present invention, an electronic device is described, comprising:

[0011] i) a semiconductor component (e.g., a semiconductor chip such as an IC chip), the semiconductor component comprising a plurality of connection pads on at least one major surface;

[0012] ii) a redistribution layer structure coupled to the main surface of the semiconductor device, wherein the redistribution layer structure comprises:

[0013] iia) a first main surface electrically associated with (directly or indirectly connected to) a main surface of the semiconductor element, and

[0014] iib) a second main surface opposite to the first main surface,

[0015] iii) a plurality of first pads, the first pads being (preferably) arranged to be exposed on the first main surface and electrically connected to a plurality of connection pads (of the semiconductor element), and

[0016] iv) (preferably) a plurality of second pads exposed at the second major surface (wherein at least some of the second pads are associated / correspond to respective first pads);

[0017] v) a component carrier (e.g., a printed circuit board or IC substrate, a mounting base) coupled to the redistribution layer structure (particularly on a second surface of the redistribution layer structure), wherein the component carrier comprises:

[0018] va) at least one electrically insulating layer structure (e.g. a resin), and

[0019] vb) at least one electrically conductive layer structure (eg copper), wherein the at least one electrically conductive layer structure is electrically connected to the plurality of second pads (of the redistribution layer structure); and

[0020] vi) at least one functional element, in particular the functional element is arranged in and / or on a component carrier (the component carrier can also be a mounting base, between which another component carrier is arranged, see e.g. Figure 3 ).

[0021] Therefore, at least some of the second pads are offset in a plan view (when viewed along the z-axis, in other words, when viewed along the normal vector of the xy plane) relative to the position of the corresponding first pad toward at least one functional element (in other words: the second pad is offset toward the functional element relative to its corresponding first pad).

[0022] In the context of this document, the term "semiconductor element" may particularly refer to an element, such as a component, comprising at least one semiconductor material, i.e., a material having an electrical conductivity between that of a conductor (e.g., copper) and an insulator (e.g., resin). Such semiconductor materials are used, for example, in (integrated) circuits. Thus, a semiconductor element may comprise one or more circuits, such as a bare wafer or a contained / packaged chip. The semiconductor element includes electrical connection pads on at least one (main) surface. In an example, the connection pads are formed at the lower main surface of the semiconductor element. In another example, the connection pads are formed at the upper main surface of the semiconductor element.

[0023] In other words, the connection pads may be provided on a surface where the semiconductor element interacts with another structure, preferably a redistribution layer structure; the interaction may include mechanical coupling between the semiconductor element and the another structure and / or electrical coupling between the semiconductor element and the another structure.

[0024] In the context of this document, the term "redistribution layer structure" may refer to an RDL as described above. Furthermore, the RDL structure may comprise a first (upper) main surface and an opposite (lower) main surface. The RDL structure may comprise electrical pads at both main surfaces to convert a first pad size into a second pad size. In an example, the first main surface comprises a plurality of first pads (connection pads to be connected to semiconductor elements), while the second main surface comprises a plurality of second pads (to be connected to component carriers, in particular functional elements of the component carriers).

[0025] In an example, the redistribution layer structure further includes at least one, preferably a plurality of, electrically insulating layer structures and at least one, preferably a plurality of, electrically conductive layer structures, the electrically conductive layer structures being connected to one another to connect (at least some of) the plurality of first pads to (at least some of) the corresponding plurality of second pads. In an example, the electrically insulating layer structure comprises an organic or inorganic material (particularly without fiber filler, with spherical filler, without filler, or without fabric).

[0026] In the context of this document, the term "functional element" may particularly refer to any physical element / device that provides at least one technical function and is configured to be mounted or embedded in a (further) component carrier. In an example, the functional element can be pre-manufactured and mounted / embedded as an inlay. Although the functional element may include one or more components, the functional inlay may only be different from the (electronic) component. In an example, it may be necessary to establish one or more electrical connections between the semiconductor element and the functional element, in particular connections with respect to signal transmission, power supply and grounding. Other functions may include at least one of the following: power functions (e.g., passive components such as filters, capacitors, inductors) and / or active components (e.g., DC-DC converters, buck converters, power management integrated circuits), security functions (e.g., memories, encryption engines, clocks), thermal functions, electro-optical functions (e.g., conversion, transmission), optical functions (e.g., reflectors, waveguides), shielding functions (e.g., electromagnetic compatibility).

[0027] In the context of this document, the term "major surface" may particularly refer to one of the two opposite largest surfaces of a device. The major surfaces may be connected by a circumferential sidewall. The thickness of a device, such as a stack, may be defined by the distance between the two opposite major surfaces.

[0028] In the context of this document, the term "second pad is offset relative to the corresponding first pad in plan view" may in particular describe a situation in which the second pad (located at the second main surface of the RDL structure) is displaced relative to the (respectively associated) first pad (located at the first main surface of the RDL structure). This offset can here be oriented depending on the position of the functional element in or on the component carrier. In other words, the second pad is not formed at a position corresponding to the position of the corresponding first pad (for example along the z-direction), but is moved / arranged closer to the functional element (i.e. the second pad is offset away from an imaginary vertical line (along the z-direction) drawn through the corresponding first pad).

[0029] The biasing may be obtained by at least one, preferably a plurality of electrically insulating layer structures and at least one, preferably a plurality of electrically conductive layer structures of the redistribution layer structure, which are connected to each other to connect the first pad with the respective second pad.

[0030] In the context of this document, the term "component carrier" may particularly refer to any support structure capable of accommodating one or more components on and / or in the component carrier for providing mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical and / or electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate, an IC (integrated circuit) substrate, or a mounting base.

[0031] In the context of this article, the term "IC substrate" can particularly refer to a small component carrier. Relative to a PCB, an IC substrate can be a relatively small component carrier on which one or more components can be mounted, and can be used as a connection medium between one or more chips and another PCB. More specifically, an IC substrate can be understood as a component carrier for electrical connectors or electrical networks and for connectors that are comparable to a printed circuit board (PCB) but have a relatively high density of lateral and / or vertical arrangements. Lateral connectors are, for example, conductive paths, while vertical connectors can be, for example, drill holes. These lateral connectors and / or vertical connectors are arranged in the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated components or unaccommodated components (such as bare wafers), in particular IC chips and printed circuit boards or intermediate printed circuit boards. In an example, an IC substrate can be considered as, for example, an interposer between an electronic component and a printed circuit board.

[0032] In the context of this document, "IC substrate" should not be understood as any substrate suitable for supporting an IC. Instead, "IC substrate" may be a technical term for a specific high-density PCB comprising common PCB materials.

[0033] According to an exemplary embodiment, the present invention may be based on the insight that when a second pad (located at the component carrier side of an RDL structure) is biased toward a functional element (e.g., a functional element of the component carrier) compared to a corresponding opposite first pad (connected to a semiconductor element), an electrical connection between electrical parts of an electronic device (wherein the semiconductor element is connected to the component carrier via a redistribution layer structure) may be provided in an efficient, reliable, and design-flexible manner.

[0034] This allows the distribution of electrical contacts to be optimized based on the architecture of the component carrier and functional elements. The electronic device can enhance the interaction between semiconductor components and (additional) component carriers (functional elements). This optimizes the layout of the component carrier's electrically conductive structures and the layout of embedded components. This concept is particularly suitable for electronic devices with multiple functions, for example, for component carriers with ten or more embedded functional elements located in different locations.

[0035] Exemplary embodiments

[0036] According to embodiments, at least some of the second pads are offset relative to the first pad along the bias direction by a distance that is at least the width of the first and / or second pads. This can provide the advantage that the bias is sufficiently large to achieve particularly efficient and position-optimized electrical connections. The width of the pad can be considered to be the width in the (x, y) planar direction. In the case of circular pads, the diameter can be considered to be the width of the pad.

[0037] According to another embodiment, at least some of the second pads are offset relative to the first pads and grouped in subsections of the second main surface. This can provide the advantage that the subgroups of the second pads can be efficiently allocated with respect to their functions and / or corresponding functional elements. For example, a first group of second pads can be associated with a first functional element, while a second group of second pads can be associated with a second functional element. In this case, the first group can be biased toward the first functional element, while the second group can be biased toward the second functional element. Thus, grouping can enable a particularly efficient architecture.

[0038] According to another embodiment, only at least some of the second pads are offset in plan view relative to the position of the corresponding first pads toward the functional element. In particular, the remaining pads are located and / or offset and / or grouped in the remaining portion of the second main surface. This can provide the advantage of significantly increasing design flexibility. While some second pads (subgroups) can be offset, for example, into the first subsection of the second main surface, other second pads (subgroups) can remain in their position, for example, in the second subsection of the second main surface.

[0039] According to another embodiment, some of the plurality of connection pads are configured to transmit signals input to / output from the semiconductor element. According to another embodiment, some of the plurality of connection pads are configured to transmit power to the semiconductor element. According to another embodiment, some of the plurality of connection pads are configured to ground the semiconductor element. This can provide the advantage that technically / economically important and / or established functions can be processed and implemented directly for the corresponding functional element.

[0040] According to another embodiment, some of the plurality of second pads that are offset relative to corresponding first pads in plan view are second pads that:

[0041] i) the second pad is configured to transmit a signal input to / output from the semiconductor element, and / or

[0042] ii) the second pad is configured to deliver power to the semiconductor device, and / or

[0043] iii) The second pad is configured to ground the semiconductor element.

[0044] As described above, in this way, important functions can be directly improved based on the biased second pad.

[0045] According to another embodiment, at least some of the second pads are electrically connected to corresponding first pads, and corresponding first pads are connected to corresponding connection pads, such that each of at least some of the second pads is configured to:

[0046] i) transmitting a signal input to / output from a semiconductor device, and / or

[0047] ii) delivering power to semiconductor devices, and / or

[0048] iii) Ground the semiconductor element.

[0049] As described above, in this way, important functions can be directly improved based on the biased second pad.

[0050] According to another embodiment, at least one functional element comprises an (electronic) component for managing / transmitting / requesting a specific signal, and / or power supply, and / or ground connection. According to another embodiment, the plurality of second pads are offset relative to the corresponding first pads in plan view, such that the required second pads are configured as follows:

[0051] i) transmitting signals input to / output from a semiconductor device, and / or

[0052] ii) delivering power to semiconductor devices, and / or

[0053] iii) is grounded,

[0054] is biased toward the position of the functional element.

[0055] This may provide the advantage that (electronic) components may be supported and connected in an efficient and reliable manner, whereby the connection layout is optimized due to the biasing of the second pads according to their specific function and the corresponding functional elements.

[0056] According to another embodiment, at least one functional element includes at least one functional volume portion. This can bring the advantage of significantly increasing design flexibility. In addition, by providing two or more functional volume portions in a functional element, efficient miniaturization can be achieved. The term "functional volume portion" in the context of this document can refer to a sub-portion of a functional element. For example, a functional element can include multiple different (independent) functional volume portions.

[0057] The functional volume portion combined with the offset of the second pad enhances the grouping of specific functions at specific locations (i.e., in terms of planar position and / or thickness position) of the electronic device, thereby allowing the pad to be offset towards a recognized optimal position to achieve an optimized connection layout.

[0058] According to further embodiments, at least one of the functional volume portions comprises at least one of the following:

[0059] i) a power distribution function, in particular a redistribution structure,

[0060] ii) power delivery functionality, in particular, the power delivery functionality being provided by a plurality of embedded capacitor components,

[0061] iii) at least one safety-related component,

[0062] iv) at least one thermal management structure,

[0063] v) at least one electro-optical structure.

[0064] This can provide the following advantages: technically / economically important functions can be combined into a functional element, which is efficiently electrically connected to the offset second pad. In particular, in the case of component carriers comprising multiple functional elements and / or functional volume parts, the offset second pad can achieve the necessary efficient electrical connection.

[0065] According to another embodiment, at least one functional volume portion is electrically connected (only connected or most of the connections are connected) to a second pad configured as follows:

[0066] i) transmitting / receiving signals input to / output from the semiconductor device, and / or

[0067] ii) delivering power to semiconductor devices, and / or

[0068] iii) is grounded, and

[0069] is biased towards the location of the functional volume portion.

[0070] Similar to the case of the functional elements described above, important functional volume sections can be efficiently connected with a high degree of design flexibility.

[0071] According to another embodiment, at least one functional volume (and / or functional element) is arranged in a layer structure (e.g., a core layer structure) of the component carrier. In particular, at least one functional volume (and / or functional element) is arranged in a cavity provided in the layer structure of the component carrier. This can offer the advantage that the functional element can be embedded in the layers of the stack, thereby being protected and requiring less space.

[0072] According to another embodiment, the component carrier comprises an integrated circuit substrate, in particular wherein a redistribution layer structure (as an interposer) is connected to the integrated circuit substrate (see, for example, Figure 2 ).

[0073] According to another embodiment, the redistribution layer structure is bonded (at least partially embedded) to a component carrier (see, for example, Figure 6 ) or a mounting base (see below). In particular, the first main surface / first pad faces / is exposed to one (upper) main surface of the component carrier or the mounting base. As a result, the electronic device can require less space and the RDL structure is protected in the component carrier material.

[0074] According to another embodiment, the component carrier comprises a mounting base (further component carrier), in particular the mounting base is a printed circuit board and / or an interposer. The description of the embodiment of the component carrier can also apply to the mounting base when it is configured as a component carrier. Thus, a further component carrier can be arranged between the RDL structure and the component carrier (mounting base), see for example Figure 3 In another embodiment, the mounting base may be configured as a substrate for supporting the component carrier, such as a frame structure.

[0075] According to another embodiment, a component carrier, in particular configured as an IC substrate, is connected (mounted or at least partially embedded) to the mounting base.

[0076] Thus, an electronic device may include a plurality of electronic parts that may be electrically interconnected in an efficient and reliable manner.

[0077] According to another embodiment, at least one of the functional element and / or the functional volume portion is located in / on the mounting base, or at least one of the functional element and / or the functional volume portion is located in / on the component carrier (IC) substrate, and at least some of the second pads are offset towards the position of the functional element and / or the functional volume portion in plan view (see, for example, Figure 3 In this embodiment, the component carrier can serve as a further intermediate layer between the semiconductor elements and the electronics part (here the mounting base), wherein the functional parts are located in the electronics part.

[0078] Independently of the position of at least one of the functional elements and / or functional volume parts in the electronic device, in particular the electronic package, and / or regardless of the position of at least one of the functional elements and / or functional volume parts in one of the components constituting the package (mounting base, component carrier (IC) substrate), the second pad is offset along the plan view, thereby optimizing the connection in the assembly direction of the package components.

[0079] According to another embodiment, a plurality of functional elements (and / or a plurality of functional volume sections) are provided, in particular some of said functional elements and / or functional volume sections are arranged / located at the same vertical level relative to the thickness of the component carrier and / or the mounting base (see, for example, Figure 5 This can offer the advantage of being able to efficiently and reliably implement these functions at the same area / level / layer, using the same features / dimensions / materials required to implement them. Furthermore, these functions can be manufactured using a common process, for example by embedding them in a component carrier cavity. While the first group of second pads can be biased toward the first functional component, the second group of second pads can be biased (in the other direction) toward the second functional component.

[0080] According to another embodiment, at least one of the functional elements and / or functional volume sections is arranged at a first vertical level (on / in a layer) of the component carrier (or mounting base), and at least one further functional element and / or functional volume section is arranged at a second vertical level of the component carrier (or mounting base).

[0081] According to another embodiment, at least some of the second pads are biased towards at least one of the functional elements and / or functional volume portions, and other second pads are biased towards / arranged in alignment with another functional element and / or functional volume portion (see, e.g. Figure 5).

[0082] In an example, the first vertical level and the second vertical level are defined by a layer structure of a component carrier (or mounting base).In another example, the first vertical level is located in the component carrier and the second vertical level is located in the mounting base.

[0083] According to another embodiment, at least some of the second pads are offset in a plan view relative to the corresponding first pads in different directions toward the position of the corresponding functional element and / or functional volume portion (see, for example, Figure 4 and Figure 5 ). In the case where multiple functional elements are located at different positions, it may be very advantageous to offset the positions of the corresponding second pads accordingly. In particular, the second pads associated with one function may be grouped and then biased toward the functional element.

[0084] According to another embodiment, the semiconductor element and the redistribution structure are integrated into a component assembly. This can offer the advantage of enabling the creation of a highly compact electronic device. Such a component assembly (e.g., a package) can be handled and mounted on (or embedded in) a component carrier in a flexible manner.

[0085] According to another embodiment, the redistribution layer structure has a planar area extension that is equal to or smaller than the planar extension of the semiconductor element. Material and effort can be saved when the dimensions of the redistribution layer structure are sufficient to fulfill its (insertion) function.

[0086] According to exemplary embodiments, the present invention can focus on the change in the distribution of contacts from the chip (semiconductor element) level to the opposite redistribution layer side in relation to the PCB / substrate layout (i.e., the arrangement structure of vias / components), and ultimately on the combination of some contacts in the redistribution layer to simplify the interaction between the chip and the PCB / substrate. The present invention is particularly useful when bundled contacts (secondary pads) with a common function (e.g., signal contacts) are grouped (and / or moved) toward specific sub-areas in the main surface of the PCB / substrate due to their specific configuration.

[0087] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate), and an interposer.

[0088] In one embodiment, the component carrier is formed as a plate. This facilitates a compact design, while still providing a large base for components mounted thereon. Furthermore, bare chips (dies), in particular, as an example of embedded electronic components, can be easily embedded in thin boards such as printed circuit boards due to their low thickness.

[0089] In an embodiment, a component carrier stack includes at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the aforementioned electrically insulating layer structure and the electrically conductive layer structure, formed, in particular, by applying mechanical pressure and / or heat. The aforementioned stack can provide a plate-like component carrier that can provide a large, yet still very thin and compact, mounting surface for additional components.

[0090] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying heat. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise resin and / or glass fiber, so-called prepregs, or FR4 materials. The electrically conductive layer structures may be connected to one another in a desired manner by forming holes through the laminate, for example by means of laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material, in particular copper, thereby forming vias or any other through-hole connections. A filled hole connecting the entire stack (a through-hole connection extending through a plurality of layers or the entire stack) or connecting at least two electrically conductive layers is referred to as a via. Similarly, optical interconnects may be formed through the layers of the stack to receive an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in a printed circuit board, a printed circuit board is typically configured to accommodate one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. The one or more components can be connected to the corresponding major surface by soldering. The dielectric portion of the PCB may include a resin with reinforcing fibers (e.g., glass fibers).

[0091] In the context of this application, the term "substrate" can particularly refer to a small component carrier. Relative to a PCB, a substrate can be a relatively small component carrier on which one or more components can be mounted, and can be used as a connection medium between one or more chips and another PCB. For example, the substrate can have approximately the same size as the components (particularly electronic components) to be mounted on the substrate (for example, in the case of a chip scale package (CSP)). In another embodiment, the size of the substrate can greatly exceed the allocated components (for example, in a flip chip ball grid array (FCBGA) configuration). More specifically, a substrate can be understood as a component carrier for electrical connectors or electrical networks and a component carrier for connectors that are arranged horizontally and / or vertically, but with a relatively high density, comparable to a printed circuit board (PCB). Horizontal connectors are, for example, conductive paths, while vertical connectors can be, for example, drilled holes. These horizontal and / or vertical connectors are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated components or unaccommodated components (such as bare wafers) - particularly IC chips - and a printed circuit board or an intermediate printed circuit board. Therefore, the term “substrate” also includes “IC substrate.” The dielectric part of the substrate may comprise a resin with reinforcement particles, such as reinforcement spheres, in particular glass spheres.

[0092] The substrate or interposer may include or be composed of at least one layer of glass, silicon (Si), and / or a photoimageable or dry-etchable organic material such as an epoxy-based laminate material (e.g., an epoxy-based laminate film), or a polymer composite (which may or may not include photosensitive and / or heat-sensitive molecules) such as polyimide or polybenzoxazole.

[0093] In an embodiment, at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a bismaleimide-triazine resin, a polyphenylene derivative (e.g., based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and / or combinations thereof. Reinforcement structures, such as meshes, fibers, spheres, or other types of filler particles, made of glass (multilayer glass), may also be used to form a composite. Semi-cured resins combined with reinforcing agents, such as fibers impregnated with the above resins, are called prepregs. These prepregs are typically named after their properties, such as FR4 or FR5, which describe their flame retardant properties. Although prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates (e.g., laminate films) or photoimageable dielectric materials, may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins may be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low or ultra-low DK materials can be applied as electrically insulating layer structures in the component carrier.

[0094] In an embodiment, at least one electrically conductive layer structure comprises at least one of copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (particularly doped) silicon, titanium, and platinum. Although copper is generally preferred, other materials or other types of coatings thereof, particularly coatings with superconducting materials or conductive polymers such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), are also possible.

[0095] At least one additional component can be embedded in the stack and / or can be surface mounted on the stack. The component and / or at least one additional component can be selected from: a non-conductive inlay, a conductive inlay (e.g., a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g., a heat pipe), a light guiding element (e.g., an optical waveguide or optical conductor connector), an electronic component, or a combination thereof. The inlay can be, for example, a metal block with or without a coating of insulating material (IMS-inlay), which can be embedded or surface mounted to promote heat dissipation. Suitable materials are defined by their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides, and / or ceramics, such as copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). Other geometries with increased surface area are also often used to increase the heat exchange capacity. Furthermore, the component may be an active electronic component (implementing at least one pn junction), a passive electronic component, such as a resistor, an inductor, or a capacitor), an electronic chip, a memory device (e.g., a DRAM or other data memory), a filter, an integrated circuit (such as a field programmable gate array (FPGA), a programmable array logic (PAL), a general array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (e.g., a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET)). The power management components are all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and / or any other suitable inorganic compound), optoelectronic interface elements, light-emitting diodes, optical couplers, voltage converters (e.g., DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips, and energy harvesting units. However, other components may also be embedded in the component carrier. For example, a magnetic element may be used as a component. Such a magnetic element may be a permanent magnetic element (e.g., a ferromagnetic element, an antiferromagnetic element, a multiferroic element, or a ferrimagnetic element, such as a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer, or other component carrier, for example in a board-in-board configuration. The component can be surface mounted on the component carrier and / or embedded in the interior of the component carrier. In addition, other components can be used as components, in particular components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagated from the environment.

[0096] In an embodiment, the component carrier is a laminated component carrier. In this embodiment, the component carrier is a composite of multiple layers that are stacked and connected together by applying pressure and / or heat.

[0097] After processing the internal layer structure of the component carrier, one or both main surfaces of the processed layer structure can be covered symmetrically or asymmetrically with one or more further electrically insulating and / or electrically conductive layer structures (in particular by lamination). In other words, the layer buildup can be continued until the desired number of layers is obtained.

[0098] After the formation of the stack of electrically insulating and electrically conductive layer structures is complete, the resulting layer structure or component carrier can be subjected to a surface treatment.

[0099] In particular, regarding surface treatment, an electrically insulating solder resist can be applied to one or both major surfaces of a laminate or component carrier. For example, the solder resist can be formed over the entire major surface and then patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to an electronic peripheral. Surface portions of the component carrier that remain covered with the solder resist, particularly those containing copper, can be effectively protected from oxidation or corrosion.

[0100] In terms of surface treatment, a surface treatment can also be selectively applied to exposed electrically conductive surface portions of a component carrier. This surface treatment can be an electrically conductive covering material on exposed electrically conductive layer structures (e.g., pads, conductive traces, etc., particularly comprising or consisting of copper) on the surface of the component carrier. If such exposed electrically conductive layer structures are not protected, the exposed electrically conductive component carrier material (particularly copper) can oxidize, making the component carrier less reliable. The surface treatment can then be formed, for example, as a joint between a surface-mounted component and the component carrier. The surface treatment has the function of protecting the exposed electrically conductive layer structures (particularly copper circuits) and can facilitate bonding to one or more components, such as by soldering. Examples of suitable materials for the surface treatment include organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel electroless palladium immersion gold (ENEPIG), gold (particularly hard gold), chemical tin (chemically plated and electroplated), nickel gold, nickel palladium, etc. Furthermore, nickel-free surface treatments are available, particularly for high-speed applications. Examples are ISIG (Immersion Silver / Gold) and EPAG (Electroless Palladium Autocatalytic Gold).

[0101] The aspects defined above and further aspects of the invention are apparent from the strength of the embodiments described hereinafter and will be explained with reference to these examples of embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and will be described with reference to these examples of embodiment.

[0103] Figures 1 to 6 Electronic devices according to exemplary embodiments of the present invention are respectively shown.

[0104] Figure 7 a and Figure 7 b shows an example of a conventional device.

[0105] Figure 8 a. Figure 8 b and Figure 9 A plan view of an offset second pad at a second major surface is shown according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0106] The drawings in the accompanying drawings are schematic illustrations only. In different drawings, similar or identical elements are provided with the same reference numerals.

[0107] Figure 1 An electronic device 100 according to an exemplary embodiment of the present invention is shown. The electronic device 100 comprises in principle three parts: a semiconductor element 110 , a redistribution layer (RDL) structure 120 and a component carrier 130 , wherein the RDL structure serves as an interposer between the semiconductor element 110 and the component carrier 130 .

[0108] In this example, the semiconductor element 110 is a packaged IC (chip) that includes a plurality of exposed electrical connection pads 112 at a lower / bottom major surface 111 .

[0109] The redistribution layer structure 120 includes a plurality of electrically conductive traces and vias embedded in a dielectric material. A first (upper) main surface 121 of the RDL structure 120 is electrically associated with the (lower) main surface 111 of the semiconductor element 110, i.e., the first (upper) main surface 121 of the RDL structure 120 is in contact with the (lower) main surface 111 of the semiconductor element 110. A second (lower) main surface 122 of the RDL structure 120 is arranged opposite the first main surface 121 and is associated with the component carrier 130. In addition, the redistribution layer structure 120 includes a plurality of first pads 123, which are arranged on the (upper) first main surface 121 and are electrically connected to the plurality of (small) connection pads 112 of the semiconductor element 110. The RDL structure 120 also includes a plurality of second pads 124, which are exposed at the (lower) second main surface 122 and are electrically connected to the (large) electrical contacts (not shown) of the component carrier 130.

[0110] In this example, the component carrier 130 is configured as a printed circuit board (PCB) or an IC substrate having a multi-layer stack (not shown in detail). The component carrier 100 includes a plurality of electrically insulating layer structures 132 and electrically conductive layer structures 134 in the stack. Some of the electrically conductive layer structures 134 are electrically connected (via the above-mentioned electrical contacts) to a plurality of second pads 124 (shown only schematically) of the RDL structure 120.

[0111] The electronic device 100 further comprises a functional element 140 which is embedded in the component carrier 130 (laminate) in this example. It can be seen that at least some of the second pads 124 are in side view (in plan view, in FIG. 1 ). Figure 8 8a and 8b) are offset relative to the corresponding first pad 123 along the offset direction OD. The offset (shift) is thereby directed toward the position of the functional element 140. The offset of the second pad 124 relative to the first pad 123 is at least the width of the first pad 123 and / or the second pad 124 in the offset direction OD.

[0112] Figure 2 FIG. 1 shows an electronic device 100 according to another exemplary embodiment of the present invention. Figure 1 The example described in is very similar. The difference is that the component carrier 130 is thinner (in the z-direction) and comprises a plurality of electrical contacts 135 at the lower main surface, which are implemented here in the form of solder balls. In this example, the component carrier 100 is configured as an IC substrate.

[0113] Figure 3An electronic device 100 according to another exemplary embodiment of the present invention is shown. In this example, the electronic device 100 further comprises a mounting base 138, which is another component carrier in this case. For example, the component carrier 130 can be configured as an IC substrate, while the further component carrier 138 can be configured as a printed circuit board (or a frame structure). The component carrier 130 is mounted to the mounting base 138 via electrical contacts 135 (solder balls). In the example shown, the functional element 140 is embedded in the mounting base 138 (part of the electronic device 100) rather than in the component carrier 130.

[0114] The second pad 124 is biased in an offset direction OD (in plan view) toward the position of the functional element 140 in the mounting base 138 .

[0115] Figure 4 FIG2 shows an electronic device 100 according to another exemplary embodiment of the present invention. In this example, the electronic device 100 is provided with not one but three functional elements (also considered functional element volume portions) 140a-140c. The first functional element 140a is embedded in the right peripheral edge of the component carrier 130, while the second functional element 140b is embedded in the left peripheral edge of the component carrier 130. Furthermore, the third functional element 140c is embedded in the center of the mounting base 138.

[0116] At this time, the second pads 124 are divided into subgroups according to the positions of the corresponding functional elements 140a-140c. Each subgroup of the second pads 124 is offset relative to the corresponding first pad 123 with respect to a subsection of the second main surface 122. In the illustrated example, the first group 124a of the second pads 124 is offset toward the first functional element 140a along a first offset direction OD1 (i.e., offset to the right). The second group 124b of the second pads 124 is offset toward the second functional element 140b along a second offset direction OD2 (i.e., offset to the left). In addition, the third group 124c of the second pads 124 is offset toward (or alternatively, aligned with) the third functional element 140c along a third offset direction OD3 (i.e., offset toward the center of the second main surface 122).

[0117] Figure 5An electronic device 100 according to another exemplary embodiment of the present invention is shown. In this example, the component carrier 130 is configured as a multilayer stacked printed circuit board having a plurality of electrically insulating layer structures 132a, 132b. While the first and second functional elements 140a, 140b are located at the outer periphery (in the respective cavities) of the upper electrically insulating layer structure 132a of the component carrier 130 (located at the same vertical level), the third functional element 140c is located in the center (in the cavity of the lower electrically insulating layer structure 132b) of the component carrier 130.

[0118] As above Figure 4 As described above, the first group 124a of the second pads 124 is biased toward the first functional element 140a (OD1), while the second group 124b of the second pads 124 is biased toward the second functional element 140b (OD2). The third group 124c of the second pads 124 is biased toward the center of the second major surface 122 toward the third functional element 140c (or alternatively, is aligned only with the center of the second major surface 122).

[0119] Figure 6 FIG. 1 shows an electronic device 100 according to another exemplary embodiment of the present invention. Figure 1 The embodiment described in is very similar, except that the redistribution layer structure 120 is embedded in the component carrier 130 (instead of being mounted on the component carrier 130). The second pad 124 is offset towards the functional element 140 in the same way.

[0120] Figure 8 8a and 8b respectively show a plan view (along the z-axis on the xy plane) of the second major surface 122 of the redistribution layer structure 120 according to an exemplary embodiment of the present invention.

[0121] Figure 8 a: shows three subgroups 124a - 124c of the second pads 124 , which are respectively offset relative to corresponding first pads 123 (not shown).

[0122] The first group 124 a of the second pads 124 is dedicated to transmitting signals input to / output from the semiconductor element 110 to the functional element 140 .

[0123] The second group 124 b of the second pads 124 is dedicated to supplying power to the semiconductor element 110 and / or the functional element 140 .

[0124] The third group 124 c of the second pads 124 is dedicated to grounding the semiconductor element 110 .

[0125] Figure 8 b: In this example, some of the second pads 124 (here, the second group 124b) are the remaining pads, grouped in the remaining portion of the second major surface 122, and are not offset (with respect to the second pads 124). Figure 7 b for comparison).

[0126] Figure 9 FIG. 1 shows a plan view (along the z-axis on the xy plane) of the second main surface 122 of the redistribution layer structure 120 according to another exemplary embodiment of the present invention. Figure 8 Compared to the embodiments of FIG8a and FIG8b, second pads 124a and 124b are only slightly (a small amount) offset OD1 and OD2 relative to the corresponding first pads. For example, the distance by which second pads 124a and 124b are offset relative to the first pads along the offset direction OD corresponds to the width (preferably the diameter) of first pad 123 and / or second pad 124. In this example, second pads 124a and 124b, which are slightly offset in the same directions OD1 and OD2, are pads associated with the same functional element / part and / or the same type of electrical path (signal, power, or ground).

[0127] Reference numerals

[0128] 100 Electronic Devices

[0129] 110 semiconductor components

[0130] 111 Main surface of semiconductor element

[0131] 112 connection pads

[0132] 120 Redistribution layer structure

[0133] 121 first main surface

[0134] 122 second main surface

[0135] 123 multiple first pads

[0136] 124 multiple second pads

[0137] 130 Component carrier

[0138] 132 Electrical insulation layer structure

[0139] 134 Electrically conductive layer structure

[0140] 135 electrical contacts and solder balls of component carriers

[0141] 138 mounting base, other component carrier

[0142] 140 functional elements

[0143] OD offset direction

[0144] 200 Traditional electronic devices

[0145] 210 Traditional Chips

[0146] 220 Traditional Intermediary Layer

[0147] 221 Traditional upper main surface

[0148] 222 Traditional lower main surface

[0149] 223 Traditional First Mat

[0150] 224 Traditional second pad.

Claims

1. An electronic device (100), comprising: A semiconductor component (110) comprising a plurality of connection pads (112) on at least one main surface (111); A redistribution layer structure (120), the redistribution layer structure (120) being coupled to the main surface (111) of the semiconductor element (110), wherein the redistribution layer structure (120) comprises: a first main surface (121) electrically associated with the main surface (111) of the semiconductor element (110), a second main surface (122), the second main surface (122) being opposite to the first main surface (121), a plurality of first pads (123), the first pads (123) being disposed on the first main surface (121) and electrically connected to the plurality of connection pads (112), and a plurality of second pads (124), the second pads (124) being exposed at the second major surface (122); A component carrier (130, 138) coupled to the redistribution layer structure (120), wherein the component carrier (100) comprises: at least one electrically insulating layer structure (132), and at least one electrically conductive layer structure (134), wherein the at least one electrically conductive layer structure (134) is electrically connected to the plurality of second pads (124); and at least one functional element (140), the functional element (140) being arranged in / on the component carrier (130, 138); At least some of the second pads (124) are offset relative to the corresponding first pads (123) toward the position of at least one functional element (140) in a plan view.

2. The electronic device (100) according to claim 1, in, At least some of the second pads (124) are offset relative to the first pad (123) along an offset direction (OD) by a distance of at least the width of the first pad (123) and / or the second pad (124).

3. The electronic device (100) according to any one of claims 1 to 2, in, At least some of the second pads (124) are offset relative to the first pads (123) and are grouped in sub-portions of the second major surface (122).

4. The electronic device (100) according to any one of claims 1 to 3, in, Only at least some of the second pads (124) are offset in a plan view relative to the position of the corresponding first pads (123) toward the functional element (140), In particular, The remaining pads (123, 124) are positioned in the remaining portion of the second major surface (122); and / or the remaining pads (123, 124) are offset in the remaining portion of the second major surface (122); and / or the remaining pads (123, 124) are grouped in the remaining portion of the second major surface (122).

5. The electronic device (100) according to any one of claims 1 to 4, in, Some of the plurality of connection pads (112) are configured to: transmit signals input to / output from the semiconductor element (110); and / or wherein some of the plurality of connection pads (112) are configured to transmit power to the semiconductor element (110); and / or Some of the plurality of connection pads (112) are configured to ground the semiconductor element (110).

6. The electronic device (100) according to claim 5, in, Some of the plurality of second pads (124) that are offset relative to corresponding first pads (123) in a plan view are the following second pads: The second pad is configured to transmit a signal input to / output from the semiconductor element (110), and / or The second pad is configured to transmit power supply to the semiconductor element (110), and / or The second pad is configured to ground the semiconductor element (110).

7. The electronic device (100) according to claim 5 or 6, in, At least some of the second pads (124) are electrically connected to corresponding first pads (123), and wherein the corresponding first pad (123) is connected to the corresponding connection pad (112) such that each of at least some of the second pads (124) is configured as: transmitting a signal input to / output from the semiconductor element (110), and / or delivering power to the semiconductor element (110), and / or The semiconductor element (110) is grounded.

8. The electronic device (100) according to claim 7, in, At least one of the functional elements (140) includes a component for managing / transmitting / requesting a specific signal, and / or power supply, and / or ground connection, wherein the plurality of second pads (124) are offset relative to the corresponding first pads (123) in a plan view, such that the required second pads (124) are configured as follows: transmitting a signal input to / output from the semiconductor element (110), and / or delivering a power supply to the semiconductor element (110), and / or is grounded, The device is biased toward the position of the functional element (140).

9. The electronic device (100) according to any one of claims 1 to 8, in, At least one of the functional elements (140) comprises at least one functional volume portion.

10. The electronic device (100) according to claim 9, in, At least one of the functional volume sections comprises: Power distribution function, in particular, the power distribution function is a redistribution structure, and / or Power delivery functionality, in particular, the power delivery functionality is provided by a plurality of embedded capacitor components, and / or At least one safety-related component, and / or At least one thermal management structure, and / or At least one electro-optical structure.

11. The electronic device (100) according to claim 9 or 10, in, At least one of the functional volume portions is electrically connected to a second pad (124) configured to: transmitting / receiving a signal input to / output from the semiconductor element (110), and / or delivering power to the semiconductor element (110), and / or is grounded, and is biased towards the position of the functional volume portion.

12. The electronic device (100) according to any one of claims 9 to 11, wherein: At least one of the functional volume sections is arranged in a layer structure (132, 134) of the component carrier (130), In particular, at least one of the functional volume sections is arranged in a cavity provided in a layer structure (132, 134) of the component carrier (130).

13. The electronic device (100) according to any one of claims 1 to 12, wherein: The component carrier (130) includes an integrated circuit substrate, In particular, The redistribution layer (120) is connected to the integrated circuit substrate.

14. The electronic device (100) according to any one of claims 1 to 13, wherein: The component carrier (130) includes a mounting base (138), In particular, the mounting base (138) is a printed circuit board and / or an interposer, More particularly, the mounting base (138) is connected to the integrated circuit substrate.

15. The electronic device (100) according to claim 13 or 14, in, At least one of the functional element (140) and / or the functional volume portion is located in / on the mounting base (138), or at least one of the functional element (140) and / or the functional volume portion is located in / on the integrated circuit substrate (130), and At least some of the second pads (124) are offset toward the position of the functional element (140) and / or the functional volume portion in a plan view.

16. The electronic device (100) according to any one of claims 1 to 15, wherein: A plurality of functional elements (140) and / or a plurality of functional volume parts are provided, In particular, Some of the functional elements (140) and / or some of the functional volume sections are arranged at the same vertical level relative to the thickness of the component carrier (130).

17. The electronic device (100) according to any one of claims 1 to 16, wherein: At least one of the functional elements (140) and / or the functional volume sections is arranged at a first vertical level of the component carrier (130), and at least one further functional element (140) and / or functional volume section is arranged at a second vertical level of the component carrier (130, 138), wherein at least some of the second pads (124) are biased toward the at least one of the functional element (140) and / or the functional volume portion, and wherein other second pads (124) are biased toward the other functional element and / or functional volume portion.

18. The electronic device (100) according to claim 16 or 17, in, At least some of the second pads (124) are offset in different directions relative to the corresponding first pads (123) toward the positions of the corresponding functional elements (140) and / or functional volume parts in a plan view.

19. The electronic device (100) according to any one of claims 1 to 18, in, The semiconductor element (110) and the redistribution structure (120) are integrated into a component assembly.

20. The electronic device (100) according to any one of claims 1 to 19, wherein The redistribution layer structure (120) has a planar area extension that is equal to or smaller than a planar extension of the semiconductor element (110).

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