Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel and a preparation method thereof and a display device, the display panel is provided with a display area and comprises a first substrate and a second substrate which are arranged in a box-to-box mode, the first substrate is provided with a plurality of sub-pixels located in the display area, and at least one sub-pixel comprises a first electrode and a second electrode, the first substrate comprises a first substrate and an electrode structure layer arranged on the side, close to the second substrate, of the first substrate, and the electrode structure layer at least comprises a first electrode and a second electrode of at least one sub-pixel; the first substrate further comprises a heating structure layer, and the heating structure layer is located on the side, close to the first substrate, of the electrode structure layer and is configured to heat the display panel.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) have rapidly developed due to their small size, low power consumption, and zero radiation. An LCD panel consists of a cell-aligned thin-film transistor (TFT) array substrate and a color filter (CF) substrate. Liquid crystal (LC) molecules are positioned between the array and CF substrates. Controlling the common electrode and pixel electrodes creates an electric field that drives the liquid crystal deflection, achieving grayscale display. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, the present disclosure provides a display panel having a display area, including: a first substrate and a second substrate arranged in a cell, the first substrate being provided with a plurality of sub-pixels located in the display area, at least one sub-pixel including: a first electrode and a second electrode, the first substrate including: a first substrate and an electrode structure layer arranged on a side of the first substrate close to the second substrate, the electrode structure layer including at least: a first electrode and a second electrode for at least one sub-pixel;

[0005] The first substrate further includes a heating structure layer, which is located on a side of the electrode structure layer close to the first substrate and is configured to heat the display panel.

[0006] In an exemplary embodiment, the first substrate further includes: a device structure layer and an intermediate insulating layer;

[0007] The device structure layer is located on a side of the heating structure layer close to the first substrate, and the device structure layer includes: a data line, a scan line, and a pixel transistor located in the display area, and the pixel transistor is electrically connected to the data line, the scan line, and the first electrode of at least one sub-pixel respectively;

[0008] The intermediate insulating layer is located between the device structure layer and the heating structure layer, and the intermediate insulating layer includes: a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer sequentially stacked on the first substrate.

[0009] In an exemplary embodiment, the dielectric constant of the organic insulating layer is smaller than the dielectric constant of at least one of the first inorganic insulating layer and the second inorganic insulating layer, and the thickness of the organic insulating layer is greater than the thickness of at least one of the first inorganic insulating layer and the second inorganic insulating layer;

[0010] The materials for making the first inorganic insulating layer and the second inorganic insulating layer include at least silicon nitride, and the materials for making the organic insulating layer include at least organic film.

[0011] In an exemplary embodiment, a non-display area is further provided, the non-display area including: a binding area located on a first side of the display area and a frame area located on the other side of the display area, the binding area including: a first fan-out area, a second fan-out area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area;

[0012] The heating structure layer includes: at least one heating line at least partially located in the display area, at least one first heating line located in the first fan-out area, and at least one second heating line located in the second fan-out area, the driver chip area, and the binding pin area;

[0013] The at least one first heating trace is connected to the at least one heating trace and the at least one second heating trace, respectively.

[0014] In an exemplary embodiment, the device structure layer further includes: a first fan-out trace located in the first fan-out region and a second fan-out trace located in the second fan-out region, at least one first fan-out trace being electrically connected to at least one data line and at least one second fan-out trace, respectively;

[0015] An orthographic projection of at least one data line on the first substrate at least partially overlaps with an orthographic projection of at least one heating line on the first substrate;

[0016] An orthographic projection of at least one first heating trace on the first substrate at least partially overlaps with an orthographic projection of at least one first fan-out trace on the first substrate;

[0017] An orthographic projection of the at least one second heating trace on the first substrate at least partially overlaps with an orthographic projection of the at least one second fan-out trace on the first substrate.

[0018] In an exemplary embodiment, an orthographic projection of the at least one data line on the first substrate coincides with an orthographic projection of the at least one heating line on the first substrate;

[0019] An orthographic projection of at least a portion of the at least one first heating trace on the first substrate coincides with an orthographic projection of the at least one first fan-out trace on the first substrate.

[0020] In an exemplary embodiment, at least one second heating trace comprises: a first heating connection portion and a second heating connection portion; at least one second fan-out trace comprises: a first fan-out connection portion and a second fan-out connection portion;

[0021] The first heating connection portion extends along a third direction, the first fan-out connection portion extends along a fourth direction, the second fan-out connection portion and the second heating connection portion extend along a second direction, the third direction intersects the first direction, the second direction and the fourth direction respectively, the first direction is an extension direction of the scan line, and the second direction is an extension direction of the data line;

[0022] The first heating connection portion is connected to the second heating connection portion and at least one first heating line respectively, and the first fan-out connection portion is connected to the second fan-out connection portion and at least one first fan-out connection line respectively.

[0023] In an exemplary embodiment, an orthographic projection of the second heating connection portion of the at least one second heating trace on the first substrate and an orthographic projection of the second fan-out connection portion of the at least one second fan-out trace on the first substrate do not have an overlapping area;

[0024] The orthographic projections of the second heating connection portions of the other second heating traces except the target second heating trace on the first substrate are located on a side of the orthographic projection of the second heating connection portion of the target second heating trace on the first substrate away from the orthographic projection of the second fan-out connection portion of the target second fan-out trace on the first substrate, and the orthographic projections of the second fan-out connection portions of the other second fan-out traces except the target second fan-out trace on the first substrate are located on a side of the orthographic projection of the second fan-out connection portion of the target second fan-out trace on the first substrate away from the orthographic projection of the second heating connection portion of the target second heating trace on the first substrate;

[0025] A spacing along the first direction between the second heating connection portion of the target second heating trace and the second fan-out connection portion of the target second fan-out trace is greater than or equal to 10 microns;

[0026] The target second heating trace is the second heating trace having the shortest second heating connection portion along the second direction, and the target second fan-out trace is the second fan-out trace having the shortest second fan-out connection portion along the second direction.

[0027] In an exemplary embodiment, the present invention further comprises: a frame sealant located between the first substrate and the second substrate, wherein the organic insulating layer is provided with an organic via;

[0028] The orthographic projections of the organic via on the first substrate at least partially overlap with the orthographic projections of the second heating connection portion of the at least one second heating trace and the orthographic projections of the second fan-out connection portion of the at least one second fan-out trace on the first substrate, respectively, and do not overlap with the orthographic projections of the first heating connection portion of the at least one second heating trace and the orthographic projections of the first fan-out connection portion of the at least one second fan-out trace on the first substrate;

[0029] The orthographic projection of the frame sealing adhesive on the first substrate at least partially overlaps with the orthographic projection of the organic via on the first substrate, and the length of the frame sealing adhesive along the second direction is smaller than the length of the organic via along the second direction.

[0030] In an exemplary embodiment, the electrode structure layer further comprises: a plurality of data connection electrodes, and the heating structure layer further comprises: a plurality of heating connection electrodes;

[0031] The plurality of data connection electrodes correspond one-to-one to the plurality of first fan-out traces and one-to-one to the plurality of second fan-out traces, and at least one data connection electrode is electrically connected to the corresponding first fan-out trace and the corresponding second fan-out trace respectively;

[0032] The plurality of heating connection electrodes correspond one-to-one to the plurality of first heating traces, at least one heating connection electrode is electrically connected to the corresponding first heating trace, and at least one second heating trace is electrically connected to at least one heating connection electrode.

[0033] In an exemplary embodiment, the shape of the heating connection electrode includes: a plurality of annular regions extending along a first direction;

[0034] The orthographic projection of the at least one data connection electrode on the first substrate is located within the range of the orthographic projection of the at least one annular area on the first substrate.

[0035] In an exemplary embodiment, the first substrate further includes: a plurality of electrostatic discharge circuits located in the first fan-out area, at least one electrostatic discharge circuit being electrically connected to at least one first fan-out trace, and at least one electrostatic discharge circuit being electrically connected to at least one first heating trace.

[0036] In an exemplary embodiment, the plurality of electrostatic release circuits include: three rows of electrostatic release circuits, at least one row of electrostatic release circuits includes: N electrostatic release circuits, the orthographic projection of the kth first heating trace on the first substrate at least partially overlaps with the orthographic projection of the 3kth first fan-out trace on the first substrate, N≥1, 1≤k≤2N / 3.

[0037] In an exemplary embodiment, the N electrostatic discharge circuits in the first row are arranged in an interlaced manner with the N electrostatic discharge circuits in the second row, and the N electrostatic discharge circuits in the first row are arranged in a matrix with the N electrostatic discharge circuits in the third row;

[0038] The nth electrostatic discharge circuit in the first row is electrically connected to the 2n-1th first fan-out trace, the nth electrostatic discharge circuit in the second row is electrically connected to the 2nth first fan-out trace, the 3k-1th electrostatic discharge circuit in the third row is electrically connected to the 2k-1th first heating trace, and the 3kth electrostatic discharge circuit in the third row is electrically connected to the 2kth first fan-out trace;

[0039] The orthographic projection of at least a portion of the 2n-1th first fan-out trace on the first substrate and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the first row and the orthographic projection of the n+1th electrostatic discharge circuit in the first row; the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate and the orthographic projection of at least a portion of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the second row and the orthographic projection of the n+1th electrostatic discharge circuit in the second row, and the first first fan-out trace is located on a side of the first electrostatic discharge circuit in the second row away from the second first fan-out trace; the orthographic projection of at least a portion of the 2n-1th first fan-out trace on the first substrate and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the third row and the orthographic projection of the n+1th electrostatic discharge circuit in the third row on the first substrate.

[0040] In an exemplary embodiment, an orthographic projection of the 2k-th first heating trace on the first substrate at least partially overlaps with an orthographic projection of the 6k-1-th first fan-out trace on the first substrate.

[0041] In an exemplary embodiment, the N electrostatic discharge circuits in the first row are interleaved with the N electrostatic discharge circuits in the second row, and the N electrostatic discharge circuits in the second row are interleaved with the N electrostatic discharge circuits in the third row;

[0042] The nth electrostatic discharge circuit in the first row is electrically connected to the 2n-1th first fan-out trace, the nth electrostatic discharge circuit in the second row is electrically connected to the 2nth first fan-out trace, the 3k-2th electrostatic discharge circuit in the third row is electrically connected to the 2k-1th first heating trace, and the 3kth electrostatic discharge circuit in the third row is electrically connected to the 2kth first heating trace;

[0043] The orthographic projection of at least a portion of the 2n-1th first fan-out trace on the first substrate and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the first row and the orthographic projection of the n+1th electrostatic discharge circuit in the first row on the first substrate; the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate and the orthographic projection of at least a portion of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the second row and the orthographic projection of the n+1th electrostatic discharge circuit in the second row on the first substrate. and the first first fan-out routing is located on a side of the first electrostatic discharge circuit in the second row away from the second first fan-out routing; the orthographic projection of at least part of the 2n+1th first fan-out routing on the first substrate and the orthographic projection of at least part of the 2n+2th first fan-out routing on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the third row on the first substrate and the orthographic projection of the n+1th electrostatic discharge circuit in the third row on the first substrate, and the first first fan-out routing and the second first fan-out routing are located on a side of the first electrostatic discharge circuit in the third row away from the third first fan-out routing.

[0044] In an exemplary embodiment, there is no overlapping region between the orthographic projection of the 2kth first heating trace on the first substrate and the orthographic projection of the 6k-1th first fan-out trace on the first substrate.

[0045] In an exemplary embodiment, the heating structure layer further comprises: at least one frame heating trace located in the frame region;

[0046] The at least one frame heating line includes: a first frame heating line and a plurality of second frame heating lines;

[0047] The first frame heating line extends along a first direction and is located on a second side of the display area. The at least one second frame heating line extends along a second direction and is located on at least one of a third side and a fourth side of the display area. The first side and the second side are oppositely arranged, and the third side and the fourth side are oppositely arranged. The first direction is an extension direction of the scan line, and the second direction is an extension direction of the data line.

[0048] The first frame heating wiring is respectively connected to at least one second frame heating wiring and at least one heating wire.

[0049] In an exemplary embodiment, the first substrate further includes: a gate driving circuit located on at least one of the third side and the fourth side of the non-display area;

[0050] The orthographic projection of the at least one second frame heating trace on the first substrate is located on a side of the orthographic projection of the gate driving circuit on the first substrate close to the display area.

[0051] In an exemplary embodiment, the first substrate further includes: a common electrode power supply line located in the non-display area, the common electrode power supply line being located in the device structure layer, the common electrode power supply line being electrically connected to the second electrode of at least one sub-pixel, and being disposed around the display area;

[0052] The orthographic projection of at least one second frame heating trace on the first substrate at least partially overlaps with the orthographic projection of at least part of the common electrode power supply line on the first substrate.

[0053] In an exemplary embodiment, the first substrate further includes: a data driver chip located in the driver chip area and a first circuit board and a second circuit board located in the binding pin area;

[0054] The data driver chip is electrically connected to at least one second fan-out trace, the first circuit board is electrically connected to the data driver chip, and the second circuit board is electrically connected to at least one second heating trace.

[0055] In an exemplary embodiment, the first circuit board and the second circuit board are the same circuit board.

[0056] In an exemplary embodiment, the first substrate further includes: at least one electrostatic discharge circuit and a common electrode power supply line, the electrostatic discharge circuit includes: the first substrate further includes: at least one electrostatic discharge circuit, a common electrode power supply line, a first fan-out trace and a second fan-out trace

[0057] The electrostatic discharge circuit includes: at least one release transistor, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode;

[0058] The device structure layer includes: a semiconductor layer, a first conductive layer and a second conductive layer provided on the first substrate;

[0059] The semiconductor layer includes at least: an active pattern of at least one release transistor and an active pattern of at least one pixel transistor;

[0060] The first conductive layer at least includes: a scan line, a common electrode power supply line, a control electrode of at least one release transistor and a control electrode of at least one pixel transistor;

[0061] The second conductive layer at least includes: a data line, a first fan-out line, a first electrode and a second electrode of at least one release transistor, and a first electrode and a second electrode of at least one pixel transistor;

[0062] The second fan-out trace is located in the first conductive layer or the second conductive layer.

[0063] In an exemplary embodiment, the heating structure layer further comprises: a frame heating trace, and the heating structure layer comprises a third conductive layer;

[0064] The third conductive layer at least includes: a heating line, a first heating trace, a second heating trace and a frame heating trace.

[0065] In an exemplary embodiment, the electrode structure layer includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the first substrate; the first substrate further includes: at least one electrostatic discharge circuit; the electrostatic discharge circuit includes: at least one release transistor; the first substrate further includes: a data connection electrode and a release connection electrode; the data connection electrode is electrically connected to the first fan-out trace and the second fan-out trace, respectively; the release connection electrode is electrically connected to at least two release transistors, or is electrically connected to one release transistor and the first heating trace, respectively;

[0066] The fourth conductive layer at least includes: a second electrode of at least one sub-pixel;

[0067] The fifth conductive layer at least includes: a first electrode of at least one sub-pixel, a data connection electrode, and a release connection electrode.

[0068] In an exemplary embodiment, the present invention further includes: a liquid crystal layer located between the first substrate and the second substrate, the liquid crystal layer including: nematic liquid crystal;

[0069] The second substrate includes: a second substrate and an optical structure layer arranged on the second substrate, the optical structure layer includes: a black matrix layer and a filter layer, the sub-pixel includes a pixel opening, and the filter layer includes: a plurality of filters, and the orthographic projection of at least one filter on the first substrate at least partially overlaps with the orthographic projection of at least one pixel opening on the first substrate.

[0070] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display panel.

[0071] In a third aspect, the present disclosure further provides a method for preparing a display panel, configured to prepare the above-mentioned display panel, the method comprising:

[0072] forming a heating structure layer and an electrode structure layer in sequence on a first substrate to form a first base plate;

[0073] forming a second substrate;

[0074] The first substrate and the second substrate are arranged in a box.

[0075] In an exemplary embodiment, sequentially forming a heating structure layer and an electrode structure layer on the first substrate includes:

[0076] forming a device structure layer on a first substrate;

[0077] forming an intermediate insulating layer on the device structure layer;

[0078] forming a heating structure layer on the intermediate insulating layer;

[0079] forming an electrode structure layer on the heating structure layer;

[0080] The forming of the device structure layer on the first substrate comprises: forming a semiconductor layer, a first conductive layer and a second conductive layer on the first substrate;

[0081] Forming an intermediate insulating layer on the device structure layer includes: sequentially forming a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer on the device structure layer;

[0082] The forming of the electrode structure layer on the heating structure layer includes: forming a fourth conductive layer and a fifth conductive layer on the heating structure layer.

[0083] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0085] Figure 1 is a structural diagram of a display panel;

[0086] Figure 2 is a schematic cross-sectional view of a display panel;

[0087] Figure 3 is another structural schematic diagram of a display panel;

[0088] Figure 4 A top view of the heating structure layer;

[0089] Figure 5 A top view of a portion of the device structure layer;

[0090] Figure 6 for Figure 1 Schematic diagram of the structure of the middle region R1;

[0091] Figure 7 for Figure 6 Cross-section along AA direction;

[0092] Figure 8 for Figure 1 Schematic diagram of the structure of the middle region R2;

[0093] Figure 9 for Figure 8 Cross-section along BB direction;

[0094] Figure 10 is a schematic diagram of the signal lines of the second fan-out area;

[0095] Figure 11 for Figure 10 An enlarged schematic diagram of

[0096] Figure 12 for Figure 11 Cross-section along CC direction;

[0097] Figure 13 for Figure 11 Cross-section along DD direction;

[0098] Figure 14 for Figure 1 Enlarged view of the middle region R4;

[0099] Figure 15 for Figure 14 Equivalent circuit diagram of the heating connection electrode in;

[0100] Figure 16 for Figure 1 Another structural diagram of the middle region R2;

[0101] Figure 17 for Figure 1 Another structural diagram of the middle region R2;

[0102] Figure 18 for Figure 16 Equivalent circuit diagram of

[0103] Figure 19 for Figure 18 The first row of the electrostatic discharge circuit connection diagram;

[0104] Figure 20 for Figure 18 The second row of the electrostatic discharge circuit connection diagram;

[0105] Figure 21 for Figure 18 The third row of the electrostatic discharge circuit connection diagram;

[0106] Figure 22 for Figure 17 Equivalent circuit diagram of

[0107] Figure 23 for Figure 22The first row of the electrostatic discharge circuit connection diagram;

[0108] Figure 24 for Figure 22 The second row of the electrostatic discharge circuit connection diagram;

[0109] Figure 25 for Figure 22 The third row of the electrostatic discharge circuit connection diagram;

[0110] Figure 26 is the equivalent circuit diagram of the electrostatic discharge circuit;

[0111] Figure 27 Schematic diagram of the structure of the electrostatic discharge circuit;

[0112] Figure 28 for Figure 1 Schematic diagram of the structure of the middle region R5;

[0113] Figure 29 for Figure 28 An enlarged schematic diagram of the dotted box in the middle;

[0114] Figure 30 for Figure 29 Cross-section along AA direction. DETAILED DESCRIPTION

[0115] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0116] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0117] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0118] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0119] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0120] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0121] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0122] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0123] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0124] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0125] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0126] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0127] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0128] The liquid crystal material used in liquid crystal displays (LCDs) is primarily nematic liquid crystal. This means that LCDs can only operate within the temperature range where the liquid crystal material is in the nematic phase. The operating range of an LCD is the range within which the nematic phase exists. The transition temperature between the smectic and nematic phases of a liquid crystal material is typically denoted by Tsn. The temperature at which the nematic phase transitions to liquid is the clearing point temperature of the liquid crystal material, denoted by Tni. The operating temperature range of an LCD is Tni to Tsn. When the operating temperature of an LCD is lower than Tsn, the liquid crystal material is in the smectic phase or solid state (non-nematic phase), exceeding the LCD's operating temperature range. This prevents the LCD from operating normally, reducing its reliability.

[0129] Figure 1 is a structural diagram of the display panel. Figure 2 is a cross-sectional diagram of the display panel. Figure 1 and Figure 2As shown, the display panel provided by the embodiment of the present disclosure has a display area 100, including: a first substrate 10 and a second substrate 20 arranged in a box, the first substrate 10 is provided with a plurality of sub-pixels located in the display area, at least one sub-pixel includes: a first electrode and a second electrode, the first substrate 10 includes: a first substrate 11 and an electrode structure layer 12 arranged on the side of the first substrate 11 close to the second substrate 20, the electrode structure layer 12 includes at least: a first electrode and a second electrode of at least one sub-pixel.

[0130] In an exemplary embodiment, the first substrate 10 further includes a heating structure layer 13 . The heating structure layer 13 is located on a side of the electrode structure layer 12 close to the first underlay 11 and is configured to heat the display panel.

[0131] In an exemplary embodiment, one of the first electrode and the second electrode is a pixel electrode, and the other electrode is a common electrode.

[0132] In an exemplary embodiment, the first electrode and the second electrode are transparent conductive electrodes.

[0133] In an exemplary embodiment, the first substrate further includes a connecting wire connecting the second electrodes of adjacent sub-pixels. The connecting wire is disposed in the same layer as the second electrodes and is made of metal. The provision of the metal connecting wire can reduce the resistance of the film layer where the second electrodes are located, thereby improving the signal stability of the film layer where the second electrodes are located.

[0134] In an exemplary embodiment, the first substrate 11 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0135] In an exemplary embodiment, Figure 2 As shown, the display panel may further include a liquid crystal layer 30. For example, the liquid crystal layer 30 may include nematic liquid crystal.

[0136] In an exemplary embodiment, Figure 2 As shown, the second substrate 20 may include: a second substrate 21 and an optical structure layer 22 .

[0137] In an exemplary embodiment, the second substrate 21 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0138] The present disclosure can heat the display panel by providing a heating structure layer in the first substrate of the display panel, so that the display panel can be kept within the operating temperature range, which can ensure the normal operation of the display panel and improve the reliability of the display panel.

[0139] In an exemplary embodiment, Figure 3 FIG. 1 is another structural diagram of a display panel. Figure 2 and Figure 3 As shown, the first substrate 10 may further include: a device structure layer 15 and an intermediate insulating layer 14 .

[0140] In an exemplary embodiment, the device structure layer 15 is located on a side of the heating structure layer 13 that is close to the first substrate 11. The device structure layer 15 may include: data lines, scan lines, and pixel transistors T located in the display area, wherein the pixel transistors are electrically connected to the data lines, scan lines, and the first electrode of at least one sub-pixel, respectively. Multiple data lines and multiple scan lines intersect to define multiple sub-pixels. The control electrode T11 of the pixel transistor T is connected to the scan line, the first electrode T13 of the pixel transistor is connected to the data line, and the second electrode T14 of the pixel transistor is electrically connected to the first electrode of at least one sub-pixel. The pixel transistors are configured to provide a data line signal to the first electrode of the at least one sub-pixel under the control of an active level signal of the scan line.

[0141] In an exemplary embodiment, the device structure layer 15 may include: a semiconductor layer, a first conductive layer, and a second conductive layer. The transistor may include: an active pattern, a control electrode, a first electrode, and a second electrode.

[0142] The semiconductor layer includes at least an active pattern of at least one pixel transistor.

[0143] The first conductive layer at least includes: a scanning line and a control electrode of at least one pixel transistor.

[0144] The second conductive layer at least includes: a data line and a first electrode and a second electrode of at least one pixel transistor.

[0145] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0146] In an exemplary embodiment, the first conductive layer and the second conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0147] In an exemplary embodiment, the pixel transistor may have a top gate structure, or may have a bottom gate structure. Figure 3 The description is made by taking a pixel transistor with a bottom-gate structure as an example.

[0148] In an exemplary embodiment, when the pixel transistor has a top-gate structure, the semiconductor layer is located on the side of the first conductive layer closer to the first substrate, and the second conductive layer is located on the side of the first conductive layer farther from the first substrate. The device structure layer further includes: a gate insulating layer located between the semiconductor layer and the first conductive layer; and an interlayer dielectric layer located between the first and second conductive layers.

[0149] In an exemplary embodiment, Figure 3 As shown, when the pixel transistor has a bottom-gate structure, the semiconductor layer is located on the side of the first conductive layer away from the first substrate, and the second conductive layer is located on the side of the semiconductor layer away from the first substrate and is in direct contact with the semiconductor layer. The device structure layer also includes a gate insulating layer 151 located between the first conductive layer and the semiconductor layer.

[0150] In an exemplary embodiment, the intermediate insulating layer 14 is located between the device structure layer 15 and the heating structure layer 13. The intermediate insulating layer 14 may include a first inorganic insulating layer 141, an organic insulating layer 142, and a second inorganic insulating layer 143 sequentially stacked on the first substrate 11.

[0151] In an exemplary embodiment, the dielectric constant of the organic insulating layer 142 is smaller than the dielectric constant of at least one film layer of the first inorganic insulating layer 141 and the second inorganic insulating layer 143 .

[0152] In an exemplary embodiment, the dielectric constant of the organic insulating layer 142 may be approximately 3 to 3.5, and illustratively, the dielectric constant of the organic insulating layer 142 may be 3.2.

[0153] In an exemplary embodiment, the dielectric constant of the first and second inorganic insulating layers 141 and 143 may be approximately 6 to 7, and illustratively, the dielectric constant of the first and second inorganic insulating layers 141 and 143 may be 6.5.

[0154] In an exemplary embodiment, the thickness of the organic insulating layer 142 is greater than the thickness of at least one film layer of the first inorganic insulating layer 141 and the second inorganic insulating layer 143 .

[0155] In an exemplary embodiment, the first inorganic insulating layer 141 and the second inorganic insulating layer 143 are made of at least silicon nitride. The first inorganic insulating layer 141 can enhance adhesion between the device structure layer 15 and the organic insulating layer 142 , while the second inorganic insulating layer 143 can enhance adhesion between the organic insulating layer 142 and the heating structure layer 13 , thereby preventing the organic insulating layer 142 from peeling off.

[0156] In an exemplary embodiment, the material of the organic insulating layer 142 includes at least an organic film.

[0157] In an exemplary embodiment, the thickness of the organic insulating layer 142 can exceed the maximum thickness of the first inorganic insulating layer 141 and the second inorganic insulating layer 143. According to the capacitance calculation formula C = εS / 4πkd, when the thickness of the intermediate insulating layer is large enough, the capacitance between the device structure layer and the heating structure layer is small enough. Therefore, the setting method of the intermediate insulating layer set in the present invention can effectively reduce the overlapping capacitance between the heating structure layer 13 and the device structure layer 15, reduce the coupling effect between the heating structure layer and the device structure layer, and reduce the risk of poor display of the display panel.

[0158] In an exemplary embodiment, Figure 2 As shown, the first substrate 10 may further include a first passivation layer 16 located between the heating structure layer 13 and the electrode structure layer 12. The first passivation layer 16 may reduce the influence of the signal of the heating structure layer 13 on the signal in the electrode structure layer.

[0159] In an exemplary embodiment, Figure 3 As shown, the electrode structure layer at least includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the first substrate 11. The electrode structure layer may further include: a second passivation layer 123 located between the fourth conductive layer and the fifth conductive layer.

[0160] The fourth conductive layer at least includes: a second electrode 122 of at least one sub-pixel.

[0161] The fifth conductive layer at least includes: a first electrode 121 of at least one sub-pixel.

[0162] In an exemplary embodiment, the fourth conductive layer may be made of a transparent conductive material, or a transparent material and a metal material. The transparent material may be indium tin oxide (ITO) or zinc tin oxide (IZO), and the metal material may be any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). The structure may be a single layer or a multilayer composite structure, such as Mo / Cu / Mo.

[0163] In an exemplary embodiment, the fifth conductive layer may employ a transparent conductive material, such as indium tin oxide (ITO) or zinc tin oxide (IZO).

[0164] like Figure 3 As shown, the optical structure layer may include a black matrix layer 221 and a filter layer 222. The orthographic projection of the black matrix layer 221 on the first substrate at least partially overlaps with the orthographic projections of the scan lines, data lines, and at least one pixel transistor on the first substrate. The filter layer 222 includes a plurality of filters. Each sub-pixel is provided with a pixel opening, and the orthographic projection of at least one filter on the first substrate at least partially overlaps with the orthographic projection of at least one pixel opening on the first substrate.

[0165] In an exemplary embodiment, the orthographic projection of the black matrix layer on the first substrate and the orthographic projection of the filter layer on the first substrate may not have an overlapping area, or may have an overlapping area, which is not limited in the present disclosure.

[0166] In an exemplary embodiment, the color filters may include a red color filter, a green color filter, and a blue color filter.

[0167] In an exemplary embodiment, the black matrix layer and the light filter layer may be provided in the same layer, wherein the black matrix layer is provided with via holes, and the light filter layer is filled in the via holes of the black matrix layer.

[0168] In an exemplary embodiment, Figure 1 As shown, the display panel also has a non-display area. The non-display area includes a binding area 300 located on a first side of the display area 100 and a border area 200 located on the other side of the display area 100. The binding area 300 includes a first fan-out area 301, a second fan-out area 302, a driver chip area 303, and a binding pin area 304, which are sequentially arranged in a direction away from the display area 100.

[0169] Figure 4 is a top view of the heating structure layer. Figure 4As shown, the heating structure layer may include: at least one heating line 40 at least partially located in the display area 100, at least one first heating trace 41 located in the first fan-out area 301, and at least one second heating trace 42 located in the second fan-out area 302, the driver chip area 303, and the binding pin area 304. The at least one first heating trace 41 is connected to the at least one heating line 40 and the at least one second heating trace 42, respectively.

[0170] In an exemplary embodiment, the heating structure layer includes: a third conductive layer, which is a single metal film layer.

[0171] In an exemplary embodiment, the third conductive layer includes at least a heating line, a first heating trace, and a second heating trace.

[0172] In an exemplary embodiment, the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0173] In an exemplary embodiment, the heating line 40 , the first heating trace 41 , and the second heating trace 42 extend at least partially along a second direction D2 , which is an extending direction of the data line.

[0174] In an exemplary embodiment, Figure 5 This is a top view of part of the device structure layer. Figure 5 As shown, the device structure layer may further include: a first fan-out trace 51 located in the first fan-out area 301 and a second fan-out trace 52 located in the second fan-out area 302 , at least one first fan-out trace 51 being electrically connected to at least one data line 50 and at least one second fan-out trace 52 respectively.

[0175] In an exemplary embodiment, the first fan-out trace 51 is located on the second conductive layer, and the second fan-out trace 52 is located on the first conductive layer or the second conductive layer.

[0176] In an exemplary embodiment, the plurality of second fan-out traces 52 are located in the first conductive layer, or the plurality of second fan-out traces are located in the second conductive layer, or at least part of the plurality of second fan-out traces are located in the first conductive layer and at least part of the plurality of second fan-out traces are located in the second conductive layer.

[0177] In an exemplary embodiment, at least one of the first fan-out trace 51 and the second fan-out trace 52 extends at least partially along the second direction D2 .

[0178] In an exemplary embodiment, Figure 1As shown, the first substrate 10 further includes: a data driver chip 33 located in the driver chip area 303, and a first circuit board and a second circuit board 34 located in the binding pin area 304. The data driver chip 33 is electrically connected to at least one second fan-out trace, the first circuit board is electrically connected to the data driver chip, and the second circuit board 34 is electrically connected to at least one second heating trace. In the present disclosure, the first and second circuit boards are located on the same side of the display area 100 as the data driver chip, allowing the first and second circuit boards to be integrated together, thereby achieving a narrow bezel on the display panel.

[0179] In an exemplary embodiment, the first circuit board and the second circuit board may be the same circuit board, or the first circuit board and the second circuit board may be different circuit boards. Figure 1 The description is given by taking the first circuit board and the second circuit board as the same circuit board as an example.

[0180] In an exemplary embodiment, the circuit board may be a flexible circuit board.

[0181] Figure 6 for Figure 1 Schematic diagram of the structure of the middle region R1. Figure 7 for Figure 6 Cross-section along AA direction. Figure 6 and Figure 7 As shown, the orthographic projection of at least one data line 50 on the first substrate at least partially overlaps with the orthographic projection of at least one heating line 40 on the first substrate.

[0182] In an exemplary embodiment, the heating line 40 at least partially extends along a second direction D2 , which is an extending direction of the data line, and intersects the first direction D1 , which is an extending direction of the scan line 60 .

[0183] In an exemplary embodiment, an orthographic projection of the at least one data line 50 on the first substrate coincides with an orthographic projection of the at least one heating line 40 on the first substrate.

[0184] Figure 8 for Figure 1 Schematic diagram of the structure of the middle region R2, Figure 9 for Figure 8 Cross-section along BB direction. Figure 8 and Figure 9 As shown, the orthographic projection of at least one first heating trace 41 on the first substrate at least partially overlaps with the orthographic projection of at least one first fan-out trace 51 on the first substrate.

[0185] In an exemplary embodiment, the first heating trace 41 and the first fan-out trace 51 are in a zigzag shape.

[0186] In an exemplary embodiment, an orthographic projection of at least a portion of the at least one first heating trace 41 on the first substrate coincides with an orthographic projection of the at least one first fan-out trace 51 on the first substrate.

[0187] Figure 10 This is a schematic diagram of the signal lines in the second fan-out area. Figure 11 for Figure 10 An enlarged schematic diagram of Figure 12 for Figure 11 Cross-section along CC direction, Figure 13 for Figure 11 Cross-section along DD direction. Figure 11 and Figure 13 As shown, the orthographic projection of at least one second heating trace 42 on the first substrate at least partially overlaps with the orthographic projection of at least one second fan-out trace 52 on the first substrate. Figures 11 to 13 The description is made by taking as an example that at least one second fan-out trace is located in the first conductive layer, at least one second fan-out trace is located in the second conductive layer, and adjacent second fan-out traces are located in different conductive layers.

[0188] In an exemplary embodiment, the orthographic projection of at least one second fan-out trace located in the first conductive layer on the first substrate and the orthographic projection of at least one second fan-out trace located in the second conductive layer on the first substrate may be overlapped, or the orthographic projections of multiple second fan-out traces located in the first conductive layer on the first substrate and the orthographic projections of multiple second fan-out traces located in the second conductive layer on the first substrate may be alternately arranged, and the present disclosure does not impose any limitations on this.

[0189] In an exemplary embodiment, Figure 11 As shown, at least one second heating trace 42 includes a first heating connection portion 42A and a second heating connection portion 42B. At least one second fan-out line includes a first fan-out connection portion 52A and a second fan-out connection portion 52B. The first heating connection portion 42A extends along a third direction D3, the first fan-out connection portion 52A extends along a fourth direction D4, and the second fan-out connection portion 52B and the second heating connection portion 42B extend along a second direction D2. The third direction D3 intersects the first direction D1, the second direction D2, and the fourth direction D4, respectively. The first direction D1 is the direction in which the scan lines extend, and the second direction D2 is the direction in which the data lines extend.

[0190] In an exemplary embodiment, the first heating connection 42A is connected to the second heating connection 42B and the at least one first heating trace, respectively.

[0191] In an exemplary embodiment, the first fan-out connection portion 52A is connected to the second fan-out connection portion 52B and at least one first fan-out connection line, respectively.

[0192] In an exemplary embodiment, Figure 11 As shown, there is no overlapping area between the orthographic projection of the second heating connection portion 42B of at least one second heating trace 42 on the first substrate and the orthographic projection of the second fan-out connection portion 52B of at least one second fan-out trace 52 on the first substrate.

[0193] In an exemplary embodiment, the target second heating trace is the second heating trace with the shortest second heating connection portion along the second direction D2, and the target second fan-out trace is the second fan-out trace with the shortest second fan-out connection portion along the second direction D2. Figure 11 As shown, the orthographic projections of the second heating connection portions 42B of the other second heating traces except the target second heating trace on the first substrate are located on a side of the orthographic projection of the second heating connection portion 42B of the target second heating trace on the first substrate away from the orthographic projection of the second fan-out connection portion 52B of the target second fan-out trace on the first substrate, and the orthographic projections of the second fan-out connection portions 52B of the other second fan-out traces except the target second fan-out trace on the first substrate are located on a side of the orthographic projection of the second fan-out connection portion 52B of the target second fan-out trace on the first substrate away from the orthographic projection of the second heating connection portion 42B of the target second heating trace on the first substrate;

[0194] In an exemplary embodiment, Figure 11 As shown, a distance d between the second heating connection portion 42B of the target second heating trace and the second fan-out connection portion 52B of the target second fan-out trace along the first direction D1 is greater than or equal to 10 micrometers.

[0195] In an exemplary embodiment, Figure 11 As shown, the display panel may further include: a frame sealant 80 located between the first substrate 10 and the second substrate 20, and the organic insulating layer is provided in the organic via V. The frame sealant can seal the display panel to prevent liquid crystal overflow and moisture intrusion, while also maintaining the cell thickness of the display panel and adhering the first and second substrates.

[0196] In an exemplary embodiment, Figure 11 As shown, the orthographic projection of the organic via V on the first substrate at least partially overlaps with the orthographic projection of the second heating connection portion of at least one second heating trace on the first substrate and the orthographic projection of the second fan-out connection portion of at least one second fan-out trace on the first substrate, and there is no overlapping area with the orthographic projection of the first heating connection portion of at least one second heating trace on the first substrate and the orthographic projection of the first fan-out connection portion of at least one second fan-out trace on the first substrate.

[0197] In an exemplary embodiment, Figure 11 and Figure 12As shown, in the area where the organic via is located, the orthographic projection of the second fan-out trace on the first substrate and the orthographic projection of the second heating trace on the first substrate do not overlap. When the second fan-out trace is located in the first conductive layer, the insulating layer between the second fan-out trace and the second heating trace includes: an insulating layer between the device structure layers and a first inorganic insulating layer and a second inorganic insulating layer. When the second fan-out trace is located in the second conductive layer, the insulating layer between the second fan-out trace and the second heating trace includes: a first inorganic insulating layer and a second inorganic insulating layer. Although the thickness of the insulating layer in the area where the organic via is located is reduced, the spacing d between the second heating connection portion 42B of the target second heating trace and the second fan-out connection portion 52B of the target second fan-out trace 52 along the first direction D1 is greater than or equal to 10 microns. This can reduce the fringe field capacitance between the second heating trace and the second fan-out trace in some areas, minimize the coupling risk between the second heating trace and the second fan-out trace, and improve the reliability of the display panel.

[0198] In an exemplary embodiment, the orthographic projection of the sealant 80 on the first substrate at least partially overlaps with the orthographic projection of the organic via V on the first substrate, and the length of the sealant 80 along the second direction D2 is smaller than the length of the organic via V along the second direction D2.

[0199] The orthographic projection of the frame sealant 80 on the first substrate in the present disclosure at least partially overlaps with the orthographic projection of the organic via V on the first substrate. In other words, the present disclosure hollows out the organic insulating layer below the frame sealant. Since the organic insulating layer in the present disclosure is relatively thick, hollowing out the organic insulating layer below the frame sealant can better utilize the function of the frame sealant.

[0200] In an exemplary embodiment, Figure 11 and Figure 13 As shown, in the area where the second fan-out trace and the second heating trace overlap, when the second fan-out trace is located in the first conductive layer, the insulating layer between the second fan-out trace and the second heating trace includes: the insulating layer between the device structure layers, and the first inorganic insulating layer, the organic insulating layer, and the second inorganic insulating layer. When the second fan-out trace is located in the second conductive layer, the insulating layer between the second fan-out trace and the second heating trace includes: the first inorganic insulating layer, the organic insulating layer, and the second inorganic insulating layer. Due to the presence of the organic insulating layer, although the second fan-out trace and the second heating trace overlap, the coupling risk between the second fan-out trace and the second heating trace is relatively low, thus ensuring the reliability of the display panel.

[0201] In an exemplary embodiment, Figure 14 for Figure 1 An enlarged view of the middle region R4. Figure 14 As shown, the electrode structure layer further includes: a plurality of data connection electrodes 53 , and the heating structure layer further includes: a plurality of heating connection electrodes 45 .

[0202] In an exemplary embodiment, the third conductive layer may include at least a heating connection electrode.

[0203] In an exemplary embodiment, the fifth conductive layer may include at least a data connection electrode.

[0204] In an exemplary embodiment, Figure 14 As shown, the multiple data connection electrodes 53 correspond one-to-one to the multiple first fan-out traces 51 and one-to-one to the multiple second fan-out traces 52 , and at least one data connection electrode 53 is electrically connected to the corresponding first fan-out trace 51 and the corresponding second fan-out trace 52 .

[0205] In an exemplary embodiment, multiple heating connection electrodes 45 correspond one-to-one to multiple first heating traces 41, at least one heating connection electrode 45 is electrically connected to the corresponding first heating trace 41, and at least one second heating trace 42 is electrically connected to at least one heating connection electrode 45.

[0206] In an exemplary embodiment, the first substrate is provided with a first transfer via exposing the first fan-out trace, and a second transfer via exposing the second fan-out trace, and the data connection electrode 53 is connected to the first fan-out trace through the first transfer via and is electrically connected to the second fan-out trace through the second transfer via.

[0207] In an exemplary embodiment, Figure 14 As shown, the shape of the heating connection electrode 45 includes: a plurality of annular regions R extending along the first direction. The orthographic projection of at least one data connection electrode 53 on the first substrate is located within the range of the orthographic projection of at least one annular region R on the first substrate.

[0208] In an exemplary embodiment, Figure 15 for Figure 14 The equivalent circuit diagram of the heating connection electrode in FIG. Figure 15 As shown, when Figure 14 When the heating connection electrode 15 includes two annular areas R extending along the first direction, the heating connection electrode includes multiple branches, which is equivalent to multiple resistors (R1, R2 and R3) in parallel. According to the parallel resistor formula, the total resistance of the heating connection electrode is less than the resistance value of any one of R1, R2 and R3. The first heating line in the present disclosure is electrically connected to the second heating line through the heating connection electrode, which reduces the resistance of the heating line (including the first heating line, the second heating line and the heating connection electrode) located in the binding area, and can reduce the power of the heating line located in the binding area, thereby ensuring the heating effect of the heating line located in the display area.

[0209] In an exemplary embodiment, Figure 16 for Figure 1 Another structural diagram of the middle region R2, Figure 17 for Figure 1 Another structural diagram of the middle region R2. Figure 16 and Figure 17 As shown, the first substrate 10 may further include: a plurality of electrostatic release circuits 81 located in the first fan-out area, at least one electrostatic release circuit 81 being electrically connected to at least one first fan-out trace 51 , and at least one electrostatic release circuit 81 being electrically connected to at least one first heating trace 41 .

[0210] The present disclosure provides an electrostatic discharge circuit electrically connected to the first fan-out trace. When electrostatic discharge occurs in the first fan-out trace, the charge is directed out of the display panel, thereby reducing the risk of electrostatic failure. The present disclosure provides an electrostatic discharge circuit electrically connected to the first heating trace. When electrostatic discharge occurs in the first heating trace, the charge is directed out of the display panel, thereby reducing the risk of electrostatic failure.

[0211] In an exemplary embodiment, Figure 16 and Figure 17 As shown, multiple electrostatic release circuits include: three rows of electrostatic release circuits, at least one row of electrostatic release circuits includes: N electrostatic release circuits, the orthographic projection of the kth first heating trace on the first substrate and the orthographic projection of the 3kth first fan-out trace on the first substrate at least partially overlap, N≥1, 1≤k≤2N / 3.

[0212] In an exemplary embodiment, the orthographic projection of the kth first heating trace on the first substrate at least partially overlaps with the orthographic projection of the 3kth first fan-out trace on the first substrate. This can reduce the number of first heating traces and heating lines, thereby increasing the width of the first and second heating traces in the binding area. This reduces the resistance of the first and second heating traces, reduces the power of the first and second heating traces in the binding area, and ensures the heating effect of the heating lines in the display area. In an exemplary embodiment, the orthographic projection of the kth first heating trace on the first substrate can also at least partially overlap with the orthographic projection of the 6kth first fan-out trace on the first substrate.

[0213] In an exemplary embodiment, Figure 18 for Figure 16 The equivalent circuit diagram of Figure 19 for Figure 18 The first row of the electrostatic discharge circuit connection diagram is as follows: Figure 20 for Figure 18 The second row of the electrostatic discharge circuit connection diagram, Figure 21 for Figure 18 The third row of the electrostatic discharge circuit connection diagram. Figures 18 to 21As shown, the N electrostatic release circuits in the first row L1 and the N electrostatic release circuits in the second row L2 are alternately arranged, and the N electrostatic release circuits in the first row L1 and the N electrostatic release circuits in the third row L3 are arranged in a matrix.

[0214] like Figures 18 to 21 As shown, the nth electrostatic discharge circuit in the first row L1 is electrically connected to the 2n-1th first fan-out trace. For example, the first electrostatic discharge circuit in the first row L1 is electrically connected to the first first fan-out trace DL1, the second electrostatic discharge circuit in the first row L1 is electrically connected to the third first fan-out trace DL3, the third electrostatic discharge circuit in the first row L1 is electrically connected to the fifth first fan-out trace DL5, and so on.

[0215] like Figures 18 to 21 As shown, the nth electrostatic discharge circuit in the second row L2 is electrically connected to the 2nth first fan-out trace. For example, the first electrostatic discharge circuit in the second row L2 is electrically connected to the first second fan-out trace DL4, the second electrostatic discharge circuit in the second row L2 is electrically connected to the fourth first fan-out trace DL4, the third electrostatic discharge circuit in the second row L2 is electrically connected to the sixth first fan-out trace DL6, and so on.

[0216] like Figures 18 to 21 As shown, the 3k-1th electrostatic discharge circuit in the third row L3 is electrically connected to the 2k-1th first heating trace, and the 3kth electrostatic discharge circuit in the third row L3 is electrically connected to the 2kth first fan-out trace. For example, the second electrostatic discharge circuit in the third row L3 is electrically connected to the first first heating trace HL1, and the third electrostatic discharge circuit in the third row L3 is electrically connected to the second first fan-out trace HL2. The fifth electrostatic discharge circuit in the third row L3 is electrically connected to the third first heating trace HL3, and the sixth electrostatic discharge circuit in the third row L3 is electrically connected to the fourth first fan-out trace HL4.

[0217] like Figures 18 to 21 As shown, the 3k-2nd electrostatic discharge circuit in the third row L3 is a virtual electrostatic discharge circuit, ie, it is not connected to the first heating line. The 3k-2nd electrostatic discharge circuit in the third row L3 is located in the etching uniformity of the display panel.

[0218] like Figures 18 to 21As shown, the orthographic projection of at least a portion of the 2n-1th first fan-out trace and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the first row L1 and the orthographic projection of the n+1th electrostatic discharge circuit in the first row L1. For example, the orthographic projection of at least a portion of the first first fan-out trace DL1 and the orthographic projection of at least a portion of the second first fan-out trace DL2 on the first substrate are located between the orthographic projection of the first electrostatic discharge circuit in the first row L1 and the orthographic projection of the second electrostatic discharge circuit in the first row L1 on the first substrate. The orthographic projection of at least a portion of the third first fan-out trace DL3 and the orthographic projection of at least a portion of the fourth first fan-out trace DL4 on the first substrate are located between the orthographic projection of the second electrostatic discharge circuit in the first row L1 and the orthographic projection of the third electrostatic discharge circuit in the first row L1 on the first substrate, and so on.

[0219] like Figures 18 to 21 As shown, the orthographic projections of at least a portion of the 2nth first fan-out trace and at least a portion of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projections of the nth electrostatic discharge circuit in the second row L2 and the orthographic projections of the n+1th electrostatic discharge circuit in the second row L2, and the first first fan-out trace is located on a side of the first electrostatic discharge circuit in the second row L2 away from the second first fan-out trace. For example, the orthographic projections of at least a portion of the second first fan-out trace DL2 and at least a portion of the third first fan-out trace DL3 on the first substrate are located between the orthographic projections of the first electrostatic discharge circuit in the second row L2 and the orthographic projections of the second electrostatic discharge circuit in the second row L2, respectively. The orthographic projections of at least a portion of the fourth first fan-out trace DL4 and at least a portion of the fifth first fan-out trace DL5 on the first substrate are located between the orthographic projections of the second electrostatic discharge circuit in the second row L2 and the orthographic projections of the fifth electrostatic discharge circuit in the second row L2, respectively, and so on.

[0220] like Figures 18 to 21As shown, the orthographic projection of at least a portion of the 2n-1th first fan-out trace and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the third row L3 and the orthographic projection of the n+1th electrostatic discharge circuit in the third row L3 on the first substrate. For example, the orthographic projection of at least a portion of the first first fan-out trace DL1 and the orthographic projection of at least a portion of the second first fan-out trace DL2 on the first substrate are located between the orthographic projection of the first electrostatic discharge circuit in the third row L3 and the orthographic projection of the second electrostatic discharge circuit in the third row L3 on the first substrate. The orthographic projection of at least a portion of the third first fan-out trace DL3 and the orthographic projection of at least a portion of the fourth first fan-out trace DL4 on the first substrate are located between the orthographic projection of the second electrostatic discharge circuit in the first row L1 and the orthographic projection of the third electrostatic discharge circuit in the third row L3 on the first substrate, and so on.

[0221] In an exemplary embodiment, Figure 18 and Figure 21 As shown, the orthographic projection of the 2kth first heating trace on the first substrate at least partially overlaps with the orthographic projection of the 6k-1th first fan-out trace on the first substrate. For example, the orthographic projection of the second first heating trace HL2 on the first substrate at least partially overlaps with the orthographic projection of the fifth first fan-out trace DL5 on the first substrate, and the orthographic projection of the fourth first heating trace HL4 on the first substrate at least partially overlaps with the orthographic projection of the eleventh first fan-out trace DL 11 The orthographic projections on the first substrate at least partially overlap. Although the orthographic projection of the 2kth first heating trace on the first substrate in the present disclosure at least partially overlaps with the orthographic projection of the 6k-1th first fan-out trace on the first substrate, due to the thickness angle of the intermediate insulating layer, the risk of coupling between the 2kth first heating trace and the 6k-1th first fan-out trace is negligible.

[0222] Figure 16 The arrangement of the provided electrostatic discharge circuit and the winding method of the first fan-out line and the first heating line can avoid the difference in resistance of at least two first fan-out lines. The difference in resistance of at least two first heating lines can reduce the risk of poor display of the display panel.

[0223] In an exemplary embodiment, Figure 22 for Figure 17 The equivalent circuit diagram of Figure 23 for Figure 22 The first row of the electrostatic discharge circuit connection diagram is as follows: Figure 24 for Figure 22 The second row of the electrostatic discharge circuit connection diagram, Figure 25 for Figure 22 The third row of the electrostatic discharge circuit connection diagram. Figures 22 to 25 As shown, the N electrostatic release circuits in the first row L1 are alternately arranged with the N electrostatic release circuits in the second row L2 , and the N electrostatic release circuits in the second row L2 are alternately arranged with the N electrostatic release circuits in the third row L3 .

[0224] like Figures 22 to 25 As shown, the nth electrostatic discharge circuit in the first row L1 is electrically connected to the 2n-1th first fan-out trace. For example, the first electrostatic discharge circuit in the first row L1 is electrically connected to the first first fan-out trace DL1, the second electrostatic discharge circuit in the first row L1L1 is electrically connected to the third first fan-out trace DL3, the third electrostatic discharge circuit in the first row L1 is electrically connected to the fifth first fan-out trace DL5, and so on.

[0225] like Figures 22 to 25 As shown, the nth electrostatic discharge circuit in the second row L2 is electrically connected to the 2nth first fan-out trace. For example, the first electrostatic discharge circuit in the second row L2 is electrically connected to the first second fan-out trace DL4, the second electrostatic discharge circuit in the second row L2 is electrically connected to the fourth first fan-out trace DL4, the third electrostatic discharge circuit in the second row L2 is electrically connected to the sixth first fan-out trace DL6, and so on.

[0226] like Figures 22 to 25 As shown, the 3k-2 electrostatic discharge circuit in the third row L3 is electrically connected to the 2k-1 first heating trace, and the 3k electrostatic discharge circuit in the third row L3 is electrically connected to the 2k first heating trace. For example, the first electrostatic discharge circuit in the third row L3 is electrically connected to the first first heating trace HL1, and the third electrostatic discharge circuit in the third row L3 is electrically connected to the second first fan-out trace HL2. The fourth electrostatic discharge circuit in the third row L3 is electrically connected to the third first heating trace HL4, and the sixth electrostatic discharge circuit in the third row L3 is electrically connected to the fourth first fan-out trace HL4.

[0227] like Figures 22 to 25 As shown, the 3k-1th electrostatic discharge circuit in the third row L3 is a virtual electrostatic discharge circuit, ie, it is not connected to the first heating line. The 3k-1th electrostatic discharge circuit in the third row L3 is located in the etching uniformity of the display panel.

[0228] like Figures 22 to 25As shown, the orthographic projection of at least a portion of the 2n-1th first fan-out trace and the orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the first row L1 and the orthographic projection of the n+1th electrostatic discharge circuit in the first row L1. For example, the orthographic projection of at least a portion of the first first fan-out trace DL1 and the orthographic projection of at least a portion of the second first fan-out trace DL2 on the first substrate are located between the orthographic projection of the first electrostatic discharge circuit in the first row L1 and the orthographic projection of the second electrostatic discharge circuit in the first row L1 on the first substrate. The orthographic projection of at least a portion of the third first fan-out trace DL3 and the orthographic projection of at least a portion of the fourth first fan-out trace DL4 on the first substrate are located between the orthographic projection of the second electrostatic discharge circuit in the first row L1 and the orthographic projection of the third electrostatic discharge circuit in the first row L1 on the first substrate, and so on.

[0229] like Figures 22 to 25 As shown, the orthographic projections of at least a portion of the 2nth first fan-out trace and at least a portion of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projections of the nth electrostatic discharge circuit in the second row L2 and the orthographic projections of the n+1th electrostatic discharge circuit in the second row L2, and the first first fan-out trace is located on a side of the first electrostatic discharge circuit in the second row L2 away from the second first fan-out trace. For example, the orthographic projections of at least a portion of the second first fan-out trace DL2 and at least a portion of the third first fan-out trace DL3 on the first substrate are located between the orthographic projections of the first electrostatic discharge circuit in the second row L2 and the orthographic projections of the second electrostatic discharge circuit in the second row L2, respectively. The orthographic projections of at least a portion of the fourth first fan-out trace DL4 and at least a portion of the fifth first fan-out trace DL5 on the first substrate are located between the orthographic projections of the second electrostatic discharge circuit in the second row L2 and the orthographic projections of the fifth electrostatic discharge circuit in the second row L2, respectively, and so on.

[0230] like Figures 22 to 25As shown, the orthographic projection of at least part of the 2n+1th first fan-out trace on the first substrate and the orthographic projection of at least part of the 2n+2th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the third row L3 on the first substrate and the orthographic projection of the n+1th electrostatic discharge circuit in the third row L3 on the first substrate, and the first first fan-out trace and the second first fan-out trace are located on a side of the first electrostatic discharge circuit in the third row L3 away from the third first fan-out trace. Illustratively, the orthographic projection of at least part of the third first fan-out trace DL3 on the first substrate and the orthographic projection of at least part of the fourth first fan-out trace DL4 on the first substrate are located between the orthographic projection of the first electrostatic release circuit of the third row L3 on the first substrate and the orthographic projection of the second electrostatic release circuit of the third row L3 on the first substrate, the orthographic projection of at least part of the fifth first fan-out trace DL5 on the first substrate and the orthographic projection of at least part of the sixth first fan-out trace DL6 on the first substrate are located between the orthographic projection of the second electrostatic release circuit of the first row L1 on the first substrate and the orthographic projection of the third electrostatic release circuit of the third row L3 on the first substrate, and so on.

[0231] In an exemplary embodiment, the orthographic projection of the 2kth first heating trace on the first substrate does not overlap with the orthographic projection of the 6k-1th first fan-out trace on the first substrate. Exemplarily, the orthographic projection of the second first heating trace HL2 on the first substrate does not overlap with the orthographic projection of the fifth first fan-out trace DL5 on the first substrate, and the orthographic projection of the fourth first heating trace HL4 on the first substrate does not overlap with the orthographic projection of the eleventh first fan-out trace DL 11 There is no overlapping area of ​​the orthographic projection on the first substrate.

[0232] Figure 17 The arrangement of the provided electrostatic discharge circuit and the winding method of the first fan-out line and the first heating line can avoid the difference in resistance of at least two first fan-out lines. The difference in resistance of at least two first heating lines can reduce the risk of poor display of the display panel.

[0233] Figure 26 is the equivalent circuit diagram of the electrostatic discharge circuit, Figure 27 Figure 2 is a schematic diagram of the structure of the electrostatic discharge circuit. Figure 26As shown, at least one electrostatic discharge circuit includes: a first release transistor ET1, a second release transistor ET2, a third release transistor ET3, and a fourth release transistor ET4. The control electrode and first electrode of the first release transistor ET1 are electrically connected to the first signal terminal V1, respectively; the second electrode of the first release transistor ET2 is electrically connected to the node N; the control electrode and second electrode of the second release transistor ET2 are electrically connected to the node N, respectively; the first electrode of the second release transistor ET2 is electrically connected to the first signal terminal V1; the control electrode and first electrode of the third release transistor ET3 are electrically connected to the node N, respectively; the second electrode of the third release transistor ET3 is electrically connected to the second signal terminal V2; the control electrode and second electrode of the fourth release transistor ET4 are electrically connected to the second signal terminal V2, respectively; and the first electrode of the fourth release transistor is electrically connected to the node N.

[0234] In an exemplary embodiment, the first signal terminal V1 is electrically connected to the common electrode power supply line 70, and the second signal terminal V2 is electrically connected to the first fan-out trace or the first heating trace. When the electrostatic discharge circuit is electrically connected to the first fan-out trace, the second signal terminal V2 is electrically connected to the first fan-out trace. When the electrostatic discharge circuit is electrically connected to the first heating trace, the second signal terminal V2 is electrically connected to the first heating trace.

[0235] like Figure 27 As shown, the semiconductor layer may include at least an active pattern ET1 - 2 of a first release transistor, an active pattern ET2 - 2 of a second release transistor, an active pattern ET3 - 2 of a third release transistor, and an active pattern ET4 - 2 of a fourth release transistor.

[0236] like Figure 27 As shown, the active pattern ET1-2 of the first release transistor, the active pattern ET2-2 of the second release transistor, the active pattern ET3-2 of the third release transistor, and the active pattern ET4-2 of the fourth release transistor are separately provided. At least one of the active pattern ET1-2 of the first release transistor, the active pattern ET2-2 of the second release transistor, the active pattern ET3-2 of the third release transistor, and the active pattern ET4-2 of the fourth release transistor extends along the second direction D2.

[0237] like Figure 27 As shown, the first conductive layer may include at least a control electrode ET1 - 1 of a first release transistor, a control electrode ET2 - 1 of a second release transistor, a control electrode ET3 - 1 of a third release transistor, and a control electrode ET4 - 1 of a fourth release transistor.

[0238] like Figure 27As shown, the control electrode ET2-1 of the second release transistor and the control electrode ET3-1 of the third release transistor are integrally structured and extend along the second direction D2. The integral structure of the control electrode ET1-1 of the first release transistor, the control electrode ET2-1 of the second release transistor, and the control electrode ET3-1 of the third release transistor, as well as the control electrode ET4-1 of the fourth release transistor, are arranged sequentially along the second direction D2.

[0239] like Figure 27 As shown, the second conductive layer may include at least: a first electrode ET1-3 and a second electrode ET1-4 of a first release transistor, a first electrode ET2-3 and a second electrode ET2-4 of a second release transistor, a first electrode ET3-3 and a second electrode ET3-4 of a third release transistor, and a first electrode ET4-3 and a second electrode ET4-4 of a fourth release transistor.

[0240] like Figure 27 As shown, the first electrode ET1-3 of the first release transistor and the first electrode ET2-3 of the second release transistor are an integrated structure, the second electrode ET1-4 of the first release transistor and the second electrode ET2-4 of the second release transistor are an integrated structure, the first electrode ET3-3 of the third release transistor and the first electrode ET4-3 of the fourth release transistor are an integrated structure, and the second electrode ET3-4 of the third release transistor and the second electrode ET4-4 of the fourth release transistor are an integrated structure.

[0241] like Figure 27 As shown, the integrated structure of the first electrode ET1 - 3 of the first release transistor and the first electrode ET2 - 3 of the second release transistor at least partially extends along the second direction D2 .

[0242] like Figure 27 As shown, the integrated structure of the second electrode ET1 - 4 of the first release transistor and the second electrode ET2 - 4 of the second release transistor at least partially extends along the second direction D2 .

[0243] like Figure 27 As shown, the integrated structure of the first electrode ET3 - 3 of the third release transistor and the first electrode ET4 - 3 of the fourth release transistor at least partially extends along the second direction D2 .

[0244] like Figure 27 As shown, the integrated structure of the second electrode ET3 - 4 of the third release transistor and the second electrode ET4 - 4 of the fourth release transistor at least partially extends along the second direction D2 .

[0245] In an exemplary embodiment, Figure 27As shown, the display panel further includes: a plurality of first release connection electrodes EL1, a plurality of second release connection electrodes EL2, and a plurality of third release connection electrodes EL3 located on the fifth conductive layer. The first release connection electrodes EL1 are connected to the integrated structure of the first electrode ET1-3 of the first release transistor and the first electrode ET2-3 of the second release transistor, and the control electrode ET1-1 of the first release transistor, respectively, through vias. The second release connection electrodes EL2 are connected to the integrated structure of the control electrode ET2-1 of the second release transistor and the control electrode ET3-1 of the third release transistor, the second electrode ET1-4 of the first release transistor and the second electrode ET2-4 of the second release transistor, the first electrode ET3-3 of the third release transistor, and the first electrode ET4-3 of the fourth release transistor, respectively, through vias. The third release connection electrode EL3 is connected to the integrated structure of the second electrode ET3-4 of the third release transistor and the second electrode ET4-4 of the fourth release transistor, and the control electrode ET4-1 of the fourth release transistor, respectively, through vias.

[0246] like Figure 16 and Figure 17 As shown, at least one first heating trace is connected to the electrostatic discharge circuit via a third release connection electrode connected to the electrostatic discharge circuit.

[0247] like Figure 16 and Figure 17 As shown, at least one first fan-out trace and the second electrode of the fourth release transistor (also the second electrode of the third release transistor) in the connected electrostatic discharge circuit are integrated into a structure.

[0248] In an exemplary embodiment, Figure 4 As shown, the heating structure layer further includes: at least one frame heating line located in the frame area. The at least one frame heating line includes: a first frame heating line 43 and a plurality of second frame heating lines 44.

[0249] The present disclosure can provide auxiliary heating for the edge of the display area by setting frame heating lines, thereby preventing the edge from dissipating heat too quickly and causing uneven heating effect.

[0250] In an exemplary embodiment, Figure 4 As shown, the first frame heating line 43 extends along the first direction D1 and is located on the second side of the display area. At least one second frame heating line 44 extends along the second direction D2 and is located on at least one of the third and fourth sides of the display area. The first side and the second side are arranged opposite each other, and the third side and the fourth side are arranged opposite each other.

[0251] like Figure 4 As shown, the first frame heating line 43 is connected to at least one second frame heating line 44 and at least one heating line 40 respectively.

[0252] In an exemplary embodiment, Figure 28 for Figure 1 Schematic diagram of the structure of the middle area R5, Figure 29 for Figure 28 The enlarged schematic diagram of the dotted box in the middle, Figure 30 for Figure 29 Cross-section along AA direction. Figure 1 、 Figures 28 to 30 As shown, the first substrate 10 further includes a gate drive circuit located on at least one of the third and fourth sides of the non-display area. The orthographic projection of at least one second frame heating trace 44 on the first substrate is located on a side of the orthographic projection of the gate drive circuit on the first substrate that is closer to the display area.

[0253] The present disclosure can avoid the influence of the second frame heating trace on the gate driving circuit by arranging at least one second frame heating trace 44 on the first substrate so that the orthographic projection of the gate driving circuit on the first substrate is located on the side close to the display area.

[0254] In an exemplary embodiment, Figure 1 As shown, the first substrate 10 also includes: a common electrode power supply line 70 located in the non-display area, the common electrode power supply line 70 is located in the device structure layer, the common electrode power supply line 70 is electrically connected to the second electrode of at least one sub-pixel, and is arranged around the display area 100.

[0255] In an exemplary embodiment, at least a portion of the common electrode power supply line 70 is located in the first fan-out region.

[0256] like Figure 28 As shown, the orthographic projection of at least one second frame heating trace 44 on the first substrate at least partially overlaps with the orthographic projection of at least a portion of the common electrode power supply line 70 on the first substrate. Since the insulating layer between the second frame heating trace 44 and the common electrode power supply line 70 includes: an intermediate insulating layer and an insulating layer in the device structure layer, and the thickness angle of the intermediate insulating layer 14, even if there is overlap between the second frame heating trace and the common electrode power supply line, the coupling risk between the two is relatively small and will not affect the reliability of the display panel.

[0257] like Figure 8 As shown, the orthographic projection of the common electrode power supply line 70 on the first substrate also at least partially overlaps with the orthographic projections of the first fan-out trace 51 and the first heating trace 41 on the first substrate.

[0258] In an exemplary embodiment, Figure 1 As shown, the display panel may further include a feedback signal line FBL. At least a portion of the feedback signal line FBL is located on a side of the gate driving circuit GOA away from the display area 100.

[0259] In an exemplary embodiment, Figure 1 As shown, the display panel may further include a ground line GNL. At least a portion of the ground line GNL is located on a side of the feedback signal line FBL away from the display area 100. The ground line GNL is disposed around at least one side of the display area.

[0260] The embodiments of the present disclosure further provide a method for preparing a display panel, which is configured to prepare the display panel provided by any of the aforementioned embodiments.

[0261] In an exemplary embodiment, a method for preparing a display panel may include the following steps:

[0262] Step S1: forming a heating structure layer and an electrode structure layer in sequence on a first substrate to form a first base plate.

[0263] Step S2: forming a second substrate.

[0264] Step S3: aligning the first substrate and the second substrate.

[0265] In an exemplary embodiment, step S1 may include:

[0266] Step S11: forming a device structure layer on a first substrate.

[0267] Step S11 may include: forming a semiconductor layer, a first conductive layer, and a second conductive layer on a first substrate. Specifically, forming a semiconductor layer, a first conductive layer, and a second conductive layer on a first substrate may include: depositing a first conductive film on the first substrate, patterning the first conductive film to form a first conductive layer, depositing a first insulating film on the first conductive layer, patterning the first insulating film to form a gate insulating layer, forming a semiconductor film on the gate insulating layer, patterning the semiconductor film to form a semiconductor layer, forming a second conductive film on the semiconductor layer, and patterning the second conductive film to form a second conductive layer; or, forming a semiconductor layer, a first conductive layer, and a second conductive layer on the first substrate may include: depositing a semiconductor film on the first substrate, patterning the semiconductor film to form a semiconductor layer, depositing a first insulating film on the semiconductor layer, patterning the first insulating film to form a gate insulating layer, depositing a first conductive film on the gate insulating layer, patterning the first conductive film to form a first conductive layer, depositing a second insulating film on the first conductive layer, patterning the second insulating film to form an interlayer dielectric layer, forming a second conductive film on the interlayer dielectric layer, and patterning the second conductive film to form a second conductive layer.

[0268] The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials; and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be carried out by any one or more of spraying, spin coating, and inkjet printing; and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0269] Step S12: forming an intermediate insulating layer on the device structure layer.

[0270] Step S12 may include: sequentially forming a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer on the device structure layer through a patterning process.

[0271] In an exemplary embodiment, forming a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer in sequence on the device structure layer through a patterning process may include: depositing a first inorganic insulating film, an organic film, and a second inorganic insulating film in sequence on the device structure layer, and patterning the first inorganic insulating film, the organic film, and the second inorganic insulating film through a patterning process to form the first inorganic insulating layer, the organic insulating layer, and the second inorganic insulating layer; or, depositing a first inorganic insulating film on the device structure layer, patterning the first inorganic insulating film through a patterning process to form the first inorganic insulating layer, depositing an organic film on the first inorganic insulating layer, patterning the organic film through a patterning process to form the organic insulating layer, depositing a second inorganic insulating film on the organic insulating layer, and patterning the second inorganic insulating film through a patterning process to form the second inorganic insulating layer.

[0272] Step S13: forming a heating structure layer on the intermediate insulating layer.

[0273] Step S13 may include: depositing a third conductive film on the intermediate insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer.

[0274] Step S14: forming an electrode structure layer on the heating structure layer.

[0275] Step S14 may include: sequentially forming a first passivation layer, a fourth conductive layer, a second passivation layer, and a fifth conductive layer on the heating structure layer through a patterning process.

[0276] In an exemplary embodiment, when the fourth conductive layer includes a metal material and a transparent conductive material, the fourth conductive layer is formed on the heating structure layer using a half-gray tone mask.

[0277] In an exemplary embodiment, forming the second substrate may include providing a second substrate, and forming an optical structure layer on the second substrate.

[0278] An embodiment of the present disclosure further provides a display device, which includes: a display panel.

[0279] The display panel is the display panel provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0280] In an exemplary embodiment, the display device may further include: a backlight module located on a side of the first substrate away from the second substrate, wherein the backlight module is configured to emit light toward the display panel.

[0281] In an exemplary embodiment, the display device may be any product or component with a display function, such as a liquid crystal display (LCD), electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0282] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0283] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0284] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display panel having a display area, characterized in that: include: A first substrate and a second substrate are arranged in a cell, wherein the first substrate is provided with a plurality of sub-pixels located in the display area, at least one sub-pixel includes: a first electrode and a second electrode, and the first substrate includes: a first substrate and an electrode structure layer arranged on a side of the first substrate close to the second substrate, the electrode structure layer includes at least: a first electrode and a second electrode of the at least one sub-pixel; The first substrate further includes a heating structure layer, which is located on a side of the electrode structure layer close to the first substrate and is configured to heat the display panel.

2. The display panel according to claim 1, wherein: The first substrate further includes: a device structure layer and an intermediate insulating layer; The device structure layer is located on a side of the heating structure layer close to the first substrate, and the device structure layer includes: a data line, a scan line, and a pixel transistor located in the display area, and the pixel transistor is electrically connected to the data line, the scan line, and the first electrode of at least one sub-pixel respectively; The intermediate insulating layer is located between the device structure layer and the heating structure layer, and the intermediate insulating layer includes: a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer sequentially stacked on the first substrate.

3. The display panel according to claim 2, wherein: The dielectric constant of the organic insulating layer is smaller than the dielectric constant of at least one of the first inorganic insulating layer and the second inorganic insulating layer, and the thickness of the organic insulating layer is greater than the thickness of at least one of the first inorganic insulating layer and the second inorganic insulating layer; The materials for making the first inorganic insulating layer and the second inorganic insulating layer include at least silicon nitride, and the materials for making the organic insulating layer include at least organic film.

4. The display panel according to claim 2, further comprising a non-display area, wherein: The non-display area includes: a binding area located on a first side of the display area and a frame area located on the other side of the display area, and the binding area includes: a first fan-out area, a second fan-out area, a driver chip area, and a binding pin area arranged in sequence in a direction away from the display area; The heating structure layer includes: at least one heating line at least partially located in the display area, at least one first heating line located in the first fan-out area, and at least one second heating line located in the second fan-out area, the driver chip area, and the binding pin area; The at least one first heating trace is connected to the at least one heating trace and the at least one second heating trace, respectively.

5. The display panel according to claim 4, wherein: The device structure layer further includes: a first fan-out trace located in the first fan-out area and a second fan-out trace located in the second fan-out area, at least one first fan-out trace being electrically connected to at least one data line and at least one second fan-out trace respectively; An orthographic projection of at least one data line on the first substrate at least partially overlaps with an orthographic projection of at least one heating line on the first substrate; An orthographic projection of at least one first heating trace on the first substrate at least partially overlaps with an orthographic projection of at least one first fan-out trace on the first substrate; An orthographic projection of the at least one second heating trace on the first substrate at least partially overlaps with an orthographic projection of the at least one second fan-out trace on the first substrate.

6. The display panel according to claim 5, wherein: The orthographic projection of at least one data line on the first substrate coincides with the orthographic projection of at least one heating line on the first substrate; An orthographic projection of at least a portion of the at least one first heating trace on the first substrate coincides with an orthographic projection of the at least one first fan-out trace on the first substrate.

7. The display panel according to claim 5, wherein: At least one second heating trace includes: a first heating connection portion and a second heating connection portion; at least one second fan-out trace includes: a first fan-out connection portion and a second fan-out connection portion; The first heating connection portion extends along a third direction, the first fan-out connection portion extends along a fourth direction, the second fan-out connection portion and the second heating connection portion extend along a second direction, the third direction intersects the first direction, the second direction and the fourth direction respectively, the first direction is an extension direction of the scan line, and the second direction is an extension direction of the data line; The first heating connection portion is connected to the second heating connection portion and at least one first heating line respectively, and the first fan-out connection portion is connected to the second fan-out connection portion and at least one first fan-out connection line respectively.

8. The display panel according to claim 7, wherein: An orthographic projection of the second heating connection portion of the at least one second heating trace on the first substrate and an orthographic projection of the second fan-out connection portion of the at least one second fan-out trace on the first substrate do not overlap with each other; The orthographic projections of the second heating connection portions of the other second heating traces except the target second heating trace on the first substrate are located on a side of the orthographic projection of the second heating connection portion of the target second heating trace on the first substrate away from the orthographic projection of the second fan-out connection portion of the target second fan-out trace on the first substrate, and the orthographic projections of the second fan-out connection portions of the other second fan-out traces except the target second fan-out trace on the first substrate are located on a side of the orthographic projection of the second fan-out connection portion of the target second fan-out trace on the first substrate away from the orthographic projection of the second heating connection portion of the target second heating trace on the first substrate; A spacing along the first direction between the second heating connection portion of the target second heating trace and the second fan-out connection portion of the target second fan-out trace is greater than or equal to 10 microns; The target second heating trace is the second heating trace having the shortest second heating connection portion along the second direction, and the target second fan-out trace is the second fan-out trace having the shortest second fan-out connection portion along the second direction.

9. The display panel according to claim 7, wherein: Also includes: A frame sealant is located between the first substrate and the second substrate, and the organic insulating layer is provided with an organic via; The orthographic projections of the organic via on the first substrate at least partially overlap with the orthographic projections of the second heating connection portion of the at least one second heating trace and the orthographic projections of the second fan-out connection portion of the at least one second fan-out trace on the first substrate, respectively, and do not overlap with the orthographic projections of the first heating connection portion of the at least one second heating trace and the orthographic projections of the first fan-out connection portion of the at least one second fan-out trace on the first substrate; The orthographic projection of the frame sealing adhesive on the first substrate at least partially overlaps with the orthographic projection of the organic via on the first substrate, and the length of the frame sealing adhesive along the second direction is smaller than the length of the organic via along the second direction.

10. The display panel according to claim 5, wherein: The electrode structure layer further includes: a plurality of data connection electrodes, and the heating structure layer further includes: a plurality of heating connection electrodes; The plurality of data connection electrodes correspond one-to-one to the plurality of first fan-out traces and one-to-one to the plurality of second fan-out traces, and at least one data connection electrode is electrically connected to the corresponding first fan-out trace and the corresponding second fan-out trace respectively; The plurality of heating connection electrodes correspond one-to-one to the plurality of first heating traces, at least one heating connection electrode is electrically connected to the corresponding first heating trace, and at least one second heating trace is electrically connected to at least one heating connection electrode.

11. The display panel according to claim 10, wherein: The shape of the heating connection electrode includes: a plurality of annular areas extending along a first direction; The orthographic projection of the at least one data connection electrode on the first substrate is located within the range of the orthographic projection of the at least one annular area on the first substrate.

12. The display panel according to claim 4, wherein: The first substrate further includes: a plurality of electrostatic discharge circuits located in the first fan-out area, at least one electrostatic discharge circuit is electrically connected to at least one first fan-out trace, and at least one electrostatic discharge circuit is electrically connected to at least one first heating trace.

13. The display panel according to claim 12, wherein: The multiple electrostatic release circuits include: three rows of electrostatic release circuits, at least one row of electrostatic release circuits includes: N electrostatic release circuits, the orthographic projection of the kth first heating line on the first substrate and the orthographic projection of the 3kth first fan-out line on the first substrate at least partially overlap, N≥1, 1≤k≤2N / 3.

14. The display panel according to claim 13, wherein: The N electrostatic discharge circuits in the first row and the N electrostatic discharge circuits in the second row are arranged alternately, and the N electrostatic discharge circuits in the first row and the N electrostatic discharge circuits in the third row are arranged in a matrix; The nth electrostatic discharge circuit in the first row is electrically connected to the 2n-1th first fan-out trace, the nth electrostatic discharge circuit in the second row is electrically connected to the 2nth first fan-out trace, the 3k-1th electrostatic discharge circuit in the third row is electrically connected to the 2k-1th first heating trace, and the 3kth electrostatic discharge circuit in the third row is electrically connected to the 2kth first fan-out trace; An orthographic projection of at least a portion of the 2n-1th first fan-out trace on the first substrate and an orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between an orthographic projection of the nth electrostatic discharge circuit in the first row on the first substrate and an orthographic projection of the n+1th electrostatic discharge circuit in the first row on the first substrate; The orthographic projection of at least part of the 2nth first fan-out trace on the first substrate and the orthographic projection of at least part of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic release circuit in the second row and the orthographic projection of the n+1th electrostatic release circuit in the second row on the first substrate, and the first first fan-out trace is located on the side of the first electrostatic release circuit in the second row away from the second first fan-out trace; the orthographic projection of at least part of the 2n-1th first fan-out trace on the first substrate and the orthographic projection of at least part of the 2nth first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic release circuit in the third row and the orthographic projection of the n+1th electrostatic release circuit in the third row on the first substrate.

15. The display panel according to claim 14, wherein: The orthographic projection of the 2kth first heating trace on the first substrate at least partially overlaps with the orthographic projection of the 6k-1th first fan-out trace on the first substrate.

16. The display panel according to claim 13, wherein: The N electrostatic discharge circuits in the first row are arranged alternately with the N electrostatic discharge circuits in the second row, and the N electrostatic discharge circuits in the second row are arranged alternately with the N electrostatic discharge circuits in the third row; The nth electrostatic discharge circuit in the first row is electrically connected to the 2n-1th first fan-out trace, the nth electrostatic discharge circuit in the second row is electrically connected to the 2nth first fan-out trace, the 3k-2th electrostatic discharge circuit in the third row is electrically connected to the 2k-1th first heating trace, and the 3kth electrostatic discharge circuit in the third row is electrically connected to the 2kth first heating trace; An orthographic projection of at least a portion of the 2n-1th first fan-out trace on the first substrate and an orthographic projection of at least a portion of the 2nth first fan-out trace on the first substrate are located between an orthographic projection of the nth electrostatic discharge circuit in the first row on the first substrate and an orthographic projection of the n+1th electrostatic discharge circuit in the first row on the first substrate; The orthographic projection of at least part of the 2nth first fan-out trace on the first substrate and the orthographic projection of at least part of the 2n+1th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the second row and the orthographic projection of the n+1th electrostatic discharge circuit in the second row on the first substrate, and the first first fan-out trace is located on a side of the first electrostatic discharge circuit in the second row away from the second first fan-out trace; the orthographic projection of at least part of the 2n+1th first fan-out trace on the first substrate and the orthographic projection of at least part of the 2n+2th first fan-out trace on the first substrate are located between the orthographic projection of the nth electrostatic discharge circuit in the third row and the orthographic projection of the n+1th electrostatic discharge circuit in the third row on the first substrate, and the first first fan-out trace and the second first fan-out trace are located on a side of the first electrostatic discharge circuit in the third row away from the third first fan-out trace.

17. The display panel according to claim 16, wherein: There is no overlapping area between the orthographic projection of the 2kth first heating trace on the first substrate and the orthographic projection of the 6k-1th first fan-out trace on the first substrate.

18. The display panel according to claim 4, wherein: The heating structure layer further includes: at least one frame heating trace located in the frame area; The at least one frame heating line includes: a first frame heating line and a plurality of second frame heating lines; The first frame heating line extends along a first direction and is located on a second side of the display area. The at least one second frame heating line extends along a second direction and is located on at least one of a third side and a fourth side of the display area. The first side and the second side are oppositely arranged, and the third side and the fourth side are oppositely arranged. The first direction is an extension direction of the scan line, and the second direction is an extension direction of the data line. The first frame heating wiring is respectively connected to at least one second frame heating wiring and at least one heating wire.

19. The display panel according to claim 10, wherein: The first substrate further includes: a gate driving circuit located on at least one of the third side and the fourth side of the non-display area; The orthographic projection of the at least one second frame heating trace on the first substrate is located on a side of the orthographic projection of the gate driving circuit on the first substrate close to the display area.

20. The display panel according to claim 18, wherein The first substrate further includes: a common electrode power supply line located in the non-display area, the common electrode power supply line being located in the device structure layer, the common electrode power supply line being electrically connected to the second electrode of at least one sub-pixel, and being arranged around the display area; The orthographic projection of at least one second frame heating trace on the first substrate at least partially overlaps with the orthographic projection of at least part of the common electrode power supply line on the first substrate.

21. The display panel according to claim 5, wherein The first substrate further includes: a data driver chip located in the driver chip area and a first circuit board and a second circuit board located in the binding pin area; The data driver chip is electrically connected to at least one second fan-out trace, the first circuit board is electrically connected to the data driver chip, and the second circuit board is electrically connected to at least one second heating trace.

22. The display panel according to claim 21, wherein: The first circuit board and the second circuit board are the same circuit board.

23. The display panel according to claim 2, wherein: The first substrate further includes: at least one electrostatic discharge circuit, a common electrode power supply line, a first fan-out line and a second fan-out line The electrostatic discharge circuit includes: at least one release transistor, the transistor including: an active pattern, a control electrode, a first electrode and a second electrode; The device structure layer includes: a semiconductor layer, a first conductive layer and a second conductive layer provided on the first substrate; The semiconductor layer includes at least: an active pattern of at least one release transistor and an active pattern of at least one pixel transistor; The first conductive layer at least includes: a scan line, a common electrode power supply line, a control electrode of at least one release transistor and a control electrode of at least one pixel transistor; The second conductive layer at least includes: a data line, a first fan-out line, a first electrode and a second electrode of at least one release transistor, and a first electrode and a second electrode of at least one pixel transistor; The second fan-out trace is located in the first conductive layer or the second conductive layer.

24. The display panel according to claim 4, wherein: The heating structure layer further includes: a frame heating wiring, and the heating structure layer includes a third conductive layer; The third conductive layer at least includes: a heating line, a first heating trace, a second heating trace and a frame heating trace.

25. The display panel according to claim 4, wherein: The electrode structure layer includes: a fourth conductive layer and a fifth conductive layer sequentially stacked on the first substrate; the first substrate further includes: at least one electrostatic discharge circuit; the electrostatic discharge circuit includes: at least one release transistor; the first substrate further includes: a data connection electrode and a release connection electrode; the data connection electrode is electrically connected to the first fan-out trace and the second fan-out trace respectively; the release connection electrode is electrically connected to at least two release transistors respectively, or is electrically connected to one release transistor and the first heating trace respectively; The fourth conductive layer at least includes: a second electrode of at least one sub-pixel; The fifth conductive layer at least includes: a first electrode of at least one sub-pixel, a data connection electrode, and a release connection electrode.

26. The display panel according to claim 1, wherein Also includes: a liquid crystal layer located between the first substrate and the second substrate, the liquid crystal layer comprising: nematic liquid crystal; The second substrate includes: a second substrate and an optical structure layer arranged on the second substrate, the optical structure layer includes: a black matrix layer and a filter layer, the sub-pixel includes a pixel opening, and the filter layer includes: a plurality of filters, and the orthographic projection of at least one filter on the first substrate at least partially overlaps with the orthographic projection of at least one pixel opening on the first substrate.

27. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 26.

28. A method for preparing a display panel, characterized in that: The method is configured to prepare the display panel according to any one of claims 1 to 26, the method comprising: forming a heating structure layer and an electrode structure layer in sequence on a first substrate to form a first base plate; forming a second substrate; The first substrate and the second substrate are arranged in a box.

29. The method according to claim 28, characterized in that The sequentially forming of a heating structure layer and an electrode structure layer on the first substrate comprises: forming a device structure layer on a first substrate; forming an intermediate insulating layer on the device structure layer; forming a heating structure layer on the intermediate insulating layer; forming an electrode structure layer on the heating structure layer; The forming of the device structure layer on the first substrate comprises: forming a semiconductor layer, a first conductive layer and a second conductive layer on the first substrate; Forming an intermediate insulating layer on the device structure layer includes: sequentially forming a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer on the device structure layer; The forming of the electrode structure layer on the heating structure layer includes: forming a fourth conductive layer and a fifth conductive layer on the heating structure layer.

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