Display device

Abstract

The display device may include a first color sub-pixel arranged in a first row and disposed on the substrate, a second color sub-pixel arranged in a second row and disposed on the substrate, and a third color sub-pixel arranged in a third row and disposed on the substrate. Further, the display device may include a first gate line disposed between the first row and the second row, the first gate line being connected to a first group of sub-pixels among the first color sub-pixels arranged in the first row and the second color sub-pixels arranged in the second row, and a second gate line disposed between the second row and the third row, the second gate line being connected to a second group of sub-pixels among the second color sub-pixels arranged in the second row, the second gate line is connected to a second group of sub-pixels in the second color sub-pixels arranged in the second row and a third color sub-pixel arranged in the third row.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0029837 filed in Korea on February 29, 2024, and No. 10-2024-0159096 filed in Korea on November 11, 2024, the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device capable of reducing manufacturing costs and power consumption. Background Art

[0004] The liquid crystal display device includes a liquid crystal panel that displays images through a pixel matrix using electrical and optical properties (such as refractive index and dielectric constant) of liquid crystal having anisotropy, a driving circuit that drives the liquid crystal panel, and a backlight unit that irradiates light to the liquid crystal panel.

[0005] Liquid crystal display devices are being developed in the direction of reducing manufacturing costs and power consumption, and therefore, methods for reducing manufacturing costs and power consumption without reducing resolution or compromising image quality are needed. In addition, there is also a need for a display device having a configuration that can reduce power consumption, reduce wiring to save space, and increase device life, while also being adapted to prevent image defects. Summary of the Invention

[0006] The present disclosure provides a display device capable of improving low-grayscale stain or low-grayscale image defects by compensating for differences in luminance sensitivity by differently applying an S factor of a driving transistor to each of three-color sub-pixels.

[0007] Problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will become apparent to those skilled in the art to which the technical idea of ​​the present disclosure belongs based on the following description.

[0008] To achieve these and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, there is provided a display device according to an embodiment, the display device may include: a first horizontal line including a plurality of first color sub-pixels arranged in a horizontal direction; a second horizontal line including a plurality of second color sub-pixels arranged in a horizontal direction; a third horizontal line including a plurality of third color sub-pixels arranged in a horizontal direction; a first gate line disposed between the first horizontal line and the second horizontal line and connected to the first horizontal line and to some of the sub-pixels of the second horizontal line; a second gate line disposed between the second horizontal line and the third horizontal line , and is connected to the third horizontal line, and is connected to the remaining sub-pixels of the second horizontal line; the first column line to the fourth column line are formed by alternately arranging the first color sub-pixels to the third color sub-pixels of the first horizontal line to the third horizontal line in the vertical direction; a first data line is arranged on the left side of the first column line and is connected to the first color sub-pixel and the third color sub-pixel in the first column line; a third data line is arranged on the right side of the second column line and is connected to the first color sub-pixel and the third color sub-pixel in the second column line; and a second data line is arranged between the first column line and the second column line and is connected to the second color sub-pixel in the first column line and the second column line.

[0009] According to another aspect of the present disclosure, a display device according to an embodiment is provided, which may include: a first horizontal line including a plurality of first color sub-pixels arranged in a horizontal direction; a second horizontal line including a plurality of second color sub-pixels arranged in a horizontal direction; a third horizontal line including a plurality of third color sub-pixels arranged in a horizontal direction; a first gate line arranged between the first horizontal line and the second horizontal line, connected to the first horizontal line, and connected to some sub-pixels of the second horizontal line; a second gate line arranged between the second horizontal line and the third horizontal line, connected to the third horizontal line, and connected to the remaining sub-pixels in the second horizontal line; first to fourth column lines formed by alternately arranging the first to third color sub-pixels of the first to third horizontal lines in a vertical direction; a first data line arranged on the left side of the first column line, and connected to the first and third color sub-pixels in the first column line; a (2-1)th data line arranged between the first column line and the second column line and connected to the second color sub-pixel in the first column line; and the (3-1)th data line, which is arranged between the first column line and the second column line and connected to the second color sub-pixel in the second column line; the fourth data line, which is arranged between the second column line and the third column line and connected to the first color sub-pixel and the third color sub-pixel in the second column line; and the fifth data line, which is arranged between the second column line and the third column line and connected to the first color sub-pixel and the third color sub-pixel in the third column line; the (2-2)th data line, which is arranged between the third column line and the fourth column line and connected to the second color sub-pixel in the third column line; and the (3-2)th data line, which is arranged between the third column line and the fourth column line and connected to the second color sub-pixel in the fourth column line; and the sixth data line, which is arranged on the right side of the fourth column line and connected to the first color sub-pixel and the third color sub-pixel in the fourth column line, the (2-1)th data line is connected to the (2-2)th data line, and the (3-1)th data line is connected to the (3-2)th data line.

[0010] According to another aspect of the present disclosure, a display device is provided, including: first color sub-pixels arranged in a first row and set on a substrate; second color sub-pixels arranged in a second row and set on the substrate; third color sub-pixels arranged in a third row and set on the substrate; a first gate line arranged between the first row and the second row, the first gate line being connected to a first group of sub-pixels among the first color sub-pixels arranged in the first row and the second color sub-pixels arranged in the second row; and a second gate line arranged between the second row and the third row, the second gate line being connected to a second group of sub-pixels among the second color sub-pixels arranged in the second row and the third color sub-pixels arranged in the third row.

[0011] The display device also includes a first column of sub-pixels, including: first-first color sub-pixels among the first color sub-pixels arranged in the first row, first-second color sub-pixels among the second color sub-pixels arranged in the second row, and first-third color sub-pixels among the third color sub-pixels arranged in the third row; a second column of sub-pixels, including: second-first color sub-pixels among the first color sub-pixels arranged in the first row, second-second color sub-pixels among the second color sub-pixels arranged in the second row, and second-third color sub-pixels among the third color sub-pixels arranged in the third row; a first data line connected to the first-first color sub-pixels in the first column and the first-third color sub-pixels in the first column; a second data line arranged between the first column and the second column, the second data line connected to the first-second color sub-pixels in the first column and the second-second color sub-pixels in the third column; and a third data line connected to the second-first color sub-pixels in the second column and the second-third color sub-pixels in the second column.

[0012] The display device also includes: a controller electrically connected to the first color sub-pixel, the second color sub-pixel and the third color sub-pixel, the controller being configured to: during odd frames, provide a data voltage having a first polarity to the first data line, provide a data voltage having a second polarity opposite to the first polarity to the second data line, and provide a data voltage having the second polarity to the third data line, and during even frames, provide a data voltage having the second polarity to the first data line, provide a data voltage having the first polarity to the second data line, and provide a data voltage having the first polarity to the third data line.

[0013] The first gate line and the second gate line overlap a common electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, and wherein the first data line, the second data line, and the third data line are spaced apart from and do not overlap the common electrode.

[0014] The display device also includes: a first column of sub-pixels, including: first-first color sub-pixels among the first color sub-pixels arranged in the first row, first-second color sub-pixels among the second color sub-pixels arranged in the second row, and first-third color sub-pixels among the third color sub-pixels arranged in the third row; a second column of sub-pixels, including: second-first color sub-pixels among the first color sub-pixels arranged in the first row, second-second color sub-pixels among the second color sub-pixels arranged in the second row, and second-third color sub-pixels among the third color sub-pixels arranged in the third row; a first data line, connected to the first-first color sub-pixels in the first column and the first-third color sub-pixels in the first column; a second data line, arranged between the first column and the second column, the second data line connected to the first-second color sub-pixels in the first column; and a third data line, arranged between the first column and the second column, the third data line connected to the second-second color sub-pixels in the second column.

[0015] The display device also includes: a controller electrically connected to the first color sub-pixel, the second color sub-pixel and the third color sub-pixel, the controller being configured to: during odd frames, provide a data voltage having a first polarity to the second data line, provide a data voltage having a second polarity opposite to the first polarity to the first data line, and provide a data voltage having the first polarity to the third data line, and during even frames, provide a data voltage having the first polarity to the first data line, provide a data voltage having the second polarity to the second data line, and provide a data voltage having the second polarity to the third data line.

[0016] The display device also includes: a controller connected to the first color sub-pixel, the second color sub-pixel and the third color sub-pixel, the controller being configured to: drive the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the horizontal direction according to a two-dot inversion driving method, and drive the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in the vertical direction according to a one-two-dot mixed inversion driving method, the one-two-dot mixed inversion driving method including a one-dot inversion driving method mixed with a two-dot inversion driving method.

[0017] According to another aspect of the present disclosure, a display device according to an embodiment is provided, which may include a first horizontal line including first color sub-pixels arranged in a horizontal direction; a second horizontal line including second color sub-pixels arranged in a horizontal direction; a third horizontal line including third color sub-pixels arranged in a horizontal direction; a first gate line arranged between the first horizontal line and the second horizontal line, and connected to the first horizontal line, and connected to some sub-pixels of the second horizontal line; a second gate line arranged between the second horizontal line and the third horizontal line, and connected to the third horizontal line, and connected to the remaining sub-pixels of the second horizontal line; column lines, each column line including first color sub-pixels to third color sub-pixels of the first horizontal line to the third horizontal line alternately arranged in a vertical direction; a first type of data line arranged on a first side of each column line, and connected to the first color sub-pixel and the third color sub-pixel of each column line; and a second type of data line arranged on a second side of each column line, and connected to the second color sub-pixel of each column line, wherein the second type of data line and the first type of data line are arranged in parallel between adjacent column lines.

[0018] The first-category data lines include a first-category first data line, a first-category third data line, a first-category fifth data line, and a first-category sixth data line that are arranged on a first side of each of the first to fourth column lines and connected to the first color sub-pixel and the third color sub-pixel of each of the first to fourth column lines.

[0019] The second type of data lines includes: a second type (2-1) data line and a second type (2-2) data line, which are arranged on the second side of each of the first column line and the third column line and connected to the second color sub-pixel of each of the first column line and the third column line; and a second type (4-1) data line and a second type (4-2) data line, which are arranged on the second side of each of the second column line and the fourth column line and connected to the second color sub-pixel of each of the second column line and the fourth column line, the (2-1) data line is connected to the (2-2) data line, and the (4-1) data line is connected to the (4-2) data line.

[0020] The first to third horizontal lines are driven at a double rate by the first gate line and the second gate line.

[0021] During the first horizontal period in which the gate-on voltage is driven to the first gate line, the first color sub-pixel of the first horizontal line connected to the first data line and the fifth data line is charged by receiving the first color data signal of the first polarity, and the first color sub-pixel connected to the third data line and the sixth data line is charged by receiving the first color data signal of the second polarity, and the second color sub-pixel of the second horizontal line connected to the (2-1)th data line is charged by receiving the second color data signal of the second polarity, and the second color sub-pixel connected to the (4-1)th data line is charged by receiving the second color data signal of the first polarity.

[0022] During the second horizontal period in which the gate-on voltage is driven to the second gate line, the second color sub-pixel of the second horizontal line connected to the (2-2) data line is charged by receiving the second color data signal of the second polarity, and the second color sub-pixel connected to the (4-2) data line is charged by receiving the second color data signal of the first polarity, and the third color sub-pixel of the third horizontal line connected to the first data line and the fifth data line is charged by receiving the third color data signal of the first polarity, and the third color sub-pixel connected to the third data line and the sixth data line is charged by receiving the third color data signal of the second polarity.

[0023] The first data line, the (4-1)th data line and the (4-2)th data line apply data signals having polarities opposite to those of the data signals of the (2-1)th data line, the (2-2)th data line, the third data line and the sixth data line, and the polarities of the data signals applied to each of the first data line to the sixth data line are the same in one frame and are opposite for adjacent frames.

[0024] The first to third color sub-pixels have long sides in the horizontal direction and short sides in the vertical direction.

[0025] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are examples, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure and are briefly described as follows:

[0027] Figure 1 is a block diagram illustrating a configuration of a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is a diagram illustrating an example of a structure of a sub-pixel according to an embodiment of the present disclosure.

[0029] Figure 3A is a diagram showing an embodiment according to the present disclosure. Figure 2 A cross-sectional view showing an example of a cross-sectional structure of a data line region taken along line II′ is shown in FIG. Figure 3B is a diagram showing an embodiment according to the present disclosure Figure 2 2 is a cross-sectional view of an example of a cross-sectional structure of a gate line region taken along line II-II′.

[0030] Figure 4 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to an embodiment of the present disclosure.

[0031] Figure 5 is a diagram showing an embodiment of the present disclosure. Figure 4 FIG. 1 is a diagram showing an example of an inversion driving method in an odd-numbered frame of a liquid crystal panel.

[0032] Figure 6 is a diagram showing an embodiment of the present disclosure. Figure 4 FIG. 1 is a diagram showing an example of an inversion driving method in an even-numbered frame of a liquid crystal panel.

[0033] Figure 7 According to the embodiment of the present disclosure Figure 5 An example of a driving waveform diagram of an odd-numbered frame of a liquid crystal panel is shown in FIG.

[0034] Figure 8 According to the embodiment of the present disclosure Figure 6 An example of a driving waveform diagram of an even-numbered frame of a liquid crystal panel is shown in FIG.

[0035] Figure 9 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to an embodiment of the present disclosure.

[0036] Figure 10 is a diagram showing an embodiment of the present disclosure. Figure 9 FIG. 1 is a diagram showing an example of an inversion driving method in an odd-numbered frame of a liquid crystal panel.

[0037] Figure 11 is a diagram showing an embodiment of the present disclosure. Figure 9 FIG. 1 is a diagram showing an example of an inversion driving method in an even-numbered frame of a liquid crystal panel.

[0038] Figure 12 According to the embodiment of the present disclosure Figure 10 An example of a driving waveform diagram of an odd-numbered frame of a liquid crystal panel is shown in FIG.

[0039] Figure 13 According to the embodiment of the present disclosure Figure 11 An example of a driving waveform diagram of an even-numbered frame of a liquid crystal panel is shown in FIG.

[0040] Figure 14 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to an embodiment of the present disclosure.

[0041] Figure 15 Is to show about Figure 14 FIG. 1 is a diagram showing an example of an inversion driving method in an odd-numbered frame of a liquid crystal panel.

[0042] Figure 16 Is to show about Figure 14 FIG. 1 is a diagram showing an example of an inversion driving method in an even-numbered frame of a liquid crystal panel.

[0043] Figure 17 It's about Figure 15 An example of a driving waveform diagram of an odd-numbered frame of a liquid crystal panel is shown in FIG.

[0044] Figure 18 It's about Figure 16 An example of a driving waveform diagram of an even-numbered frame of a liquid crystal panel is shown in FIG. DETAILED DESCRIPTION

[0045] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments and with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0046] The shapes, sizes, ratios, angles, and numbers disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the key points of the present disclosure, the detailed description will be omitted.

[0047] In cases where “including,” “having,” and “comprising” are used in this specification, another component may further be present unless “only” is used. Terms in the singular form may include plural forms unless otherwise indicated.

[0048] When constituting an element, the element is interpreted as including an error area although there is no explicit description thereof.

[0049] When describing a positional relationship, for example, when the positional order is described as "on," "above," "below," "under," and "immediately adjacent," unless "exactly" or "directly" is used, cases where there is no contact between them may be included.

[0050] If a first element is referred to as being "on" a second element, this does not necessarily mean that the first element is located above the second element in the drawings. The upper and lower portions of an object of interest can vary depending on the orientation of the object. Therefore, reference to a first element being "on" a second element includes both references to the first element being "below" the second element in the drawings or in actual configuration, and references to the first element being "above" the second element.

[0051] When describing a temporal relationship, for example, when a temporal order is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "only" or "directly" is used.

[0052] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0053] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each element of the first element, the second element, and the third element.

[0054] The features of various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may perform various mutual operations and technology drives. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0055] In the drawings, the same or similar elements are denoted by the same reference numerals although they are depicted in different drawings.

[0056] In the embodiments of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode can be used interchangeably. Therefore, the source electrode can be a drain electrode, and the drain electrode can be a source electrode. In addition, the source electrode in any embodiment of the present disclosure can be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be the source electrode in another embodiment of the present disclosure.

[0057] In one or more embodiments of the present disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0058] Figure 1 is a block diagram illustrating a configuration of a display device according to an embodiment of the present disclosure, Figure 2 is a diagram showing an example of a sub-pixel structure according to an embodiment of the present disclosure, Figure 3A is a diagram showing an embodiment according to the present disclosure Figure 2 A cross-sectional view showing an example of a cross-sectional structure of a data line region taken along line II′ is shown in FIG. Figure 3B is a cross-sectional view illustrating an example of a cross-sectional structure of a gate line region along line II-II′ according to an embodiment of the present disclosure.

[0059] Reference Figure 1 The display device 1000 may include a liquid crystal panel 100, a driving circuit 900, and a power management circuit 700. The display device 1000 may also include: a backlight unit disposed on the rear surface of the liquid crystal panel 100 to provide light to the display area DA of the liquid crystal panel 100; and a backlight driving circuit for driving the backlight unit. The driving circuit 900 may include a gate driving circuit 200 (e.g., a gate driver), a data driving circuit 300 (e.g., a data driver), a timing controller 400, a level shifter 500, a gamma voltage generator 600, etc., and the gate driving circuit 200 may be embedded in the liquid crystal panel 100 (e.g., a gate-in-panel (GIP) circuit).

[0060] The liquid crystal panel 100 may include a display area DA in which subpixels SP are arranged in a matrix, and a bezel area BZ surrounding the periphery of the display area DA. The display area DA of the liquid crystal panel 100 may display an image by including a plurality of pixels composed of three or four color subpixels SP that transmit light of different colors.

[0061] The liquid crystal panel 100 may include: a first substrate and a second substrate, the first substrate and the second substrate being combined with a liquid crystal layer interposed therebetween; and polarizing plates attached to outer surfaces of the first substrate and the second substrate, respectively. The thin film transistor TFT of the sub-pixel SP, the signal lines and electrodes connected to the thin film transistor TFT (including the gate line GL, the data line DL, the pixel electrode PX ( Figure 2 ) and the circuit including the gate driving circuit 200 can be provided on the first substrate. The common electrode COM can be provided on either the first substrate or the second substrate. The black matrix and color filter of the sub-pixel SP can be provided on either the first substrate or the second substrate.

[0062] In an embodiment, the liquid crystal panel 100 may further include a touch sensor that is arranged to overlap with the display area DA to sense a user's touch. The touch sensor may be arranged on the display area DA of the liquid crystal panel 100, or the divided common electrodes COM of the liquid crystal panel 100 may be used as touch electrodes.

[0063] Each subpixel SP can be independently driven by a thin-film transistor (TFT) connected to a gate line GL and a data line DL. Each subpixel SP may include a thin-film transistor (TFT) connected to the gate line GL and the data line DL, a liquid crystal capacitor (Clc) connected in parallel to the thin-film transistor (TFT), and a storage capacitor (Cst). The liquid crystal capacitor (Clc) can charge the difference between the data signal supplied to the pixel electrode PX via the thin-film transistor (TFT) and the common voltage supplied to the common electrode COM, and can drive the liquid crystal according to the charged voltage to control light transmittance. The storage capacitor (Cst) can be used to stably maintain the charged voltage in the liquid crystal capacitor (Clc) when the thin-film transistor (TFT) is turned off.

[0064] Each sub-pixel SP can adjust the transmittance of light transmitted from the backlight unit through the liquid crystal panel 100 and the polarizing plate by changing the liquid crystal arrangement direction by driving the liquid crystal according to the charging voltage. Each sub-pixel SP can represent the grayscale of the image by multiplying the brightness of the backlight unit by the transmittance controlled by the data signal in each sub-pixel SP.

[0065] The liquid crystal layer of the liquid crystal capacitor Clc in each sub-pixel SP can be driven in a twisted nematic (TN) mode or a vertical alignment (VA) mode by a vertical electric field applied through the pixel electrode PX and the common electrode COM, can be driven in an in-plane switching (IPS) mode by a horizontal electric field applied through the pixel electrode PX and the common electrode COM, or can be driven in a Fringe Field Switching (FFS) mode by a fringe electric field applied through the pixel electrode PX and the common electrode COM.

[0066] In an embodiment, the pixel electrode PX and the common electrode COM of each sub-pixel SP may overlap each other on the first substrate, with an insulating layer interposed between the pixel electrode PX and the common electrode COM; and may include a plurality of slits, in which one of the pixel electrode PX and the common electrode COM overlaps with the other electrodes; and the liquid crystal layer may be driven in an FFS mode by applying a fringe electric field to the liquid crystal layer.

[0067] In the display area DA of the liquid crystal panel 100 , sub-pixels SP of different colors may be alternately and repeatedly arranged in the vertical direction Y, and sub-pixels SP of the same color may be arranged in the horizontal direction X.

[0068] In an embodiment, red (R), green (G), and blue (B) sub-pixels SP may be alternately and repeatedly arranged in the vertical direction Y, and sub-pixels SP of the same color may be arranged along the horizontal direction X. In other words, the sub-pixels in each row may have the same color. Therefore, compared with a related-art liquid crystal panel in which R, G, and B sub-pixels are alternately arranged in the horizontal direction X, the liquid crystal panel 100 according to an embodiment can reduce the number of data lines DL, and thus, can reduce the number of data integrated circuits IC included in the data driving circuit 300, thereby reducing the manufacturing cost of the display device 1000.

[0069] In an embodiment, the plurality of data lines DL disposed in the display area DA of the liquid crystal panel 100 may include first-type data lines connected to sub-pixels of different colors and second-type data lines connected to sub-pixels of the same color, which will be described in detail later.

[0070] The liquid crystal panel 100 according to the embodiment can drive an R horizontal line including a plurality of R sub-pixels, a G horizontal line including a plurality of G sub-pixels, and a B horizontal line including a plurality of B sub-pixels in a double rate driving manner by using two gate lines. Therefore, the liquid crystal panel 100 according to the embodiment can reduce the number of gate lines GL compared to the number of R, G, and B horizontal lines, and therefore, the manufacturing cost of the display device 1000 can be reduced. In other words, the gate lines GL of the liquid crystal panel 100 can be less than the number of rows of sub-pixels (for example, some of the sub-pixels in two adjacent horizontal rows can share the same gate line). In addition, for example, some sub-pixels in a horizontal row can be connected to one gate line, while the remaining sub-pixels in the same horizontal row can be connected to another gate line (for example, a row of sub-pixels can be separately connected to two different gate lines).

[0071] In an embodiment, each subpixel SP may have a horizontal stripe shape including long sides parallel to a horizontal direction X (ie, an extending direction of the gate line GL) and short sides parallel to a vertical direction Y (ie, an extending direction of the data line DL).

[0072] Reference Figure 2 The thin film transistor TFT of the subpixel SP according to an embodiment can be connected to the gate line GL in the horizontal direction X, the data line DL in the vertical direction Y, and the pixel electrode PX. The common electrode COM can be arranged to overlap the pixel electrode PX with at least one insulating layer interposed therebetween, and can include a plurality of slits overlapping the pixel electrode PX. The pixel electrode PX and the common electrode COM can have a long side in the horizontal direction X and a short side in the vertical direction Y. The common electrode COM can overlap the gate line GL with a plurality of insulating layers interposed therebetween.

[0073] Reference Figure 3A , the data line DL may be disposed on the gate insulating layer GI on the first substrate SUB and may be covered by the passivation layer PAS (eg, not overlapped with the common electrode COM).

[0074] Reference Figure 3B The gate line GL may be disposed on the first substrate SUB and may be covered by the gate insulating layer GI. The common electrode COM may overlap the gate line GL, with the gate insulating layer GI and the passivation layer PAS stacked on the gate line GL interposed between the common electrode COM and the gate line GL. Therefore, compared to a related-art liquid crystal panel in which the data line and the common electrode overlap with each other and the common electrode has a passivation layer interposed therebetween, the liquid crystal panel 100 according to the embodiment can reduce the parasitic capacitance load of the data line DL. In other words, according to the embodiment, the data line can be spaced apart from the common electrode COM so that they do not overlap, thereby reducing parasitic capacitance.

[0075] Therefore, the liquid crystal panel 100 according to an embodiment of the present disclosure may reduce power consumption by reducing a load on the data lines DL, and may prevent image quality defects by reducing a ripple effect of a common voltage.

[0076] The plurality of transistors including the gate driving circuit 200 provided in the display area DA and the bezel area BZ of the liquid crystal panel 100 may include LTPS transistors using LTPS semiconductors or oxide transistors using metal oxide semiconductors.

[0077] The gate driver circuit 200 can be disposed in either of the two bezel regions BZ of the liquid crystal panel 100, where the two bezel regions BZ face the area DA interposed therebetween; or the gate driver circuit 200 can be disposed in both bezel regions BZ. The gate driver circuit 200 can be embedded in the bezel region BZ using a gate in panel (GIP) type, and include thin film transistors formed using the same process as the thin film transistors TFT in the display area DA.

[0078] The gate driving circuit 200 can operate by receiving a plurality of gate control signals provided from the timing controller 400 through the level shifter 500. The gate driving circuit 200 can receive the plurality of gate control signals from the timing controller 400. The gate driving circuit 200 can be controlled by the plurality of gate control signals and can individually drive the gate lines GL of the liquid crystal panel 100. The gate driving circuit 200 can output a scan signal of a gate-on voltage to the corresponding gate line GL during a driving period of each gate line GL, and can output a gate-off voltage to the corresponding gate line GL during a non-driving period of each gate line GL.

[0079] The level shifter 500 may receive the control signal from the timing controller 400 to generate a plurality of gate control signals by level-shifting or logic-processing the control signal, and output the plurality of gate control signals to the gate driving circuit 200 .

[0080] The gamma voltage generator 600 can generate a plurality of reference gamma voltages having different voltage levels and output the generated gamma voltages to the data driving circuit 300. The gamma voltage generator 600 can generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and output the generated gamma voltages to the data driving circuit 300. The gamma voltage generator 600 can be configured as a programmable gamma integrated circuit (IC) and can generate or adjust the reference gamma voltages according to gamma data provided from the timing controller 400 and output the generated gamma voltages to the data driving circuit 300.

[0081] The data drive circuit 300 can convert digital data and data control signals received from the timing controller 400 into analog data signals to provide the data signals to the data lines DL of the liquid crystal panel 100. The data drive circuit 300 can subdivide the multiple reference gamma voltages provided by the gamma voltage generator 600 to convert the digital data into analog data voltages using the subdivided gamma voltages. The data drive circuit 300 can determine the polarity of the data voltage based on the polarity control signal. The data drive circuit 300 can determine the data voltage using a column inversion method in which the polarities of adjacent data lines DL are opposite to each other, and output the data voltage to the multiple data lines DL.

[0082] The data driving circuit 300 may include at least one data integrated circuit IC. The data IC may be embedded in the bezel region BZ of the liquid crystal panel 100 or may be embedded in a circuit film connected to the liquid crystal panel 100.

[0083] The timing controller 400 can receive source images and timing control signals from an external host system. The host system can be any system such as a computer, TV system, set-top box, tablet computer, or portable terminal such as a mobile phone. The timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal.

[0084] The timing controller 400 can control the gate driver circuit 200 and the data driver circuit 300 using timing control signals provided from the host system and timing setting information stored therein. The timing controller 400 can generate a plurality of gate control signals for controlling the driving timing of the gate driver circuit 200 and output the generated gate control signals to the gate driver circuit 200. The timing controller 400 according to an embodiment can generate a control signal for timing control and output the generated control signal to the level shifter 500, so that the level shifter 500 can generate a plurality of gate control signals and provide the plurality of gate control signals to the gate driver circuit 200. The timing controller 400 can generate a plurality of data control signals for controlling the driving timing of the data driver circuit 300 and output the generated data control signals to the data driver circuit 300.

[0085] The timing controller 400 can perform various image processing, including brightness correction, etc., to reduce power consumption by using input image data, and can output the image-processed data to the data driving circuit 300. For example, the timing controller 400 can perform an overdrive process in which an overshoot value or undershoot value is added to each pixel data according to the difference in pixel data between adjacent frames to improve the response speed of the liquid crystal. The timing controller 400 can align the image-processed data according to the sub-pixel arrangement of the liquid crystal panel 100 and output the aligned data to the data driving circuit 300.

[0086] The power management circuit 700 can generate and provide a plurality of driving voltages required for driving the driving circuit 900 and the liquid crystal panel 100. The power management circuit 700 can generate and provide a gate-on voltage and a gate-off voltage to the gate driving circuit 200 of the liquid crystal panel 100, and can generate and provide a common voltage to the common electrode COM of the liquid crystal panel 100. The power management circuit 700 can generate and provide a plurality of driving voltages required for the operation of the data driving circuit 300, the timing controller 400, the level shifter 500, and the gamma voltage generator 600.

[0087] Figure 4 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to an embodiment.

[0088] Reference Figure 4 The display area of ​​the liquid crystal panel according to the embodiment may include a pixel matrix including a plurality of horizontal lines HL1 to HL6, ... composed of a plurality of sub-pixels arranged along the horizontal direction X, and a plurality of column lines CL1 to CL4, ... composed of a plurality of sub-pixels arranged along the vertical direction Y. Hereinafter, the arrangement structure of the first horizontal line HL1a to the sixth horizontal line HL6a and the first column line CL1 to the fourth column line CL4 in the pixel matrix will be described as an example. For example, some of the gate lines may be shared by some of the sub-pixels in two adjacent rows, which can reduce wiring, lower power consumption, improve manufacturing efficiency, and save space, thereby providing higher resolution.

[0089] Each column line CLn (where n=1, 2, 3, 4) includes first to third color subpixels arranged alternately in the vertical direction Y (e.g., RGB repeats), and each horizontal line HLm (where m=1, 2, 3, 4, 5, 6) includes subpixels of the same color arranged in the horizontal direction X. The 3m-2th horizontal line HL3m-2 (e.g., HL1 and HL4) includes a first color subpixel (e.g., red), the 3m-1th horizontal line HL3m-1 (e.g., HL2 and HL5) includes a second color subpixel (e.g., green), and the 3mth horizontal line HL3m (e.g., HL3 and HL6) includes a third color subpixel (e.g., blue). For example, the first, second, and third color subpixels may be R, G, and B subpixels, but the present embodiment is not limited thereto.

[0090] The first to sixth horizontal lines HL1 to HL6 and the first to fourth column lines CL1 to CL4 may be driven using the first to fourth gate lines GL1 to GL4 and the first to sixth data lines DL1 to DL6. For example, the number of gate lines is less than the number of rows of subpixels.

[0091] The gate lines GL1 to GL4 may extend in the horizontal direction X and may be arranged in parallel in the vertical direction Y. The gate lines GL1 to GL4 may be driven by a gate driving circuit 200 ( Figure 1 ) to sequentially drive the gate signals Gate1 to Gate4.

[0092] The first to third horizontal lines HL1, HL2, and HL3 can be driven in a double-rate driving manner by the first gate line GL1 and the second gate line GL2, and the fourth to sixth horizontal lines HL4, HL5, and HL6 can be driven in a double-rate driving manner by the third gate line GL3 and the fourth gate line GL4. Therefore, the display device according to the embodiment can reduce the number of gate lines to less than the number of horizontal lines.

[0093] The first horizontal line HL1 and the third horizontal line HL3 can be driven by the first gate line GL1 and the second gate line GL2, respectively. The second horizontal line HL2 can be driven separately by the first gate line GL1 and the second gate line GL2. In other words, some sub-pixels in the second horizontal line HL2 can be controlled by the first gate line GL1, and the remaining sub-pixels in the second horizontal line HL2 can be controlled by the second gate line GL2.

[0094] The TFTs of the R subpixels 11, 12, 13, and 14 of the first horizontal line HL1 can be connected to the first gate line GL1 disposed between the first horizontal line HL1 and the second horizontal line HL2. The TFTs of the B subpixels 31, 32, 33, and 34 of the third horizontal line HL3 can be connected to the second gate line GL2 disposed between the second horizontal line HL2 and the third horizontal line HL3. The TFTs of the G subpixels 21 and 23 of the odd-numbered column lines CL1 and CL3 of the second horizontal line HL2 can be connected to the first gate line GL1, and the TFTs of the G subpixels 22 and 24 of the even-numbered column lines CL2 and CL4 of the second horizontal line HL2 can be connected to the second gate line GL2.

[0095] In the same manner, the fourth to sixth horizontal lines HL4, HL5, and HL6 can be connected to the third gate line GL3 and the fourth gate line GL4. In other words, each group of two gate lines can control three rows of sub-pixels of the corresponding group (for example, GL1 and GL2 for HL1, HL2, and HL3, and GL3 and GL4 for HL4, HL5, and HL6, etc.).

[0096] The data lines DL1 to DL6 may extend in the vertical direction Y to cross the gate lines GL1 to GL4 and may be arranged side by side in the horizontal direction X. Figure 1 ) of the output channel data pads DP1 to DP6 from the data driving circuit 300 ( Figure 1 ) provides data signals Data1 to Data6 separately for the data lines DL1 to DL6.

[0097] The first column line CL1 and the second column line CL2 can receive data signals Data1, Data2, and Data3 via the first to third data lines DL1, DL2, and DL3, and the third column line CL3 and the fourth column line CL4 can receive data signals Data4, Data5, and Data6 via the fourth to sixth data lines DL4, DL5, and DL6. For example, each group of three adjacent data lines can control two columns of sub-pixels in the corresponding group (e.g., DL1, DL2, and DL3 for CL1 and CL2, and DL4, DL5, and DL6 for CL3 and CL4, and so on).

[0098] The TFTs of the R subpixel 11, R subpixel 41, B subpixel 31, and B subpixel 61 of the first column line CL1 can be connected to the first data line DL1 disposed on the left side of the first column line CL1. The R subpixel 12, R subpixel 42, B subpixel 32, and B subpixel 62 of the second column line CL2 can be connected to the third data line DL3 disposed on the right side of the second column line CL2. The TFTs of the G subpixels 21, 51, 22, and 52 of the first column line CL1 and the second column line CL2 can be connected to the second data line DL2 disposed between the first column line CL1 and the second column line CL2.

[0099] In the same manner, the third column line CL3 and the fourth column line CL4 may be connected to the fourth to sixth data lines DL4 , DL5 , and DL6 .

[0100] One data line DL2 may be provided between the first column line CL1 and the second column line CL2, and two data lines DL3 and DL4 may be provided between the second column line CL2 and the third column line CL3. One data line DL5 may be provided between the third column line CL3 and the fourth column line CL4, and two data lines DL6 and DL7 may be provided between the fourth column line CL4 and the fifth column line CL5. One data line may be provided between column lines adjacent to each other in the horizontal direction X, or two data lines may be provided, and the arrangement structure of one data line and the arrangement structure of two data lines may be alternately repeated in the horizontal direction X.

[0101] The data lines DL1 to DL6 may include: first-category data lines DL1, DL3, DL4, and DL6 connected to the R and B subpixels of each column line CLn (where n=1, 2, 3, 4) to provide R and B data signals; and second-category data lines DL2 and DL5 connected to the G subpixel of each CLn (where n=1, 2, 3, 4) to provide G data signals. The second-category data lines DL2 and DL5 can prevent differences in the amount of charged data of the same color due to different types of data lines by providing data signals of the same color, thereby preventing brightness deviation of the same color. For example, each of the first-category data lines can be connected to a column of subpixels to provide data to red and blue subpixels, while each of the second-category data lines can be mixed or alternately connected between two adjacent column subpixels to provide data to the green subpixel, but embodiments are not limited thereto.

[0102] By driving the data driving circuit 300 ( Figure 1) column inversion method, the polarities of the data signals Data1, Data3 and Data5 of the odd data lines DL1, DL3 and DL5 and the polarities of the data signals Data2, Data4 and Data6 of the even data lines DL2, DL4 and DL6 can be opposite to each other and can be inverted for each frame, which can extend the service life of the device and improve image quality.

[0103] Figure 5 According to the embodiment of the present disclosure Figure 4 FIG. 1 is a diagram showing an example of an inversion driving method for an odd-numbered frame of a liquid crystal panel, Figure 6 According to the embodiment of the present disclosure Figure 4 FIG. 1 is a diagram showing an example of an inversion driving method for an even-numbered frame of a liquid crystal panel, Figure 7 According to the embodiment of the present disclosure Figure 5 An example of a driving waveform diagram for an odd frame of a liquid crystal panel is shown in FIG. Figure 8 According to the embodiment of the present disclosure Figure 6 An example of a driving waveform diagram for an even frame of a liquid crystal panel is shown in FIG.

[0104] Reference Figure 5 and Figure 7 In an odd frame (first frame), the gate driving circuit 200 ( Figure 1 ) outputted from the data driving circuit 300 ( ) the gate-on voltage VON of the first gate signal Gate1 to the fourth gate signal Gate4 sequentially drives the first gate line GL1 to the fourth gate line GL4, and the first gate line GL1 to the fourth gate line GL4 can receive the gate-off voltage VOFF. The first data line DL1 to the sixth data line DL6 can provide the gate-off voltage VON from the data driving circuit 300 ( Figure 1 During odd frames, the odd data lines DL1, DL3, and DL5 may provide positive data signals Data1, Data3, and Data5, and the even data lines DL2, DL4, and DL6 may provide negative data signals Data2, Data4, and Data6.

[0105] During the first horizontal period in which the gate-on voltage VON is supplied to the first gate line GL1 in an odd frame, the R subpixels 11, 12, 13, and 14 of the first horizontal line HL1 may respectively charge the R+, R+, R-, and R- data signals supplied through the first data line DL1, the third data line DL3, the fourth data line DL4, and the sixth data line DL6, and the first G subpixel 21 and the third G subpixel 23 of the second horizontal line HL2 may respectively charge the G- and G+ data signals supplied through the second data line DL2 and the fifth data line DL5.

[0106] During the second horizontal period in which the gate-on voltage VON is provided to the second gate line GL2, the B sub-pixels 31, 32, 33 and 34 of the third horizontal line HL3 can respectively charge the B+, B+, B- and B- data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, and the second G sub-pixel 22 and the fourth G sub-pixel 24 of the second horizontal line HL2 can respectively charge the G- and G+ data signals provided through the second data line DL2 and the fifth data line DL5.

[0107] During the third horizontal period in which the gate-on voltage VON is provided to the third gate line GL3, the R sub-pixels 41, 42, 43 and 44 of the fourth horizontal line HL4 can be respectively charged with the R+, R+, R- and R- data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, and the first G sub-pixel 51 and the third G sub-pixel 53 of the fifth horizontal line HL5 can be respectively charged with the G- and G+ data signals provided through the second data line DL2 and the fifth data line DL5.

[0108] During the fourth horizontal period in which the gate-on voltage VON is supplied to the fourth gate line GL4, the B subpixels 61, 62, 63, and 64 of the sixth horizontal line HL6 may be charged with the B+, B+, B-, and B- data signals supplied through the first data line DL1, the third data line DL3, the fourth data line DL4, and the sixth data line DL6, respectively, and the second G subpixel 52 and the fourth G subpixel 54 of the fifth horizontal line HL5 may be charged with the G- and G+ data signals supplied through the second data line DL2 and the fifth data line DL5, respectively. For example, for each adjacent pair of subpixel columns, the green subpixel may be controlled with a different polarity than the red and blue subpixels, and the polarity scheme may be different or alternating for two adjacent columns in each group, but embodiments are not limited thereto.

[0109] Reference Figure 6 and Figure 8 In the even frame (second frame), the liquid crystal panel can charge a data signal with a polarity opposite to that of the data signal of the odd frame. During the even frame, the odd data lines DL1, DL3, and DL5 can provide negative data signals Data1, Data3, and Data5, and the even data lines DL2, DL4, and DL6 can provide positive data signals Data2, Data4, and Data6. For example, in the odd frame, the six data lines can be controlled with alternating positive and negative data signals, and then in the even frame, the polarity can be switched, and the six data lines can be controlled with alternating positive and negative data signals.

[0110] During the first horizontal period of driving the first gate line GL1 in an even frame, the R sub-pixels 11, 12, 13 and 14 of the first horizontal line HL1 can be charged with the R-, R-, R+ and R+ data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, respectively, and the first G sub-pixel 21 and the third G sub-pixel 23 of the second horizontal line HL2 can be charged with the G+ and G- data signals provided through the second data line DL2 and the fifth data line DL5, respectively.

[0111] During the second horizontal period of driving the second gate line GL2 in the even frame, the B sub-pixels 31, 32, 33 and 34 of the third horizontal line HL3 can be charged with the B-, B-, B+ and B+ data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, respectively, and the second G sub-pixel 22 and the fourth G sub-pixel 24 of the second horizontal line HL2 can be charged with the G+ and G- data signals provided through the second data line DL2 and the fifth data line DL5, respectively.

[0112] During the third horizontal period of driving the third gate line GL3 in the even frame, the R sub-pixels 41, 42, 43 and 44 of the fourth horizontal line HL4 can be charged with the R-, R-, R+ and R+ data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, respectively, and the first G sub-pixel 51 and the third G sub-pixel 53 of the fifth horizontal line HL5 can be charged with the G+ and G- data signals provided through the second data line DL2 and the fifth data line DL5, respectively.

[0113] During the fourth horizontal period of driving the fourth gate line GL4 in the even frame, the B sub-pixels 61, 62, 63 and 64 of the sixth horizontal line HL6 can be charged with the B-, B-, B+ and B+ data signals provided through the first data line DL1, the third data line DL3, the fourth data line DL4 and the sixth data line DL6, respectively, and the second G sub-pixel 52 and the fourth G sub-pixel 54 of the fifth horizontal line HL5 can be charged with the G+ and G- data signals provided through the second data line DL2 and the fifth data line DL5, respectively.

[0114] Figures 4 to 6 The liquid crystal panel shown in FIG. 1 can be driven by a one-dot two-dot hybrid inversion method in which one-dot inversion drive in the horizontal direction X, one-dot inversion drive in the vertical direction Y, and two-dot inversion drive are mixed.

[0115] Figure 9 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to another embodiment of the present disclosure.

[0116] and Figure 4 Compared with the LCD panel shown in Figure 9 The liquid crystal panel shown in FIG has a different structure in which two data lines are arranged between adjacent column lines. For example, Figure 9 The liquid crystal panel shown in FIG has four gate lines GL1a, GL2a, GL3a, and GL4a and eight data lines DL1a, DL21a, DL31a, DL4a, DL5a, DL22a, DL32a, and DL6a, wherein the eight data lines are supplied with data from six sources, for example, six data pads DP1a, DP2a, DP3a, DP4a, DP5a, and DP6a. In other words, the data lines DL21a and DL22a branch from the same data pad DP2a, and the data lines DL31a and DL32a branch from the same data pad DP3a.

[0117] Reference Figure 9 In the liquid crystal panel according to the embodiment, the first to sixth horizontal lines HL1a to HL6a and the first to fourth column lines CL1a to CL4a can be driven by using the first to fourth gate lines GL1a to GL4a and the first to sixth data lines DL1a to DL6a. For example, Figure 9 The LCD panel shown in Figure 4 The configuration in is similar, except that instead of setting one data line between the green sub-pixels of two adjacent columns, two data lines can be set between the green sub-pixels of two adjacent columns.

[0118] The first to third horizontal lines HL1a, HL2a, and HL3a can be driven in a double-rate driving manner through the first gate line GL1a, the second gate line GL2a, and the fourth to sixth horizontal lines HL4a, HL5a, and HL6a can be driven in a double-rate driving manner through the third gate line GL3a and the fourth gate line GL4a. Therefore, the display device according to the embodiment can reduce the number of gate lines to less than the number of horizontal lines.

[0119] The gate lines GL1a to GL4a can receive signals from the gate driving circuit 200 ( Figure 1 ) are driven sequentially by gate signals Gate1a to Gate4a.

[0120] The TFTs a of the Ra sub-pixels 11 a, 12 a, 13 a, and 14 a of the first horizontal line HL1 a can be connected to a first gate line GL1 a disposed between the first horizontal line HL1 a and the second horizontal line HL2 a. The TFTs a of the Ba sub-pixels 31 a, 32 a, 33 a, and 34 a of the third horizontal line HL3 a can be connected to a second gate line GL2 a disposed between the second horizontal line HL2 a and the third horizontal line HL3 a. The TFTs a of the first Ga sub-pixel 21 a and the second Ga sub-pixel 22 a of the first horizontal line HL1 a can be connected to the first gate line GL1 a, and the TFTs a of the third Ga sub-pixel 23 a and the fourth Ga sub-pixel 24 a of the first horizontal line HL1 a can be connected to the second gate line GL2 a.

[0121] In the same manner, the fourth to sixth horizontal lines HL4a, HL5a, and HL6a may be connected to the third and fourth gate lines GL3a and GL4a.

[0122] The data lines DL1a to DL6a can be connected to the data driving circuit 300 ( Figure 1 ) data pads DP1a to DP6a individually receive data signals Data1a to Data6a.

[0123] The (2-1)th data line DL21a and the (3-1)th data line DL31a can be arranged in parallel between the first column line CL1a and the second column line CL2a. The fourth data line DL4a and the fifth data line DL5a can be arranged in parallel between the second column line CL2a and the third column line CL3a. The (2-2)th data line DL22a and the (3-2)th data line DL32a can be arranged in parallel between the third column line CL3a and the fourth column line CL4a. The (2-2)th data line DL22a can be connected to the (2-1)th data line DL21a in the link region and can be connected to the second data pad DP2a. The (3-2)th data line DL32a can be connected to the (3-1)th data line DL31a in the link region and can be connected to the third data pad DP3a. For example, the data lines DL2a and DL2b branch from the same data pad DP2, and the data lines DL3a and DL3b branch from the same data pad DP3.

[0124] The first column line CL1a can receive data signals Data1a and Data2a via the first data line DL1a and the (2-1)th data line DL21a, which are located on the left and right sides of the first column line CL1a. The Ra sub-pixel 11a, Ra sub-pixel 41a, Ba sub-pixel 31a, and Ba sub-pixel 61a of the first column line CL1a can be connected to the first data line DL1a on the left side via TFTa to receive the data signal Data1a. The Ga sub-pixels 21a and 51a of the first column line CL1a can be connected to the (2-1)th data line DL21a on the right side via TFTa to receive the data signal Data2a.

[0125] The second column line CL2a can receive data signals Data3a and Data4a via the (3-1)th data line DL31a and the fourth data line DL4a, which are arranged on the left and right sides of the second column line CL2a. The Ga sub-pixels 22a and 52a of the second column line CL2a can be connected to the (3-1)th data line DL31a on the left side via TFTa to receive the data signal Data3a. The Ra sub-pixels 12a, Ra sub-pixel 42a, Ba sub-pixel 32a, and Ba sub-pixel 62a of the second column line CL2a can be connected to the fourth data line DL4a on the right side via TFTa to receive the data signal Data4a.

[0126] The third column line CL3a can receive data signals Data5a and Data2a via the fifth data line DL5a and the (2-2)th data line DL2a, which are arranged on the left and right sides of the third column line CL3a. The Ra sub-pixel 13a, Ra sub-pixel 43a, and Ba sub-pixel 33a, Ba sub-pixel 63a of the third column line CL3a can be connected to the fifth data line DL5a on the left side via TFTa to receive the data signal Data5a. The Ga sub-pixels 23a and 53a of the third column line CL3a can be connected to the (2-2)th data line DL22a on the right side via TFTa to receive the data signal Data2a.

[0127] The fourth column line CL4a can receive data signals Data3a and Data6a via the (3-2)th data line DL32a and the sixth data line DL6a, which are arranged on the left and right sides of the fourth column line CL4a. The Ga sub-pixels 24a and 54a of the fourth column line CL4a can be connected to the (3-2)th data line DL32a on the left side via TFTa to receive the data signal Data3a. The Ra sub-pixel 14a, Ra sub-pixel 44a, Ba sub-pixel 34a, and Ba sub-pixel 64a of the fourth column line CL4a can be connected to the sixth data line DL6a on the right side via TFTa to receive the data signal Data6a.

[0128] The data lines DL1 a to DL6 a may include first-category data lines DL1 a , DL4 a , DL5 a , and DL6 a , and second-category data lines DL21 a , DL22 a , DL31 a , and DL32 a .

[0129] The first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a, and the first-class sixth data line DL6a can be connected to the Ra and Ba sub-pixels (first color sub-pixels and second color sub-pixels) of each column line CLn (where n=1, 2, 3, 4) to provide Ra data signals and Ba data signals Data1a, Data4a, Data5a, and Data6a. The first-class first data line DL1a and the first-class fifth data line DL5a are respectively arranged on the left side of the odd-numbered column lines CL1a and CL3a, and can be connected to the Ra sub-pixel and Ba sub-pixel (first color sub-pixel and third color sub-pixel) through TFTa. The first-class fourth data line DL4a and the first-class sixth data line DL6a are respectively arranged on the right side of the even-numbered column lines CL2a and CL4a, and can be connected to the Ra sub-pixel and Ba sub-pixel (first color sub-pixel and second color sub-pixel) through TFTa.

[0130] Each of the second-class data lines DL21a, DL22a, DL31a, and DL32a is connected to the Ga subpixel (second color subpixel) of each column line CLn (where n=1, 2, 3, 4) to provide Ga data signals Data2a and Data3a. The second-class data lines DL21a, DL22a, DL31a, and DL32a can improve image quality by providing data signals of the same color, thereby preventing brightness deviation caused by different charge amounts of the same color. The second-class (2-1) data line DL21a and the second-class (2-2) data line DL22a are respectively arranged on the right side of the odd-numbered column lines CL1 and CL3, and can be connected to the Ga subpixel (second color subpixel) through TFTa. The second-class (3-1) data line DL31a and the second-class (3-2) data line DL32a are respectively arranged on the left side of the even-numbered column lines CL2 and CL4, and can be connected to the Ga subpixel (first color subpixel and second color subpixel) through TFTa. The TFTa of the Ga sub-pixel (second color sub-pixel) connecting the second-class (2-1) data line DL21a and the second-class (3-1) data line DL31a with the first column line CL1a and the second column line CL2a can be driven by the odd-numbered gate lines GL1a and GL3a. The TFTa of the Ga sub-pixel (second color sub-pixel) connecting the second-class (2-2) data line DL22a and the second-class (3-2) data line DL32a with the third column line CL3a and the fourth column line CL4a can be driven by the even-numbered gate lines GL2a and GL3a.

[0131] By driving the data driving circuit 300 ( Figure 1 ) column inversion method, the polarities of the data signals Data1a, Data3a and Data5a of the odd data lines DL1a, DL31a, DL32a and DL5a and the polarities of the data signals Data2a, Data4a and Data6a of the even data lines DL21a, DL22a, DL4a and DL6a can be opposite to each other and can be inverted for each frame.

[0132] Figure 10 yes Figure 9 FIG. 1 is a diagram showing an example of an inversion driving method for an odd-numbered frame of a liquid crystal panel, Figure 11 yes Figure 9 Schematic diagram of an example of an inversion driving method for an even-numbered frame of a liquid crystal panel, Figure 12 yes Figure 10 An example of a driving waveform diagram for an odd-numbered frame of a liquid crystal panel is shown in FIG. Figure 13 yes Figure 11 An example of a driving waveform diagram for an even frame of a liquid crystal panel is shown in FIG.

[0133] Reference Figure 10 and Figure 12 In an odd frame (first frame), for each horizontal period 1H, the first to fourth gate lines GL1a to GL4a may be driven by the gate driving circuit 200 ( Figure 1 ) outputted from the first gate signal Gate1a to the fourth gate signal Gate4a of the gate turn-on voltage VON sequentially drive. The first data line DL1a to the sixth data line DL6a can provide from the data driving circuit 300 ( Figure 1 ) output first to sixth data signals Data1a to Data6a. During odd frames, the odd data lines, i.e., the (3-1)th data line DL1a, the (3-2)th data line DL31a, and the fifth data line DL5a, may provide negative (-) data signals Data1a, Data3a, and Data5a, and the even data lines, i.e., the (2-1)th data line DL21a, the (2-2)th data line DL22a, the fourth data line DL4a, and the sixth data line DL6a, may provide positive (+) data signals Data2a, Data4a, and Data6a.

[0134] In an odd frame, during the first horizontal period in which the first gate line GL1a is driven by the gate-on voltage VON, the Ra sub-pixels 11a, 12a, 13a and 14a of the first horizontal line HL1a can respectively charge the Ra-data signal Data1a, Ra+data signal Data4a, Ra-data signal Data5a and Ra+data signal Data6a provided through the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the first Ga sub-pixel 21a and the second Ga sub-pixel 22a of the second horizontal line HL2a can respectively charge the Ga+data signal Data2a and the Ga-data signal Data3a provided through the second-class (2-1) data line DL21a and the second-class (3-1) data line DL31a.

[0135] In the odd frame, during the second horizontal period in which the second gate line GL2a is driven by the gate-on voltage VON, the Ba sub-pixels 31a, 32a, 33a and 34a of the third horizontal line HL3a can respectively charge the Ba-data signal Data1a, Ba+data signal Data4a, Ba-data signal Data5a and Ba+data signal Data6a provided through the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the third Ga sub-pixel 23a and the fourth Ga sub-pixel 24a of the second horizontal line HL2a can respectively charge the Ga+data signal Data2a and the Ga-data signal Data3a provided through the second-class (2-2) data line DL22a and the second-class (3-2) data line DL32a.

[0136] In the odd frame, during the third horizontal period in which the third gate line GL3a is driven by the gate-on voltage VON, the Ra sub-pixels 41a, 42a, 43a and 44a of the fourth horizontal line HL4a can respectively charge the Ra-data signal Data1a, Ra+data signal Data4a, Ra-data signal Data5a and Ra+data signal Data6a provided by the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the first Ga sub-pixel 51a and the second Ga sub-pixel 52a of the fifth horizontal line HL5a can respectively charge the Ga+data signal Data2a and the Ga-data signal Data3a provided by the second-class (2-1) data line DL21a and the second-class (3-1) data line DL31a.

[0137] In the odd frame, during the fourth horizontal period in which the fourth gate line GL4a is driven by the gate-on voltage VON, the Ba sub-pixels 61a, 62a, 63a and 64a of the sixth horizontal line HL6a can respectively charge the Ba-data signal Data1a, Ba+data signal Data4a, Ba-data signal Data5a and Ba+data signal Data6a provided through the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the third Ga sub-pixel 53a and the fourth Ga sub-pixel 54a of the fifth horizontal line HL5a can respectively charge the Ga+data signal Data2a and the Ga-data signal Data3a provided through the second-class (2-2) data line DL22a and the second-class (3-2) data line DL32a.

[0138] Reference Figure 11 and Figure 13 In the even frame (the second frame), the liquid crystal panel can charge the data signal with a polarity opposite to that of the odd frame. During the even frame, the odd data lines, i.e., the (3-1)th data line, the (3-2)th data line, and the fifth data line DL1a, DL31a, DL32a, DL5a, can provide positive (+) data signals Data1a, Data3a, and Data5a, and the even data lines, i.e., the (2-1)th data line DL21a, the (2-2)th data line DL22a, the fourth data line DL4a, and the sixth data line DL6a, can provide negative data signals Data2a, Data4a, and Data6a.

[0139] In an even frame, during the first horizontal period in which the first gate line GL1a is driven by the gate-on voltage VON, the Ra sub-pixels 11a, 12a, 13a and 14a of the first horizontal line HL1a can respectively charge the Ra+ data signal Data1a, Ra- data signal Data4a, Ra+ data signal Data5a and Ra- data signal Data6a provided through the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the first Ga sub-pixel 21a and the second Ga sub-pixel 22a of the second horizontal line HL2 can respectively charge the Ga- data signal Data2a and the Ga+ data signal Data3a provided through the second-class (2-1) data line DL21a and the (3-1) data line DL31a.

[0140] In the even frame, during the second horizontal period in which the second gate line GL2a is driven by the gate-on voltage VON, the Ba sub-pixels 31a, 32a, 33a and 34a of the third horizontal line HL3a can respectively charge the Ba+ data signal Data1a, Ba- data signal Data4a, Ba+ data signal Data5a and Ba- data signal Data6a provided through the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the third Ga sub-pixel 23a and the fourth Ga sub-pixel 24a of the second horizontal line HL2a can respectively charge the Ga- data signal Data2a and the Ga+ data signal Data3a provided through the second-class (2-2) data line DL22a and the second-class (3-2) data line DL32a.

[0141] In the even frame, during the third horizontal period in which the third gate line GL3a is driven by the gate-on voltage VON, the Ra sub-pixels 41a, 42a, 43a and 44a of the fourth horizontal line HL4a can be respectively charged with the Ra+ data signal Data1a, Ra- data signal Data4a, Ra+ data signal Data5a and Ra- data signal Data6a provided by the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the first Ga sub-pixel 51a and the second Ga sub-pixel 52a of the fifth horizontal line HL5a can be respectively charged with the Ga+ data signal Data2a and the Ga- data signal Data3a provided from the second-class (2-1) data line DL21a and the second-class (3-1) data line DL31a.

[0142] In the even frame, during the fourth horizontal period in which the fourth gate line GL4a is driven by the gate-on voltage VON, the Ba sub-pixels 61a, 62a, 63a and 64a of the sixth horizontal line HL6a can respectively charge the Ba-data signal Data1a, Ba+data signal Data4a, Ba-data signal Data5a and Ba+data signal Data6a provided by the first-class first data line DL1a, the first-class fourth data line DL4a, the first-class fifth data line DL5a and the first-class sixth data line DL6a, and the third Ga sub-pixel 53a and the fourth Ga sub-pixel 54a of the fifth horizontal line HL5a can respectively charge the Ga+data signal Data2a and the Ga-data signal Data3a provided by the second-class (2-2) data line DL22a and the second-class (3-2) data line DL32a.

[0143] Figures 9 to 11The liquid crystal panel shown in FIG. 1 can be driven by a one-dot two-dot hybrid inversion method in which one-dot inversion drive in the horizontal direction X, one-dot inversion drive in the vertical direction Y, and two-dot inversion drive are mixed.

[0144] Figure 14 is a diagram illustrating an example of a pixel arrangement structure of a liquid crystal panel according to an embodiment of the present disclosure.

[0145] and Figure 9 Compared with the LCD panel shown in Figure 14 The liquid crystal panel shown in FIG has a structure in which first-type data lines and second-type data lines are uniformly arranged between adjacent column lines.

[0146] Reference Figure 14 In the liquid crystal panel according to the embodiment, the first to sixth horizontal lines HL1b to HL6b and the first to fourth column lines CL1b to CL4b may be driven by using the first to fourth gate lines GL1b to GL4b and the first to sixth data lines DL1b to DL6b.

[0147] The first to third horizontal lines HL1b, HL2b, and HL3b can be driven at a double rate by the first gate line GL1b and the second gate line GL2b, and the fourth to sixth horizontal lines HL4b, HL5b, and HL6b can be driven at a double rate by the third gate line GL3b and the fourth gate line GL4b. Therefore, the display device according to the embodiment can reduce the number of gate lines compared to the number of horizontal lines.

[0148] By Figure 1 ) separately receives gate signals Gbte1b to Gbte4b to sequentially drive the gate lines GL1b to GL4b.

[0149] The TFTb of the Rb sub-pixels 11b, 12b, 13b, and 14b of the first horizontal line HL1b can be connected to the first gate line GL1b disposed between the first horizontal line HL1b and the second horizontal line HL2b. The TFTb of the Bb sub-pixels 31b, 32b, 33b, and 34b of the third horizontal line HL3b can be connected to the second gate line GL2b disposed between the second horizontal line HL2b and the third horizontal line HL3b. The TFTb of the first Gb sub-pixel 21b and the second Gb sub-pixel 22b of the first horizontal line HL1 can be connected to the first gate line GL1b, and the TFTb of the third Gb sub-pixel 23b and the fourth Gb sub-pixel 24b of the first horizontal line HL1b can be connected to the second gate line GL2b.

[0150] In the same manner, the fourth to sixth horizontal lines HL4b, HL5b, and HL6b may be connected to the third and fourth gate lines GL3b and GL4b.

[0151] The data lines DL1b to DL6b can be connected to the data driving circuit 300 ( Figure 1 ) data pads DP1b to DP6b individually receive data signals Dbtb1b to Dbtb6b.

[0152] The (2-1)th data line DL21b and the third data line DL3b can be arranged in parallel between the first column line CL1b and the second column line CL2b. The (4-1)th data line DL41b and the fifth data line DL5b can be arranged in parallel between the second column line CL2b and the third column line CL3b. The (2-2)th data line DL22b and the sixth data line DL6b can be arranged in parallel between the third column line CL3b and the fourth column line CL4b. The (2-2)th data line DL22b can be connected to the (2-1)th data line DL21b in the link area and can be connected to the second data pad DP2b. The (4-2)th data line DL42b can be connected to the (4-1)th data line DL41b in the link area and can be connected to the fourth data pad DP4b.

[0153] The first column line CL1b can receive data signals Data1b and Data2b via the first data line DL1b and the (2-1)th data line DL21b, which are located on the left and right sides of the first column line CL1b. The Rb sub-pixels 11b and 41b and the Bb sub-pixels 31b and 61b of the first column line CL1b can be connected to the first data line DL1b on the left side via TFTb to receive the data signal Data1b. The Gb sub-pixels 21b and 51b of the first column line CL1b can be connected to the (2-1)th data line DL21b on the right side via TFTb to receive the data signal Data2b.

[0154] The second column line CL2b can receive data signals Data3b and Data4b via the third data line DL3b and the (4-1)th data line DL41b, which are arranged on the left and right sides of the second column line CL2b. The Rb sub-pixels 12b, 42b and the Bb sub-pixels 32b, 62b of the second column line CL2b can be connected to the third data line DL3b on the left side via TFTb to receive the data signal Data3b. The Gb sub-pixels 22b and 52b of the second column line CL2b can be connected to the (4-1)th data line DL41b on the right side via TFTb to receive the data signal Data4b.

[0155] The third column line CL3b can receive data signals Data5b and Data2b via the fifth data line DL5b and the (2-2)th data line DL22b, which are arranged on the left and right sides of the third column line CL3b. The Rb sub-pixels 13b, 43b and the Bb sub-pixels 33b, 63b of the third column line CL3b can be connected to the fifth data line DL5b on the left side via TFTb to receive the data signal Data5b. The Gb sub-pixels 23b and 53b of the third column line CL3b can be connected to the (2-2)th data line DL22b on the right side via TFTb to receive the data signal Data2b.

[0156] The fourth column line CL4b can receive data signals Data6b and Data4b via the sixth data line DL6b and the (4-2)th data line DL42b, which are arranged on the left and right sides of the fourth column line CL4b. The Rb sub-pixels 14b and 44b and the Bb sub-pixels 34b and 64b of the fourth column line CL4b can be connected to the sixth data line DL6b on the left side via TFTb to receive the data signal Data6b. The Gb sub-pixels 24b and 54b of the fourth column line CL4b can be connected to the (4-2)th data line DL42b on the right side via TFTb to receive the data signal Data4b.

[0157] The data lines DL1b to DL6b may include first-category data lines DL1b, DL3b, DL5b, and DL6b and second-category data lines DL21b, DL41b, DL22b, and DL42b.

[0158] Each of the first-type data lines DL1b, DL3b, DL5b and DL6b can be set on the left side of each column line CLn (n=1, 2, 3, 4) and can be connected to the Rb sub-pixel and the Bb sub-pixel (first color sub-pixel and second color sub-pixel) through TFTb to provide Rb data signals and Bb data signals Data1b, Data3b, Data5b and Data6b.

[0159] Each of the second-category data lines DL21b, DL41b, DL22b, and DL42b is positioned to the right of each column line CLn (n=1, 2, 3, 4) and is connected to the Gb subpixel (second color subpixel) via a TFTb to provide Gb data signals Data2b and Data4b. The second-category data lines DL21b, DL41b, DL22b, and DL42b can improve image quality by providing data signals of the same color, thereby preventing brightness deviation caused by differences in the amount of charge of the same color. The TFTb connecting the second-category (2-1) data line DL21b and the (4-1) data line DL41b to the Gb subpixels (second color subpixels) of the first column line CL1b and the second column line CL2b can be driven by the odd-numbered gate lines GL1b and GL3b. TFTb connecting the second-type (2-2)th and (4-2)th data lines DL22b and DL42b with the Gb subpixels (second color subpixels) of the third and fourth column lines CL3b and CL4b may be driven by the even-numbered gate lines GL2b and GL3b.

[0160] By driving the column inversion method of the data driving circuit 300 (see Figure 1 ), the polarities of the data signals Data1b, Data4b, and Data5b of the first data line DL1b, the fourth data line DL41b, DL42b, and the fifth data line DL5b and the polarities of the data signals Data2b, Data3b, and Data6b of the second data line DL21b, DL22b, the third data line DL3b, and the sixth data line DL6b may be opposite to each other and may be inverted for each frame.

[0161] Figure 15 It's about Figure 14 FIG shows an example of an inversion driving method for an odd-numbered frame of a liquid crystal panel, Figure 16 It's about Figure 14 FIG shows an example of an inversion driving method for an even-numbered frame of a liquid crystal panel, Figure 17 It's about Figure 15 FIG shows an example of an inversion driving method for an odd-numbered frame of a liquid crystal panel, and Figure 18 It's about Figure 16 An example of a driving waveform diagram of an even-numbered frame of a liquid crystal panel is shown in FIG.

[0162] Reference Figure 15 and Figure 17 , in the odd frame (first frame), the gate drive circuit 200 ( Figure 1) outputted from the first gate signal Gbte1b to the fourth gate signal Gbte4b, the gate-on voltage VON sequentially drives the first gate line GL1b to the fourth gate line GL4b in units of a horizontal period of 1H. The first data line DL1b to the sixth data line DL6b can provide the gate-on voltage VON outputted from the data driving circuit 300 ( Figure 1 ) output first to sixth data signals Data1b to Data6b. During odd frames, the first data line DL1b, the (4-1)th data line DL41b, the (4-2)th data line DL42b, and the fifth data line DL5b may provide negative (-) data signals Data1b, Data3b, and Data5b, and the (2-1)th data line DL21b, the (2-2)th data line DL22b, the third data line DL3b, and the sixth data line DL6b may provide positive (+) data signals Data2b, Data4b, and Data6b.

[0163] In an odd frame, during a first horizontal period in which the first gate line GL1b is driven by the gate-on voltage VON, the Rb sub-pixels 11b, 12b, 13b, and 14b of the first horizontal line HL1b can respectively charge the Rb-data signal Data1b, the Rb+data signal Data4b, the Rb-data signal Data5b, and the Rb-data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b, and the first-class sixth data line DL6b, and the first Gb sub-pixel 21b and the second Gb sub-pixel 22b of the second horizontal line HL2b can respectively charge the Gb+data signal Data2b and the Gb-data signal Data4b provided through the second-class (2-1)th data line DL21b and the second-class (4-1)th data line DL41b.

[0164] In the odd frame, during the second horizontal period in which the second gate line GL2b is driven by the gate-on voltage VON, the Bb sub-pixels 31b, 32b, 33b and 34b of the third horizontal line HL3b can respectively charge the Bb-data signal Data1b, Bb+data signal Data3b, Bb-data signal Data5b and Bb-data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b and the first-class sixth data line DL6b, and the third Gb sub-pixel 23b and the fourth Gb sub-pixel 24b of the second horizontal line HL2b can respectively charge the Gb+data signal Data2b and the Gb-data signal Data4b provided through the second-class (2-2) data line DL22b and the second-class (4-2) data line DL42b.

[0165] In the odd frame, during the third horizontal period in which the third gate line GL3b is driven by the gate-on voltage VON, the Rb sub-pixels 41b, 42b, 43b and 44b of the fourth horizontal line HL4b can respectively charge the Rb-data signal Data1b, Rb+data signal Data3b, Rb-data signal Data5b and Rb+data signal Data6b provided through the first data line DL1b, the third data line DL3b, the fifth data line DL5b and the sixth data line DL6b, and the first Gb sub-pixel 51b and the second Gb sub-pixel 52b of the fifth horizontal line HL5b can respectively charge the Gb+data signal Data2b and the Gb-data signal Data4b provided through the second-class (2-1)th data line DL21b and the second-class (4-1)th data line DL41b.

[0166] In the odd frame, during the fourth horizontal period in which the fourth gate line GL4b is driven by the gate-on voltage VON, the Bb sub-pixels 61b, 62b, 63b and 64b of the sixth horizontal line HL6b can respectively charge the Bb-data signal Data1b, Bb+data signal Data3b, Bb-data signal Data5b and Bb+data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b and the first-class sixth data line DL6b, and the Gb-third sub-pixel 53b and the fourth Gb sub-pixel 54b of the fifth horizontal line HL5b can respectively charge the Gb+data signal Data2b and the Gb-data signal Data4b provided through the second-class (2-2)th data line DL22b and the second-class (4-2)th data line DL42b.

[0167] Reference Figure 16 and Figure 18 In the even frame (second frame), the liquid crystal panel can charge the data signal with a polarity opposite to that of the odd frame. During the even frame, the first data line DL1b, the (4-1)th data line DL41b, the (4-2)th data line DL42b, and the fifth data line DL5b can provide positive (+) data signals Data1b, Data4b, and Data5b, and the (2-1)th data line DL21b, the (2-2)th data line DL22b, the third data line DL3b, and the sixth data line DL6b can provide negative (-) data signals Data2b, Data3b, and Data6b.

[0168] In an even frame, during the first horizontal period in which the first gate line GL1b is driven by the gate-on voltage VON, the Rb sub-pixels 11b, 12b, 13b, and 14b of the first horizontal line HL1b can respectively charge the Rb+ data signal Data1b, the Rb- data signal Data3b, the Rb+ data signal Data5b, and the Rb- data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b, and the first-class sixth data line DL6b, and the first Gb sub-pixel 21b and the second Gb sub-pixel 22b of the second horizontal line HL2b can respectively charge the Gb- data signal Data2b and the Gb+ data signal Data4b provided through the second-class (2-1)th data line DL21b and the second-class (4-1)th data line DL41b.

[0169] In an even frame, during the second horizontal period in which the second gate line GL2b is driven by the gate-on voltage VON, the Bb sub-pixels 31b, 32b, 33b and 34b of the third horizontal line HL3b can respectively charge the Bb+ data signal Data1b, Bb- data signal Data3b, Bb+ data signal Data5b and Bb- data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b and the first-class sixth data line DL6b, and the third Gb sub-pixel 23b and the fourth Gb sub-pixel 24b of the second horizontal line HL2b can respectively charge the Gb- data signal Data2b and the Gb+ data signal Data4b provided through the second-class (2-2) data line DL22b and the second-class (4-2) data line DL42b.

[0170] In an even frame, during the third horizontal period in which the third gate line GL3b is driven by the gate-on voltage VON, the Rb sub-pixels 41b, 42b, 43b and 44b of the fourth horizontal line HL4b can respectively charge the Rb+ data signal Data1b, Rb- data signal Data3b, Rb+ data signal Data5b and Rb- data signal Data6b provided through the first data line DL1b, the third data line DL3b, the fifth data line DL5b and the sixth data line DL6b, and the first Gb sub-pixel 51b and the second Gb sub-pixel 52b of the fifth horizontal line HL5b can respectively charge the Gb- data signal Data2b and the Gb+ data signal Data4b provided through the second-class (2-1)th data line DL21b and the second-class (4-1)th data line DL41b.

[0171] In an even frame, during the fourth horizontal period in which the fourth gate line GL4b is driven by the gate-on voltage VON, the Bb sub-pixels 61b, 62b, 63b and 64b of the sixth horizontal line HL6b can respectively charge the Bb+ data signal Data1b, Bb- data signal Data3b, Bb+ data signal Data5b and Bb- data signal Data6b provided through the first-class first data line DL1b, the first-class third data line DL3b, the first-class fifth data line DL5b and the first-class sixth data line DL6b, and the third Gb sub-pixel 53b and the fourth Gb sub-pixel 54b of the fifth horizontal line HL5b can respectively charge the Gb- data signal Data2b and the Gb+ data signal Data4b provided through the second-class (2-2) data line DL22b and the second-class (4-2) data line DL42b.

[0172] Figures 14 to 16 The liquid crystal panel shown in can be driven in a one-dot two-dot hybrid inversion method in which one-dot inversion drive in the horizontal direction X, one-dot inversion drive in the vertical direction Y, and two-dot inversion drive are mixed.

[0173] Therefore, the present disclosure may have the following advantages.

[0174] According to an embodiment of the present disclosure, each sub-pixel has a long side in the horizontal direction and a short side in the vertical direction, and the common electrode does not overlap with the data line, thereby reducing the load of the data line to achieve a low power consumption effect, and reducing the ripple effect of the common voltage to prevent image quality defects.

[0175] According to an embodiment of the present disclosure, by using a double-rate driving method of three horizontal lines and two gate lines (for example, 2 gate lines for controlling 3 rows of sub-pixels), the manufacturing cost can be reduced by reducing the number of gate lines compared to the number of horizontal lines, thereby achieving the effect of reducing production energy consumption and reducing greenhouse gases.

[0176] According to an embodiment of the present disclosure, a display device according to an embodiment may include first-type data lines alternately providing dual-color data signals and second-type data lines providing same-color data signals, and the second-type data lines provide the same-color data signals to prevent same-color brightness deviation.

[0177] According to an embodiment of the present disclosure, a display device according to an embodiment can achieve low power consumption by providing data signals to multiple data lines in a column inversion method, and can improve image quality without generating flicker by mixing liquid crystal panels in a 1-dot 2-dot inversion method.

[0178] According to an embodiment of the present disclosure, a display device according to some embodiments can improve image quality by compensating for the brightness sensitivity difference caused by the current sensitivity difference between R / G / B sub-pixels, thereby improving low-grayscale stains or low-grayscale image defects, and can further provide improved image quality even under low power consumption by improving low-grayscale stains or defects.

[0179] The display device according to one or more embodiments of the present disclosure can be applied to various electronic devices. For example, the display device according to the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic diaries, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigators, vehicle navigators, vehicle display devices, televisions, wallpaper display devices, signage devices, gaming devices, notebook computers, monitors, cameras, video cameras, and household appliances.

[0180] The above-mentioned features, structures and effects of the present disclosure are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. In addition, those skilled in the art can realize the features, structures and effects described in at least one embodiment of the present disclosure through the combination or modification of other embodiments. Therefore, the content associated with the combination and modification should be interpreted as being within the scope of the present disclosure.

[0181] It will be apparent to those skilled in the art that various substitutions, modifications, and variations may be made within the scope of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is indicated by the appended claims, and all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as included within the scope of the present disclosure.

Claims

1. A display device, comprising: A first horizontal line includes first color sub-pixels arranged in a horizontal direction; a second horizontal line comprising second color sub-pixels arranged along the horizontal direction; a third horizontal line comprising third color sub-pixels arranged along the horizontal direction; a first gate line disposed between the first horizontal line and the second horizontal line and connected to the first color sub-pixels in the first horizontal line and to some of the second color sub-pixels in the second horizontal line; a second gate line disposed between the second horizontal line and the third horizontal line, connected to the third horizontal line, and connected to the remaining sub-pixels of the second color sub-pixels in the second horizontal line; The first column line, the second column line, the third column line and the fourth column line each include first color sub-pixels to third color sub-pixels arranged alternately in the vertical direction from the first horizontal line to the third horizontal line; a first data line disposed on the left side of the first column line and connected to the first color sub-pixel and the third color sub-pixel in the first column line; a third data line, disposed on the right side of the second column line and connected to the first color sub-pixel and the third color sub-pixel in the second column line; as well as The second data line is disposed between the first column line and the second column line and is connected to the second color sub-pixel in the first column line and the second color sub-pixel in the second column line.

2. The display device according to claim 1, wherein The first to third horizontal lines are configured to be driven by the first gate line and the second gate line in a double rate driving manner.

3. The display device according to claim 1 , further comprising: a fourth data line, arranged in parallel with the third data line and between the second column line and the third column line, the fourth data line being connected to the first color sub-pixel and the third color sub-pixel in the third column line; a sixth data line, disposed on the right side of the fourth column line and connected to the first color sub-pixel and the third color sub-pixel in the fourth column line; as well as The fifth data line is disposed between the third column line and the fourth column line and is connected to the second color sub-pixel in the third column line and the second color sub-pixel in the fourth column line.

4. The display device according to claim 3, wherein During a first horizontal period in which a gate-on voltage is applied to the first gate line, The first color sub-pixels in the first horizontal line connected to the first data line and the third data line are configured to be charged by receiving a first color data signal of a first polarity, and the first color sub-pixels in the first horizontal line connected to the fourth data line and the sixth data line are configured to be charged by receiving a first color data signal of a second polarity, and The second color sub-pixels in the second horizontal line connected to the second data line are configured to be charged by receiving the second color data signal of the second polarity, and the other second color sub-pixels in the second horizontal line connected to the fifth data line are configured to be charged by receiving the second color data signal of the first polarity.

5. The display device according to claim 3, wherein During a second horizontal period in which the gate-on voltage is applied to the second gate line, The third color sub-pixels in the third horizontal line connected to the first data line and the third data line are configured to be charged by receiving a third color data signal of a first polarity, and the third color sub-pixels in the third horizontal line connected to the fourth data line and the sixth data line are configured to be charged by receiving a third color data signal of a second polarity, and The second color sub-pixels in the second horizontal line connected to the second data line are configured to be charged by receiving the second color data signal of the second polarity, and the other second color sub-pixels in the second horizontal line connected to the fifth data line are configured to be charged by receiving the second color data signal of the first polarity. The display device according to claim 3 , wherein: Each of the first to sixth data lines is configured to receive a data signal having a polarity opposite to that of an adjacent data line, and The polarity of the data signal applied to each of the first to sixth data lines is the same polarity in one frame and is opposite to that in adjacent frames.

7. The display device according to claim 1, wherein Each of the first to third color sub-pixels has a long side in the horizontal direction and a short side in the vertical direction.

8. A display device comprising: A first horizontal line includes first color sub-pixels arranged in a horizontal direction; a second horizontal line comprising second color sub-pixels arranged along the horizontal direction; a third horizontal line comprising third color sub-pixels arranged along the horizontal direction; a first gate line disposed between the first horizontal line and the second horizontal line and connected to the first color sub-pixels in the first horizontal line and to some of the second color sub-pixels in the second horizontal line; a second gate line disposed between the second horizontal line and the third horizontal line and connected to the third color sub-pixels in the third horizontal line and to the remaining second color sub-pixels in the second horizontal line; First to fourth column lines, each comprising an alternating arrangement of first to third color sub-pixels in the first to third horizontal lines in the vertical direction; a first data line disposed on the left side of the first column line and connected to the first color sub-pixel and the third color sub-pixel in the first column line; a (2-1)th data line disposed between the first column line and the second column line and connected to the second color sub-pixel in the first column line; and a (3-1)th data line disposed between the first column line and the second column line and connected to the second color sub-pixel in the second column line; a fourth data line disposed between the second column line and the third column line and connected to the first color subpixel and the third color subpixel in the second column line; and a fifth data line disposed between the second column line and the third column line and connected to the first color subpixel and the third color subpixel in the third column line; a (2-2)th data line, disposed between the third column line and the fourth column line and connected to the second color sub-pixel in the third column line; and a (3-2)th data line, disposed between the third column line and the fourth column line and connected to the second color sub-pixel in the fourth column line; as well as a sixth data line, disposed on the right side of the fourth column line and connected to the first color sub-pixel and the third color sub-pixel in the fourth column line; wherein the (2-1)th data line is connected to the (2-2)th data line, and Wherein, the (3-1)th data line is connected to the (3-2)th data line.

9. The display device according to claim 8, wherein The first to third horizontal lines are configured to be driven by the first gate line and the second gate line in a double rate driving manner.

10. The display device according to claim 8, wherein During a first horizontal period in which a gate-on voltage is applied to the first gate line, The first color sub-pixels in the first horizontal line connected to the first data line and the fifth data line are configured to be charged by receiving a first color data signal of a first polarity, and the first color sub-pixels in the first horizontal line connected to the fourth data line and the sixth data line are configured to be charged by receiving a first color data signal of a second polarity, and The second color sub-pixel in the second horizontal line connected to the (2-1)th data line is configured to be charged by receiving the second color data signal of the second polarity, and the other second color sub-pixel in the second horizontal line connected to the (3-1)th data line is configured to be charged by receiving the second color data signal of the first polarity.

11. The display device according to claim 8, wherein During a second horizontal period in which a gate-on voltage is applied to the second gate line, The third color sub-pixels in the third horizontal line connected to the first data line and the fifth data line are configured to be charged by receiving a third color data signal of a first polarity, and the third color sub-pixels in the third horizontal line connected to the fourth data line and the sixth data line are configured to be charged by receiving a third color data signal of a second polarity, and The second color sub-pixel in the second horizontal line connected to the (2-2)th data line is configured to be charged by receiving the second color data signal of the second polarity, and the other second color sub-pixel in the second horizontal line connected to the (3-2)th data line is configured to be charged by receiving the second color data signal of the first polarity.

12. The display device according to claim 8, wherein Each of the first to sixth data lines is configured to receive a data signal having a polarity opposite to that of an adjacent data line, and The polarity of the data signal applied to each of the first to sixth data lines is the same polarity in one frame and is opposite to that in adjacent frames.

13. The display device according to claim 8, wherein Each of the first to third color sub-pixels has a long side in the horizontal direction and a short side in the vertical direction.

14. A display device comprising: first color sub-pixels arranged in a first row and disposed on a substrate; second color sub-pixels arranged in a second row and disposed on the substrate; third color sub-pixels arranged in a third row and disposed on the substrate; a first gate line disposed between the first row and the second row, the first gate line being connected to a first group of sub-pixels of the first color arranged in the first row and the second color arranged in the second row; as well as A second gate line is disposed between the second row and the third row, and is connected to a second group of second color subpixels arranged in the second row and third color subpixels arranged in the third row.

15. The display device according to claim 14, further comprising: a first column of subpixels, comprising: first-first color subpixels arranged among the first color subpixels in the first row, first-second color subpixels arranged among the second color subpixels in the second row, and first-third color subpixels arranged among the third color subpixels in the third row; a second column of sub-pixels, comprising: second-first color sub-pixels arranged among the first color sub-pixels in the first row, second-second color sub-pixels arranged among the second color sub-pixels in the second row, and second-third color sub-pixels arranged among the third color sub-pixels in the third row; a first data line connected to the first-first color sub-pixels in the first column and the first-third color sub-pixels in the first column; a second data line disposed between the first column and the second column, the second data line being connected to the first-second color sub-pixels in the first column and the second-second color sub-pixels in the second column; and The third data line is connected to the second-first color sub-pixels in the second column and the second-third color sub-pixels in the second column.

16. The display device according to claim 15, further comprising: a controller electrically connected to the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, the controller being configured to: During an odd frame, a data voltage having a first polarity is supplied to the first data line, a data voltage having a second polarity opposite to the first polarity is supplied to the second data line, and a data voltage having the first polarity is supplied to the third data line, and During an even frame, the data voltage having the second polarity is supplied to the first data line, the data voltage having the first polarity is supplied to the second data line, and the data voltage having the second polarity is supplied to the third data line.

17. The display device according to claim 15, wherein The first gate line and the second gate line overlap with a common electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, and The first data line, the second data line and the third data line are spaced apart from and do not overlap with the common electrode.

18. The display device according to claim 14, further comprising: a first column of subpixels, comprising: first-first color subpixels arranged among the first color subpixels in the first row, first-second color subpixels arranged among the second color subpixels in the second row, and first-third color subpixels arranged among the third color subpixels in the third row; a second column of sub-pixels, comprising: second-first color sub-pixels arranged among the first color sub-pixels in the first row, second-second color sub-pixels arranged among the second color sub-pixels in the second row, and second-third color sub-pixels arranged among the third color sub-pixels in the third row; a first data line connected to the first-first color sub-pixels in the first column and the first-third color sub-pixels in the first column; a second data line disposed between the first column and the second column, the second data line being connected to the first-second color sub-pixels in the first column; and A third data line is disposed between the first column and the second column, and the third data line is connected to the second-second color sub-pixel in the second column.

19. The display device according to claim 18, further comprising: a controller electrically connected to the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, the controller being configured to: During an odd frame, a data voltage having a first polarity is supplied to the second data line, a data voltage having a second polarity opposite to the first polarity is supplied to the first data line, and a data voltage having the second polarity is supplied to the third data line, and During an even frame, the data voltage having the first polarity is supplied to the first data line, the data voltage having the second polarity is supplied to the second data line, and the data voltage having the first polarity is supplied to the third data line.

20. The display device according to claim 14, further comprising: a controller connected to the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel, the controller being configured to: The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are driven in the horizontal direction according to a two-dot inversion driving method, and The first color sub-pixel, the second color sub-pixel and the third color sub-pixel are driven in the vertical direction according to a one-two-dot mixed inversion driving mode, wherein the one-two-dot mixed inversion driving mode includes a one-dot inversion driving mode mixed with a two-dot inversion driving mode.

21. A display device comprising: A first horizontal line includes first color sub-pixels arranged in a horizontal direction; a second horizontal line comprising second color sub-pixels arranged along the horizontal direction; a third horizontal line comprising third color sub-pixels arranged along the horizontal direction; a first gate line disposed between the first horizontal line and the second horizontal line and connected to the first horizontal line and to some sub-pixels of the second horizontal line; a second gate line disposed between the second horizontal line and the third horizontal line, connected to the third horizontal line, and connected to the remaining sub-pixels of the second horizontal line; column lines, each column line comprising first to third color sub-pixels in the first to third horizontal lines alternately arranged in a vertical direction; a first type of data line disposed on a first side of each of the column lines and connected to the first color sub-pixel and the third color sub-pixel of each of the column lines; as well as a second type of data line disposed on a second side of each of the column lines and connected to a second color sub-pixel of each of the column lines; The second type of data lines and the first type of data lines are arranged in parallel between adjacent column lines.

22. The display device according to claim 21, wherein The first-category data lines include a first-category first data line, a first-category third data line, a first-category fifth data line, and a first-category sixth data line that are arranged on a first side of each of the first to fourth column lines and connected to the first color sub-pixel and the third color sub-pixel of each of the first to fourth column lines.

23. The display device according to claim 22, wherein The second type of data lines include: A second-type (2-1)th data line and a second-type (2-2)th data line are disposed on a second side of each of the first column line and the third column line and are connected to a second color sub-pixel of each of the first column line and the third column line; and A second-type (4-1)th data line and a second-type (4-2)th data line are disposed on a second side of each of the second column line and the fourth column line and are connected to a second color sub-pixel of each of the second column line and the fourth column line, The (2-1)th data line is connected to the (2-2)th data line, and The (4-1)th data line is connected to the (4-4)th data line.

24. The display device according to claim 21, wherein The first to third horizontal lines are driven at a double rate by the first gate line and the second gate line.

25. The display device according to claim 23, wherein During a first horizontal period in which a gate-on voltage is driven to the first gate line, charging the first color sub-pixels of the first horizontal line connected to the first data line and the fifth data line by receiving the first color data signal of the first polarity, and charging the first color sub-pixels connected to the third data line and the sixth data line by receiving the first color data signal of the second polarity, and By receiving the second color data signal of the second polarity, the second color sub-pixel of the first horizontal line connected to the (2-1)th data line is charged, and by receiving the second color data signal of the first polarity, the second color sub-pixel connected to the (4-1)th data line is charged.

26. The display device according to claim 23, wherein During a second horizontal period in which a gate-on voltage is driven to the second gate line, The second color sub-pixel of the third horizontal line connected to the (2-2)th data line is charged by receiving the second color data signal of the second polarity, and the second color sub-pixel connected to the (4-2)th data line is charged by receiving the second color data signal of the first polarity, and By receiving the third color data signal of the first polarity, the third color sub-pixels of the second horizontal line connected to the first data line and the fifth data line are charged, and by receiving the third color data signal of the second polarity, the third color sub-pixels connected to the third data line and the sixth data line are charged.

27. The display device according to claim 23, wherein The first data line, the (4-1)th data line, and the (4-2)th data line apply data signals having polarities opposite to those of the data signals of the (2-1)th data line, the (2-2)th data line, the third data line, and the sixth data line, and The polarity of the data signal applied to each of the first to sixth data lines is the same in one frame and is reversed for each frame.

28. The display device according to claim 21, wherein The first to third color sub-pixels have long sides in the horizontal direction and short sides in the vertical direction.

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