PID control algorithm for optimizing BP neural network by SMU-particle swarm optimization based on FPGA

Abstract

The invention provides a PID (Proportion Integration Differentiation) control algorithm for optimizing a BP (Back Propagation) neural network based on an SMU (Source Measurement Unit)-particle swarm optimization algorithm realized on the basis of an FPGA (Field Programmable Gate Array). The PID control algorithm comprises the following steps of: feeding back real-time data through an input module, namely an ADC (Analog Performing error calculation on the input data by adopting a BP neural network module to generate an initial control signal; a particle swarm optimization (PSO) algorithm is utilized to dynamically optimize the weight and bias of the BP neural network, optimized parameters are input into a PID controller module, and a control instruction is generated; and the actuator is driven by an output module, namely a DAC (digital-to-analog converter), so that control operation is completed. According to the algorithm, synchronous processing of BP neural network forward propagation, particle swarm optimization (PSO) parameter iteration and PID control instruction generation is realized through a parallel computing architecture of the FPGA, the system response time is shortened by more than 40%, the millisecond-level real-time control requirement is met, and the algorithm has a good application prospect.

Description

Technical Field

[0001] The present invention relates to the field of automatic control technology, in particular to an intelligent control system, and specifically to an SMU-particle swarm algorithm optimized BP neural network PID control algorithm implemented based on FPGA. Background Art

[0002] In automatic control systems, traditional PID (Proportional-Integral-Derivative) control algorithms often face difficulties in parameter adjustment, slow response, and insufficient stability when dealing with nonlinear and time-varying systems. While the differential control step can predict error trends, it can lead to system oscillation or instability in practice, especially in systems with large inertia or hysteresis components. To address these issues, a differential term is often introduced into the controller to preemptively suppress errors and prevent significant overshoot of the controlled variable.

[0003] Although BP neural networks are widely used for adaptive parameter adjustment to improve control system performance, their convergence speed is significantly affected by the initial parameter settings. Particle swarm optimization (PSO), a global optimization technique, can effectively optimize neural network parameters, thereby improving control accuracy. However, existing solutions often rely on software implementation, which limits their application in applications with high real-time requirements.

[0004] The purpose of this invention is to optimize PID control through FPGA hardware platform, combined with PSO algorithm and BP neural network, so as to significantly improve the response speed and control accuracy of the system and meet the high real-time requirements. Summary of the Invention

[0005] The purpose of the present invention is to provide an SMU-particle swarm optimization BP neural network PID control algorithm based on FPGA to solve the problems in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solution: The present invention provides an SMU-particle swarm optimization BP neural network PID control algorithm based on FPGA, comprising the following steps:

[0007] (1) Real-time data fed back by the input module, namely the ADC (analog-to-digital converter);

[0008] (2) Using the BP neural network module to calculate the error of the input data and generate the initial control signal;

[0009] (3) Using the particle swarm optimization (PSO) algorithm to dynamically optimize the weights and biases of the BP neural network, including:

[0010] a. Initialize the position and velocity of the particle swarm and set the fitness function;

[0011] b. Iteratively update the particle's velocity and position, adjusting parameters based on the global optimal solution and the individual optimal solution;

[0012] (4) Input the optimized parameters into the PID controller module to generate control instructions;

[0013] (5) The output module, namely DAC (digital-to-analog converter), drives the actuator to complete the control operation.

[0014] Preferably, the BP neural network module includes an input layer, a hidden layer and an output layer, wherein:

[0015] Forward propagation uses FPGA to implement weight weighting and activation function calculation;

[0016] Backpropagation updates the weights using the mean squared error loss function.

[0017] Preferably, the speed and position update formula of the particle swarm optimization algorithm is:

[0018]

[0019] Among them, W is the inertia factor, C1 and C2 are acceleration constants, r1 and r2 are random numbers between 0 and 1, and P i k is the optimal position of the individual, G k is the global optimal position.

[0020] Preferably, the PID controller module uses fixed-point operations to implement proportional, integral and differential control strategies to improve calculation efficiency and accuracy.

[0021] Preferably, the FPGA implementation includes Verilog codes of the following modules: an input module, a BP neural network module, a particle swarm optimization module, a PID controller module and an output module.

[0022] The BP neural network PID control system optimized by SMU-particle swarm algorithm implemented based on FPGA includes: sensor, FPGA chip, actuator and data conversion module (ADC / DAC).

[0023] The present invention has at least the following beneficial effects:

[0024] (1) The present invention provides an FPGA-based SMU-particle swarm optimization BP neural network PID control algorithm. This algorithm uses the FPGA's parallel computing architecture to achieve synchronous processing of BP neural network forward propagation, particle swarm optimization (PSO) parameter iteration, and PID control instruction generation. The system response time is shortened by more than 40%, meeting millisecond-level real-time control requirements, and has good application prospects.

[0025] (2) The present invention provides an FPGA-based SMU-particle swarm optimization algorithm to optimize the BP neural network PID control algorithm. The PSO algorithm dynamically optimizes the weights and biases of the BP neural network, solving the problem of traditional BP neural network dependence on initial parameters, making the PID parameter adaptive adjustment more accurate, and reducing the steady-state error to within ±0.5%.

[0026] (3) The FPGA-based SMU-particle swarm optimization BP neural network PID control algorithm provided by the present invention combines the differential control strategy with the PSO global search capability to effectively suppress overshoot and oscillation in complex dynamic systems, improve the smoothness of the control process, and is suitable for high inertia or lag scenarios.

[0027] (4) The SMU-particle swarm algorithm based on FPGA provided by the present invention optimizes the BP neural network PID control algorithm, adopts FPGA fixed-point operation to implement the PID control strategy, reduces the occupation of logic resources, and supports flexible expansion and multi-task parallel processing through modular Verilog code design (input module, BP neural network module, etc.). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a flow chart of the algorithm provided by the present invention. DETAILED DESCRIPTION

[0029] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by technicians in the technical field to which the present invention belongs. The terms used in this specification and in the description of the present invention are only for the purpose of describing specific embodiments and are not used to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0030] Example

[0031] like Figure 1 As shown in the figure, the FPGA-based SMU-Particle Swarm Optimization BP Neural Network PID control algorithm includes the following steps:

[0032] (1) The BP neural network module includes input layer, hidden layer and output layer, which are fed back by real-time data from the input module, namely ADC (Analog-to-Digital Converter).

[0033] Forward propagation uses FPGA to implement weight weighting and activation function calculation;

[0034] Backpropagation updates the weights through the mean squared error loss function;

[0035] (2) Using the BP neural network module to calculate the error of the input data and generate the initial control signal;

[0036] (3) Using the particle swarm optimization (PSO) algorithm to dynamically optimize the weights and biases of the BP neural network, including:

[0037] a. Initialize the position and velocity of the particle swarm and set the fitness function;

[0038] b. Iteratively update the particle's velocity and position, adjusting parameters based on the global optimal solution and the individual optimal solution;

[0039] (4) The optimized parameters are input into the PID controller module to generate control instructions. The PID controller module uses fixed-point operations to implement proportional, integral, and differential control strategies to improve calculation efficiency and accuracy.

[0040] (5) The output module, or DAC (digital-to-analog converter), drives the actuator to complete the control operation. The output module drives the actuator to complete the control operation. The actuator can be a motor, valve, heater, etc., and performs the corresponding action according to the control instruction.

[0041] The speed and position update formula of the particle swarm optimization algorithm is:

[0042]

[0043] Among them, W is the inertia factor, C1 and C2 are acceleration constants, r1 and r2 are random numbers between 0 and 1, and P i k is the optimal position of the individual, G k is the global optimal position.

[0044] The PID controller module uses fixed-point operations to implement proportional, integral and differential control strategies to improve computational efficiency and accuracy.

[0045] The FPGA implementation includes the Verilog codes of the following modules: input module, BP neural network module, particle swarm optimization module, PID controller module and output module.

[0046] The FPGA-based SMU-Particle Swarm Optimization (SMU-PSO) algorithm optimizes the BP neural network PID control system, including FPGA chip control and data conversion module (ADC / DAC) control. This system can quickly respond to real-time data changes and achieve precise control through an optimized PID control strategy.

[0047] This embodiment has at least the following beneficial effects:

[0048] Through the parallel computing architecture of FPGA, the synchronous processing of BP neural network forward propagation, particle swarm optimization (PSO) parameter iteration and PID control instruction generation is achieved, and the system response time is shortened by more than 40%, meeting the millisecond-level real-time control requirements.

[0049] The PSO algorithm dynamically optimizes the weights and biases of the BP neural network, solving the problem of traditional BP neural networks relying on initial parameters, making the adaptive adjustment of PID parameters more accurate and reducing the steady-state error to within ±0.5%.

[0050] Combining the differential control strategy with the PSO global search capability, it effectively suppresses overshoot and oscillation in complex dynamic systems, improves the smoothness of the control process, and is suitable for high inertia or lag scenarios.

[0051] FPGA fixed-point operation is used to implement PID control strategy to reduce logic resource usage. At the same time, modular Verilog code design (input module, BP neural network module, etc.) supports flexible expansion and multi-task parallel processing.

[0052] Based on actual needs, the data conversion module (ADC) converts analog signals into digital signals for processing by the FPGA chip. The input module integrated within the FPGA chip receives these digital signals and passes them to the BP neural network module. The BP neural network module performs forward propagation calculations on this data to generate initial control signals. Subsequently, the particle swarm optimization (PSO) algorithm module optimizes the weights and biases of the BP neural network to find more optimal control parameters. The optimized parameters are passed to the PID controller module, which generates the final control instructions based on these parameters. Finally, the output module converts these control instructions into analog signals (via the DAC) and drives the actuator to produce the corresponding output, thereby achieving precise control of the SMU (source measure unit) voltage and current.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Under the idea of ​​the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The SMU-particle swarm optimization algorithm based on FPGA is optimized for BP neural network PID control algorithm, which is characterized by: The following steps are involved: (1) Real-time data fed back by the input module, namely the ADC (analog-to-digital converter); (2) Using the BP neural network module to calculate the error of the input data and generate the initial control signal; (3) Using the particle swarm optimization (PSO) algorithm to dynamically optimize the weights and biases of the BP neural network, including: a. Initialize the position and velocity of the particle swarm and set the fitness function; b. Iteratively update the particle's velocity and position, adjusting parameters based on the global optimal solution and the individual optimal solution; (4) Input the optimized parameters into the PID controller module to generate control instructions; (5) The output module, namely DAC (digital-to-analog converter), drives the actuator to complete the control operation.

2. The FPGA-based SMU-Particle Swarm Optimization BP Neural Network PID control algorithm according to claim 1 is characterized in that: The BP neural network module includes an input layer, a hidden layer and an output layer, wherein: Forward propagation uses FPGA to implement weight weighting and activation function calculation; Backpropagation updates the weights using the mean squared error loss function.

3. The FPGA-based SMU-Particle Swarm Optimization (PSO) algorithm for optimizing BP neural network PID control algorithm according to claim 1 is characterized in that: The speed and position update formulas of the particle swarm optimization algorithm are: Among them, W is the inertia factor, C1 and C2 are acceleration constants, r1 and r2 are random numbers between 0 and 1, and P i k is the optimal position of the individual, G k is the global optimal position.

4. The FPGA-based SMU-Particle Swarm Optimization BP Neural Network PID control algorithm according to claim 1 is characterized in that: The PID controller module uses fixed-point operations to implement proportional, integral and differential control strategies to improve computational efficiency and accuracy.

5. The FPGA-based SMU-Particle Swarm Optimization BP Neural Network PID control algorithm according to claim 1 is characterized in that: The FPGA implementation includes Verilog codes of the following modules: an input controller module, a BP neural network module, a particle swarm optimization module, a PID controller module, and an output controller module.

6. A control system based on the algorithm according to any one of claims 1 to 5, characterized in that: include: FPGA chip control, data conversion module (ADC / DAC) control.

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