High voltage domain control potential generation device

Abstract

The application relates to the field of high-voltage chip design, and discloses a high-voltage domain control potential generating device. The device comprises an anti-backflow protection module, a voltage limiting module, a high-voltage domain generating module and a high-voltage domain monitoring module; wherein the anti-backflow protection module uses a MOS tube array to perform anti-backflow protection on a power supply; the voltage limiting module provides a bias current and a low-voltage protection voltage; the high-voltage domain generating module is used to generate and maintain a high-voltage domain; and the high-voltage domain monitoring module respectively monitors a power supply voltage in real time. When the device is designed to generate a high-voltage domain, the anti-backflow protection module and the high-voltage domain monitoring module are added, the device can automatically respond to power supply voltage changes, real-time adjustment of the working state is realized, voltage loss and power consumption problems in a traditional scheme are avoided, meanwhile, no complex external control signal is needed, and the reliability and stability of system work are greatly improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to a high-voltage domain controlled potential generation technique. Background Technology

[0002] With the development of electric vehicles, smart homes, and distributed power generation, chips are evolving towards higher voltages and greater power to meet the personalized needs of different application scenarios. Simultaneously, driven by the concept of green energy conservation, high-voltage chips are placing greater emphasis on energy efficiency improvement and energy management. This makes the generation and management of high-voltage domain control potentials a significant technical challenge.

[0003] In existing technologies, two solutions are typically used to avoid reverse current flow: one is to utilize the unidirectional conductivity of diodes, such as... Figure 2 The circuit structure shown is an example. However, the diodes in this design exhibit a forward voltage drop, inevitably leading to voltage loss and increased power consumption. Furthermore, in practical applications, special attention must be paid to the isolation of the diode devices to avoid transistor effects.

[0004] Another common approach is to achieve this by adding external control signals, such as... Figure 3 The circuit structure shown is an example of a scheme that prevents current backflow by controlling the conduction state of the MOSFET using a Control signal. However, this scheme relies on complex control signals and logic timing, which significantly increases the design difficulty in high-voltage environments and can easily introduce system instability factors.

[0005] Furthermore, existing high-voltage domain control potential generation schemes often require the use of a large number of LDMOS transistors to withstand high voltages, which not only increases design complexity but also raises costs. At the same time, the lack of a real-time monitoring mechanism for the high-voltage domain makes it difficult to detect and respond to abnormal situations in a timely manner.

[0006] In particular, existing technologies struggle to guarantee reliable system operation in the event of a sudden power outage, potentially leading to irreversible damage. This is especially dangerous under high-voltage conditions, severely impacting system stability and reliability.

[0007] Therefore, there is an urgent need for a new high-voltage domain control potential generation device that can avoid the problem of current backflow, without bringing additional power consumption and complex control logic, and at the same time realize the real-time monitoring and protection functions of the high-voltage domain. Summary of the Invention

[0008] The purpose of this application is to provide a high-voltage domain controlled potential generation device to solve the problems mentioned in the background art.

[0009] This application discloses a high-voltage domain controlled potential generation device, comprising:

[0010] The backflow prevention module has an input voltage VIN connected to its input terminal and a high voltage domain power supply potential VCCH output terminal, and an external capacitor CL is connected to the chip.

[0011] The voltage limiting module has a first input terminal connected to the input voltage, a second input terminal connected to the high voltage domain power supply potential, and an output terminal outputting a bias current ibn.

[0012] A high-voltage domain generation module has its input terminal connected to the high-voltage domain power supply potential, its first output terminal outputting the high-voltage domain ground potential VSSH, and its second output terminal outputting the high-voltage domain sampling voltage Vsns.

[0013] The high-voltage domain monitoring module has a first input terminal connected to the high-voltage domain power supply potential, a second input terminal connected to the bias current, a third input terminal connected to the high-voltage domain sampling voltage, a fourth input terminal connected to the high-voltage domain ground potential, and an output terminal that outputs a control signal VOK_vcch.

[0014] In a preferred embodiment, the high-voltage domain control potential generating device operates as follows:

[0015] When the input voltage rises from 0, the input voltage is input to the anti-backflow protection module to charge the external capacitor, so that the high voltage domain power supply potential starts to rise synchronously. At the same time, the voltage limiting module starts to work automatically and outputs the bias current.

[0016] When the high voltage domain power supply potential rises from 0, the high voltage domain generation module outputs the high voltage domain ground potential and the high voltage domain sampling voltage, and the high voltage domain ground potential and the high voltage domain sampling voltage rise synchronously with the high voltage domain power supply potential.

[0017] When the high voltage domain power supply potential rises from 0 to a set threshold, the high voltage domain monitoring module, upon receiving the high voltage domain sampling voltage, outputs the control signal according to the state of the high voltage domain power supply potential.

[0018] Once the input voltage has risen and stabilized, if a sudden power failure occurs, the anti-backflow protection module triggers the protection mechanism. The path between the high-voltage power supply potential and the input voltage is forcibly disconnected. Due to the voltage stabilization effect of the external capacitor, the high-voltage power supply potential slowly decreases to ensure the normal operation of the system for a period of time and avoid irreversible damage to the system caused by a sudden power failure.

[0019] In a preferred embodiment, the backflow prevention module includes: a first resistor R1, whose input terminal is connected to the input voltage and whose output terminal outputs the input node voltage VIN_in; a first P-type lateral diffused metal-oxide-semiconductor transistor pmos1, whose drain is connected to the input node voltage, whose source is connected to the second control voltage Vsh, and whose gate is connected to the first control voltage Vgh; a second P-type LDMOS transistor pmos2, whose drain is connected to the high voltage domain power supply potential, whose source is connected to the second control voltage, and whose gate is connected to the first control voltage; a first Zener diode zd1, whose anode is connected to the first control voltage and whose cathode is connected to the second control voltage; and a second resistor R2, one end of which is connected to the first control voltage and the other end of which is connected to the high voltage domain power supply potential.

[0020] In a preferred embodiment, the high-voltage domain generation module includes: a second Zener diode zd2, whose anode is connected to the high-voltage domain power supply potential and whose cathode is connected to a third control voltage Vg; a third resistor R3, one end of which is connected to the third control voltage and the other end of which is connected to a fourth control voltage Vbn; a first N-type metal-oxide-semiconductor transistor nmos1, whose source is connected to ground potential avss, and whose gate and drain are short-circuited and connected to the fourth control voltage; a first capacitor C1, one end of which is connected to the high-voltage domain power supply potential and the other end of which is connected to the third control voltage; and a second capacitor C2, one end of which is connected to the high-voltage domain power supply potential. The first P-type metal-oxide-semiconductor transistor (PMOS3) has its source connected to the high-voltage domain power supply potential, and its gate and drain short-circuited and connected to the fifth control voltage Vbp; the fourth resistor R4 has one end connected to the fifth control voltage and the other end connected to the high-voltage domain sampling voltage; the fifth resistor R5 has one end connected to the high-voltage domain sampling voltage and the other end connected to the high-voltage domain ground potential; the second P-type MOS transistor PMOS4 has its source connected to the high-voltage domain ground potential, its gate connected to the third control voltage, and its drain connected to the ground potential.

[0021] In a preferred embodiment, the high-voltage domain monitoring module includes: a sixth resistor R6, one end of which is connected to the high-voltage domain sampling voltage, and the other end of which is connected to the seventh control voltage Vsns_ft; a third capacitor C3, one end of which is connected to the seventh control voltage, and the other end of which is connected to the high-voltage domain ground potential; a second N-type MOSFET nmos2, the source of which is connected to the high-voltage domain ground potential, the drain of which is connected to the sixth control voltage Vibn, and the gate of which is connected to the seventh control voltage; a fourth capacitor C4, one end of which is connected to the high-voltage domain power supply potential, and the other end of which is connected to the sixth control voltage; a first Schmitt trigger sm1, the input of which is connected to the sixth control voltage, the power supply of which is connected to the high-voltage domain power supply potential, the ground of which is connected to the high-voltage domain ground potential, and the output of which is connected to the input of a first inverter INV1; the power supply and ground of the first inverter are respectively connected to the high-voltage domain power supply potential and the high-voltage domain ground potential, and the output of the first inverter outputs the control signal.

[0022] In a preferred embodiment, when the input voltage rises from 0V, the input voltage charges the source of the first P-type LDMOS transistor due to the parasitic diode of the first P-type LDMOS transistor. The first resistor limits the current protection circuit. When the second control voltage is charged to the threshold voltage Vth, the first and second P-type LDMOS transistors begin to conduct. The input voltage charges the external capacitor through the channels of the first and second P-type LDMOS transistors, causing the high-voltage power supply potential to rise. The first Zener diode simultaneously stabilizes the gate and source voltage difference of the first and second P-type LDMOS transistors, protecting them from overvoltage problems.

[0023] In a preferred embodiment, when the input voltage is suddenly de-energized after stabilization, the source voltages of the first and second P-type LDMOS transistors are charged and maintained by the high-voltage power supply potential due to the parasitic diode of the second P-type LDMOS transistor. At this time, the second control voltage is equal to the high-voltage power supply potential minus the parasitic diode voltage drop Vdio. Meanwhile, the source voltages of the first and second P-type LDMOS transistors are equal to the high-voltage power supply potential. This causes the first and second P-type LDMOS transistors to enter the off state, thereby automatically disconnecting the path between the input voltage and the high-voltage power supply potential, effectively preventing the current from the high-voltage power supply potential from flowing back into the input voltage terminal.

[0024] In a preferred embodiment, the relationship between the high-voltage domain ground potential and the high-voltage domain power supply potential satisfies the following formula: VSSH=VCCH-Vzd+Vth, where Vzd is the Zener voltage of the second Zener diode and Vth is the threshold voltage of the second P-type MOS transistor.

[0025] In a preferred embodiment, when the high-voltage domain sampling voltage is greater than the threshold voltage, the second N-type MOS transistor begins to pull down the sixth control voltage. When the pull-down capability is greater than the pull-up capability of the bias current, the sixth control voltage gradually decreases until the output of the first Schmitt trigger flips to output a low level, and the control signal outputs a high level through the first inverter.

[0026] Compared with the prior art, the high-voltage domain controlled potential generating device proposed in this application has the following advantages:

[0027] By using an array structure of P-type LDMOS transistors pmos1 and pmos2 in the backflow prevention module, and utilizing their parasitic diode characteristics, adaptive conduction control between the power supply voltage VIN and the voltage VCCH is achieved. Figure 2 Compared to the traditional diode solution shown, this solution avoids the voltage drop and increased power consumption caused by the forward voltage drop of the diode dio1, and eliminates the need for additional device isolation, thus avoiding the transistor effect.

[0028] and Figure 3 Compared with the traditional scheme that relies on the external control signal Control, this application does not require complex logic timing control during actual operation. When the power supply voltage VIN is powered on, the backflow protection module automatically starts and when the power supply voltage VIN is powered off, it automatically shuts off the path between the power supply voltage VIN and the voltage VCCH, avoiding energy loss and system instability. It is particularly suitable for applications in high-voltage environments.

[0029] The high-voltage domain generation module of this application utilizes components such as Zener diode ZD2, resistors R3-R5, and P-type LDMOS transistor PMOS4 (e.g., Figure 5 As shown, this generates the control potentials VCCH and VSSH in the high-voltage domain, simplifying subsequent high-voltage circuit design. It eliminates the need for numerous LDMOS transistors to withstand the high voltage, reducing design complexity and cost. The high-voltage domain monitoring module (such as...) generates the control potentials VCCH and VSSH in the high-voltage domain, simplifying subsequent high-voltage circuit design. It eliminates the need for numerous LDMOS transistors to withstand the high voltage, reducing design complexity and cost. Figure 6 As shown, the high voltage domain voltages VCCH and VSSH are monitored in real time through an n-type MOS transistor nmos2, a Schmitt trigger sm1, and an inverter inv1. When the high voltage domain is working normally, the output signal VOK_vcch is provided, which facilitates subsequent logic control.

[0030] The entire high-voltage domain control potential generation device adopts an adaptive structural design, independent of external control. It automatically realizes high-voltage domain potential generation, monitoring, and protection functions based on the power supply voltage VIN state, significantly improving the reliability and stability of the system. Especially in the event of a sudden power failure, the voltage regulation effect of the external capacitor CL causes the voltage VCCH to decrease slowly, providing sufficient buffer time for the system and avoiding the risk of system damage under high-voltage conditions.

[0031] In summary, the high-voltage domain control potential generation device proposed in this application has a simple circuit structure, is easy to control, and is reliable in operation. It overcomes many defects in the prior art and has broad application prospects in the field of high-voltage chip design.

[0032] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a high-voltage domain control potential generating device according to an embodiment of this application;

[0034] Figure 2 This is a traditional diode solution;

[0035] Figure 3 A backflow prevention protection scheme that relies on control signals and logic;

[0036] Figure 4 It is an anti-backflow protection module in a high-voltage domain control potential generating device according to an embodiment of this application;

[0037] Figure 5 It is a high-voltage domain generation module of a high-voltage domain control potential generation device according to an embodiment of this application;

[0038] Figure 6 It is a high-voltage domain monitoring module of a high-voltage domain control potential generation device according to an embodiment of this application. Detailed Implementation

[0039] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0040] Explanation of some concepts:

[0041] High voltage domain: refers to the operating region in an integrated circuit with a relatively high potential difference. In this application, it is composed of the high voltage domain power supply potential VCCH and the high voltage domain ground potential VSSH.

[0042] LDMOS: an abbreviation for Laterally Diffused Metal Oxide Semiconductor, is a power transistor structure commonly used in high-voltage applications.

[0043] Backflow protection: a protection mechanism to prevent current from flowing back from the load terminal to the power supply terminal, which is implemented in this application through a special P-type LDMOS transistor array structure.

[0044] Parasitic diode: The PN junction diode inherent in the MOS transistor structure is cleverly utilized in this application to achieve adaptive conduction control.

[0045] Zener diode: A special type of diode that can operate stably under reverse breakdown voltage (Zener voltage) and is often used for voltage stabilization and voltage limiting protection.

[0046] Threshold voltage: The minimum gate-source voltage required for a MOS transistor to turn on, denoted as Vth in this application.

[0047] Schmitt trigger: A comparator circuit with hysteresis characteristics that can suppress noise interference in the input signal and improve the reliability of signal conversion.

[0048] External capacitors: Capacitive elements connected to the outside of an integrated circuit chip, denoted by CL in this application, are used to stabilize voltage and provide energy reserves when the power supply is lost.

[0049] Power failure protection: A mechanism to protect circuits and systems from damage when the power supply voltage suddenly drops or disappears.

[0050] Transistor effect: In integrated circuits, the parasitic transistor phenomenon that may occur when diode isolation is insufficient can lead to abnormal circuit operation.

[0051] High voltage domain sampling voltage: In this application, it is represented by Vsns, which is a sampling signal of the potential state of the high voltage domain and is used to monitor the operating state of the high voltage domain.

[0052] Bias current: The reference current that provides a stable operating point for the circuit, denoted as ibn in this application.

[0053] Control signal VOK_vcch: An output signal indicating the normal operating state of the high voltage domain, providing a basis for subsequent logic control.

[0054] Adaptive structure: A circuit structure that can automatically adjust its operating state according to changes in the environment or conditions, without the need for external control intervention.

[0055] Voltage limiting module: A functional unit that limits and stabilizes voltage, and in this application, it also provides bias current.

[0056] Name correspondence explanation

[0057] To make the technical solutions claimed in this application clearer and more explicit, a more standardized naming convention for technical features was used in the foregoing description of the invention, which corresponds to the naming convention used below. For ease of understanding, the correspondence between the technical feature names used in the foregoing description and the technical feature names used below is explained as follows:

[0058] Resistors:

[0059] The first resistor R1 corresponds to resistor R1 in the following text.

[0060] The second resistor R2 corresponds to the resistor R2 mentioned below.

[0061] The third resistor R3 corresponds to resistor R3 mentioned below.

[0062] The fourth resistor R4 corresponds to resistor R4 mentioned below.

[0063] The fifth resistor R5 corresponds to resistor R5 mentioned below.

[0064] The sixth resistor R6 corresponds to resistor R6 mentioned below.

[0065] Capacitors:

[0066] The first capacitor C1 corresponds to capacitor C1 in the following text.

[0067] The second capacitor C2 corresponds to capacitor C2 mentioned below.

[0068] The third capacitor C3 corresponds to capacitor C3 mentioned below.

[0069] The fourth capacitor C4 corresponds to capacitor C4 mentioned below.

[0070] The external capacitor CL corresponds to the capacitor CL mentioned below or the off-chip capacitor CL.

[0071] MOSFETs:

[0072] The first P-type LDMOS transistor pmos1 corresponds to the P-type LDMOS transistor pmos1 mentioned below. The second P-type LDMOS transistor pmos2 corresponds to the P-type LDMOS transistor pmos2 mentioned below. The first P-type MOS transistor pmos3 corresponds to the p-type MOS transistor pmos3 mentioned below.

[0073] The second P-type MOSFET pmos4 corresponds to the P-type LDMOS transistor pmos4 mentioned below. The first N-type MOSFET nmos1 corresponds to the n-type MOSFET nmos1 mentioned below.

[0074] The second N-type MOSFET nmos2 corresponds to the n-type MOSFET nmos2 diode category mentioned below:

[0075] The first Zener diode zd1 corresponds to the Zener diode zd1 mentioned below.

[0076] The second Zener diode zd2 corresponds to the Zener diode zd2 mentioned below.

[0077] Other components:

[0078] The first Schmitt trigger sm1 corresponds to the Schmitt trigger sm1 mentioned below.

[0079] The first inverter INV1 corresponds to inverter INV1 in the following text.

[0080] Voltage type:

[0081] The input voltage VIN corresponds to the supply voltage VIN mentioned below.

[0082] The input node voltage VIN_in corresponds to the voltage VIN_in mentioned below.

[0083] The high voltage domain power supply potential VCCH corresponds to the voltage VCCH mentioned below.

[0084] The high voltage domain ground potential VSSH corresponds to the voltage VSSH mentioned below.

[0085] The high-voltage domain sampling voltage Vsns corresponds to the high-voltage domain sampling voltage Vsns mentioned below.

[0086] The first control voltage Vgh corresponds to the voltage Vgh or gate voltage mentioned below.

[0087] The second control voltage Vsh corresponds to the voltage Vsh or source voltage mentioned below.

[0088] The third control voltage Vg corresponds to the voltage Vg mentioned below.

[0089] The fourth control voltage Vbn corresponds to the voltage Vbn mentioned below.

[0090] The fifth control voltage Vbp corresponds to the voltage Vbp mentioned below.

[0091] The sixth control voltage Vibn corresponds to the voltage Vibn mentioned below.

[0092] The seventh control voltage Vsns_ft corresponds to the voltage Vsns_ft mentioned below.

[0093] Threshold and reference voltage:

[0094] The threshold voltage Vth corresponds to the LDMOS transistor threshold voltage Vth mentioned below.

[0095] The Zener voltage Vzd corresponds to the Zener diode Zener voltage Vzd mentioned below.

[0096] The parasitic diode voltage drop Vdio corresponds to the parasitic diode voltage drop Vdio mentioned below.

[0097] Current:

[0098] The bias current ibn corresponds to the current ibn mentioned below.

[0099] Other potentials:

[0100] The ground potential avss corresponds to the ground potential avss mentioned below.

[0101] Control signals:

[0102] The control signal VOK_vcch corresponds to the signal VOK_vcch mentioned below.

[0103] Work mode:

[0104] The first working mode corresponds to Mode 1 in the following text.

[0105] The second working mode corresponds to Mode Two in the following text.

[0106] The embodiments, illustrations and related descriptions in this specification all use the original naming conventions. When reading, you can refer to the above correspondences for understanding. The scope of protection of this application shall be determined by the claims.

[0107] Furthermore, in this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "pmos1" and "first P-type LDMOS transistor pmos1" refer to the same technical feature, "VOK_vcch" and "control signal VOK_vcch" refer to the same technical feature, and other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to, the technical features mentioned above.

[0108] The following is a brief summary of some of the innovative aspects of this application:

[0109] In summary, in the field of high-voltage chip design, with the continuous expansion of applications such as electric vehicles, smart homes, and distributed power generation, increasingly higher demands are being placed on the chip's operating voltage range, power handling capabilities, and energy management efficiency. However, existing technologies for generating control potentials in the high-voltage domain generally suffer from technical problems such as large voltage loss, high power consumption, poor anti-interference capabilities, and susceptibility to instability. Especially... Figure 2 The traditional diode dio1 scheme shown and Figure 3 The solutions shown, which rely on the control signal Control, are all unable to simultaneously solve multiple problems such as voltage loss, control complexity, and system reliability, thus creating hidden dangers for the application of high-voltage chips.

[0110] Through long-term exploration and repeated experiments, the inventors of this application have developed a novel high-voltage domain controlled potential generation device. This device, as follows... Figure 1 As shown, it cleverly integrates the backflow prevention protection module, the voltage limiting module, the high voltage domain generation module, and the high voltage domain monitoring module into one unit. Through the intricate yet coordinated interaction among these modules, an adaptive, reliable, and interference-resistant control architecture is formed.

[0111] Specifically, this application employs many unique technical features in its circuit design: such as Figure 4 As shown, in the backflow prevention module, the characteristics of the P-type LDMOS transistors pmos1 and pmos2 array and their parasitic diodes, combined with the stabilizing effect of the Zener diode zd1, are cleverly used to construct an adaptive turn-on and turn-off mechanism. This avoids the voltage loss problem in traditional diode solutions and simplifies the control timing by eliminating the need for an external control signal. Figure 5As shown, in the high-voltage domain generation module, the conversion relationship between voltage VCCH and sampling voltage Vsns (VSSH = VCCH - Vzd + Vth) is realized through Zener diode zd2 voltage regulation, capacitors C1 and C2 filtering, and the precise coordination of P-type LDMOS transistor pmos4 and resistors R3, R4, and R5, providing a stable and reliable operating voltage for subsequent circuits; Figure 6 As shown, in the high voltage domain monitoring module, an RC filter network consisting of resistor R6 and capacitor C3 is used to suppress high-frequency interference. Together with n-type MOS transistor nmos2, capacitor C4, Schmitt trigger sm1 and inverter inv1, the difference between voltage VCCH and voltage VSSH is accurately monitored. Finally, the output signal VOK_vcch indicates the high voltage domain state, providing a basis for system control decisions.

[0112] Due to the innovative design and synergistic cooperation of the aforementioned technical features, the high-voltage domain control potential generation device of this application exhibits many outstanding technical effects: it can not only adaptively respond to changes in power supply voltage VIN and adjust its working state in real time, but also reliably protect the system from damage through the energy storage function of the external capacitor CL in the event of power supply sudden changes or even power failure, thus significantly improving the overall working stability of the high-voltage chip; at the same time, the device also integrates high-voltage domain monitoring functions, which greatly facilitates subsequent logic control and failure protection judgment, and improves the system's intelligence level; more importantly, the device of this application does not require complex external control, but can cope with changing operating conditions, reducing design difficulty while ensuring control reliability, demonstrating extremely high technical value.

[0113] In summary, the high-voltage domain control potential generation device proposed in this application addresses the practical challenges faced in the design of high-voltage chips. It tackles multiple technical challenges from various perspectives, comprehensively resolving core technical difficulties such as stability, reliability, and power consumption in the high-voltage domain control potential generation process through innovative circuit design, ingenious functional integration, and sophisticated complementary control. The entire device architecture is streamlined yet sophisticated, with efficient and robust control, and diverse yet coordinated functions, demonstrating the inventor's extraordinary creativity and unique technical conception. Undoubtedly, this application holds significant technical importance in related fields and will have a positive impact on promoting the widespread application and technological advancement of high-voltage chips.

[0114] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0115] like Figures 1 to 6 As shown, the first embodiment of this application relates to a high-voltage domain controlled potential generating device, comprising:

[0116] The backflow prevention module has an input terminal connected to the power supply voltage VIN and an output terminal outputting voltage VCCH, with an external capacitor CL connected to the chip.

[0117] The voltage limiting module has a first input terminal connected to the power supply voltage VIN, a second input terminal connected to the voltage VCCH, and an output terminal outputting current ibn.

[0118] A high voltage domain generation module has its input terminal connected to the voltage VCCH, its first output terminal outputting voltage VSSH, and its second output terminal outputting high voltage domain sampling voltage Vsns.

[0119] The high voltage domain monitoring module has a first input terminal connected to the voltage VCCH, a second input terminal connected to the current ibn, a third input terminal connected to the high voltage domain sampling voltage Vsns, a fourth input terminal connected to the voltage VSSH, and an output terminal that outputs the signal VOK_vcch.

[0120] The high-voltage domain control potential generating device operates as follows:

[0121] When the power supply voltage VIN rises from 0, the power supply voltage VIN is input to the anti-backflow protection module to charge the external capacitor, so that the voltage VCCH starts to rise synchronously. At the same time, the voltage limiting module starts to work automatically and outputs the current ibn.

[0122] When the voltage VCCH rises from 0, the high voltage domain generation module outputs the voltage VSSH and the high voltage domain sampling voltage Vsns, and the voltage VSSH and the high voltage domain sampling voltage Vsns rise synchronously with the voltage VCCH.

[0123] When the voltage VCCH rises from 0 to a set threshold, the high voltage domain monitoring module, after receiving the high voltage domain sampling voltage Vsns, outputs the signal VOK_vcch according to the state of the voltage VCCH.

[0124] Once the power supply voltage VIN has risen and stabilized, if the power supply voltage VIN suddenly drops, the anti-backflow protection module triggers the protection mechanism. The path between the voltage VCCH and the power supply voltage VIN is forcibly disconnected. Due to the voltage regulation effect of the external capacitor, the voltage VCCH slowly decreases to ensure the normal operation of the system for a period of time and avoid irreversible damage to the system caused by a sudden power failure.

[0125] Optional, see Figure 4The backflow prevention module includes: a resistor R1, whose input terminal is connected to the power supply voltage VIN and whose output terminal outputs voltage VIN_in; a P-type LDMOS transistor pmos1, whose drain is connected to voltage VIN_in, whose source is connected to voltage Vsh, and whose gate is connected to voltage Vgh; a P-type LDMOS transistor pmos2, whose drain is connected to voltage VCCH, whose source is connected to voltage Vsh, and whose gate is connected to voltage Vgh; a Zener diode zd1, whose anode is connected to voltage Vgh and whose cathode is connected to voltage Vsh; and a resistor R2, one end of which is connected to voltage Vgh and the other end of which is connected to voltage VCCH.

[0126] Optional, see Figure 5 The high-voltage domain generation module includes: a Zener diode zd2, whose anode is connected to the voltage VCCH and whose cathode is connected to the voltage Vg; a resistor R3, one end of which is connected to the voltage Vg and the other end of which is connected to the voltage Vbn; an n-type MOSFET nmos1, whose source is connected to ground potential avss, and whose gate and drain are short-circuited and connected to the voltage Vbn; a capacitor C1, one end of which is connected to the voltage VCCH and the other end of which is connected to the voltage Vg; a capacitor C2, one end of which is connected to the voltage VCCH and the other end of which is connected to the voltage VSSH; a p-type MOSFET pmos3, whose source is connected to the voltage VCCH, and whose gate and drain are short-circuited and connected to the voltage Vbp; a resistor R4, one end of which is connected to the voltage Vbp and the other end of which is connected to the high-voltage domain sampling voltage Vsns; a resistor R5, one end of which is connected to the high-voltage domain sampling voltage Vsns and the other end of which is connected to the voltage VSSH; and a p-type LDMOS transistor pmos4, whose source is connected to the voltage VSSH, whose gate is connected to the voltage Vg, and whose drain is connected to the ground potential avss.

[0127] Optional, see Figure 6 The high-voltage domain monitoring module includes: a resistor R6, one end of which is connected to the high-voltage domain sampling voltage Vsns, and the other end of which is connected to voltage Vsns_ft; a capacitor C3, one end of which is connected to voltage Vsns_ft, and the other end of which is connected to voltage VSSH; an n-type MOSFET nmos2, the source of which is connected to voltage VSSH, the drain of which is connected to voltage Vibn, and the gate of which is connected to voltage Vsns_ft; a capacitor C4, one end of which is connected to voltage VCCH, and the other end of which is connected to voltage Vibn; a Schmitt trigger sm1, the input of which is connected to voltage Vibn, the power supply of which is connected to voltage VCCH, the ground of which is connected to voltage VSSH, and the output of which is connected to the input of inverter INV1; the power supply and ground of inverter INV1 are respectively connected to voltage VCCH and voltage VSSH, and the output of inverter INV1 outputs the signal VOK_vcch.

[0128] Optional, see Figure 4 When the power supply voltage VIN rises from 0V, due to the parasitic diode of the P-type LDMOS transistor pmos1, the power supply voltage VIN will charge the source of the P-type LDMOS transistor pmos1. The resistor R1 limits the current protection circuit. When the voltage Vsh is charged to the threshold voltage Vth of the P-type LDMOS transistor, the P-type LDMOS transistors pmos1 and pmos2 begin to conduct. The power supply voltage VIN charges the external capacitor through the channels of the P-type LDMOS transistors pmos1 and pmos2, causing the voltage VCCH to rise. The Zener diode zd1 simultaneously stabilizes the gate and source voltage difference of the P-type LDMOS transistors pmos1 and pmos2, protecting the P-type LDMOS transistors pmos1 and pmos2 from overvoltage problems.

[0129] Optional, see Figure 4 When the power supply voltage VIN is suddenly de-energized after stabilization, due to the parasitic diode of the P-type LDMOS transistor pmos2, the source voltages of the P-type LDMOS transistors pmos1 and pmos2 will be charged and maintained by the voltage VCCH. At this time, the voltage Vsh is equal to the voltage VCCH minus the forward voltage drop Vdio of the parasitic diode. Meanwhile, the source voltages of the P-type LDMOS transistors pmos1 and pmos2 are equal to the voltage VCCH. This causes the P-type LDMOS transistors pmos1 and pmos2 to enter the off state, thereby automatically disconnecting the path between the power supply voltage VIN and the voltage VCCH, effectively preventing the current of the voltage VCCH from flowing back into the power supply voltage VIN terminal.

[0130] Optional, see Figure 5 The relationship between the voltage VSSH and the voltage VCCH satisfies the following formula: VSSH=VCCH-Vzd+Vth, where Vzd is the Zener voltage of the Zener diode zd2 and Vth is the threshold voltage of the P-type LDMOS transistor pmos4.

[0131] Optional, see Figure 6 When the high-voltage domain sampling voltage Vsns is greater than the threshold voltage of the n-type MOS transistor, the n-type MOS transistor nmos2 starts to pull down the voltage Vibn. When the pull-down capability is greater than the pull-up capability of the current ibn, the voltage Vibn gradually decreases until the output of the Schmitt trigger sm1 flips to output a low level, and the inverter INV1 outputs a high-level signal VOK_vcch.

[0132] To make the technical solution of this application clearer and more understandable, the following is combined with Figures 1 to 6 Preferred embodiments of this application are described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0133] Figure 1 The overall architecture of a high-voltage domain controlled potential generation device is shown. For example... Figure 1 As shown, the device includes four main functional modules: backflow prevention module, voltage limiting module, high voltage domain generation module, and high voltage domain monitoring module.

[0134] The backflow prevention module's input is connected to the power supply voltage VIN, and its output is the output voltage VCCH connected to an external capacitor CL. This module effectively prevents current from flowing back from the load to the power supply. When the power supply voltage VIN fails, it automatically disconnects the path between VIN and VCCH, utilizing the energy storage characteristics of the external capacitor CL to ensure that the system can continue to operate normally for a period of time in the event of a sudden power failure.

[0135] The voltage limiting module has its first input connected to the power supply voltage VIN, its second input connected to the voltage VCCH, and its output terminal outputting a current ibn. This module provides a stable bias current ibn to the system and automatically starts during system operation without requiring an external control signal.

[0136] The high-voltage domain generation module has an input connected to the voltage VCCH, a first output voltage VSSH, and a second output voltage Vsns. This module generates a high-voltage domain control potential, where VSSH serves as the ground potential of the high-voltage domain and, together with VCCH, forms a complete high-voltage domain. Simultaneously, the output sampling voltage Vsns is used to monitor the state of the high-voltage domain.

[0137] The high-voltage domain monitoring module has its first input connected to voltage VCCH, its second input connected to current ibn, its third input connected to the high-voltage domain sampling voltage Vsns, and its fourth input connected to voltage VSSH. The output is the signal VOK_vcch. This module monitors the high-voltage domain voltage in real time to ensure it remains within the allowable operating range. When the high-voltage domain is operating normally, it outputs a high-level signal VOK_vcch, facilitating subsequent logic design.

[0138] The signal flow direction of the entire system is as follows Figure 1As shown, the power supply voltage VIN first enters the reverse current protection module, generating voltage VCCH and charging the external capacitor CL. Voltage VCCH serves as the power supply potential input to the high-voltage domain generation module, generating voltage VSSH and sampling voltage Vsns. The voltage limiting module provides the bias current ibn. Finally, the high-voltage domain monitoring module receives these signals, monitors the operating status of the high-voltage domain, and outputs the signal VOK_vcch. This architecture design ensures reliable system operation under sudden power surges, eliminating the need for external enable signals and significantly improving system reliability.

[0139] Figure 2 The circuit structure of a traditional diode-based reverse current protection scheme is shown. For example... Figure 2 As shown, the circuit includes a power supply voltage VIN, a diode dio1, an output voltage Vout1, and a capacitor Cin. In this traditional scheme, the power supply voltage VIN is connected to the output terminal Vout1 through the diode dio1, and the capacitor Cin is connected between VIN and ground. The diode dio1 utilizes its unidirectional conductivity to allow current to flow from VIN to Vout1 while preventing current from flowing back from Vout1 to VIN, thus achieving basic reverse current protection. However, this traditional scheme has significant drawbacks. First, the diode dio1 has a forward voltage drop, resulting in a voltage loss from VIN to Vout1, increasing system power consumption. Second, in practical applications, special attention needs to be paid to the isolation of the diode device to avoid transistor effects. These problems limit the effectiveness of this scheme in high-voltage, low-power scenarios. Compared to... Figure 1 The traditional diode solution, while simple in structure, cannot meet the demands of modern high-voltage chips for high efficiency, low loss, and high reliability, especially in terms of limited protection against sudden power surges. This embodiment successfully overcomes the aforementioned shortcomings of the traditional diode solution through a more complex but more efficient reverse-current protection mechanism.

[0140] Figure 3 The circuit structure of another backflow prevention protection scheme that relies on control signals and logic is shown. For example... Figure 3 As shown, the circuit includes a power supply voltage VIN, P-type MOSFETs pm1 and pm2, an N-type MOSFET nm1, resistors res1, res2 and res3, a control signal Control, and an output voltage Vout2.

[0141] In this circuit, the power supply voltage VIN is connected to the drain of the P-type MOSFET pm1, and the source of pm1 is connected to the drain of pm2 through resistor res1. The source output voltage of pm2 is Vout2. P-type MOSFETs pm1 and pm2 have parasitic diodes pdio1 and pdio2, respectively. The gate of the N-type MOSFET nm1 is connected to the control signal Control through resistor res3, the drain of nm1 is connected to the gates of pm1 and pm2, and the source of nm1 is connected to ground through resistor res2.

[0142] The working principle of this scheme is to control the N-type MOSFET nm1 by the control signal Control, thereby adjusting the gate voltage of the P-type MOSFETs pm1 and pm2, thus controlling the on and off states of pm1 and pm2, realizing bidirectional switching function, and preventing current backflow.

[0143] However, this approach has significant drawbacks. First, it heavily relies on external control signals and complex logic circuits, making the design quite complex. Second, in high-voltage environments, the design difficulty increases significantly due to the need for precise control of multiple transistor states. Furthermore, the high timing requirements of the control signals increase the system's complexity and instability.

[0144] In contrast, this embodiment, for example Figure 1 The proposed solution does not rely on external control signals and achieves backflow protection through an adaptive circuit structure, which greatly simplifies system design, improves system reliability, and is particularly suitable for applications in high-voltage environments.

[0145] Figure 4 The detailed circuit structure of the backflow prevention protection module in the high-voltage domain control potential generation device proposed in this embodiment is shown. Figure 4 As shown, the module includes resistors R1 and R2, P-type LDMOS transistors pmos1 and pmos2, Zener diode zd1, power supply voltage VIN, voltage VIN_in, voltage Vgh, voltage Vsh, voltage VCCH, and external capacitor CL.

[0146] In this circuit, the input terminal of resistor R1 is connected to the power supply voltage VIN, and the output terminal outputs the voltage VIN_in. The drain of the P-type LDMOS transistor pmos1 is connected to VIN_in, the source to Vsh, and the gate to Vgh. The drain of the P-type LDMOS transistor pmos2 is connected to VCCH, the source to Vsh, and the gate to Vgh. The anode of the Zener diode zd1 is connected to Vgh, and the cathode to Vsh. One end of resistor R2 is connected to voltage Vgh, and the other end is connected to voltage VCCH. An external capacitor CL is connected between voltage VCCH and ground.

[0147] The anti-backflow protection module operates in two modes: Mode 1 and Mode 2. In Mode 1, when the chip is not powered on, the initial values ​​of voltages VCCH and VSSH are both 0. When the chip powers on, the power supply voltage VIN rises from 0V. Due to the parasitic diode of the P-type LDMOS transistor pmos1, the power supply voltage VIN charges the source voltage Vsh of pmos1, and resistor R1 limits the current protection circuit. When voltage Vsh is charged to the threshold voltage Vth of the P-type LDMOS transistor, Pmos1 and Pmos2 begin to conduct. The power supply voltage VIN charges the external capacitor CL through the channels of Pmos1 and Pmos2, causing voltage VCCH to rise accordingly. At the same time, Zener diode zd1 begins to stabilize the voltage difference between the gate voltage Vgh and the source voltage Vsh of P-type LDMOS transistors pmos1 and pmos2, protecting P-type LDMOS transistors pmos1 and pmos2 from overvoltage problems.

[0148] In Mode 2, after the chip has been powered on and stabilized, if the power supply voltage VIN suddenly drops, due to the parasitic diode of the P-type LDMOS transistor pmos2, the source voltage Vsh of both P-type LDMOS transistors pmos1 and pmos2 will be charged high by the voltage VCCH and maintained. At this time, the voltage Vsh is equal to the voltage VCCH minus the forward voltage drop Vdio of the parasitic diode. Meanwhile, the source voltage of both P-type LDMOS transistors pmos1 and pmos2 is equal to the voltage VCCH. This causes P-type LDMOS transistors pmos1 and pmos2 to enter the off state, thereby automatically disconnecting the path between the power supply voltage VIN and the voltage VCCH, effectively preventing current from flowing back into the power supply terminal from the VCCH terminal.

[0149] The circuit structure of this backflow prevention module is very simple. It can automatically achieve backflow prevention without relying on external control signals. It can effectively protect the system in the event of sudden changes in power supply voltage, greatly improving the reliability and stability of the system.

[0150] Figure 5 The detailed circuit structure of the high-voltage domain generation module in the high-voltage domain control potential generation device proposed in this embodiment is shown. For example... Figure 5 As shown, the module includes Zener diode zd2, resistors R3, R4 and R5, n-type MOSFET nmos1, capacitors C1 and C2, p-type MOSFET pmos3, p-type LDMOS transistor pmos4, voltages VCCH, Vg, Vbn, Vbp, high-voltage domain sampling voltage Vsns, voltage VSSH, and ground potential avss.

[0151] In this circuit, the anode of Zener diode zd2 is connected to voltage VCCH, and the cathode is connected to voltage Vg. One end of capacitor C1 is connected to voltage VCCH, and the other end is connected to voltage Vg, in parallel with Zener diode zd2. One end of resistor R3 is connected to voltage Vg, and the other end is connected to voltage Vbn. The source of n-type MOSFET nmos1 is connected to ground potential avss, and the gate and drain are short-circuited and connected to voltage Vbn, forming a diode connection structure. The source of p-type MOSFET pmos3 is connected to voltage VCCH, and the gate and drain are short-circuited and connected to voltage Vbp, also forming a diode connection structure. One end of resistor R4 is connected to voltage Vbp, and the other end is connected to the high-voltage domain sampling voltage Vsns. One end of resistor R5 is connected to the high-voltage domain sampling voltage Vsns, and the other end is connected to voltage VSSH. One end of capacitor C2 is connected to voltage VCCH, and the other end is connected to voltage VSSH. The source of p-type LDMOS transistor pmos4 is connected to voltage VSSH, the gate is connected to voltage Vg, and the drain is connected to ground potential avss.

[0152] In this high-voltage domain generation module, Zener diode ZD2 and capacitor C1 are used to stabilize voltage Vg. Resistor R3 and n-type MOSFET NMOS1 are used to limit current. P-type MOSFET PMOS3, resistors R4 and R5, and capacitor C2 are used to stabilize voltage VSSH. By adjusting the resistance ratio of resistors R4 and R5, the value of the high-voltage domain sampling voltage Vsns relative to voltage VCCH can be adjusted, providing a reference for subsequent high-voltage domain monitoring. P-type LDMOS transistor PMOS4 is used to maintain voltage VSSH and withstand high voltage.

[0153] The core function of this module is to generate the high-voltage domain control potential VSSH, which is related to the voltage VCCH as VSSH = VCCH - Vzd + Vth, where Vzd is the Zener voltage of the Zener diode zd2 and Vth is the threshold voltage of the P-type LDMOS transistor pmos4. In this way, the high-voltage domain generation module establishes a stable high-voltage domain, with the power supply potential of the high-voltage domain being voltage VCCH and the ground potential being voltage VSSH. This simplifies subsequent high-voltage design and avoids the need to use a large number of LDMOS transistors to withstand high voltage.

[0154] This high-voltage domain generation module has a compact structure and well-defined functions. It can reliably generate the required high-voltage domain control potential, providing a solid power environment foundation for the entire system.

[0155] Figure 6 The detailed circuit structure of the high-voltage domain monitoring module in the high-voltage domain control potential generation device proposed in this embodiment is shown. For example... Figure 6As shown, the module includes resistor R6, capacitors C3 and C4, n-type MOSFET nmos2, Schmitt trigger sm1, inverter INV1, voltage VCCH, current ibn, high-voltage domain sampling voltage Vsns, voltage Vsns_ft, voltage VSSH, and output signal VOK_vcch.

[0156] In this circuit, one end of resistor R6 is connected to the high-voltage domain sampling voltage Vsns, and the other end is connected to voltage Vsns_ft. One end of capacitor C3 is connected to voltage Vsns_ft, and the other end is connected to voltage VSSH. The source of the n-type MOSFET nmos2 is connected to voltage VSSH, the drain to voltage Vibn, and the gate to voltage Vsns_ft. One end of capacitor C4 is connected to voltage VCCH, and the other end is connected to voltage Vibn. The input of Schmitt trigger sm1 is connected to voltage Vibn, the power supply to voltage VCCH, and the ground to voltage VSSH. The output is connected to the input of inverter INV1. The power supply and ground of inverter INV1 are connected to voltage VCCH and voltage VSSH, respectively, and the output is the signal VOK_vcch.

[0157] The high-voltage domain monitoring module works as follows: Based on the high-voltage domain sampling voltage Vsns, when Vsns exceeds the threshold voltage of an n-type MOSFET, the n-type MOSFET nmos2 begins to pull down the voltage Vibn. When the pull-down capability of nmos2 exceeds the pull-up capability of the current ibn, the voltage Vibn gradually decreases until the output of the Schmitt trigger sm1 flips, outputting a low level. After passing through the inverter INV1, a high-level signal VOK_vcch is finally output, indicating that the high-voltage domain is working normally.

[0158] The use of Schmitt trigger sm1 improves the circuit's anti-interference capability and avoids false triggering at critical states. Inverter INV1 ensures the correct polarity output of signal VOK_vcch. The entire monitoring circuit has a simple structure and complete functions, capable of real-time monitoring of the high-voltage domain's operating status. When the difference between voltage VCCH and voltage VSSH reaches a set threshold, it outputs signal VOK_vcch, facilitating subsequent logic design.

[0159] This high-voltage domain monitoring module is a crucial component of this embodiment. By monitoring the actual state of the high-voltage domain in real time, it significantly improves the reliability of the system. Compared to traditional high-voltage domain generation technologies, this embodiment adds this monitoring function, enabling the system to understand the operating status of the high-voltage domain and make timely adjustments, effectively avoiding instability that may occur under high-voltage environments.

[0160] The working principle of the high-voltage domain controlled potential generation device proposed in this embodiment is as follows:

[0161] As the power supply voltage VIN rises from 0, it charges the external capacitor CL through the reverse current protection module. For example... Figure 4 As shown, the power supply voltage VIN is first input to the drain of the P-type LDMOS transistor pmos1 through resistor R1. Due to the parasitic diode of the P-type LDMOS transistor pmos1, the power supply voltage VIN charges the source voltage Vsh of the P-type LDMOS transistor pmos1. When the voltage Vsh is charged up to the threshold voltage Vth of the P-type LDMOS transistor, both P-type LDMOS transistors pmos1 and pmos2 begin to conduct. The power supply voltage VIN charges the external capacitor CL through the channels of the P-type LDMOS transistors pmos1 and pmos2, causing the voltage VCCH to rise synchronously. At the same time, the Zener diode zd1 begins to stabilize the voltage difference between the gate and source of the P-type LDMOS transistors pmos1 and pmos2, protecting them from overvoltage problems.

[0162] Simultaneously, the voltage limiting module begins to operate automatically and outputs a current ibn. This current is used in subsequent high-voltage domain monitoring.

[0163] As the voltage VCCH rises from 0, it is input to the high-voltage domain generation module. For example... Figure 5 As shown, voltage VCCH generates a stable voltage Vg through Zener diode zd2 and capacitor C1. The gate of the P-type LDMOS transistor pmos4 is connected to voltage Vg, the source is connected to voltage VSSH, and the drain is connected to ground potential avss. Due to the characteristics of the P-type LDMOS transistor pmos4, when voltage VCCH rises, voltage VSSH also rises accordingly. The relationship can be expressed as: VSSH = VCCH - Vzd + Vth, where Vzd is the Zener voltage of Zener diode zd2, and Vth is the threshold voltage of P-type LDMOS transistor pmos4. Simultaneously, a high-voltage domain sampling voltage Vsns is generated through the voltage divider network of p-type MOS transistor pmos3 and resistors R4 and R5. This voltage is used for subsequent monitoring. Therefore, voltage VSSH and high-voltage domain sampling voltage Vsns rise synchronously with voltage VCCH.

[0164] Once the voltage VCCH rises from 0 to the set threshold, the high-voltage domain monitoring module begins operation. For example... Figure 6As shown, the high-voltage domain sampling voltage Vsns is input to voltage Vsns_ft through resistor R6 and connected to the gate of the n-type MOSFET nmos2. When the high-voltage domain sampling voltage Vsns is greater than the threshold voltage of the n-type MOSFET nmos2, nmos2 starts to conduct, pulling down voltage Vibn. When the pull-down capability of nmos2 is greater than the pull-up capability of the current ibn, voltage Vibn gradually decreases until the input voltage of Schmitt trigger sm1 is lower than its trigger threshold, at which point Schmitt trigger sm1 outputs a low level. After passing through inverter INV1, the final output signal is a high-level signal VOK_vcch, indicating that the high-voltage domain is working normally and the system can start normal operation.

[0165] Once the power supply voltage VIN has risen and stabilized, if a sudden power outage occurs, the backflow protection module will trigger its protection mechanism. For example... Figure 4 As shown, due to the parasitic diode of the P-type LDMOS transistor pmos2, the source voltages of both P-type LDMOS transistors pmos1 and pmos2 are clamped at VCCH-Vdio by the voltage VCCH, where Vdio is the forward voltage drop of the parasitic diode. The gate voltages of both P-type LDMOS transistors pmos1 and pmos2 are VCCH, which causes the gate-source voltages of both P-type LDMOS transistors pmos1 and pmos2 to be zero or negative, thus entering the turn-off state and automatically disconnecting the path between the power supply voltage VIN and the voltage VCCH. At this time, the voltage VCCH will decrease slowly due to the voltage regulation effect of the external capacitor CL, rather than suddenly dropping, thus ensuring that the system can operate normally for a period of time and avoiding irreversible damage to the system caused by a sudden power failure.

[0166] Throughout the entire operation, the high-voltage domain control potential generating device of this embodiment does not rely on any external control signal. It can automatically adjust the working mode according to the state of the power supply voltage VIN, realize the generation, monitoring and protection functions of the high-voltage domain, and greatly improve the reliability and stability of the system operation.

[0167] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0168] The high-voltage domain control potential generation device provided in this example includes a backflow prevention protection module, a voltage limiting module, a high-voltage domain generation module, and a high-voltage domain monitoring module; wherein:

[0169] The backflow prevention module has its input terminal connected to the power supply voltage VIN, and its output terminal outputs the voltage VCCH, with an external capacitor CL connected to it.

[0170] The voltage limiting module has its first input terminal connected to the power supply voltage VIN, its second input terminal connected to the voltage VCCH, and its output terminal outputting the current ibn.

[0171] The high voltage domain generation module is connected to the voltage VCCH at its input terminal, outputs the voltage VSSH at its first output terminal, and outputs the high voltage domain sampling voltage Vsns at its second output terminal.

[0172] The high voltage domain monitoring module has the following inputs: first input terminal connected to voltage VCCH, second input terminal connected to current ibn, third input terminal connected to voltage Vsns, fourth input terminal connected to voltage VSSH, and output signal VOK_vcch.

[0173] The high-voltage domain controlled potential generating device operates as follows:

[0174] When the power supply voltage VIN rises from 0, the power supply voltage VIN is input to the reverse current protection module to charge the external capacitor, causing the voltage VCCH to rise synchronously. At the same time, the voltage limiting module starts to work automatically and outputs current ibn.

[0175] When the voltage VCCH rises from 0, the voltage VCCH is input to the high voltage domain generation module, and the output voltage VSSH and the high voltage domain sampling voltage Vsns are output. The voltage VSSH and the voltage Vsns rise synchronously with the voltage VCCH.

[0176] When the voltage VCCH rises from 0 to the set threshold, the high voltage domain monitoring module will output the signal VOK_vcch according to the state of the voltage VCCH after receiving the high voltage domain sampling voltage Vsns.

[0177] Once the power supply voltage VIN has risen and stabilized, if a sudden power failure occurs, the backflow protection module will trigger the protection mechanism. The path between voltage VCCH and power supply voltage VIN will be forcibly disconnected. Due to the voltage regulation effect of the external capacitor, voltage VCCH will slowly decrease to ensure the normal operation of the system for a period of time and avoid irreversible damage to the system caused by a sudden power failure.

[0178] Preferably, the backflow prevention module includes: a resistor R1, whose input terminal is connected to the power supply voltage VIN and whose output terminal outputs the voltage VIN_in; a P-type LDMOS transistor pmos1, whose drain is connected to VIN_in, source to Vsh, and gate to Vgh; a P-type LDMOS transistor pmos2, whose drain is connected to VCCH, source to Vsh, and gate to Vgh; a Zener diode zd1, whose anode is connected to Vgh and cathode to Vsh; and a resistor R2, one end of which is connected to voltage Vgh and the other end to voltage VCCH. When the power supply voltage VIN rises to a certain value, the formula for voltage VCCH is as follows:

[0179] VCCH = VIN - Vth (1)

[0180] Where: Vth is the threshold voltage of the P-type LDMOS transistor.

[0181] Preferably, the high-voltage domain generation module includes: a Zener diode zd2, whose anode is connected to voltage VCCH and whose cathode is connected to voltage Vg; a resistor R3, one end of which is connected to voltage Vg and the other end to voltage Vbn; an n-type MOSFET nmos1, whose source is connected to ground potential avss, and whose gate and drain are short-circuited and connected to voltage Vbn; a capacitor C1, one end of which is connected to voltage VCCH and the other end to voltage Vg; a capacitor C2, one end of which is connected to voltage VCCH and the other end to the output signal VSSH; a p-type MOSFET pmos3, whose source is connected to voltage VCCH, and whose gate and drain are short-circuited and connected to voltage Vbp; a resistor R4, one end of which is connected to voltage Vbp and the other end to voltage Vsns; a resistor R5, one end of which is connected to voltage Vsns and the other end to the output voltage VSSH; and a p-type LDMOS transistor pmos4, whose source is connected to the output voltage VSSH, whose gate is connected to voltage Vg, and whose drain is connected to ground potential avss. The formula for voltage VSSH is as follows:

[0182] VSSH = VCCH - Vzd + Vth (2)

[0183] Where: Vzd is the Zener voltage of the Zener diode, and Vth is the threshold voltage of the P-type LDMOS transistor.

[0184] Preferably, the high-voltage domain monitoring module includes: a resistor R6, one end of which is connected to the first input voltage Vsns and the other end of which is connected to the voltage Vsns_ft; a capacitor C3, one end of which is connected to the voltage Vsns_ft and the other end of which is connected to the voltage VSSH; an n-type MOSFET nmos2, the source of which is connected to the voltage VSSH, the drain of which is connected to the second input voltage Vibn, and the gate of which is connected to the voltage Vsns_ft; a capacitor C4, one end of which is connected to the voltage VCCH and the other end of which is connected to the second input voltage Vibn; a Schmitt trigger sm1, the input of which is connected to the second input voltage Vibn, the power supply of which is connected to the voltage VCCH, the ground of which is connected to the voltage VSSH, and the output of which is connected to the input of an inverter INV1, the power supply and ground of which are connected to the voltage VCCH and VSSH, respectively.

[0185] Compared with existing technologies, the beneficial effects of this example are as follows:

[0186] This example avoids the traditional diode approach, ensuring driving capability and low voltage loss while avoiding the transistor effect. Furthermore, in actual operation, this example requires no complex logic timing control; it automatically starts when the power supply voltage VIN is powered on and automatically shuts off the path between the power supply voltage VIN and voltage VCCH when the power supply voltage VIN is powered off, thus avoiding energy loss.

[0187] Furthermore, this example generates control potentials for the high-voltage domain, with the power supply potential of the high-voltage domain being VCCH and the ground potential being VSSH. This simplifies subsequent high-voltage design by eliminating the need for a large number of LDMOS transistors to withstand high voltage. This example also features a VCCH detection function in the high-voltage domain. When (VCCH - VSSH) reaches a set threshold, it outputs the signal VOK_vcch, further simplifying subsequent logic design.

[0188] To elaborate further, please see Figures 1-6 The high-voltage domain controlled potential generating device provided in this example, such as... Figure 1 As shown. The main functional modules included in the system are: a backflow prevention module, which effectively prevents current from flowing back from the load end to the power supply end; a voltage limiting module, which provides a current source for the system; a high voltage domain generation module, which generates a high voltage domain control potential; and a high voltage domain monitoring module, which monitors in real time whether the high voltage domain is within the allowable operating voltage range.

[0189] Anti-backflow protection module such as Figure 4 As shown, its circuit structure is very simple. Resistors R1 and R2 are used to limit transient current. The parasitic diodes of the two sets of P-type LDMOS transistors pmos1 and pmos2 form a back-to-back structure. Zener diode Zd1 is used to stabilize the voltage difference between the gate and source of P-type LDMOS transistors pmos1 and pmos2. Its operating mode is as follows:

[0190] Mode 1: When the chip is not powered on, the initial values ​​of voltages VCCH and VSSH are both 0. When the chip is powered on, the power supply voltage VIN rises from 0V. At this time, due to the parasitic diode of the P-type LDMOS transistor pmos1, the power supply voltage VIN will charge the source (voltage Vsh) of the P-type LDMOS transistor pmos1. Resistor R1 limits the current protection circuit. When the voltage Vsh is charged to a threshold voltage Vth of the P-type LDMOS transistor, the P-type LDMOS transistors pmos1 and pmos2 start to conduct. The power supply voltage VIN charges the external capacitor through the channel of the P-type LDMOS transistors pmos1 and pmos2, causing the voltage VCCH to start to rise accordingly. Zener diode ZD1 also starts to stabilize the gate and source voltage difference of the P-type LDMOS transistors pmos1 and pmos2, protecting the P-type LDMOS transistors pmos1 and pmos2 from overvoltage problems.

[0191] Mode 2: After the chip is powered on and stabilized, if the power supply voltage VIN suddenly drops, the source voltages of P-type LDMOS transistors pmos1 and pmos2 will be charged and maintained by the voltage VCCH due to the parasitic diode of P-type LDMOS transistor pmos2. At this time, the voltage Vsh = VCCH - Vdio, where Vdio is the voltage drop of the parasitic diode. Since the source voltages of P-type LDMOS transistors pmos1 and pmos2 are VCCH, this causes P-type LDMOS transistors pmos1 and pmos2 to enter the off state, thereby automatically disconnecting the path between the power supply voltage VIN and the voltage VCCH, effectively preventing the current at the voltage VCCH from flowing back into the power supply terminal.

[0192] High voltage domain generation module such as Figure 5 As shown, the system includes: Zener diode zd2 and capacitor C1 for stabilizing voltage Vg; resistor R3 and n-type MOSFET nmos1 for limiting current; p-type MOSFET pmos3 and resistors R4 and R5 and capacitor C2 for stabilizing voltage VSSH. The value of the sampling voltage Vsns relative to voltage VCCH can be adjusted by adjusting the ratio of resistors R4 and R5; and p-type LDMOS transistor pmos4 is used to maintain voltage VSSH and withstand high voltage.

[0193] High voltage domain monitoring module, such as Figure 6 As shown, based on the value of the sampling voltage Vsns, when the voltage Vsns is greater than the threshold voltage of an n-type MOS transistor, the n-type MOS transistor nmos2 starts to pull down the voltage Vibn. When the pull-down capability is greater than the pull-up capability of the current ibn, the voltage Vibn gradually decreases until the output of the Schmitt trigger sm1 flips to output a low level, and then outputs a high-level signal VOK_vcch through the inverter INV1.

[0194] The above embodiments have the following technical effects:

[0195] By using an array structure of P-type LDMOS transistors pmos1 and pmos2 in the backflow prevention module, and utilizing their parasitic diode characteristics, adaptive conduction control between the power supply voltage VIN and the voltage VCCH is achieved. Figure 2 Compared to the traditional diode solution shown, this solution avoids the voltage drop and increased power consumption caused by the forward voltage drop of the diode dio1, and eliminates the need for additional device isolation, thus avoiding the transistor effect.

[0196] and Figure 3 Compared to the traditional scheme that relies on an external control signal Control, the above embodiment does not require complex logic timing control during actual operation. When the power supply voltage VIN is powered on, the backflow protection module automatically starts and when the power supply voltage VIN is powered off, it automatically shuts off the path between the power supply voltage VIN and the voltage VCCH, avoiding energy loss and system instability. It is particularly suitable for applications in high-voltage environments.

[0197] The high-voltage domain generation module in the above embodiment utilizes components such as Zener diode zd2, resistors R3-R5, and P-type LDMOS transistor pmos4 (e.g., Figure 5 As shown, this generates the control potentials VCCH and VSSH in the high-voltage domain, simplifying subsequent high-voltage circuit design. It eliminates the need for numerous LDMOS transistors to withstand the high voltage, reducing design complexity and cost. The high-voltage domain monitoring module (such as...) generates the control potentials VCCH and VSSH in the high-voltage domain, simplifying subsequent high-voltage circuit design. It eliminates the need for numerous LDMOS transistors to withstand the high voltage, reducing design complexity and cost. Figure 6 As shown, the high voltage domain voltages VCCH and VSSH are monitored in real time through an n-type MOS transistor nmos2, a Schmitt trigger sm1, and an inverter inv1. When the high voltage domain is working normally, the output signal VOK_vcch is provided, which facilitates subsequent logic control.

[0198] The entire high-voltage domain control potential generation device adopts an adaptive structural design, independent of external control. It automatically realizes high-voltage domain potential generation, monitoring, and protection functions based on the power supply voltage VIN state, significantly improving the reliability and stability of the system. Especially in the event of a sudden power failure, the voltage regulation effect of the external capacitor CL causes the voltage VCCH to decrease slowly, providing sufficient buffer time for the system and avoiding the risk of system damage under high-voltage conditions.

[0199] In summary, the high-voltage domain control potential generation device proposed in the above embodiments has a simple circuit structure, is easy to control, and is reliable in operation. It overcomes many defects existing in the prior art and has broad application prospects in the field of high-voltage chip design.

[0200] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0201] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A high-voltage domain controlled potential generating device, characterized in that, include: The backflow prevention module has an input voltage (VIN) connected to its input terminal and a high voltage domain power supply potential (VCCH) output terminal, and an external capacitor (CL) connected to the chip. The voltage limiting module has a first input terminal connected to the input voltage, a second input terminal connected to the high voltage domain power supply potential, and an output terminal that outputs a bias current (ibn). The high voltage domain generation module has its input terminal connected to the high voltage domain power supply potential, its first output terminal outputting the high voltage domain ground potential (VSSH), and its second output terminal outputting the high voltage domain sampling voltage (Vsns). The high voltage domain monitoring module has a first input terminal connected to the high voltage domain power supply potential, a second input terminal connected to the bias current, a third input terminal connected to the high voltage domain sampling voltage, a fourth input terminal connected to the high voltage domain ground potential, and an output terminal outputting a control signal (VOK_vcch). The high-voltage domain controlled potential generating device operates as follows: When the input voltage rises from 0, the input voltage is input to the anti-backflow protection module to charge the external capacitor, so that the high voltage domain power supply potential starts to rise synchronously. At the same time, the voltage limiting module starts to work automatically and outputs the bias current. When the high voltage domain power supply potential rises from 0, the high voltage domain generation module outputs the high voltage domain ground potential and the high voltage domain sampling voltage, and the high voltage domain ground potential and the high voltage domain sampling voltage rise synchronously with the high voltage domain power supply potential. When the high voltage domain power supply potential rises from 0 to a set threshold, the high voltage domain monitoring module, upon receiving the high voltage domain sampling voltage, outputs the control signal according to the state of the high voltage domain power supply potential. Once the input voltage has risen and stabilized, if a sudden power failure occurs, the anti-backflow protection module triggers the protection mechanism. The path between the high-voltage power supply potential and the input voltage is forcibly disconnected. Due to the voltage stabilization effect of the external capacitor, the high-voltage power supply potential slowly decreases to ensure the normal operation of the system for a period of time and avoid irreversible damage to the system caused by a sudden power failure.

2. The high-voltage domain controlled potential generating device according to claim 1, characterized in that, The backflow prevention module includes: a first resistor (R1), whose input terminal is connected to the input voltage and whose output terminal outputs the input node voltage (VIN_in); a first P-type lateral diffused metal-oxide-semiconductor transistor (PDMOS) pmos1, whose drain is connected to the input node voltage, whose source is connected to the second control voltage (Vsh), and whose gate is connected to the first control voltage (Vgh); a second P-type PDMOS transistor pmos2, whose drain is connected to the high voltage domain power supply potential, whose source is connected to the second control voltage, and whose gate is connected to the first control voltage; a first Zener diode (zd1), whose anode is connected to the first control voltage and whose cathode is connected to the second control voltage; and a second resistor (R2), one end of which is connected to the first control voltage and the other end of which is connected to the high voltage domain power supply potential.

3. The high-voltage domain controlled potential generating device according to claim 1, characterized in that, The high-voltage domain generation module includes: a second Zener diode (zd2), whose anode is connected to the high-voltage domain power supply potential and whose cathode is connected to the third control voltage (Vg); a third resistor (R3), one end of which is connected to the third control voltage and the other end of which is connected to the fourth control voltage (Vbn); a first N-type metal-oxide-semiconductor transistor (NMOS) nmos1, whose source is connected to ground potential (avss), and whose gate and drain are short-circuited and connected to the fourth control voltage; a first capacitor (C1), one end of which is connected to the high-voltage domain power supply potential and the other end of which is connected to the third control voltage; and a second capacitor (C2), one end of which is connected to the high-voltage domain power supply potential. The first P-type metal-oxide-semiconductor transistor (PMOS3) has its source connected to the high-voltage domain power supply potential, and its gate and drain short-circuited and connected to the fifth control voltage (Vbp); the fourth resistor (R4) has one end connected to the fifth control voltage and the other end connected to the high-voltage domain sampling voltage; the fifth resistor (R5) has one end connected to the high-voltage domain sampling voltage and the other end connected to the high-voltage domain ground potential; the second P-type MOS transistor (PMOS4) has its source connected to the high-voltage domain ground potential, its gate connected to the third control voltage, and its drain connected to the ground potential.

4. The high-voltage domain controlled potential generating device according to claim 1, characterized in that, The high-voltage domain monitoring module includes: a sixth resistor (R6), one end of which is connected to the high-voltage domain sampling voltage, and the other end of which is connected to the seventh control voltage (Vsns_ft); a third capacitor (C3), one end of which is connected to the seventh control voltage, and the other end of which is connected to the high-voltage domain ground potential; a second N-type MOS transistor nmos2, the source of which is connected to the high-voltage domain ground potential, the drain of which is connected to the sixth control voltage (Vibn), and the gate of which is connected to the seventh control voltage; a fourth capacitor (C4), one end of which is connected to the high-voltage domain power supply potential, and the other end of which is connected to the sixth control voltage; a first Schmitt trigger (sm1), the input of which is connected to the sixth control voltage, the power supply of which is connected to the high-voltage domain power supply potential, the ground of which is connected to the high-voltage domain ground potential, and the output of which is connected to the input of a first inverter (INV1); the power supply and ground of the first inverter are respectively connected to the high-voltage domain power supply potential and the high-voltage domain ground potential, and the output of the first inverter outputs the control signal.

5. The high-voltage domain controlled potential generating device according to claim 2, characterized in that, When the input voltage rises from 0V, due to the parasitic diode of the first P-type LDMOS transistor, the input voltage charges the source of the first P-type LDMOS transistor. The first resistor limits the current protection circuit. When the second control voltage is charged to the threshold voltage (Vth), the first P-type LDMOS transistor and the second P-type LDMOS transistor begin to conduct. The input voltage charges the external capacitor through the channels of the first P-type LDMOS transistor and the second P-type LDMOS transistor, causing the high-voltage power supply potential to rise. The first Zener diode simultaneously stabilizes the gate and source voltage difference of the first P-type LDMOS transistor and the second P-type LDMOS transistor, protecting the first P-type LDMOS transistor and the second P-type LDMOS transistor from overvoltage problems.

6. The high-voltage domain controlled potential generating device according to claim 2, characterized in that, When the input voltage is suddenly de-energized after stabilizing, due to the parasitic diode of the second P-type LDMOS transistor, the source voltages of the first and second P-type LDMOS transistors will be charged and maintained by the high-voltage power supply potential. At this time, the second control voltage is equal to the high-voltage power supply potential minus the parasitic diode voltage drop (Vdio). Meanwhile, the source voltages of the first and second P-type LDMOS transistors are equal to the high-voltage power supply potential. This causes the first and second P-type LDMOS transistors to enter the off state, thereby automatically disconnecting the path between the input voltage and the high-voltage power supply potential, effectively preventing the current from the high-voltage power supply potential from flowing back into the input voltage terminal.

7. The high-voltage domain controlled potential generating device according to claim 3, characterized in that, The relationship between the high-voltage domain ground potential and the high-voltage domain power supply potential satisfies the following formula: VSSH=VCCH-Vzd+Vth, where Vzd is the Zener voltage of the second Zener diode and Vth is the threshold voltage of the second P-type MOS transistor.

8. The high-voltage domain controlled potential generating device according to claim 4, characterized in that, When the high-voltage domain sampling voltage is greater than the threshold voltage, the second N-type MOS transistor starts to pull down the sixth control voltage. When the pull-down capability is greater than the pull-up capability of the bias current, the sixth control voltage gradually decreases until the output of the first Schmitt trigger flips to output a low level, and the control signal outputs a high level through the first inverter.

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