Circuit for prolonging power-down retention time and control method thereof

Abstract

The invention discloses a circuit for prolonging power-down retention time and a control method thereof. The circuit comprises a PFC circuit, a power-down prolonging circuit and a DC-DC circuit. The power-down time prolonging circuit as a core comprises an energy storage capacitor C1, a bus capacitor C2, two series bridge arms formed by four switch tubes S1 to S4, and a resonant cavity formed by a resonant capacitor Cr and a resonant inductor Lr. When the AC source is powered down, the retention time of the output voltage can be obviously prolonged by controlling the power-down time prolonging circuit, and the switching tubes (S1-S4) can realize ZVS, so that the optimization of the circuit cost and the performance is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuits, and in particular relates to a circuit for extending power-off holding time and a control method thereof. Background Art

[0002] In recent years, with the rapid development of artificial intelligence (AI) technology, AI servers have become increasingly widely used in data centers, cloud computing, and other fields. During operation, AI servers place extremely stringent demands on the stability and reliability of their power supplies. Core components such as sophisticated AI chips are susceptible to irreversible damage when the input voltage is unstable. This can not only lead to data loss and task interruption, but can also cause permanent hardware failure, resulting in significant financial losses.

[0003] The performance of the power converters responsible for powering AI servers is directly related to the server's normal operation. If the power converter encounters insufficient input voltage during powering the AI ​​server, it must be able to maintain continuous power output for a period of time to allow the AI ​​server to perform emergency operations such as preserving cached data and safely shutting down tasks.

[0004] Specifically, when a power converter experiences insufficient input voltage, the size of its output capacitor plays a crucial role in determining how long the output voltage can be maintained. To effectively extend the time the power converter can maintain its rated output voltage after insufficient input voltage, three common approaches are: 1. Increasing the DC bus capacitor; 2. Increasing the output capacitor; and 3. Adding additional circuitry.

[0005] However, increasing capacitor capacity significantly increases size and cost, which runs counter to the current trend of increasingly miniaturized and lightweight electronic devices. This presents significant challenges in miniaturizing power converter designs. Furthermore, AI servers often operate in complex power environments, facing numerous interference factors such as mains power fluctuations and lightning surges, placing higher demands on the power converter's power loss protection capabilities.

[0006] Therefore, how to design a protection device that can effectively extend the power-off holding time and has strong anti-interference ability, so that the output voltage of the device can maintain a predetermined voltage within the holding time, while achieving the miniaturization of the protection device, has become a key technical problem that needs to be solved urgently. Summary of the Invention

[0007] In view of the above problems, the present invention provides a circuit and method for extending the power-off holding time to overcome the shortcomings of the prior art.

[0008] The invention provides a circuit for extending the power-off holding time, comprising: a PFC circuit, a power-off time extension circuit, and a DC-DC circuit. The power-off time extension circuit comprises an energy storage capacitor C1, a bus capacitor C2, a first bridge arm formed by switches S1 and S2, a second bridge arm formed by S3 and S4, and a resonant capacitor C r and resonant inductor L r The resonant cavity is composed of a PFC circuit and a DC-DC circuit topology, wherein the PFC circuit and the DC-DC circuit topology can be any known topology, and the capacity of the energy storage capacitor C1 is much larger than the capacity of the bus capacitor C2.

[0009] The PFC circuit, power-off time extension circuit and DC-DC circuit are connected in series in sequence; the drain of the switch tube S1 is connected to the positive end of the bus capacitor C2; the source of the switch tube S1 is connected to the drain of the switch tube S2 and the resonant inductor L r One end of the resonant inductor L r The other end of the resonant capacitor C r The source of the switch tube S2 is connected to the drain of the switch tube S3 and the positive end of the energy storage capacitor C1; the source of the switch tube S3 is connected to the drain of the switch tube S4 and the resonant capacitor C r The other end of the switch tube S4 is connected to the negative end of the energy storage capacitor C1 and the negative end of the bus capacitor C2;

[0010] When the AC input voltage is normal, the power-off time extension circuit operates in the first operation mode: the switches S1 and S2 in the power-off time extension circuit remain turned on, and S3 and S4 remain turned off.

[0011] When the AC input voltage is powered off, the power-off time extension circuit operates in the second operation mode: the switch tubes S1 and S2 are complementary turned on, and S3 and S4 are complementary turned on.

[0012] Preferably, the control strategy of the power-off time extension circuit in operating mode 2 adopts phase shift control: the switching frequency is kept constant, and the gain is adjusted by changing the phase shift angle; the direction of the phase shift is that the first bridge arm lags the second bridge arm. When the phase shift angle is within [0° to 90°], the gain increases with the increase of the phase shift angle; when the phase shift angle is within [90° to 180°], the gain decreases with the increase of the phase shift angle.

[0013] Preferably, the control strategy of the power-off time extension circuit in the second working mode adopts variable frequency control: keeping the phase shift angle unchanged, the gain is adjusted by changing the switching frequency; within the variable frequency range, the gain decreases as the switching frequency increases.

[0014] Preferably, the control strategy of the power-off time extension circuit in the second working mode adopts phase shift + frequency conversion control: combining phase shift control and frequency conversion control to achieve wider gain range adjustment.

[0015] Preferably, the control strategy of the power-off time extension circuit adopts phase shift + frequency conversion control: combining phase shift control and frequency conversion control to achieve wider gain range adjustment.

[0016] The present invention also provides a control method for a circuit for extending the power-off holding time, comprising the following steps:

[0017] Step 1: Start the power supply and ensure that the pre-stage PFC is functioning properly. Switches S1 and S2 are always on, switches S3 and S4 are always off, and energy storage capacitor C1 and bus capacitor C2 act together as DC bus filter capacitors. Then proceed to step 2.

[0018] Step 2: The detection device detects whether the voltage of the energy storage capacitor reaches a preset voltage. If not, return to step 1; if yes, execute step 3.

[0019] Step 3: The detection device determines whether the front-stage PFC is powered off. If not, return to step 2; if so, execute step 4.

[0020] Step 4: Enable the power-off time extension control strategy and dynamically adjust the phase shift angle or frequency of the switch tubes [S1-S4] to maintain the DC bus voltage at a predetermined voltage within the holding time.

[0021] The beneficial effects of the present invention are as follows: in the event of an input power outage, the circuit utilizes the energy stored in energy storage capacitor C1, and through the power-off time extension circuit, maintains the DC bus voltage constant during the holdup time, thereby allowing the DC-DC circuit to maintain a constant output voltage in normal operating mode. This invention effectively reduces the DC bus capacitor capacity while meeting the power-off holdup time requirement, optimizing circuit costs. Furthermore, switches S1-S4 can achieve zero voltage switching (ZVS), optimizing circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram showing the circuit structure of a circuit for extending the power-off holding time of the present invention is shown;

[0023] Figure 2 The equivalent circuit of the invention showing the working mode of the extended power-off holding time circuit when the AC input voltage is normal

[0024] Figure 3 The timing waveform of a certain working cycle in the holding time of the circuit for extending the power-off holding time of the present invention is shown in the working mode 2 when the AC input is powered off;

[0025] Figure 4 The figure shows the mode 1 equivalent circuit of the circuit for extending the power-off holding time of the present invention in the working mode 2 when the AC input is powered off;

[0026] Figure 5The second mode equivalent circuit of the circuit for extending the power-off holding time of the present invention is shown in the second working mode when the AC input is powered off;

[0027] Figure 6 The third mode equivalent circuit of the circuit for extending the power-off holding time of the present invention is shown in the second working mode when the AC input is powered off;

[0028] Figure 7 The fourth mode equivalent circuit of the circuit for extending the power-off holding time of the present invention in the working mode 2 when the AC input power is lost is shown;

[0029] Figure 8 The fifth mode equivalent circuit of the circuit for extending the power-off holding time of the present invention is shown in the second working mode when the AC input is powered off;

[0030] Figure 9 The six-modal equivalent circuit of the circuit for extending the power-off holding time of the present invention is shown in the second working mode when the AC input is powered off;

[0031] Figure 10 The figure shows the modal seven equivalent circuit of the circuit for extending the power-off holding time of the present invention in the working mode 2 when the AC input is powered off;

[0032] Figure 11 The figure shows the modal eight equivalent circuit of the circuit for extending the power-off holding time of the present invention in the working mode 2 when the AC input is powered off;

[0033] Figure 12 The voltage V of the energy storage capacitor during normal operation and maintenance time of the circuit of the present invention is shown. C1 and bus capacitor voltage V C2 the changing trend of

[0034] Figure 13 The changing trends of the circuit gain and phase shift angle of the circuit for extending the power-off holding time of the present invention are shown. DETAILED DESCRIPTION

[0035] In order to make the technical solution of the present invention clearer, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0036] See also Figure 1 The circuit structure diagram of the extended power-off holding time circuit of the present invention is shown. The extended power-off holding time circuit of the present invention includes: a PFC circuit, a power-off time extension circuit, a DC-DC circuit and a load. The power-off time extension circuit includes an energy storage capacitor C1, a bus capacitor C2, a first bridge arm composed of switch tubes S1 and S2, a second bridge arm composed of S3 and S4, and a resonant capacitor C r and resonant inductor L rThe resonant cavity is composed of a PFC circuit and a DC-DC circuit topology, wherein the PFC circuit and the DC-DC circuit topology can be any known topology, and the capacity of the energy storage capacitor C1 is much larger than the capacity of the bus capacitor C2.

[0037] The PFC circuit, power-off time extension circuit and DC-DC circuit are connected in series in sequence; the drain of the switch tube S1 is connected to the positive end of the bus capacitor C2; the source of the switch tube S1 is connected to the drain of the switch tube S2 and the resonant inductor L r One end of the resonant inductor L r The other end of the resonant capacitor C r The source of the switch tube S2 is connected to the drain of the switch tube S3 and the positive end of the energy storage capacitor C1; the source of the switch tube S3 is connected to the drain of the switch tube S4 and the resonant capacitor C r The other end of the switch tube S4 is connected to the negative end of the energy storage capacitor C1 and the negative end of the bus capacitor C2;

[0038] When the AC input voltage is normal, the power-off time extension circuit operates in the first operation mode: the switches S1 and S2 in the power-off time extension circuit remain turned on, and S3 and S4 remain turned off.

[0039] When the AC input voltage is powered off, the power-off time extension circuit operates in the second operation mode: the switch tubes S1 and S2 are complementary turned on, and S3 and S4 are complementary turned on.

[0040] Preferably, the control strategy of the power-off time extension circuit in operating mode 2 adopts phase shift control: the switching frequency is kept constant, and the gain is adjusted by changing the phase shift angle; the direction of the phase shift is that the first bridge arm lags the second bridge arm. When the phase shift angle is within [0° to 90°], the gain increases with the increase of the phase shift angle; when the phase shift angle is within [90° to 180°], the gain decreases with the increase of the phase shift angle.

[0041] Preferably, the control strategy of the power-off time extension circuit in the second working mode adopts variable frequency control: keeping the phase shift angle unchanged, the gain is adjusted by changing the switching frequency; within the variable frequency range, the gain decreases as the switching frequency increases.

[0042] Preferably, the control strategy of the power-off time extension circuit in the second working mode adopts phase shift + frequency conversion control: combining phase shift control and frequency conversion control to achieve wider gain range adjustment.

[0043] The working principle of the circuit for extending the power-off holding time of the present invention is as follows:

[0044] When the AC input voltage is normal, the power-off time extension circuit operates in working mode 1. The switches S1 and S2 in the power-off time extension circuit remain on, S3 and S4 remain off, and the energy storage capacitor C1 and the bus capacitor C2 work in parallel to reduce the bus voltage ripple. The equivalent circuit is as follows: Figure 2 shown.

[0045] Assume that at a certain moment, the AC input Vac suddenly loses power and the PFC stops working. The power-off time extension circuit switches to the second working mode: the switch tubes S1 and S2 are complementary turned on, and S3 and S4 are complementary turned on. By dynamically adjusting the phase shift pin or the switching frequency between the first switch bridge arm and the second switch bridge arm, the bus voltage is maintained at a predetermined voltage within the holding time. One of the working cycle timing waveforms is as follows Figure 3 As shown, the time-sharing equivalent circuit diagram of a working cycle is as follows Figure 4-11 shown.

[0046] refer to Figure 3 The timing waveform of a working cycle is shown as follows. The working mode of the power-off time extension circuit in working mode 2 is as follows:

[0047] Mode 1 [t0~t1]: S1 and S4 are on, S2 and S3 are off. The voltage V across the resonant cavity is ab =V1+V cd , the voltage applied across the inductor reaches its maximum value, and the inductor current rises rapidly in an approximately linear manner. At time t1, S1 is turned off, and the inductor current reaches its peak value. The time corresponding to this mode is called the phase shift time. Adjusting the phase shift time is equivalent to adjusting the phase shift angle. The equivalent circuit corresponding to mode 1 is as follows: Figure 4 shown.

[0048] Mode 2 [t1~t2]: corresponds to the dead time of the upper bridge arm. After S1 is turned off, the inductor current flows from b to a, which is recorded as the negative direction. The current has an impact on the parasitic capacitance C of the S1 tube. s1 To charge the parasitic capacitance C of S2 tube s2 Discharge is performed, so that the voltage across DS of S1 rises from 0 to V cd , the voltage across S2 ds changes from V cd If the inductor current is at its peak, after completing the charge and discharge of the parasitic capacitance, it will continue to flow through the body diode of S2 during the remaining dead time. The equivalent circuit corresponding to mode 2 is as follows: Figure 5 shown.

[0049] Mode 3 [t2-t3]: At the beginning of this mode, S2 is turned on in ZVS. At this time, V1 is connected to both ends of the resonant cavity to charge the resonant cavity, and the bus capacitor discharges the load to maintain the output voltage. During the power-off maintenance time, that is, under the boost condition, the voltage on the resonant capacitor is slightly greater than V1, so the voltage applied across the inductor is negative, and the inductor current decreases at a low slope. At t3, S4 is turned off. The equivalent circuit corresponding to mode 3 is as follows: Figure 6 shown.

[0050] Mode 4 [t3~t4]: corresponds to the dead time of the lower bridge arm. After S4 is turned off, the inductor current flows in the negative direction, and the current has a negative impact on the parasitic capacitance C of the S4 tube. s4 To charge the parasitic capacitance C of S3 tube S3 Discharge is performed, so that the voltage across DS of S4 rises from 0 to V1, and the voltage across ds of S3 drops from V1 to 0. The equivalent circuit corresponding to mode 4 is as follows: Figure 7 shown.

[0051] Mode 5 [t4-t5]: At the beginning of this mode, S3 is turned on with ZVS. At this time, the voltage across the resonant cavity is zero, and the voltage applied across the inductor reaches its maximum negative value, so the inductor current drops rapidly. This mode is the energy cycle stage, and the current direction changes from positive to negative, completing the commutation. At t5, S2 is turned off. The equivalent circuit corresponding to mode 5 is as follows: Figure 8 shown.

[0052] Mode 6 [t5~t6]: This mode re-enters the dead zone time of the upper bridge arm. Since the inductor current flows in the positive direction, the parasitic capacitance C is completed in this dead zone mode. s2 Charging and C s1 The discharge causes the voltage across DS of S2 to rise from 0 to V cd , the voltage across DS of S1 changes from V cd Drops to 0. The equivalent circuit corresponding to mode six is ​​as follows Figure 9 shown.

[0053] Mode 7 [t6-t7]: After S1 completes ZVS, the voltage applied across the resonant cavity is equal to V cd In this mode, the resonant cavity releases energy to the load. In the boost mode, the voltage on the resonant capacitor is slightly less than V cd , the inductor current rises at a low slope. At t7, S3 is turned off. The equivalent circuit corresponding to mode six is ​​as follows Figure 10 shown.

[0054] Mode 8 [t7-t8]: This mode enters the dead time of the lower bridge arm again. During the dead time, the inductor current flows in the positive direction, which affects the parasitic capacitance C s4 To charge, C s3Discharge is performed, so that the voltage across DS of S4 rises from zero to V1, and the voltage across DS of S3 drops from V1 to 0. At this point, the mode switching within a switching cycle is completed. The equivalent circuit corresponding to mode six is ​​as follows Figure 11 shown.

[0055] like Figure 12 As shown, in the normal working stage of the circuit of this embodiment, the energy storage capacitor C1 stores a lot of energy, according to the formula:

[0056]

[0057] T_hold is the power-off holding time, C is the capacitance of the energy storage capacitor C1, v1 is the voltage value of C1 at the start of power-off, v2 is the voltage value of C1 at the end of power-off, P out is the output power.

[0058] The relationship between the gain and the phase shift angle of the circuit of the present invention is as follows: Figure 13 As shown, the circuit for extending the power-off hold-up time of the present invention has a very wide gain range. Within a set hold-up time, a low v2 value can be achieved, which means that the capacitance of the energy storage capacitor C1 can be reduced, thereby optimizing the circuit cost and volume, achieving good economic benefits.

[0059] The present invention also provides a method for operating a circuit for extending the power-off holding time, comprising the following steps:

[0060] Step 1: Start the power supply and ensure that the pre-stage PFC is working properly. Switches S1 and S2 are always on, switches S3 and S4 are always off, and the energy storage capacitor C1 and bus capacitor C2 act together as DC bus filter capacitors. Then proceed to step 2.

[0061] Step 2: The detection device detects whether the voltage of the energy storage capacitor reaches the preset voltage. If not, return to step 1; if so, execute step 3;

[0062] Step 3: The detection device determines whether the front-stage PFC is powered off. If not, return to step 2; if so, execute step 4;

[0063] Step 4: Enable the power-off time extension control strategy and dynamically adjust the phase shift angle or frequency of the switch tubes [S1-S4] to maintain the DC bus voltage at a predetermined voltage within the holding time;

[0064] Well-known implementation methods and operating means are not described in detail herein to avoid confusing the various technical implementation schemes of the present invention. However, for those skilled in the art, the lack of one or more specific details or components does not affect the understanding and implementation of the present invention.

[0065] The specific implementation methods and methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for extending the power-off holding time, characterized in that: Including PFC circuit, power-off time extension circuit and DC-DC circuit; The power-off time extension circuit includes an energy storage capacitor C1, a bus capacitor C2, a first bridge arm composed of switches S1 and S2, a second bridge arm composed of S3 and S4, and a resonant capacitor C r and resonant inductor L r The PFC circuit and DC-DC circuit topology are any known topology, and the capacity of the energy storage capacitor C1 is much larger than the capacity of the bus capacitor C2; The PFC circuit, the power-off time extension circuit and the DC-DC circuit are connected in series in sequence.

2. The circuit for extending the power-off holding time according to claim 1, wherein: In the power-off time extension circuit, the drain of the switch tube S1 is connected to the positive terminal of the bus capacitor C2; the source of the switch tube S1 is connected to the drain of the switch tube S2 and the resonant inductor L r One end of the resonant inductor L r The other end of the resonant capacitor C r The source of the switch tube S2 is connected to the drain of the switch tube S3 and the positive end of the energy storage capacitor C1; the source of the switch tube S3 is connected to the drain of the switch tube S4 and the resonant capacitor C r the source of the switch tube S4 is connected to the negative end of the energy storage capacitor C1 and the negative end of the bus capacitor C2.

3. The circuit for extending the power-off holding time according to claim 2, wherein: When the AC input voltage is normal, the power-off time extension circuit operates in working mode 1: the switches S1 and S2 in the power-off time extension circuit remain turned on, and S3 and S4 remain turned off; When the AC input voltage is powered off, the power-off time extension circuit operates in the second operation mode: the switch tubes S1 and S2 are complementary turned on, and S3 and S4 are complementary turned on.

4. The circuit for extending the power-off holding time according to claim 3, wherein: The control strategy of the power-off time extension circuit in working mode 2 adopts phase shift control: keeping the switching frequency unchanged, the gain is adjusted by changing the phase shift angle; the direction of the phase shift is that the first bridge arm lags behind the second bridge arm; when the phase shift angle is within [0°~90°], the gain increases with the increase of the phase shift angle; when the phase shift angle is within [90°~180°], the gain decreases with the increase of the phase shift angle.

5. The circuit for extending the power-off holding time according to claim 3, characterized in that: The control strategy of the power-off time extension circuit in the second working mode adopts variable frequency control: keeping the phase shift angle unchanged, the gain is adjusted by changing the switching frequency; within the variable frequency range, the gain decreases as the switching frequency increases.

6. A control method for a circuit extending the power-off holding time, used in a circuit extending the power-off holding time according to any one of claims 1 to 5, characterized in that: The steps include: Step 1: Start the power supply. The pre-stage PFC works normally. Switches S1 and S2 are always on, while switches S3 and S4 are always off. The energy storage capacitor C1 and bus capacitor C2 act as DC bus filter capacitors. Step 2: The detection device detects whether the voltage of the energy storage capacitor reaches a preset voltage. If not, return to step 1; If you execute step 3; Step 3: The detection device determines whether the front-stage PFC is powered off. If not, return to step 2; if so, execute step 4; Step 4: Enable the power-off time extension control strategy and dynamically adjust the phase shift angle or frequency of the switches S1 to S4 to maintain the DC bus voltage at a predetermined voltage within the holding time.

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