Method for processing multi-granularity gated clock, electronic device and medium

Abstract

The application relates to the chip technical field, in particular to a multi-granularity gated clock processing method, electronic equipment and medium, the method comprises the following steps: S1, setting chip gated clock information {A1, A2,..., A m ,...,A M} and deep sleep module information {D1, D2,..., D m ,...,D M}; S2, setting chip gated clock control configuration information table {C1, C2,..., C m ,...,C M} based on {A1, A2,..., A n ,...,A N}; S3, acquiring a target CM n , and acquiring a corresponding target CX n based on the target CM n ; S4, configuring the chip gated clock based on the target CX n . The application reduces the complexity of gated clock processing and improves the processing efficiency of the gated clock.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a multi-granularity gated clock processing method, electronic equipment and medium. Background Art

[0002] Clock gating is a traditional dynamic low-power technology widely used in digital integrated circuit design, significantly reducing chip power consumption. However, due to the complexity of chip design, clock gating may need to be set up in multiple locations within the chip design and may also be associated with other low-power technologies. This makes the configuration of chip clock gating complex and inefficient. Furthermore, after configuring the clock gating, the validity of the clock gating must be checked, further increasing the complexity of clock gating processing and reducing its efficiency. Summary of the Invention

[0003] The present invention aims to provide a method, electronic device and medium for processing a multi-granularity gated clock, thereby reducing the complexity of gated clock processing and improving the processing efficiency of gated clock.

[0004] According to a first aspect of the present invention, a method for processing a multi-granularity gated clock is provided, comprising:

[0005] Step S1, set chip gate clock information {A1, A2, ..., A m ,...,A M} and deep sleep module information {D1,D2,...,D m ,...,D M}, A m is the gated clock module corresponding to the mth subsystem, D m A m For the corresponding deep sleep module, the value range of m is 1 to M, A m ={P1 m ,P2 m ,...,P i m ,...,P f(m) m}, P i m The gated clock module corresponding to the i-th chip IP of the m-th subsystem, IP i m ={B1 im ,B2 im ,...,B j im ,...,B g(im) im}, Bj im Cm(i,j) is the gating clock module corresponding to the jth device in the ith chip IP of the mth subsystem that needs to be set with a gating clock, and the value of j ranges from 1 to g(im), g(im) being the total number of devices in the ith chip IP of the mth subsystem that need to be set with a gating clock;

[0006] In step S2, the chip gating clock control configuration information table {C1, C2,..., C m ,...,C M} is set based on {A1, A2,..., A n ,...,A N}, C n is the nth chip gating clock control configuration information, and n ranges from 1 to N, C n ={CM n ,CX n} is the chip gating clock control configuration information table, CM n is the configuration encoding identifier corresponding to C n , CX n is the configuration encoding corresponding to C n , CX n ={CA1 n ,CD1 n ,CP1 n ,CB1 n ,CA2 n ,CD2 n ,CP2 n ,CB2 n ,...,CA m n ,CD m n ,CP m n ,CB m n ,...,CA M n ,CD M n ,CP M n ,CB M n} is the chip gating clock control configuration information table, CA m n is the first-level gating configuration encoding corresponding to CX n corresponding to the mth subsystem, CD m n is the deep sleep module encoding corresponding to CX n corresponding to the mth subsystem, CP m n is the first-level gating configuration encoding corresponding to CX nThe second-level gating configuration code corresponding to the mth subsystem, CB m n For CX n The third-level gating configuration code corresponding to the corresponding m-th subsystem;

[0007] Step S3: Get target CM n , based on the target CM n Get the corresponding target CX n ;

[0008] Step S4: Based on target CX n Configure chip gated clock.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a multi-granularity gated clock processing method, electronic device, and medium that achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0012] The present invention pre-sets gated clock modules of different granularities and chip gated clock control configuration information, and can obtain the corresponding target configuration code based only on the target configuration code identifier, thereby realizing fast and accurate configuration of gated clock modules of different granularities. The present invention reduces the complexity of gated clock processing and improves the processing efficiency of gated clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a method for processing a multi-granularity gated clock provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for processing a multi-granularity gated clock, such as Figure 1 Shown, including:

[0017] Step S1, set chip gate clock information {A1, A2, ..., A m ,...,A M} and deep sleep module information {D1,D2,...,D m ,...,D M}, A m is the gated clock module corresponding to the mth subsystem, D m A m For the corresponding deep sleep module, the value range of m is 1 to M, A m ={P1 m ,P2 m ,...,P i m ,...,P f(m) m}, P i m The gated clock module corresponding to the i-th chip IP of the m-th subsystem, IP i m ={B1 im ,B2 im ,...,B j im ,...,B g(im) im}, B j im This is the gated clock module corresponding to the jth device that needs to set the gated clock in the i-th chip IP of the m-th subsystem. The value of j ranges from 1 to g(im), and g(im) is the total number of devices that need to set the gated clock in the i-th chip IP of the m-th subsystem.

[0018] It should be noted that, based on the chip design hierarchy, clocks of varying granularity are configured by setting chip clock gating information. A chip design comprises multiple subsystems, each of which contains multiple chip IPs (Intellectual Properties). These IPs contain multiple devices, such as flip-flops or SRAMs. A subsystem's clock gating is considered a first-level clock gating, a coarse-grained clock gating used to control subsystem-level power consumption. The clock gating module corresponding to the chip IP is considered a second-level clock gating, a medium-grained clock gating used to control chip IP-level power consumption. The clock gating module corresponding to a device is considered a third-level clock gating, a fine-grained clock gating used to control device-level power consumption. The deep sleep module is often associated with clock gating control, so deep sleep module information can be set simultaneously. If deep sleep mode is not desired, the deep sleep module information can be left blank, and subsequent operations related to the deep sleep module can be omitted.

[0019] Step S2: Based on {A1, A2, ..., A m ,...,A M}Set chip gate clock control configuration information table {C1, C2, ..., C n ,...,C N}, C n The nth chip gated clock control configuration information, n ranges from 1 to N, N is the total number of gated clock control configuration information, C n ={CM n ,CX n}, CM n C n Corresponding configuration code identifier, CX n C n Corresponding configuration code, CX n ={CA1 n ,CD1 n ,CP1 n ,CB1 n ,CA2 n ,CD2 n ,CP2 n ,CB2 n ,...,CA m n ,CD m n ,CP m n ,CB m n ,...,CA M n ,CD Mn ,CP M n ,CB M n}, CA m n For CX n The first-level gating configuration code corresponding to the mth subsystem, CD m n For CX n The deep sleep module code corresponding to the mth subsystem, CP m n For CX n The second-level gating configuration code corresponding to the mth subsystem, CB m n For CX n The third-level gating configuration code corresponding to the m-th subsystem.

[0020] It should be noted that {C1,C2,...,C n ,...,C N} can include {A1,A2,...,A m ,...,A M All possible configuration combinations, or part of all possible configuration combinations, are set according to application requirements. n Set a corresponding default configuration for each level of clock gating.

[0021] Step S3: Get target CM n , based on the target CM n Get the corresponding target CX n .

[0022] It should be noted that since {CM n ,CX n}, so based on the target CM n You can directly obtain the corresponding target CX n .

[0023] Step S4: Based on target CX n Configure chip gated clock.

[0024] It should be noted that the target CX n The configuration of each level of gated clock and deep sleep module has been set up in the target CX n Configure chip gated clock.

[0025] As an example, CA m n 、CDm n , CP m n , CB m n are respectively set to a first encoding value or a second encoding value, the first encoding value representing on, and the second encoding value representing off, when the CA m n is set to the second encoding value, the corresponding CD m n must also be set to the second encoding value. Specifically, the first encoding value can be set to 0, and the second encoding value set to 1. Or the first encoding value is set to 1, and the second encoding value set to 0.

[0026] As an embodiment, the step S4 comprises:

[0027] Step S41, if the target CA m n is the first encoding value, the corresponding A m is set to the on state, if the target CA m n is the second encoding value, the corresponding A m is set to the off state.

[0028] Step S42, if the target CD m n is the first encoding value, the corresponding D m is set to the on state, if the target CD m n is the second encoding value, the corresponding D m is set to the off state.

[0029] Step S43, if the target CP m n is the first encoding value, the corresponding all P i m is set to the on state, if the target CP m n is the second encoding value, the corresponding all P i m is set to the off state.

[0030] It should be noted that through the step S43, the P i m is set to the corresponding default state.

[0031] Step S44, if the target CB m n is the first encoding value, the corresponding all B j imIn the open state, if the target CB m n Set to the second encoding value, then set all corresponding B j im The status is closed.

[0032] It should be noted that, through step S44, B j im Set to the corresponding default state.

[0033] In the processing of gated clocks, it is particularly important to verify whether the gated clock configuration is correct. Therefore, the embodiment of the present invention further provides a verification method. As an embodiment, the method further includes:

[0034] Step S10: prepare for each A m Set the corresponding checker AK m , in advance for each D m Set the corresponding inspector DK m , in advance for each P i m Set the corresponding checker PK i m , in advance for each B j im Set the corresponding checker BK j im .

[0035] After step S4, the following steps are also included:

[0036] Step S5: According to the target CX n Configuration checker, checks whether the configured chip gated clock is correct.

[0037] It should be noted that all inspectors are set up in advance and then directly based on the target CX n Configuration checker improves the efficiency and accuracy of gated clock control verification.

[0038] As an embodiment, step S5 includes:

[0039] Step S51: If the target CA m n For the first code value, set the corresponding AK m If the target CA is enabled, m n For the second code value, set the corresponding AK m The status is closed.

[0040] Step S52: If the target CD m n Set to the first encoding value, then set the corresponding DKm If the target CD is in the on state, the step S4 includes: m n If the target CD is set to the first encoding value, the corresponding DK is set to the on state. m If the target CD is set to the second encoding value, the corresponding DK is set to the off state.

[0041] The step S53 includes: m n If the target CP is in the on state, the step S53 includes: i m If the target CP is set to the first encoding value, the corresponding all PK is set to the on state. m n If the target CP is set to the second encoding value, the corresponding all PK is set to the off state. i m If the target CP is in the off state.

[0042] The step S54 includes: m n If the target CB is in the on state, the step S54 includes: j im If the target CB is set to the first encoding value, the corresponding all BK is set to the on state. m n If the target CB is set to the second encoding value, the corresponding all BK is set to the off state. j im If the target CB is in the off state.

[0043] The step S55 includes: m Checking whether the corresponding A is in the on state based on all the on AK. m Checking whether the corresponding P is in the on state based on all the on PK. i m Checking whether the corresponding B is in the on state based on all the on BK. i m If the checking result is all in the on state, the checking is passed, otherwise, the checking is not passed. j im If the checking result is all in the on state, the checking is passed, otherwise, the checking is not passed. j im If the checking result is all in the on state, the checking is passed, otherwise, the checking is not passed.

[0044] It should be noted that each checker can be set to the off state by default, and then all the checkers that need to be turned on can be turned on based on the target CX. n If the checking result is all in the on state, the checking is passed, otherwise, the checking is not passed.

[0045] It should be noted that the same application scenario is set for each level of the gate clock module configuration, and the above embodiment can be directly used, but in some scenarios, different configurations are needed for different gate clock modules of the same level. Based on this, the present embodiment further proposes the following implementation manner:

[0046] As an embodiment, the step S4 includes:

[0047] Step C41, obtain C n Each corresponding P i m Corresponding secondary configuration code EP i m , EP i m It is empty or the first encoding value or the second encoding value.

[0048] Step C42: If EP i m If it is empty, set P i m Corresponding target configuration code FP i m =CP m n , if EP i m If it is not empty, set P i m Corresponding target configuration code FP i m =EP i m .

[0049] Among them, if EP i m If it is empty, then P i m The corresponding target configuration code is directly set to the default value. If EP i m If it is not empty, then P i m The corresponding target configuration code is set to the corresponding value in the secondary configuration, so as to achieve different P i m Differentiated configuration.

[0050] Step C43, obtain C n Each corresponding B j im Corresponding secondary configuration code EB j im , EB j im It is empty or the first encoding value or the second encoding value.

[0051] Step C44, if EB j im If it is empty, set B j im Corresponding target configuration code FB j im =CB m n , if EBj im If it is not empty, set P i m Corresponding target configuration code FB j im =EB j im .

[0052] Among them, if EB j im If B is empty, j im The corresponding target configuration code is directly set to the default value. If EB j im If it is not empty, then B j im The corresponding target configuration code is set to the corresponding value in the secondary configuration, so as to achieve different B j im Differentiated configuration.

[0053] Step C45: If the target CA m n For the first code value, set the corresponding A m If the target CA is enabled, m n For the second code value, set the corresponding A m The status is closed.

[0054] Step C46: If the target CD m n Set to the first code value, then set the corresponding D m If the target CD is turned on, m n Set to the second code value, then set the corresponding D m The status is closed.

[0055] Step C47: If FP i m For the first code value, set the corresponding P i m In the open state, if FP i m For the second code value, set the corresponding P i m The status is closed.

[0056] Step C48, if FB j im For the first code value, set the corresponding B j im If FB is turned on, j imFor the second code value, set the corresponding B j im The status is closed.

[0057] For the above implementation, a corresponding verification strategy is also set. As an example, the method further includes:

[0058] Step C10: Prepare for each A m Set the corresponding checker AK m , in advance for each D m Set the corresponding inspector DK m , in advance for each P i m Set the corresponding checker PK i m , in advance for each B j im Set the corresponding checker BK j im .

[0059] After step S4, the following steps are also included:

[0060] Step C5: According to the target CA m n 、Target CD m n , FP i m 、FB j im Configuration checker, checks whether the configured chip gated clock is correct.

[0061] It should be noted that all checkers are set up in advance and then directly based on the target CA m n 、Target CD m n , FP i m 、FB j i Configuration checker improves the efficiency and accuracy of gated clock control verification.

[0062] As an embodiment, step C5 includes:

[0063] Step C51: If the target CA m n For the first code value, set the corresponding AK m If the target CA is enabled, m n For the second code value, set the corresponding AK m is closed;

[0064] Step C52: If the target CD m n Set to the first encoding value, then set the corresponding DK m If the target CD is turned on, m n If set to the second encoding value, then set the corresponding DK m is closed;

[0065] Step C53: If FP i m For the first code value, set the corresponding PK i m In the open state, if FP i m For the second code value, set the corresponding PK i m is closed;

[0066] Step C54: If FB j im For the first code value, set the corresponding BK j im If the FB j im For the second code value, set the corresponding BK j im The status is closed.

[0067] Step C55: Based on all the enabled AKs m Check the corresponding A m Whether to enable or disable, based on all enabled PK i m Check the corresponding P i m Whether to enable or disable, based on all enabled BK j im Check the corresponding B j im Whether it is enabled. If all the check results are enabled, the check passes; otherwise, the check fails.

[0068] It should be noted that each checker can be set to off by default and then based on the target CD m n FP i m 、FB j im Just open all the inspectors you want.

[0069] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0070] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0071] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0072] The embodiment of the present invention pre-sets gated clock modules of different granularities and chip gated clock control configuration information, and can obtain the corresponding target configuration code based only on the target configuration code identifier, thereby realizing fast and accurate configuration of gated clock modules of different granularities. The present invention reduces the complexity of gated clock processing and improves the processing efficiency of gated clock.

[0073] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for processing a multi-granularity gated clock, characterized in that: include: Step S1, set chip gate clock information {A1, A2, ..., A m ,...,A M } and deep sleep module information {D1,D2,...,D m ,...,D M }, A m is the gated clock module corresponding to the mth subsystem, D m A m For the corresponding deep sleep module, the value range of m is 1 to M, A m ={P1 m ,P2 m ,...,P i m ,...,P f(m) m }, P i m The gated clock module corresponding to the i-th chip IP of the m-th subsystem, IP i m ={B1 im ,B2 im ,...,B j im ,...,B g(im) im }, B j im The gated clock module corresponding to the jth device that needs to set the gated clock in the i-th chip IP of the m-th subsystem. The value of j ranges from 1 to g(im). g(im) is the total number of devices that need to set the gated clock in the i-th chip IP of the m-th subsystem. Step S2: Based on {A1, A2, ..., A m ,...,A M }Set chip gate clock control configuration information table {C1, C2, ..., C n ,...,C N }, C n The nth chip gate clock control configuration information, n ranges from 1 to N, C n ={CM n ,CX n }, CM n C n Corresponding configuration code identifier, CX n C n Corresponding configuration code, CX n ={CA1 n ,CD1 n ,CP1 n ,CB1 n ,CA2 n ,CD2 n ,CP2 n ,CB2 n ,...,CA m n ,CD m n ,CP m n ,CB m n ,...,CA M n ,CD M n ,CP M n ,CB M n }, CA m n For CX n The first-level gating configuration code corresponding to the mth subsystem, CD m n For CX n The deep sleep module code corresponding to the mth subsystem, CP m n For CX n The second-level gating configuration code corresponding to the mth subsystem, CB m n For CX n The third-level gating configuration code corresponding to the corresponding m-th subsystem; Step S3: Get target CM n , based on the target CM n Get the corresponding target CX n ; Step S4: Based on target CX n Configure chip clock gating.

2. The method according to claim 1, characterized in that CA m n 、CD m n 、CP m n , CB m n Set to the first code value or the second code value respectively. The first code value indicates opening and the second code value indicates closing. m n When set to the second coding value, the corresponding CD m n Must also be set to the second encoding value.

3. The method according to claim 2, characterized in that The step S4 comprises: Step S41: If the target CA m n For the first code value, set the corresponding A m If the target CA is enabled, m n For the second code value, set the corresponding A m is closed; Step S42: If the target CD m n Set to the first code value, then set the corresponding D m If the target CD is turned on, m n Set to the second code value, then set the corresponding D m is closed; Step S43: If the target CP m n Set to the first code value, then set all corresponding P i m In the open state, if the target CP m n Set to the second encoding value, then set all corresponding P i m is closed; Step S44: If the target CB m n Set to the first encoding value, then set all corresponding B j im In the open state, if the target CB m n Set to the second encoding value, then set all corresponding B j im It is closed.

4. The method according to claim 3, characterized in that The method further comprises: Step S10: prepare for each A m Set the corresponding checker AK m , in advance for each D m Set the corresponding inspector DK m , in advance for each P i m Set the corresponding checker PK i m , in advance for each B j im Set the corresponding checker BK j im ; After step S4, the following steps are also included: Step S5: According to the target CX n Configuration checker, checks whether the configured chip gated clock is correct.

5. The method according to claim 4, characterized in that The step S5 comprises: Step S51: If the target CA m n For the first code value, set the corresponding AK m If the target CA is enabled, m n For the second code value, set the corresponding AK m is closed; Step S52: If the target CD m n Set to the first encoding value, then set the corresponding DK m If the target CD is turned on, m n If set to the second encoding value, then set the corresponding DK m is closed; Step S53: If the target CP m n If set to the first encoding value, all corresponding PKs are set. i m In the open state, if the target CP m n If set to the second encoding value, all corresponding PKs are set i m is closed; Step S54: If the target CB m n Set to the first code value, then set all corresponding BK j im In the open state, if the target CB m n Set to the second encoding value, then set all corresponding BK j im is closed; Step S55: Based on all the enabled AK m Check the corresponding A m Whether to enable or disable, based on all enabled PK i m Check the corresponding P i m Whether to enable or disable, based on all enabled BK j im Check the corresponding B j im Whether it is enabled. If all the check results are enabled, the check passes; otherwise, the check fails.

6. The method according to claim 2, characterized in that The step S4 comprises: Step C41, obtain C n Each corresponding P i m Corresponding secondary configuration code EP i m , EP i m Empty or the first code value or the second code value; Step C42: If EP i m If it is empty, set P i m Corresponding target configuration code FP i m =CP m n , if EP i m If it is not empty, set P i m Corresponding target configuration code FP i m =EP i m ; Step C43, obtain C n Each corresponding B j im Corresponding secondary configuration code EB j im , EB j im Empty or the first code value or the second code value; Step C44, if EB j im If it is empty, set B j im Corresponding target configuration code FB j im =CB m n , if EB j im If not empty, set B j im Corresponding target configuration code FB j im =EB j im ; Step C45: If the target CA m n For the first code value, set the corresponding A m If the target CA is enabled, m n For the second code value, set the corresponding A m is closed; Step C46: If the target CD m n Set to the first code value, then set the corresponding D m If the target CD is turned on, m n Set to the second code value, then set the corresponding D m is closed; Step C47: If FP i m For the first code value, set the corresponding P i m In the open state, if FP i m For the second code value, set the corresponding P i m is closed; Step C48, if FB j im For the first code value, set the corresponding B j im If FB is turned on, j im For the second code value, set the corresponding B j im The status is closed.

7. The method according to claim 6, characterized in that The method further comprises: Step C10: Prepare for each A m Set the corresponding checker AK m , in advance for each D m Set the corresponding inspector DK m , in advance for each P i m Set the corresponding checker PK i m , in advance for each B j im Set the corresponding checker BK j im ; After step S4, the following steps are also included: Step C5: According to the target CA m n 、Target CD m n FP i m 、FB j im Configuration checker, checks whether the configured chip gated clock is correct.

8. The method according to claim 7, characterized in that The step C5 comprises: Step C51: If the target CA m n For the first code value, set the corresponding AK m If the target CA is enabled, m n For the second code value, set the corresponding AK m is closed; Step C52: If the target CD m n Set to the first encoding value, then set the corresponding DK m If the target CD is turned on, m n If set to the second encoding value, then set the corresponding DK m is closed; Step C53: If FP i m For the first code value, set the corresponding PK i m In the open state, if FP i m For the second code value, set the corresponding PK i m is closed; Step C54: If FB j im For the first code value, set the corresponding BK j im If FB is turned on, j im For the second code value, set the corresponding BK j im is closed; Step C55: Based on all the enabled AK m Check the corresponding A m Whether to enable or disable, based on all enabled PK i m Check the corresponding P i m Whether to enable or disable, based on all enabled BK j im Check the corresponding B j im Whether it is enabled. If all the check results are enabled, the check passes; otherwise, the check fails.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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