Netlist construction method, computer medium, equipment and program product

Abstract

The invention relates to the field of an EDA design technology and an advanced packaging technology, in particular to a netlist construction method, a computer medium, equipment and a program product. The method comprises the following steps: arranging an element bump and an element pin on the surface of a functional element, and connecting the element bump and the element pin through a signal line in the functional element to construct an internal connection path of the functional element; arranging at least two interposer pins on the surface of the interposer, and connecting different interposer pins in the interposer through signal lines to construct an interposer internal connection path; connecting the element pin and the interposer pin through a signal line to construct an external connection path of the interposer; acquiring position information of the element bumps, and projecting the element bumps to the surface of the interposer to acquire projection points; setting projection bumps on the projection points, and constructing a connection path; and connecting the projection bumps and the connection paths through signal lines in the intermediate layer to complete the construction of the netlist. The problem that a traditional netlist construction method cannot clearly express the connection relation of functional elements is solved.

Description

Technical Field

[0001] The present invention relates to EDA design technology and advanced packaging technology, and in particular to a netlist construction method, computer medium, device and program product. Background Art

[0002] 2.5D chip design is an advanced integrated circuit packaging technology that places multiple independent, pre-fabricated functional chips, also known as functional elements, side by side on a shared silicon interposer. High-density interconnects within the interposer then connect these chips and the interposer to the underlying packaging substrate, ultimately packaging them into a complete system. Traditional 2D chip design relies on the packaging substrate, limiting interconnect density and performance. 3D chip design, on the other hand, offers the highest density and performance potential, but faces significant thermal management and cost challenges.

[0003] Existing 2.5D chip design methods usually construct a 2.5D netlist by parsing a standard Verilog file. The standard Verilog file mainly describes the functional logical connections of circuits. Directly constructing by parsing the language cannot directly and clearly describe the physical hierarchical structure unique to 2.5D packaging, nor can it clearly express the connection relationship between functional elements. Summary of the Invention

[0004] In order to solve the problem that the traditional netlist construction method cannot clearly express the connection relationship between functional elements, the present invention provides a netlist construction method, computer medium, device and program product.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solutions: a netlist construction method for designing a chip in a program, the construction method comprising the following steps: providing a substrate, an interposer, a signal line, and at least two functional elements in the program, and placing the interposer on one side of the substrate; arranging element bumps and element pins on the surface of the functional element, and connecting the element bumps and element pins inside the functional element via signal lines to construct an internal connection path of the functional element; arranging at least two interposer pins on the surface of the interposer, and connecting different interposer pins inside the interposer via signal lines to construct an internal connection path of the interposer; placing the functional element on a side of the interposer away from the substrate, and connecting the element pins and the interposer pins via signal lines to construct an external connection path of the interposer; obtaining position information of the element bump, and projecting the element bump onto the surface of the interposer based on the position information to obtain a projection point; arranging a projection bump at the projection point, and constructing a connection path in the order of the internal connection path of the functional element, the external connection path of the interposer, and the internal connection path of the interposer; and connecting the projection bump and the connection path inside the interposer via signal lines to complete the construction of the netlist.

[0006] Preferably, before providing a substrate, an intermediate layer, a signal line and at least two functional elements, the method also includes: providing a functional element template, in which the type, length, width and substrate data of the functional element are set; obtaining a pre-placement position of the functional element, and instantiating the functional element template based on the pre-placement position to convert the functional element template into a functional element.

[0007] Preferably, the construction of the internal connection path of the functional element specifically includes: introducing a first file, the first file including the functional element name, the element pin name, the first signal line name and the element bump name; parsing the content in the first file; wherein, when parsing the functional element name, the element pin name and the element bump name, the element bump and the element pin are set on the functional element, and when parsing the first signal line name, the element bump and the element pin are connected through the first signal line.

[0008] Preferably, the construction of the internal connection path of the intermediary layer specifically includes: introducing a second file, the second file including the drive type of the pin, the drive purpose of the pin, the intermediary layer pin name and the name of the second signal line; parsing the content in the second file; wherein, one second signal line needs to connect at least two intermediary layer pins, and when parsing the drive type of the pin, the drive purpose of the pin and the name of the intermediary layer pin, a second signal line is set on one intermediary layer pin, and a second signal line is set on another intermediary layer pin, and when parsing the name of the second signal line, if the names of the second signal lines connecting two different intermediary layer pins are the same, the two different intermediary layer pins are connected through one second signal line.

[0009] Preferably, the construction of the external connection path of the intermediary layer specifically includes: introducing a third file, the third file including the functional component name, the component pin name, the pin drive type, the pin drive purpose, the intermediary layer pin name and the third signal line name; parsing the content in the third file; wherein, when parsing the pin drive type, the pin drive purpose, the component pin name and the intermediary layer pin name, the third signal line is set on one component pin, and the third signal line is set on another intermediary layer pin, and when parsing the third signal line name, if the name of the third signal line connecting the component pin and the intermediary layer pin is the same, the component pin and the intermediary layer pin are connected through a third signal line.

[0010] Preferably, projecting the component bumps onto the surface of the intermediary layer based on the position information also includes: layering the intermediary layer and at least two functional elements so that the functional elements and the intermediary layer are divided into multiple hierarchical layers; directly projecting the component bumps toward the intermediary layer based on the position information; wherein, if different functional elements need to establish a connection relationship through the intermediary layer, then after the component bumps on the different functional elements are projected onto the surface of the intermediary layer to form projection points, the formed projection points will be on the same hierarchical layer of the intermediary layer.

[0011] Preferably, the method is applied to 2.5D chip netlist construction, wherein the construction of the connection paths in the order of internal connection paths of functional components, external connection paths of interposers, and internal connection paths of interposers specifically includes: the constructed connection paths are connected in the order of component bumps, first signal lines, component pins, third signal lines, interposer pins, and second signal lines. To solve the above technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions being used to cause the computer to execute the netlist construction method described above.

[0012] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer device, applied to the above netlist construction method, including a memory, a processor and a computer program stored in the memory, and the processor executes the above computer program to implement the netlist construction method.

[0013] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program or instructions, which implements the above netlist construction method when executed by a processor.

[0014] Compared with the prior art, the netlist construction method, computer medium, device and program product provided by the present invention have the following beneficial effects: 1. An embodiment of the present invention provides a netlist construction method for designing a chip in a program, the construction method comprising the following steps: providing a substrate, an interposer, a signal line, and at least two functional elements in the program, and placing the interposer on one side of the substrate; providing element bumps and element pins on the surface of the functional element, and connecting the element bumps and element pins inside the functional element via signal lines to construct an internal connection path of the functional element; providing at least two interposer pins on the surface of the interposer, and connecting different interposer pins inside the interposer via signal lines to construct an internal connection path of the interposer; placing the functional element on a side of the interposer away from the substrate, and connecting the element pins and interposer pins via signal lines to construct an external connection path of the interposer; obtaining position information of the element bump, and projecting the element bump onto the interposer surface based on the position information to obtain a projection point; providing a projection bump at the projection point, and constructing a connection path in the order of the internal connection path of the functional element, the external connection path of the interposer, and the internal connection path of the interposer; and connecting the projection bump and the connection path inside the interposer via signal lines to complete the construction of the netlist. In this embodiment, by using a program to confirm the positional relationship between the virtual substrate, interposer and functional components, and then projecting the component bumps, errors in the parsing file or human input errors can be eliminated. In addition, this embodiment limits the path construction order to avoid path intersection conflicts, realize automatic reconstruction of netlist construction, ensure connection reliability, and clearly express the connection relationship between functional components.

[0015] 2. An embodiment of the present invention further provides a computer-readable storage medium, which has the same beneficial effects as the above-mentioned netlist construction method and is not described in detail here.

[0016] 3. An embodiment of the present invention further provides a computer device having the same beneficial effects as the above-mentioned netlist construction method, which will not be described in detail here.

[0017] 4. An embodiment of the present invention provides a computer program product, comprising a computer program or instructions, which implements the above-mentioned netlist construction method when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a flowchart of a netlist construction method provided by the first embodiment of the present invention.

[0020] Figure 2a It is a schematic diagram of constructing internal connection paths of functional elements in a netlist construction method provided by the first embodiment of the present invention.

[0021] Figure 2b This is a simplified diagram of constructing an internal connection path of an interposer layer in a netlist construction method provided by the first embodiment of the present invention.

[0022] Figure 2c This is a simplified diagram of constructing an interposer layer and a connection path of functional elements in a netlist construction method provided by the first embodiment of the present invention.

[0023] Figure 3a This is a simplified diagram of the projection of the component bumps in the 3D chip according to the first embodiment of the present invention.

[0024] Figure 3b 1 is a schematic diagram of the projection of the component bump in the 2.5D chip according to the first embodiment of the present invention.

[0025] Figure 4a It is a schematic diagram of constructing internal connection paths of functional elements in a netlist construction method provided by the first embodiment of the present invention.

[0026] Figure 4b It is a schematic diagram of constructing the internal connection path of the interposer layer of a netlist construction method provided by the first embodiment of the present invention.

[0027] Figure 4c It is a schematic diagram of constructing an interposer layer and a connection path of functional elements in a netlist construction method provided by the first embodiment of the present invention.

[0028] Figure 5 It is a schematic projection diagram of different functional elements projected onto the middle layer in the first embodiment of the present invention.

[0029] Figure 6 It is a schematic structural diagram of a computer-readable storage medium provided by the second embodiment of the present invention.

[0030] Figure 7 It is a structural diagram of a computer device provided by the third embodiment of the present invention.

[0031] Figure 8 It is a schematic diagram of the structure of a computer program product provided by the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0033] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0034] It should be understood that references to "one embodiment" or "an embodiment" throughout this specification mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the appearance of "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0035] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0036] The flow charts and block diagrams in the accompanying drawings of the present invention illustrate the possible implementation architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementation schemes, the functions marked in the box can also occur in a different order than those marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0037] The rapid advancement of semiconductor integration technology has pushed semiconductor process dimensions closer to their physical limits, ushering in the "post-Moore era." Consequently, the industry has proposed advanced chip packaging technologies to address the growing demand for high-performance, low-power, and low-latency chips. 2.5D chip netlist construction is a key step in chip design for describing and verifying the connections between multiple functional elements in 2.5D heterogeneous integrated systems.

[0038] 2.5D chip design is an advanced integrated circuit packaging technology that places multiple independent, pre-fabricated functional chips, also known as functional elements, side by side on a shared silicon interposer. High-density interconnects within the interposer then connect these chips and the interposer to the underlying packaging substrate, ultimately packaging them into a complete system. Traditional 2D chip design relies on the packaging substrate, limiting interconnect density and performance. 3D chip design, on the other hand, offers the highest density and performance potential, but faces significant thermal management and cost challenges.

[0039] Existing 2.5D chip design methods usually construct a 2.5D netlist by parsing a standard Verilog file. The standard Verilog file mainly describes the functional logical connections of circuits. Directly constructing by parsing the language cannot directly and clearly describe the physical hierarchical structure unique to 2.5D packaging, nor can it clearly express the connection relationship between functional elements.

[0040] Silicon interposer: A high-precision silicon-based thin film located between chip functional components (such as CPU, GPU, HBM memory) and the packaging substrate. Its core function is to achieve high-density, low-latency chip-to-chip interconnection through its internal multi-layer wiring.

[0041] Bump: A micro solder joint used to establish electrical and mechanical connections between a chiplet and an interposer, substrate, or other chips, and an interconnected functional element in a 2.5D / 3D package.

[0042] TSV: Short for Through-Silicon Via, it is a vertical interconnect technology used to achieve electrical connections between chips or wafers, particularly in 2.5D and 3D packaging technologies. TSV etches tiny holes in the silicon substrate or chip and fills them with conductive material (such as copper), enabling direct electrical connections between the top and bottom surfaces of a chip or between multiple layers of chips.

[0043] A functional device refers to a physical chip unit with independent circuit functionality, such as a computing core (CPU, GPU), memory controller, I / O interface, or AI accelerator. Within the package structure, a functional device is integrated onto an interposer as either an active or passive device. Furthermore, the interposer is a special functional element that serves as a carrier to connect different functional devices to each other and to the substrate.

[0044] A device template is a virtual design model of a device.

[0045] The difference between 2.5D and 3D chips: In 2.5D, the functional elements are arranged horizontally and placed side by side on the interposer. There is no direct communication between the functional elements, but rather communication is determined by the interconnection lines (TSV, through-silicon vias) in the interposer; 3D chips use a vertical stacking method, where multiple functional elements are directly stacked together and interconnected through vertical TSVs. It should be noted that the method provided by the present invention does not involve the manufacture or installation of a physical chip, but rather the use of a program to construct a virtual netlist file for chip design. Therefore, the substrate, interposer, signal lines, and functional elements provided in this embodiment are not physical functional elements, but virtual functional elements in the program. Specifically, the method provided in this application is used for 2.5D chips.

[0046] See also Figure 1 A first embodiment of the present invention provides a netlist construction method for designing a chip in a program. The construction method includes the following steps: S1, providing a substrate, an interposer, signal lines, and at least two functional components within the process, and placing the interposer on one side of the substrate; S2, providing component bumps and component pins on the surface of the functional component, and connecting the component bumps and component pins inside the functional component through signal lines to construct an internal connection path of the functional component; S3, disposing at least two interposer pins on a surface of the interposer, and connecting different interposer pins inside the interposer through signal lines to construct an internal connection path of the interposer; S4, placing the functional component on a side of the interposer away from the substrate, and connecting the component pins and the interposer pins through signal lines to build an external connection path of the interposer; S5, obtaining position information of the component bump, and projecting the component bump onto the surface of the interposer based on the position information to obtain a projection point; S6, setting a projection bump on the projection point, and constructing a connection path in the order of an internal connection path of the functional element, an external connection path of the interposer, and an internal connection path of the interposer; S7, connecting the projected bumps and the connection paths through signal lines inside the interposer to complete the construction of the netlist.

[0047] It can be understood that the method provided in this embodiment first performs structural deployment, and provides three functional elements: substrate, interposer and functional element in the program environment. The program environment can provide a virtual physical engine, modeling kernel and verification system. It should be understood that if the physical entity functional elements are directly used for design, it will consume huge costs and manpower and material resources, and the physical functional elements cannot be adjusted and modified secondary. The program environment is the only feasible carrier for netlist construction. It converts the geometric constraints, electrical rules and material properties of the physical world into a computable model, and realizes the high-density chip design tasks that are impossible to complete manually through algorithm automation. Therefore, after providing the virtual substrate, interposer, signal line and functional element in this embodiment, the positional relationship between the substrate and the interposer is first defined.

[0048] Furthermore, this embodiment first provides three types of local connection path construction. For example, the first type is the path construction inside the functional element in step S2: Figure 2a As shown in the figure, HBM is the name of the functional component, and a bump is a component convex surface, typically located on the surface of the functional component. A pin is a component pin also located on the surface of the functional component, and there is usually a certain distance between the component bump and the component pin. The position of the bump is randomly generated. When constructing the path within the functional component, it is only necessary to connect the component bump and the component pin through the signal line net.

[0049] The second type is the internal path construction of the intermediary layer in step S2: Figure 2b As shown in the figure, INTERPROSE is the name of the interposer, term1 and term2 are the names of the interposer pins on the interposer, and net1 and net2 are the names of the signal lines. When constructing the internal path of the interposer, it is only necessary to connect the interposer pins set on the interposer through the signal lines.

[0050] The third category is the path construction between cross-level functional elements in step S3: Figure 2c As shown, net3 and net4 are the names of signal lines. When building paths between functional components across multiple layers, signal lines are simply used to connect the functional components to the interposer. Furthermore, after constructing these three types of local connection paths, the positional relationship between the interposer and the functional components is defined, allowing the functional components, interposer, and substrate to be stacked together in the same order as physical functional components.

[0051] Furthermore, regarding the step of extracting the geometric position data of the component bump and projecting it onto the interposer surface to generate a projection point, it should be noted that since this is a 2.5D chip design, there is no need to provide an intuitive 3D projection in the program. Instead, it is only necessary to project the component bump vertically toward the interposer surface to generate a projection point based on its position. For example, Figure 3a In the figure, bump1 is the component bump on the HBM of the functional component. After projection, bump1 is vertically projected on the surface of the interposer close to the functional component to form a projection point, and bump2 is a projection bump set on the projection point. It should be understood that in the 3D view, the position of the projected projection point is related to the placement position between the functional component and the interposer, and it can be clearly seen in the 3D view that the projection point of the component bump on the functional component projected onto the interposer is unique.

[0052] Please continue reading Figure 3b , and converted to 2.5D view, because the positional relationship between the functional components and the interposer is determined when the functional components and the interposer are placed, the projection point of the component bump on the functional component onto the interposer is also unique, that is, each component bump will generate a corresponding projection point after projection. For example, in Figure 3b In the figure, bump1 is the component bump on the functional component HBM. After projection, bump1 forms a projection point perpendicular to the interposer surface, while bump2 is a projection bump positioned at the projection point. It should be understood that this embodiment provides automated connection based on geometric projection. This method extracts the position coordinates of the component bump, such as a three-dimensional coordinate set, and projects them perpendicularly onto the interposer surface to generate a geometric projection point. This operation is performed automatically within the program, requiring no manual intervention. A projection bump is set at the projection point as a connection anchor point within the interposer. The position of the projection point indicates that when the functional component and the interposer come into contact, the component bump and the projection bump can directly contact each other, completing the shortest electrical connection path requirement and minimizing actual signal transmission delay. In other words, this embodiment transforms the connection between the component bump and the interposer circuit into a geometric mapping problem that can be automatically calculated within the program. Furthermore, when the functional component position is adjusted, the component bump coordinates are synchronously updated. The program automatically reprojects to generate new projection points and dynamically reconstructs the position of the projection bump. Because the connection path is generated based on program rules, the newly projected bump can be quickly integrated into the existing path framework, significantly shortening the design iteration cycle.

[0053] Furthermore, after the projection bumps are set, this embodiment sets the order for constructing the netlist. The complete netlist first needs to integrate three types of local connection paths in order: internal paths of functional components: component bumps to component pins are interconnected through signal lines, external paths of the interposer: component pins to interposer pins, and internal paths of the interposer: interposer pins are interconnected through signal lines. This order will ensure that the connection paths are closed layer by layer, completing the connection in the order of component bumps, signal lines, component pins, signal lines, interposer pins, and signal lines. When the connection paths are closed layer by layer, the projection bumps will be connected to the system at the internal path stage of the interposer, completing the construction of the entire netlist.

[0054] It should be understood that traditional netlist construction methods, which only parse a standard file, cannot directly and clearly describe the physical hierarchical structure unique to 2.5D packaging, nor can they clearly express the connection relationships between functional components. However, in this embodiment, by using a program to confirm the positional relationship between the virtual substrate, interposer, and functional components, and then projecting the component bumps, errors that may occur in file parsing or human input errors can be eliminated. In addition, this embodiment defines the path construction order to avoid path intersection conflicts and achieve automated reconstruction of netlist construction, ensuring connection reliability while clearly expressing the connection relationships between functional components.

[0055] Specifically, before providing the substrate, the interposer, the signal line, and the at least two functional elements, the method further includes: Providing a functional element template, wherein the functional element type, length, width and substrate data thereof are set in the functional element template; A pre-placement position of the functional element is obtained, and the functional element template is instantiated based on the pre-placement position to convert the functional element template into a functional element.

[0056] As can be understood, this embodiment allows for pre-defined digital functional component templates within the program. For example, the templates may include functional component type identifiers, such as CPU, HBM, or GPU; geometric parameters, such as length, width, and thickness; or data about the substrate to which the functional component belongs, such as the matching substrate model and thermal expansion coefficient constraints. The pre-placed positions of the functional components serve as input parameters for instantiation. Instantiation is a key step in the electronic design process, transforming abstract functional component templates into concrete design entities. By applying specific layout positions, it converts the local geometric descriptions within the templates into absolute coordinates within a global coordinate system and establishes a real-time association between the component instances and the designed substrate. This allows for efficient and consistent generation of layout-ready and connectable functional component objects, significantly improving netlist construction and physical design efficiency. Based on this positional data, the program automatically converts local coordinates within the template, such as the offset of pins relative to the center of the functional component, into absolute coordinates within the global coordinate system. It also allows for real-time binding of the positional relationships between the instantiated functional component and the substrate and interposer. This allows designers to quickly convert functional component templates into functional components before placing the functional components, improving netlist construction efficiency.

[0057] Further, see Figure 4a In the above step S2, constructing the internal connection path of the functional element specifically includes: Importing a first file, the first file includes a functional component name, a component pin name, a first signal line name, and a component bump name; Parse the content of the first file; When parsing the function element name, element pin name and element bump name, the element bump and element pin are set on the function element; when parsing the first signal line name, the element bump and element pin are connected through the first signal line.

[0058] It is understandable that in this embodiment, when constructing a local connection path, the storage medium can be imported to form the basis for netlist construction. The first file is the pin_list file. After the first file is imported, the first file contains a large number of functional component names, component pin names, first signal line names, and component bump names. For example, Figure 4a In the example, HBM_A is the name of the functional component, pinWDQSh3_t is the name of the component pin, and A168 is the name of the component bump. When parsing the first file, if HBM_A, A168, and pinWDQSh3_t are found, the component bump A168 and the component pin pinWDQSh3_t will be automatically set on the functional component HBM_A. When WDQSh3_t is found, A168 and pinWDQSh3_t will be automatically connected through the signal line WDQSh3_t to form the following: Figure 4a The local connection path in .

[0059] It should be understood that in this implementation, virtual pins and bumps are automatically generated by parsing the file fields: the program creates virtual component pins and component bumps on the surface of the functional element according to the component pin names and component bump names in the file, and also connects them through signal lines to establish the positional relationship between the component pins and component bumps, thereby realizing seamless transmission of path data within the functional element and ensuring that the path within the functional element is completely closed.

[0060] Further, see Figure 4b In the above step S3, constructing the internal connection path of the intermediary layer specifically includes: Importing a second file, the second file includes the pin drive type, the pin drive purpose, the interposer pin name, and the second signal line name; Parse the content of the second file; Among them, a second signal line needs to connect at least two interposer pins. When parsing the pin's drive type, the pin's drive purpose and the interposer pin name, a second signal line is set on one interposer pin, and a second signal line is set on another interposer pin. When parsing the second signal line name, if the second signal lines connecting two different interposer pins have the same name, the two different interposer pins are connected through one second signal line.

[0061] It can be understood that the second file is a term_lis file. After the second file is introduced, the second file contains a large number of interposer pin names and the drive types and drive purposes of the pins corresponding to the interposer pins. For example, Figure 4b INTERPOSER in the file is the name of the interposer, and pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are the names of the interposer pins. When parsing the second file, when pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are parsed, the interposer pins pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] will be automatically set on the interposer. In addition, the pin's drive type and drive purpose will also be parsed during the pin setting process. It should be noted that there are three types of pin drive types, namely input, output, and inout. Input represents the signal transmitted from the interposer to the pin, output represents the signal transmitted from the pin to the interposer, and input represents the signal transmitted within the interposer and between the pins. There are two main drive purposes of the pin, one is signal use and the other is power use. The pin drive can limit the function of the pin. That is, when parsing the pin drive type, pin drive purpose and interposer pin name, the pin location can be constructed in the interposer. When further parsing chip_top_A_SD_WDQSh_t[3], pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are automatically connected through the signal line chip_top_A_SD_WDQSh_t[3]. Figure 4b The local connection path in .

[0062] It should be understood that in this implementation, virtual pins are automatically generated by parsing the file fields: the program creates virtual interposer pins on the interposer surface according to the interposer pin names in the file, connects different interposer pins through signal lines, and determines the positional relationship between different interposer pins, thereby achieving seamless transmission of path data within the interposer and ensuring that the path within the interposer is completely closed.

[0063] Further, see Figure 4c In the above step S4, constructing the external connection path of the intermediary layer specifically includes: Importing a third file, the third file includes the function component name, component pin name, pin drive type, pin drive purpose, interposer pin name, and third signal line name; Parse the content of the third file; Among them, when parsing the pin drive type, the pin drive purpose, the component pin name and the interposer pin name, a third signal line is set on one component pin, and a third signal line is set on another interposer pin. When parsing the name of the third signal line, if the name of the third signal line connecting the component pin and the interposer pin is the same, the component pin and the interposer pin are connected through one third signal line.

[0064] It can be understood that the third file is a term_map file. After the third file is introduced, the second file contains a large number of functional component names, component pin names, interposer pin names, and pin drive types and drive purposes. For example, Figure 4b INTERPOSER is the interposer name, HBM_A and chip_top are the functional component names, pinWDQSh3_t and pinWDQSh3_t[3] are the component pin names, and pinHBM_A_SD_WDQSh3_t and pinchip_top_A_SD_WDQSh_t[3] are the interposer pin names. When parsing the third file, if INTERPOSER, HBM_A and chip_top are parsed, the component pins on the functional component and the interposer pins on the interposer will be automatically connected. When pinWDQSh3_t and pinHBM_A_SD_WDQSh3_t are parsed, the drive type and drive purpose of pinWDQSh3_t and pinHBM_A_SD_WDQSh3_t will be parsed first. When HBM_A_SD_WDQSh3_t is parsed, the pinWDQSh3_t and pinHBM_A_SD_WDQSh3_t will be automatically connected through the signal line HBM_A_SD_WDQSh3_t. The component pin pinWDQSh3_t[3] on the functional component chip_top and the interposer pin pinchip_top_A_SD_WDQSh_t[3] on the interposer are connected through the signal line chip_top_A_SD_WDQSh_t[3], which will not be described in detail again.

[0065] It can be understood that in this implementation, by parsing the file fields, the component pins and the intermediary layer pins are automatically connected through signal lines according to the drive type and drive purpose of the pins, and the positional relationship between the component pins and the intermediary layer pins is determined, thereby achieving seamless transmission of path data between the functional element and the intermediary layer, ensuring that the path between the intermediary layer and the functional element is completely closed.

[0066] Specifically, the present invention provides a complete method for constructing a 2.5D netlist, innovatively using pin_list, term_list, and term_map as storage media for the basis of netlist construction. Compared with Verilog files, the storage method proposed in this embodiment makes it easier to discover the relative relationships between various pins, functional components, and signal lines, which is intuitive and clear.

[0067] Specifically, projecting the component bump onto the interposer surface based on the position information further includes: performing layered processing on the intermediary layer and the at least two functional elements so that the functional elements and the intermediary layer are divided into a plurality of hierarchical layers; Directly projecting the component bump toward the interposer based on the position information; If different functional components need to establish a connection relationship through an interposer, after the component bumps on the different functional components are projected onto the surface of the interposer to form projection points, the formed projection points will be on the same hierarchical layer of the interposer.

[0068] It should be understood that the interposer and functional components are composed of multiple layered structures with inconsistent materials. Usually, signal lines are set on the same layer, and only in special cases will signal lines be set on different layers. Therefore, if different functional components need to be connected together through the same interposer and the connection relationship between them is obtained when building the netlist, it is necessary to project the projection bumps corresponding to the component bumps on different functional components onto the same layer of the interposer as much as possible. Figure 5 As shown in the figure, the functional element HBM1 is divided into n1 layers, and the element bump 1 is set on its a layer. The functional element HBM2 is divided into n2 layers, and the element bump 3 is set on its b layer. When the element bump 1 is projected onto the interposer, and when the element bump 2 is projected onto the interposer to form a projection point, the two projection points will be on the same hierarchical layer of the interposer. Figure 5 As shown, the interposer is divided into n3 layers, and projection bumps bump2 and bump4 are respectively set on two projection points, and bump2 and bump4 are both located on the cth layer of the interposer.

[0069] Furthermore, the method provided in this embodiment is applied to the construction of a 2.5D chip netlist. The connection path is constructed in the order of the internal connection path of the functional element, the external connection path of the interposer, and the internal connection path of the interposer. Specifically, the constructed connection path will be connected in the order of the component bump, the first signal line, the component pin, the third signal line, the interposer pin, and the second signal line. It should be understood that the existing method cannot obtain the connection relationship between these components. In this embodiment, the path construction order is limited to avoid path intersection conflicts, realize the automatic reconstruction of the netlist construction, ensure the connection reliability, and clearly express the connection relationship between the functional elements.

[0070] Please combine Figure 1 and Figure 6 The second embodiment of this embodiment further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the above-mentioned netlist construction method.

[0071] The computer-readable storage medium provided in the embodiment of the present invention has the same beneficial effects as the above-mentioned netlist construction method, which will not be described in detail here.

[0072] Please combine Figure 1 and Figure 7 The third embodiment of this embodiment also provides a computer device, which is applied to the above-mentioned netlist construction method, including a memory, a processor and a computer program stored in the memory, and the processor executes the above-mentioned computer program to implement the netlist construction method.

[0073] The computer device provided by the embodiment of the present invention has the same beneficial effects as the above-mentioned netlist construction method, which will not be described in detail here.

[0074] Please combine Figure 1 and Figure 8 The fourth embodiment of this embodiment further provides a computer program product, including a computer program or instructions, which implements the above-mentioned netlist construction method when executed by a processor.

[0075] The computer program product provided by the embodiment of the present invention has the same beneficial effects as the above-mentioned netlist construction method, which will not be described in detail here.

[0076] The above is a detailed introduction to a netlist construction method, computer medium, device and program product disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent replacements and improvements made within the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A netlist construction method for designing a chip in a program, characterized by: The construction method comprises the following steps: Provide a substrate, an interposer, signal lines, and at least two functional components within the process, and place the interposer on one side of the substrate; Arranging component bumps and component pins on the surface of the functional component, and connecting the component bumps and component pins via signal lines inside the functional component to construct an internal connection path of the functional component; At least two interposer pins are provided on the surface of the interposer, and different interposer pins are connected inside the interposer through signal lines to construct an internal connection path of the interposer; Place the functional components on the side of the interposer away from the substrate, and connect the component pins and the interposer pins through signal lines to build an external connection path for the interposer; Acquire position information of the component bump, and project the component bump onto the surface of the interposer based on the position information to obtain a projection point; Setting projection bumps on the projection points, and constructing connection paths in the order of internal connection paths of the functional elements, external connection paths of the intermediary layers, and internal connection paths of the intermediary layers; The projection bumps and connection paths are connected by signal lines inside the interposer to complete the construction of the netlist.

2. The netlist construction method according to claim 1, wherein: Before providing a substrate, an interposer, a signal line, and at least two functional elements, the method further includes: Providing a functional element template, wherein the functional element type, length, width and substrate data thereof are set in the functional element template; A pre-placement position of the functional element is obtained, and the functional element template is instantiated based on the pre-placement position to convert the functional element template into a functional element.

3. The netlist construction method according to claim 2, wherein: The construction of the internal connection path of the functional element specifically includes: Importing a first file, the first file includes a functional component name, a component pin name, a first signal line name, and a component bump name; Parse the content of the first file; When parsing the function element name, element pin name and element bump name, the element bump and element pin are set on the function element; when parsing the first signal line name, the element bump and element pin are connected through the first signal line.

4. The netlist construction method according to claim 2, wherein: The construction of the internal connection path of the intermediary layer specifically includes: Importing a second file, the second file includes the pin drive type, the pin drive purpose, the interposer pin name, and the second signal line name; Parse the content of the second file; Among them, a second signal line needs to connect at least two interposer pins. When parsing the pin's drive type, the pin's drive purpose and the interposer pin name, a second signal line is set on one interposer pin, and a second signal line is set on another interposer pin. When parsing the second signal line name, if the second signal lines connecting two different interposer pins have the same name, the two different interposer pins are connected through one second signal line.

5. The netlist construction method according to claim 2, wherein: The construction of the external connection path of the intermediary layer specifically includes: Importing a third file, the third file includes the function component name, component pin name, pin drive type, pin drive purpose, interposer pin name, and third signal line name; Parse the content of the third file; Among them, when parsing the pin drive type, the pin drive purpose, the component pin name and the interposer pin name, a third signal line is set on one component pin, and a third signal line is set on another interposer pin. When parsing the name of the third signal line, if the name of the third signal line connecting the component pin and the interposer pin is the same, the component pin and the interposer pin are connected through one third signal line.

6. The netlist construction method according to claim 1, wherein: Projecting the component bump onto the interposer surface based on the position information further includes: performing layered processing on the intermediary layer and the at least two functional elements so that the functional elements and the intermediary layer are divided into a plurality of hierarchical layers; Directly projecting the component bump toward the interposer based on the position information; If different functional components need to establish a connection relationship through the interposer, after the component bumps on the different functional components are projected onto the surface of the interposer to form projection points, the formed projection points will be on the same hierarchical layer of the interposer.

7. The netlist construction method according to claim 6, wherein: The method is applied to constructing a 2.5D chip netlist, and constructing a connection path in the order of an internal connection path of a functional element, an external connection path of an interposer, and an internal connection path of an interposer specifically includes: The constructed connection path is connected in the order of component bump, first signal line, component pin, third signal line, interposer pin, and second signal line.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the netlist construction method according to any one of claims 1 to 7.

9. A computer device, applied to the netlist construction method according to any one of claims 1 to 7, characterized in that: The system comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the netlist construction method.

10. A computer program product, characterized in that: The method comprises a computer program or an instruction, wherein when the computer program or the instruction is executed by a processor, the method for constructing a netlist according to any one of 1 to 7 is implemented.

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