Circuit-level simulation method for single-particle latch-up effect
By establishing the SPICE model parameter relationship between the layout geometric dimensions and the parasitic latch structure of the CMOS process, circuit-level batch simulation is realized, which solves the problem of evaluating the anti-single-particle latch effect of integrated circuits and improves the reliability evaluation efficiency of integrated circuits in the radiation environment.
Patent Information
- Application Number
- CN202510532412.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-08-29
AI Technical Summary
The prior art has insufficient simulation capabilities in evaluating the anti-single-particle latch effect of integrated circuits, it is difficult to support the simulation of batch circuits or large-scale circuits, and it is impossible to effectively evaluate the performance of non-ideal parasitic bipolar transistor structures.
Through device-level simulation, the corresponding relationship between the layout geometry and the SPICE model parameters of the parasitic latch structure of CMOS process is established, and the SPICE netlist is generated using TCAD simulation and scripts to achieve circuit-level batch simulation to evaluate the anti-single-particle latch capability.
It significantly improves the reliability evaluation efficiency of integrated circuits in radiated environments, and can quickly and accurately evaluate the latch resistance after reinforcement of the layout.
Smart Images
Figure CN120562355A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit radiation resistance design, and in particular to a circuit-level simulation method for single-particle latch-up effect. Background Art
[0002] The Earth is surrounded by a complex radiation environment, primarily consisting of galactic cosmic rays and solar energetic particles from space, as well as various high-energy particles on the ground. Galactic cosmic rays are primarily composed of protons and alpha particles, with a wide range of energies; solar energetic particles, on the other hand, are primarily composed of protons and helium nuclei, with energies concentrated in the low-megaelectronvolt range. The widespread use of integrated circuits in fields such as aerospace inevitably exposes them to this radiation environment. High-energy particles in these environments can cause ionization and displacement effects on materials, leading to device performance degradation or functional failure. Single-event latch-up (SEL) is a significant factor affecting device reliability. This effect occurs when heavy ions bombard sensitive device regions, generating electron-hole pairs. These pairs are collected in the depletion region of the PN junction, resulting in transient current spikes that disrupt the device's electrostatic potential, turning on parasitic bipolar transistors and creating positive feedback, ultimately causing device failure.
[0003] Currently, CMOS process integrated circuits use N-type wells and P-type wells to form PN junctions for electrical isolation. NMOS is fabricated in PWs, and PMOS is fabricated in NWs. In this process, parasitic bipolar transistor structures and well resistors together form a parasitic PNPN structure. Under bombardment by high-energy particles, the parasitic PNPN structure can be triggered to form a low-resistance path, thereby burning out the integrated circuit. Traditional SEL mitigation methods rely primarily on process optimization or local layout hardening. In terms of simulation, TCAD simulation technology is widely used for device-level analysis, enabling detailed simulation of the radiation resistance performance of individual devices. Foundries also typically provide standard bipolar transistor cell libraries, which contain both lateral PNP and vertical NPN transistors, and provide corresponding models for circuit design simulation. These standard cell libraries have fixed device sizes and magnification factors, which can support circuit-level simulation analysis to a certain extent.
[0004] However, the existing technology has obvious deficiencies in the evaluation of anti-SEL capabilities. Although TCAD simulation can perform device-level analysis, it is difficult to support the simulation of batch circuits or large-scale circuits, and cannot meet the needs of complex integrated circuit design. In addition, the device size and amplification factor of the standard bipolar transistor cell library provided by the Foundry are fixed, and different amplification factors cannot be obtained by changing the device size, which limits the adaptability to different design requirements. More importantly, in the actual CMOS process, in addition to the standard bipolar transistor cell library, there are many non-ideal parasitic bipolar transistor structures. The parameters of these structures are different, and the existing technology cannot use circuit simulation to evaluate their performance. Therefore, the existing technology lacks a circuit-level fast simulation method that can extract parasitic PNPN structure models in combination with layout geometry parameters to quickly and accurately evaluate the anti-latch capability after layout reinforcement. Summary of the Invention
[0005] To address the aforementioned technical issues of low efficiency and insufficient model accuracy in existing single-event latch-up resistance assessments, a circuit-level simulation method for single-event latch-up effects is provided. Through device-level simulation, the present invention establishes a correspondence between layout geometry and SPICE model parameters for parasitic latch-up structures in CMOS processes. This enables batch circuit-level simulation and assessment of single-event latch-up resistance, significantly improving the efficiency of integrated circuit reliability assessments in radiation environments.
[0006] The technical means adopted in the present invention are as follows:
[0007] A circuit-level simulation method for single-event latch-up effect, comprising:
[0008] S1. In the radiation-hardened circuit layout, use the geometric parameter extraction script to obtain the key geometric parameters of the radiation-hardened design;
[0009] S2. Using TCAD simulation, the corresponding relationship between key geometric parameters and parasitic latch structure parameters is obtained;
[0010] S3. Use scripts to batch extract the feature dimensions of the layout and generate a SPICE netlist with a latch structure based on the corresponding relationship;
[0011] S4. Use SPICE simulation to evaluate the layout's ability to resist single-particle latch-up and implement circuit-level simulation of single-particle latch-up.
[0012] Furthermore, in step S1, the radiation hardening design specifically includes:
[0013] Increasing the distance between the NMOS and PMOS active regions increases the base width of the lateral parasitic NPN transistor, increases the probability of carrier recombination, and reduces the BJT current gain;
[0014] A guard ring is set around the NMOS and PMOS active areas and connected to the well contact. The guard ring reduces the well / substrate resistance and feedback loop gain by connecting more contact holes in parallel, making the base of the parasitic PNP tube very close to the power supply potential, avoiding the vertical parasitic PNP from turning on, and thus forming a positive feedback loop, reducing the sensitivity of the SEL of the CMOS circuit. More contact holes are drilled on the well contact guard ring to reduce the substrate resistance and well resistance.
[0015] Furthermore, in step S1 , the key geometric parameters include: the distance between the active area and the distance between the guard ring well and the active area, and the distance between the guard rings.
[0016] Furthermore, step S2 specifically includes:
[0017] S21. Use TCAD device modeling tools to perform process modeling;
[0018] S22. Perform irradiation simulation using a heavy ion implantation model of a TCAD device-level simulation tool to obtain corresponding relationships between key geometric parameters and parasitic latch structure parameters in the CMOS process.
[0019] S23, extracting parameters of the parasitic latch structure, including well resistance, substrate resistance, and SPICE model parameters of NPN and PNP bipolar transistors;
[0020] S24. Adjust the key geometric parameters of the guard ring and active area, repeat TCAD modeling and simulation, and establish a lookup table of layout geometric parameters and parasitic latch structure SPICE model parameters.
[0021] Furthermore, the device modeling tool in step S21 provides a detailed simulation of the semiconductor manufacturing process, including doping, thin film deposition, oxidation, and etching process steps, and simulates the impact of various process parameters on the final device characteristics; based on the layout geometry, the process steps and parameters are defined to construct a radiation-hardened layout device-level model.
[0022] Furthermore, step S22 specifically includes:
[0023] Specify the time when particles are injected into the device, describe the location where heavy ions enter the device, define the vector of the particle movement direction, define the linear transmission of heavy ions, and define the length and characteristic distance of particle incidence; after adding the heavy ion injection model, if the ground current increases and does not return to the initial value, single-particle latch-up occurs.
[0024] Furthermore, in the CMOS process, the N-well and the P-substrate form a parasitic PNPN structure, which includes vertical NPN and lateral PNP bipolar transistors. The SEL triggering condition is:
[0025] I particle *Rwell >V th
[0026] Among them, I particle is the single-particle transient current, R well is the well resistance, V th is the parasitic PNP transistor on-state voltage.
[0027] Furthermore, step S3 specifically includes:
[0028] The feature size is extracted from the layout, and a SPICE netlist with a latch structure is generated using a script based on the lookup table constructed by the device-level simulation in step S24.
[0029] Furthermore, step S4 specifically includes:
[0030] S41. A pulse current source is used to simulate irradiation. The double exponential current source is a classic model for simulating single-event transient current pulses. The mathematical expression is as follows:
[0031] I (t) =I0*(e -t / τ1 -e -t / τ2 )
[0032] Where I0 is the peak current, τ1 is the charge collection time constant, and τ2 is the time constant for initializing the particle trajectory.
[0033] A current pulse is injected into the sensitive node to simulate the conduction of the parasitic PNPN structure triggered by single-particle injection, causing the latch-up current to continue to rise. If SEL is not triggered, the ground current returns to normal after the current pulse. If SEL is triggered, the power supply current continues to rise and cannot be recovered. The critical trigger conditions are recorded and compared with the critical trigger conditions of TCAD simulation to evaluate the circuit's resistance to single-particle latch-up and realize circuit-level simulation of single-particle latch-up.
[0034] Compared with the prior art, the present invention has the following advantages:
[0035] The present invention provides a circuit-level simulation method for single-particle latch-up effects. Through device-level simulation, a correspondence between layout geometry and SPICE model parameters of parasitic latch-up structures in CMOS processes is established. This method enables batch simulation and evaluation of single-particle latch-up resistance at the circuit level, significantly improving the efficiency of reliability assessment of integrated circuits in radiation environments.
[0036] Based on the above reasons, the present invention can be widely promoted in fields such as integrated circuit radiation resistance design. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0038] Figure 1 Flow chart of the method of the present invention.
[0039] Figure 2 A diagram of a parasitic latch structure of a CMOS process provided in an embodiment of the present invention.
[0040] Figure 3 This is a schematic diagram of the core idea of the present invention. DETAILED DESCRIPTION
[0041] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.
[0042] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or apparatuses.
[0043] like Figure 1 As shown, the present invention provides a circuit-level simulation method for a single-particle latch-up effect, comprising:
[0044] S1. In the radiation-hardened circuit layout, use the geometric parameter extraction script to obtain the key geometric parameters of the radiation-hardened design;
[0045] S2. Use TCAD simulation to obtain the corresponding relationship between key geometric parameters and parasitic latch structure parameters; that is, extract the IV characteristic curve of the parasitic BJT and fit the SPICE model parameters; and extract the well resistance and substrate resistance values of the latch structure.
[0046] S3. Use scripts to batch extract the feature dimensions of the layout and generate a SPICE netlist with a latch structure based on the corresponding relationship;
[0047] S4. Use SPICE simulation to evaluate the layout's ability to resist single-particle latch-up and implement circuit-level simulation of single-particle latch-up.
[0048] In specific implementation, as a preferred embodiment of the present invention, in step S1, the radiation-resistant reinforcement design specifically includes:
[0049] Increasing the distance between the NMOS and PMOS active regions increases the base width of the lateral parasitic NPN transistor, increases the probability of carrier recombination, and reduces the BJT current gain;
[0050] A guard ring is set around the NMOS and PMOS active areas and connected to the well contact. The guard ring reduces the well / substrate resistance and feedback loop gain by connecting more contact holes in parallel, making the base of the parasitic PNP tube very close to the power supply potential, avoiding the vertical parasitic PNP from turning on, and thus forming a positive feedback loop, reducing the sensitivity of the SEL of the CMOS circuit. More contact holes are drilled on the well contact guard ring to reduce the substrate resistance and well resistance.
[0051] In specific implementation, as a preferred embodiment of the present invention, in step S1, the key geometric parameters include: the distance between the active area and the distance between the guard ring well and the active area, and the distance between the guard rings.
[0052] In specific implementation, as a preferred embodiment of the present invention, step S2 specifically includes:
[0053] S21. Use device modeling tools to perform process modeling;
[0054] S22. Perform irradiation simulation using a heavy ion implantation model of a device-level simulation tool to obtain the corresponding relationship between key geometric parameters such as active area distance and parasitic latch structure parameters in the CMOS process;
[0055] S23, extracting parameters of the parasitic latch structure, including well resistance, substrate resistance, and SPICE model parameters of NPN and PNP bipolar transistors;
[0056] S24. Adjust the key geometric parameters of the guard ring and active area, repeat TCAD modeling and simulation, and establish a lookup table of layout geometric parameters and parasitic latch structure SPICE model parameters.
[0057] In specific implementation, as a preferred embodiment of the present invention, the device modeling tool in step S21 provides a detailed simulation of the semiconductor manufacturing process, including doping, thin film deposition, oxidation, and etching process steps, and simulates the influence of various process parameters on the final device characteristics; according to the layout geometry, the process steps and parameters are defined to construct a radiation-hardened layout device-level model.
[0058] In specific implementation, as a preferred embodiment of the present invention, step S22 specifically includes:
[0059] Specify the time when particles are injected into the device, describe the location where heavy ions enter the device, define the vector of the particle movement direction, define the linear transmission of heavy ions, and define the length and characteristic distance of particle incidence; after adding the heavy ion injection model, if the ground current increases and does not return to the initial value, single-particle latch-up occurs.
[0060] In a specific implementation, as a preferred embodiment of the present invention, in a CMOS process, the N well and the P substrate form a parasitic PNPN structure, including vertical NPN and lateral PNP bipolar transistors, and the SEL triggering condition is:
[0061] I particle *R well >V th
[0062] Among them, I particle is the single-particle transient current, R well is the well resistance, V th is the parasitic PNP transistor conduction voltage. In this embodiment, Figure 2 As shown, the CMOS parasitic latch structure is as follows:
[0063] An NPN bipolar transistor consists of an NMOS N+ region (emitter), a P-substrate (base), and an N-well (collector). A PNP bipolar transistor consists of a PMOS P+ region (emitter), an N-well (base), and a P-substrate (collector). The well resistor is formed by the N-well resistor. The substrate resistor is formed by the P-substrate resistor. The two parasitic bipolar transistors form a silicon controlled rectifier (SCR) structure.
[0064] In specific implementation, as a preferred embodiment of the present invention, step S3 specifically includes:
[0065] The feature size is extracted from the layout, and a SPICE netlist with a latch structure is generated using a script based on the lookup table constructed by the device-level simulation in step S24. In this embodiment, the SPICE netlist is an input file used by the SPICE simulator to describe an electronic circuit. It lists the components of the circuit (such as resistors, MOS tubes, BJTs, etc.) and their connection relationships in a text format. The SPICE simulator (Simulation Program with Integrated Circuit Emphasis) is designed to provide efficient and accurate simulation support for the design of integrated circuits and electronic systems. Its core function is to simulate the behavior of circuits in static, dynamic and frequency domains through mathematical modeling and numerical calculations, thereby assisting engineers in verifying functions, optimizing performance and predicting potential problems during the design phase.
[0066] In specific implementation, as a preferred embodiment of the present invention, step S4 specifically includes:
[0067] S41. A pulse current source is used to simulate irradiation. The double exponential current source is a classic model for simulating single-event transient current pulses. The mathematical expression is as follows:
[0068] I (t) =I0*(e -t / τ1 -e -t / τ2 )
[0069] Where I0 is the peak current, τ1 is the charge collection time constant, and τ2 is the time constant for initializing the particle trajectory.
[0070] A current pulse is injected into the sensitive node to simulate the conduction of the parasitic PNPN structure triggered by single-particle injection, causing the latch-up current to continue to rise. If SEL is not triggered, the ground current returns to normal after the current pulse. If SEL is triggered, the power supply current continues to rise and cannot be recovered. The critical trigger conditions are recorded and compared with the critical trigger conditions of TCAD simulation to evaluate the circuit's resistance to single-particle latch-up and realize circuit-level simulation of single-particle latch-up.
[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A circuit-level simulation method for single-event latch-up, characterized in that: include: S1. In the radiation-hardened circuit layout, use the geometric parameter extraction script to obtain the key geometric parameters of the radiation-hardened design; S2. Using TCAD simulation, the corresponding relationship between key geometric parameters and parasitic latch structure parameters is obtained; S3. Use scripts to batch extract the feature dimensions of the layout and generate a SPICE netlist with a latch structure based on the corresponding relationship; S4. Use SPICE simulation to evaluate the layout's ability to resist single-particle latch-up and implement circuit-level simulation of single-particle latch-up.
2. The circuit-level simulation method for single-event latch-up according to claim 1, wherein: In step S1, the radiation hardening design specifically includes: Increasing the distance between the NMOS and PMOS active regions increases the base width of the lateral parasitic NPN transistor, increases the probability of carrier recombination, and reduces the BJT current gain; A guard ring is set around the NMOS and PMOS active areas and connected to the well contact. The guard ring reduces the well / substrate resistance and feedback loop gain by connecting more contact holes in parallel, making the base of the parasitic PNP tube very close to the power supply potential, avoiding the vertical parasitic PNP from turning on, and thus forming a positive feedback loop, reducing the sensitivity of the SEL of the CMOS circuit. More contact holes are drilled on the well contact guard ring to reduce the substrate resistance and well resistance.
3. The circuit-level simulation method for single event latch-up according to claim 1, wherein: In step S1 , the key geometric parameters include: the distance between the active area and the distance between the guard ring well and the active area, and the distance between the guard rings.
4. The circuit-level simulation method for single event latch-up according to claim 1, wherein: Step S2 specifically includes: S21. Use TCAD device modeling tools to perform process modeling; S22. Perform irradiation simulation using a heavy ion implantation model of a TCAD device-level simulation tool to obtain corresponding relationships between key geometric parameters and parasitic latch structure parameters in the CMOS process. S23, extracting parameters of the parasitic latch structure, including well resistance, substrate resistance, and SPICE model parameters of NPN and PNP bipolar transistors; S24. Adjust the key geometric parameters of the guard ring and active area, repeat TCAD modeling and simulation, and establish a lookup table of layout geometric parameters and parasitic latch structure SPICE model parameters.
5. The circuit-level simulation method for single-event latch-up according to claim 4, wherein: The device modeling tool in step S21 provides a detailed simulation of the semiconductor manufacturing process, including doping, thin film deposition, oxidation, and etching process steps, and simulates the impact of various process parameters on the final device characteristics; Based on the layout geometry, process steps and parameters are defined to build a radiation-hardened layout device-level model.
6. The circuit-level simulation method for single-event latch-up according to claim 4, wherein: Step S22 specifically includes: Specify the time when particles are injected into the device, describe the location where heavy ions enter the device, define the vector of the particle movement direction, define the linear transmission of heavy ions, and define the length and characteristic distance of particle incidence; after adding the heavy ion injection model, if the ground current increases and does not return to the initial value, single-particle latch-up occurs.
7. The circuit-level simulation method for single-event latch-up according to claim 4, wherein: In the CMOS process, the N-well and P-substrate form a parasitic PNPN structure, which includes vertical NPN and lateral PNP bipolar transistors. The SEL triggering conditions are: I particle *R well >V th Among them, I particle is the single-particle transient current, R well is the well resistance, V th is the parasitic PNP transistor on-state voltage.
8. The circuit-level simulation method for single event latch-up according to claim 1, wherein: Step S3 specifically includes: The feature size is extracted from the layout, and a SPICE netlist with a latch structure is generated using a script based on the lookup table constructed by the device-level simulation in step S24.
9. The circuit-level simulation method for single event latch-up according to claim 1, wherein: Step S4 specifically includes: S41. A pulse current source is used to simulate irradiation. The double exponential current source is a classic model for simulating single-event transient current pulses. The mathematical expression is as follows: I (t) =I0*(ie -t / τ1 -have been -t / τ2 ) Where I0 is the peak current, τ1 is the charge collection time constant, and τ2 is the time constant for initializing the particle trajectory. A current pulse is injected into the sensitive node to simulate the conduction of the parasitic PNPN structure triggered by single-particle injection, causing the latch-up current to continue to rise. If SEL is not triggered, the ground current returns to normal after the current pulse. If SEL is triggered, the power supply current continues to rise and cannot be recovered. The critical trigger conditions are recorded and compared with the critical trigger conditions of TCAD simulation to evaluate the circuit's resistance to single-particle latch-up and realize circuit-level simulation of single-particle latch-up.