Wiring time optimization method considering wiring area granularity

Abstract

The invention belongs to the technical field of circuit wiring, and discloses a wiring time optimization method considering wiring area granularity, which comprises the following steps: S10, data processing: after reading in a GUIDE file, processing grids of a wiring area through a step length formula; marking an obstacle area, and constructing an initial wiring grid considering wiring obstruction; s20, track distribution is carried out on wiring metal wires, and the read-write authority of the wiring space of the adjacent layer is opened for each PANEL area; when metal wires generate conflicts, whether redundant wiring resources exist in a wiring area of an adjacent layer of a current wiring area or not is inquired firstly, and if the wiring resources exist and design rule violation is not caused after the current wiring section is allocated to the adjacent layer, track allocation of the current wiring section is successful; and S30, wiring is carried out, wiring is carried out on the wiring segment by using the wiring grid, and labyrinth wiring is carried out in the currently extracted wiring array by using a multi-thread bidirectional wiring method. According to the invention, the wiring process is efficient, universal and manually controllable.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit wiring, and in particular relates to a wiring time optimization method considering wiring area granularity. Background Art

[0002] Routing is the most complex and time-consuming step in the entire very large-scale integrated circuit (VLSI) physical design process. To reduce routing complexity, the entire routing process is now divided into two phases: 1) global routing and 2) detailed routing. The primary goal of global routing is to provide guidance for subsequent detailed routing, thereby reducing routing complexity and overall time overhead. The final output is a global cell (GCELL)-level path for each net. This path is routed only between coarse-grained global routing cells, providing routing guidance for subsequent detailed routing. Because the connections between GCELLs in global routing cannot be directly represented as metal lines, track allocation is required for these connections. After track allocation, detailed routing must meet key constraints such as routability and design rule violations locally, while minimizing wire length and the number of vias.

[0003] Before routing, track allocation will roughly allocate the connection lines in the global routing solution (GUIDE file) to different tracks in the routing area to pre-process the routing metal lines. The latest track allocation algorithm is a negotiated track allocation algorithm, in which the routing metal lines are called iroutes. Before track allocation, the multiple GCELLs that the iroute passes through are merged together as a PANEL, and track allocation is performed in each different PANEL. The initial stage of track allocation uses a greedy algorithm to effectively identify the initial track allocation results that allow iroute overlap, followed by an overlap reduction stage, which iteratively performs wire removal and rerouting to eliminate iroute overlap as much as possible. In the commonly used NTA algorithm, metal lines are routed to different tracks with a smaller overlap cost, but in more congested areas, the reduction in overlap cost may not be significant. At the same time, after the wire removal and rerouting process in the overlap reduction stage is completed, there is still a considerable amount of overlapping area in the PANEL, which may cause short circuits in local areas. In the subsequent wire removal and rerouting stage, attempts will be repeatedly made to reroute these short-circuited metal wires, resulting in a lot of time consumption. When congestion caused by these overlaps occurs, even if there are additional wiring resources in the upper and lower layers adjacent to the current wiring area, they will not be used by the metal lines of the current layer. Therefore, this also causes a waste of wiring resources to a certain extent.

[0004] After the track allocation is completed, each metal wire will have its own track. The detailed routing phase that follows will interconnect all related metal wires that have not yet been connected, as well as related pins and other components, so that the complete functionality of the circuit can be realized. In the algorithm of the latest router TritonRoute-WXL, routing still uses the traditional breadth-first A* path search algorithm. However, due to the "overlap" problem in the track allocation phase and the huge amount of redundant data information introduced during the routing process, its routing is particularly time-consuming. Although an innovative queue-based wire removal and rerouting algorithm has been proposed, the number of metal wires required for wire removal and rerouting is still too large, which further affects the time consumption of its routing.

[0005] In this router's rerouting method, the conflicting and conflicted nets are referred to as "aggressors" and "victims," ​​respectively. A rerouting queue (also used for initial routing) is established. At the start of routing, all routed nets are added to the routing queue, and the net at the head of the queue is removed in order to complete the routing operation. However, due to various routing cost constraints, some nets may be "incorrectly" routed due to excessive costs, such as routing directly across an already routed net, resulting in routing conflicts. The currently incorrectly routed net is called the "victim," and the net that causes the victim to be incorrectly routed is called the "aggressor." The attacker's presence encroaches on the victim's path, which was originally routable, causing routing failures on the victim and ultimately generating routing violations. When a routing conflict occurs, the nets belonging to both the attacker and victim are completely removed and added to the end of the rerouting queue, awaiting rerouting. When the routing queue routes to the nets belonging to both the attacker and victim, it attempts to reroute the victim before rerouting the attacker, minimizing routing violations.

[0006] The TritonRoute-WXL algorithm uses a queue-based routing and rerouting method to reduce design rule violations to near zero, essentially resolving the design rule violation issue. However, due to the high complexity and sheer scale of routing, the overall routing time remains unchanged. Furthermore, because each step in the routing process considers more constraints, the data structure is extremely large, generating a significant amount of redundant data at each step, further increasing routing time.

[0007] Furthermore, traditional routing algorithms rarely consider the construction of routing grids. Routing grids are extracted from tracks within the design file. Tracks of varying spans create grids with varying granularity, leading to completely different search spaces during the subsequent routing phase, impacting routing success rates and other factors. A smaller search space leads to faster convergence, but also increases the risk of routing violations. Balancing the impact of routing grid granularity and routing speed on final routing quality can significantly improve existing routing quality. Summary of the Invention

[0008] In order to solve the above problems, the present invention proposes a wiring time optimization method that takes the wiring area granularity into consideration, and the wiring process is efficient, universal and manually controllable.

[0009] To achieve the above object, the present invention adopts a technical solution: a wiring time optimization method considering the granularity of wiring area, comprising the steps of: S10, data processing: After reading the GUIDE file, the grid of the routing area is processed using the step size formula to coarsen the routing grid and reduce unnecessary redundant search space; while building the grid, the obstacle area is marked to construct the initial routing grid that takes routing obstacles into consideration; S20, track allocation is performed for routing metal lines. After the PANEL is divided, track allocation is performed. At the same time, read and write permissions for the routing space of the adjacent layers are opened for each PANEL area. When a metal line conflict occurs, the routing area of ​​the adjacent layer of the current routing area is first checked to see if there are excess routing resources. If there are routing resources, and allocating the current routing segment to the adjacent layer does not cause design rule violations, the track allocation for the current routing segment is successful. S30, routing is performed using the routing grid extracted in the data processing stage to route the routing segments. At the same time, a multi-threaded bidirectional routing method is used to perform maze routing in the currently extracted routing array. The currently routed array can be used as a path storage array to provide path search support for subsequent wiring removal and rerouting.

[0010] Furthermore, the data processing process includes the following steps: All routing segment information is obtained from the GUIDE file, and the predetermined track information read from the design file is obtained from the global database. The center lines of all routing metal wires are aligned with the tracks. After reading the data from the GUIDE file, the distribution of metal wires in different tracks is obtained, that is, the guidance information for metal wire routing. At the same time, the LUT lookup table is used to search for all pins and obstacles in the current area and calculate the track information they occupy, which serves as the basis for subsequent wiring array extraction; After all the wire path guide information, pins, and obstruction object information are calculated, the stride K is calculated; the stride K is used to determine the span between the two selected tracks; After the span K is determined, the track represented by the current wiring area is extracted to obtain a wiring path diagram.

[0011] Furthermore, the calculation formula of the stride K is: ; Among them, P represents the number of pins in the current routing area; T represents the number of tracks in the current routing area, including the number of tracks in the priority direction and the non-priority direction; parameter A represents the ratio of the obstruction area in the current routing area to the area of ​​the entire routing area, which is used to calculate the impact of the obstruction on the current routing area; parameter and Parameters are user-defined to meet and requirements; When user-defined parameters The closer it is to 1, the smaller the impact of the number of pins on the current routing track; when the user customizes the parameter The closer it is to 1, the smaller the impact of the obstacle metal occupying the track on the wiring track.

[0012] Furthermore, a two-dimensional plane array is used to represent the wiring path Figure 3 The dimensional structure is called a wiring array, and the extraction process of the wiring array includes the following steps: Starting from the first track t=1, when the span is 3, the selected track sequence is <1, 4, 7, 10, ...>. The tracks occupied by pins and obstruction objects are used as candidate paths for the routing array. At the same time, the tracks occupied by all metal wire guides read from GUIDE and the tracks occupied by the start and end points of the routing algorithm are also used as candidate paths for the routing array. The final routing array is extracted from the candidate paths of the routing array.

[0013] Furthermore, the track allocation stage includes the steps of: According to the wiring array extracted by data processing, the entire wiring plane is divided into different panels, and within each panel, the initial allocation of the NTA algorithm is used, and the initial track is allocated to the metal wire indicated by the wiring guide information within each panel using a greedy algorithm; After the initial allocation is completed, the algorithm process enters the overlap reduction phase, opening the read and write permissions of the corresponding wiring areas of the adjacent layers for the current wiring layer, so as to make more reasonable use of wiring resources.

[0014] Furthermore, when entering the overlap reduction stage, the read and write permissions of the current wiring area to its adjacent layers are opened. Therefore, when the metal lines on the track overlap, the adjacent wiring layers are first searched for overlapping solutions. If no overlap occurs after trying to allocate the current metal line to the adjacent layer wiring area, the current attempted solution will be used as the final solution for the wiring metal line.

[0015] Furthermore, in the overlap reduction phase: The overlap cost c of the current layer i The calculation formula is: ; Where, is the area of ​​the area where metal line i overlaps with other metal lines on the current layer, which is calculated based on the geometric relationship of the routing area; is the length of metal wire i, and Used to adjust the impact of different factors on overlapping costs; among them, Emphasize the impact of overlapping areas, Emphasize wire length.

[0016] The cost p of metal lines after being allocated to adjacent layers i The calculation formula is: ; Where, is the overlapping cost of metal line i in adjacent layers, represents the penalty cost after being allocated to adjacent layers, is a constant less than or equal to 1, p i Used to control the impact of penalty costs on the final total cost; Whether to move to the adjacent area: ; in, is a binary variable, =1 means there is overlap in adjacent layers, and the adjacent layer movement cost in the formula is prohibited, that is, the metal line cannot be moved to the adjacent layer; = 0 means there is no overlap in adjacent layers. Only when the current metal line is allowed to move to the adjacent layer; If the current routing metal line is found to still have overlap or design violations after trying to allocate it to the same routing area of ​​the adjacent layer, it is considered that the adjacent layer allocation has failed; after the stage of all metal lines trying to allocate to the adjacent layer is completed, iterative wiring and rerouting are performed for these metal lines that failed to be allocated to find a solution that reduces the overlap cost.

[0017] Furthermore, in step S30, a multi-threaded bidirectional multi-path maze routing method is used to find an interconnected line for all components associated with metal wires and pins through a maze routing algorithm, thereby realizing interconnection between components and obtaining the final routing result.

[0018] Furthermore, starting from the current routing starting point s, the Manhattan distance is calculated for each routing position in the routing array, and a diffusion calculation is performed on each grid to obtain the Manhattan distance of each position in the current routing array; The current routing array is further split into smaller routing regions of different size ranges, and the Manhattan distance is calculated in each region using multi-threading. After calculating the Manhattan distance of each grid in the entire array, a multi-threaded approach is used to start from the starting point s and the end point t and walk towards each other to find a possible wiring path.

[0019] Furthermore, if the start and end points are completely separated by obstacles, there is no valid path in the current routing area that can connect the start and end points, and the path backtracking algorithm cannot find any available path, then the current line net is marked as routing failure; In the post-processing stage, the interconnected objects that have no access at all will be subjected to final wiring removal and re-routing.

[0020] The beneficial effects of adopting this technical solution are: The present invention can provide an efficient, universal and human-controllable routing grid coarsening algorithm to reduce the routing search space and improve the routing speed.

[0021] The present invention proposes an efficient and universal algorithm for performing multi-level track allocation in the track allocation stage, thereby reducing the number of repeated iterations in the post-processing stage and further improving the routing speed.

[0022] The present invention proposes an efficient and universal multi-threaded bidirectional multi-path maze routing based on a coarsened routing grid to reduce redundant data during routing, thereby accelerating the path tracing process and improving the overall routing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic flow chart of a wiring time optimization method considering wiring area granularity according to the present invention; Figure 2: is an extraction diagram of a wiring array in an embodiment of the present invention, wherein: (a) is the initial state, (b) is the extracted wiring array; Figure 3 This is a multi-level track allocation diagram in an embodiment of the present invention, where: (a) is the initial track allocation, (b) is the multi-level allocation, and (c) is the final result; Figure 4 The initial wiring path array and its expansion diagram in an embodiment of the present invention, where: (a) is the initial wiring array, (b) is the path cost expansion; Figure 5 Graph of the multi-threaded maze routing algorithm in an embodiment of the present invention, where: (a) is the diffusion path distance, (b) is the path backtracking; Figure 6 This is a graph where the starting and ending points are completely separated by obstacles in an embodiment of the present invention, where: (a) is the Manhattan distance of the failed path, and (b) is the backtracking of the failed path. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0025] In this embodiment, see Figure 1 As shown, the present invention proposes a wiring time optimization method considering the wiring area granularity, comprising the steps of: S10, data processing: After reading the GUIDE file, the grid of the routing area is processed using the step size formula to coarsen the routing grid and reduce unnecessary redundant search space to achieve the purpose of accelerating routing. While building the grid, the obstacle area (the area affected by other metals or fixed shapes) is marked to construct the initial routing grid that takes routing obstacles into consideration. S20, track allocation for routing metal lines. After dividing the PANEL, the NTA algorithm is used to allocate the tracks. However, while allocating, the read and write permissions of the routing space of the adjacent layers are opened for each PANEL area. When a metal line conflict occurs, unlike the direct iterative wiring removal and rerouting of the NTA algorithm, the routing area of ​​the adjacent layers of the current routing area is first checked to see if there are excess routing resources. If there are routing resources, and allocating the current routing segment to the adjacent layer does not cause design rule violations, the track allocation of the current routing segment is successful. This avoids potential multiple wiring removal and rerouting processes, fully utilizing the resources of each layer while also accelerating the entire routing process. S30: Routing is performed using the routing grid extracted during the data processing phase to route the routing segments. A multi-threaded bidirectional routing method is used to perform maze routing within the currently extracted routing array. The currently routed array serves as a path storage array, supporting path finding for subsequent routing removal and rerouting. This reduces redundant data during the routing process, thereby improving routing efficiency.

[0026] As an optimization solution of the above embodiment, the data processing process includes the following steps: All routing segment information is obtained from the GUIDE file, and the predetermined track information read from the design file is obtained from the global database. The center lines of all routing metal wires are aligned with the tracks to avoid potential design rule violations. After reading the data from the GUIDE file, the distribution of metal wires on different tracks is obtained, that is, the guidance information for metal wire routing. At the same time, the LUT lookup table is used to search for all pins and obstacles in the current area and calculate the track information they occupy, which serves as the basis for subsequent wiring array extraction; After all the wire path guide information, pins, and obstruction object information are calculated, the stride K is calculated; the stride K is used to determine the span between the two selected tracks; After the span K is determined, the track represented by the current wiring area is extracted to obtain a wiring path diagram.

[0027] The calculation formula of the stride K is: ; Among them, P represents the number of pins in the current routing area; T represents the number of tracks in the current routing area, including the number of tracks in the priority direction and the non-priority direction; parameter A represents the ratio of the obstruction area in the current routing area to the area of ​​the entire routing area, which is used to calculate the impact of the obstruction on the current routing area; parameter and Parameters are user-defined to meet and requirements; When user-defined parameters The closer it is to 1, the smaller the impact of the number of pins on the current routing track; when the user customizes the parameter The closer it is to 1, the smaller the impact of the obstacle metal occupying the track on the wiring track.

[0028] By properly setting and The value of can balance the impact of pins and obstacles on the number of tracks in more complex routing situations, thereby designing a more appropriate routing area.

[0029] Use a two-dimensional plane array to represent the wiring path Figure 3 dimensional structure, called wiring array, the extraction process of the wiring array is as follows Figure 2 As shown, the steps include: Starting from the first track t=1, when the span is 3, the selected track sequence is <1,4,7,10,...>. However, considering that objects such as obstacles and pins will occupy some tracks, which will have a certain impact on subsequent track allocation and routing, the tracks occupied by pins and obstacles are used as candidate paths for the routing array. At the same time, the tracks occupied by all metal wire guides read from GUIDE and the tracks occupied by the start and end points of the routing algorithm are also used as candidate paths for the routing array to expand the number of candidate tracks of the entire routing array, thereby ensuring a sufficiently large routing area for all objects to be interconnected. The final routing array is extracted from the candidate paths of the routing array, such as Figure 2 As shown in (b) in .

[0030] As an optimization solution of the above embodiment, the track allocation stage includes the following steps: According to the wiring array extracted by data processing, the entire wiring plane is divided into different PANELs, and within each PANEL, the initial allocation of the NTA algorithm is used, such as Figure 3 As shown in (a), a greedy algorithm is used to allocate initial tracks to the metal wires indicated by the wiring guide information within each PANEL; After the initial allocation is completed, the algorithm process enters the overlap reduction phase, opening the read and write permissions of the corresponding wiring areas of the adjacent layers for the current wiring layer, so as to make more reasonable use of wiring resources.

[0031] Enter the overlap reduction phase, such as Figure 3 As shown in (b), the current routing area has the read and write permissions for its adjacent layers open. Therefore, when the metal lines on the track overlap, the adjacent routing layers are first searched for a solution to whether there is overlap. If no overlap occurs after trying to allocate the current metal line to the adjacent layer routing area, the current attempted solution is used as the final solution for the routing metal line, as shown in Figure 1. Figure 3 It should be noted that in chip design, in order to avoid problems such as crosstalk, the routing directions of adjacent layers are generally perpendicular to each other. The adjacent layer referred to in this invention means the nearest layer with the same routing direction as the current layer, that is, Figure 3 In the M1 and M3 layers, the wiring direction of the M2 layer is vertical. In order to better illustrate the technology used in this method, the schematic diagram of the M2 layer is not drawn.

[0032] During the overlap reduction phase: The overlap cost c of the current layer i The calculation formula is: ; Where, is the area of ​​the area where metal line i overlaps with other metal lines on the current layer, which is calculated based on the geometric relationship of the routing area; is the length of metal wire i. Generally speaking, the longer the metal wire, the greater the routing complexity and potential overlap issues; and Used to adjust the impact of different factors on overlapping costs; among them, Emphasize the impact of overlapping areas, Emphasize wire length.

[0033] The cost p of metal lines after being allocated to adjacent layers i The calculation formula is: ; Where, is the overlapping cost of metal line i in adjacent layers, represents the penalty cost after being assigned to the adjacent layer, and the cost is a random value not greater than half of the overlapping cost, that is, , Is a constant less than or equal to 1, used to control the penalty cost to the final total cost p i The impact depends on the user; Whether to move to the adjacent area: ; in, is a binary variable, =1 means there is overlap in adjacent layers, and the adjacent layer movement cost in the formula is prohibited, that is, the metal line cannot be moved to the adjacent layer; = 0 means there is no overlap in adjacent layers. Only when the current metal line is allowed to move to the adjacent layer; If the current routing metal line is found to still have overlap or design violations after trying to allocate it to the same routing area of ​​the adjacent layer, it is considered that the adjacent layer allocation has failed; after the stage of all metal lines trying to allocate to the adjacent layer is completed, iterative wiring and rerouting are performed for these metal lines that failed to be allocated to find a solution that reduces the overlap cost.

[0034] Because potential overlapping costs are avoided as much as possible through a multi-level track allocation algorithm before attempting to remove and re-route the wires, the workload of removing and re-routing the wires in the iterative phase is greatly reduced, thereby speeding up the entire track allocation process and potentially improving the overall efficiency of the wiring.

[0035] like Figure 4 As shown, Figure 4 (a) in the figure shows the wiring array generated during the data processing phase. After the current wiring start point s and end point t are added to the array, an initial wiring array result is formed, in which the center line of each grid is aligned with the track, and the wiring segments are arranged in the center of each grid, thereby aligning with the track. The grid with a value of -2 in the grid represents the track segment occupied by the pin or obstacle during the data processing phase, and the wiring segments around the pin or obstacle are more likely to generate violations than other wiring areas. Therefore, after considering various pins and obstacles during the data processing phase, their surroundings will be defined as "areas with possible violations", and the size of this area will vary depending on different objects. In the present invention, a grid with a value of -1 is used to represent it uniformly, such as Figure 4 As shown in (b) in . Figure 4 (b) in the figure shows the final routing grid before routing. This grid is represented by a two-dimensional array. The remaining blank areas are set to zero in the design, indicating "reachable paths." With this expanded routing array, we can apply a maze routing algorithm to the starting point (s) and end point (t) of the interconnected nodes to find the corresponding routing path.

[0036] In step S30, a multi-threaded bidirectional multi-path maze routing method is used to find an interconnected line for all components associated with metal wires and pins through a maze routing algorithm, thereby realizing interconnection between components and obtaining the final routing result.

[0037] Figure 5 The calculation of Manhattan distance and the path backtracking process after the calculation are completed are shown. Figure 5 As shown in (a), starting from the current routing starting point s, the Manhattan distance is calculated for each routable position in the routing array. For example, starting from s, the Manhattan distance is calculated for the grids in the four directions above, below, left, and right. However, to the right and below s, there are routing areas where violations may occur, that is, grids with a grid value of -1, so these grids with a value of -1 are ignored in the calculation. The calculation is then diffused for each grid to obtain the Manhattan distance for each position in the current routing array. In order to further speed up the current routing process, the current routing array is further split into smaller routing areas of different size ranges, and the Manhattan distance is calculated in each area using multi-threading, thereby speeding up the calculation process of the Manhattan distance of the entire grid. The calculation method is still the same as Figure 5 As shown in (a) in .

[0038] After calculating the Manhattan distance of each grid in the entire array, we use multi-threading to start from the starting point s and the end point t and move in opposite directions to find the possible wiring path; Figure 5As shown in (b), with s and t as the starting points and t and s as the end points, two possible routing paths are found using a multi-threaded approach. After the two paths are found, they will be recorded in the array at the same time, so that the next time a path is found, the maze algorithm can be avoided to perform repeated path search work, unless a complete path is not found from s to t. Figure 5 (b) in the figure shows a case of bidirectional path search, where the paths found by s and t are not the same path.

[0039] In the process of searching for a path, there is another situation, that is, s and t find the same path, which will not affect the final result, because our ultimate goal in the wiring stage is to find a wiring path connecting the starting and ending points.

[0040] Bidirectional multi-threaded path search ensures that when there is a path between the starting and ending points, at least one available path can be found. Figure 5 As shown in (b), two paths are found. After allocating the metal wires to the two paths, their costs are compared and the path with the lower cost is used as the final wiring path array.

[0041] This method not only accelerates routing but also potentially finds multiple available routing paths. This provides more possibilities for finding new paths for conflicting paths during the subsequent rerouting phase, potentially avoiding multiple rerouting cycles. Furthermore, because the array only records potential path information, finding a new path from the starting point to the end point is extremely fast and accurate. Furthermore, because the path array only stores a limited amount of digital information, its memory overhead is almost negligible, and memory issues caused by the transmission of redundant information during routing are avoided.

[0042] Meanwhile, in this routing array, grids with a value of -1 are still "pathways" for routing, but there's a greater chance of design rule violations when routing from the current area. If, when backtracking, all other available directions are -1, any direction is selected as the next routing path until it passes through the area covered by the current grid with a value of -1, or reaches a dead end.

[0043] like Figure 6 As shown in the figure, when the start and end points are completely separated by obstacles, there is no valid path in the current routing area that can connect the start and end points, and no available path can be found through the path backtracking algorithm, then the current wire net is marked as routing failure; the routing failure path will be used in the final post-processing stage by using the less efficient but more common traditional wire removal and rerouting method to find possible connecting paths for the current routing failure object in a larger routing area.

[0044] In the post-processing stage, interconnected objects that have no access at all will be subjected to final rewiring. In this stage, the queue-based rewiring method in the router TritonRoute-WXL is used to rewire all unrouted objects on a finer routing grid and a larger range to achieve 100% connection between all interconnected components.

[0045] Since the above steps have minimized violations and other situations as much as possible, the number of objects that need to be re-routed in the post-processing stage will be greatly reduced, thereby greatly improving the efficiency of the re-route stage, which has the largest number of iterations and is the most time-consuming in the entire wiring process.

[0046] Through the above steps, the present invention can help achieve higher quality track allocation results through sophisticated design of data structures and algorithms in different routing stages, while improving the overall efficiency and quality of the routing stage.

[0047] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A routing time optimization method considering routing area granularity, characterized in that: Including steps: S10, data processing: after reading the GUIDE file, the grid of the routing area is processed using the step size formula to coarsen the routing grid and reduce unnecessary redundant search space; While building the grid, the obstacle areas are marked to construct the initial routing grid that takes routing obstacles into consideration; S20, track allocation is performed for routing metal lines. After the PANEL is divided, track allocation is performed. At the same time, read and write permissions for the routing space of the adjacent layers are opened for each PANEL area. When a metal line conflict occurs, the routing area of ​​the adjacent layer of the current routing area is first checked to see if there are excess routing resources. If there are routing resources, and allocating the current routing segment to the adjacent layer does not cause design rule violations, the track allocation for the current routing segment is successful. S30, routing is performed using the routing grid extracted in the data processing stage to route the routing segments. At the same time, a multi-threaded bidirectional routing method is used to perform maze routing in the currently extracted routing array. The currently routed array can be used as a path storage array to provide path search support for subsequent wiring removal and rerouting.

2. The method for optimizing wiring time considering wiring area granularity according to claim 1, characterized in that: The data processing process includes the following steps: All routing segment information is obtained from the GUIDE file, and the predetermined track information read from the design file is obtained from the global database. The center lines of all routing metal wires are aligned with the tracks. After reading the data from the GUIDE file, the distribution of metal wires in different tracks is obtained, that is, the guidance information for metal wire routing. At the same time, the LUT lookup table is used to search for all pins and obstacles in the current area and calculate the track information they occupy, which serves as the basis for subsequent wiring array extraction; After all the wire path guide information, pins, and obstruction object information are calculated, the stride K is calculated; the stride K is used to determine the span between the two selected tracks; After the span K is determined, the track represented by the current wiring area is extracted to obtain a wiring path diagram.

3. The method for optimizing wiring time considering wiring area granularity according to claim 2, characterized in that: The calculation formula of the stride K is: ； Among them, P represents the number of pins in the current routing area; T represents the number of tracks in the current routing area, including the number of tracks in the priority direction and the non-priority direction; parameter A represents the ratio of the obstruction area in the current routing area to the area of ​​the entire routing area, which is used to calculate the impact of the obstruction on the current routing area; parameter and Parameters are user-defined to meet and requirements; When user-defined parameters The closer it is to 1, the smaller the impact of the number of pins on the current routing track; when the user customizes the parameters The closer it is to 1, the smaller the impact of the obstacle metal occupying the track on the wiring track.

4. The method for optimizing wiring time considering wiring area granularity according to claim 3, characterized in that: A two-dimensional planar array is used to represent the three-dimensional structure of the wiring path diagram, which is called a wiring array. The extraction process of the wiring array includes the following steps: Starting from the first track t=1, when the span is 3, the selected track sequence is <1, 4, 7, 10, ...>. The tracks occupied by pins and obstruction objects are used as candidate paths for the routing array. At the same time, the tracks occupied by all metal wire guides read from GUIDE and the tracks occupied by the start and end points of the routing algorithm are also used as candidate paths for the routing array. The final routing array is extracted from the candidate paths of the routing array.

5. The method for optimizing wiring time considering wiring area granularity according to claim 1, characterized in that: The track allocation stage includes the following steps: According to the wiring array extracted by data processing, the entire wiring plane is divided into different panels, and within each panel, the initial allocation of the NTA algorithm is used, and the initial track is allocated to the metal wire indicated by the wiring guide information within each panel using a greedy algorithm; After the initial allocation is completed, the algorithm process enters the overlap reduction phase, opening the read and write permissions of the corresponding wiring areas of the adjacent layers for the current wiring layer, so as to make more reasonable use of wiring resources.

6. The method for optimizing wiring time considering wiring area granularity according to claim 5, characterized in that: Entering the overlap reduction stage, the current wiring area has read and write permissions for its adjacent layers. Therefore, when metal lines on the track overlap, the adjacent wiring layers are first searched for overlap solutions. If no overlap occurs after trying to allocate the current metal line to the adjacent layer wiring area, the current attempted solution will be used as the final solution for the wiring metal line.

7. The method for optimizing wiring time considering wiring area granularity according to claim 5, characterized in that: During the overlap reduction phase: Overlap cost of the current layer The calculation formula is: ； Where, is the area of ​​the area where metal line i overlaps with other metal lines on the current layer, which is calculated based on the geometric relationship of the routing area; is the length of metal wire i, and Used to adjust the impact of different factors on overlapping costs; among them, Emphasize the impact of overlapping areas, Emphasis on wire length; Cost of metal lines after being distributed to adjacent layers The calculation formula is: ； Where, is the overlapping cost of metal line i in adjacent layers, represents the penalty cost after being allocated to adjacent layers, Is a constant less than or equal to 1, used to control the penalty cost to the final total cost the impact of; Whether to move to the adjacent area: ； in, is a binary variable, =1 means there is overlap in adjacent layers, and the adjacent layer movement cost in the formula is prohibited, that is, the metal line cannot be moved to the adjacent layer; = 0 means there is no overlap in adjacent layers; that is, when Only when the current metal line is allowed to move to the adjacent layer; If the current routing metal line is found to still have overlap or design violations after trying to allocate it to the same routing area of ​​the adjacent layer, it is considered that the adjacent layer allocation has failed; after the stage of all metal lines trying to allocate to the adjacent layer is completed, iterative wiring and rerouting are performed for these metal lines that failed to be allocated to find a solution that reduces the overlap cost.

8. The method for optimizing wiring time considering wiring area granularity according to claim 1, characterized in that: In step S30, a multi-threaded bidirectional multi-path maze routing method is used to find an interconnected line for all components associated with metal wires and pins through a maze routing algorithm, thereby realizing interconnection between components and obtaining the final routing result.

9. The method for optimizing wiring time considering wiring area granularity according to claim 8, characterized in that: Starting from the current routing starting point s, the Manhattan distance is calculated for each routing position in the routing array, and the diffusion calculation is performed on each grid to obtain the Manhattan distance of each position in the current routing array; The current routing array is further split into smaller routing regions of different size ranges, and the Manhattan distance is calculated in each region using multi-threading. After calculating the Manhattan distance of each grid in the entire array, a multi-threaded approach is used to start from the starting point s and the end point t and walk towards each other to find a possible wiring path.

10. The method for optimizing routing time considering routing area granularity according to claim 9, characterized in that: If the start and end points are completely separated by obstacles, there is no valid path in the current routing area that can connect the start and end points, and the path backtracking algorithm cannot find any available path, then the current line network is marked as routing failure; In the post-processing stage, the interconnected objects that have no access at all will be subjected to final wiring removal and re-routing.

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