Display device

Abstract

The present disclosure relates to a display device in which sub-pixels of a portion of a display panel are driven at a first frequency of a low frequency and sub-pixels of another portion of the display panel are driven at a second frequency of a high frequency. There is provided a display device including: a display panel including a plurality of sub-pixels; a data driver configured to output a data voltage and an update voltage to the display panel; a gate driver configured to output a scan signal and an initialization signal to the display panel; and a timing controller configured to output a timing control signal to the data driver and the gate driver, in which the data voltage is a signal changed to a level corresponding to the gradation value, and the update voltage is a signal swinging between an on level and an off level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0029524, filed on February 29, 2024, which is hereby incorporated by reference herein in its entirety for all purposes. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device of which a portion can be driven at a low frequency and another portion can be driven at a high frequency. Background Art

[0004] The display device may be mounted on electronic products or home appliances such as a TV, a monitor, a laptop computer, a smartphone, a tablet computer, an electronic tablet, a wearable device, a watch, a navigation system, or a vehicle control display device, and used as a screen to display images.

[0005] Display devices can display moving images. This is done by converting still images on a frame-by-frame basis. Recently, moving image sources have become increasingly high-definition, such as 4K and 8K. In particular, when displaying images such as games, faster scene changes are required.

[0006] Multiple screens can be displayed on a display device. For example, a background screen can be displayed, and a video can be displayed on a portion of the screen. The image on the background screen changes slightly, while the image on the video screen changes significantly. Summary of the Invention

[0007] The present disclosure is directed to a display device that can be driven at different frequencies for each portion of a screen of the display device. The present disclosure relates to a display device in which a portion can be driven at a low frequency and another portion can be driven at a high frequency. For example, a portion on which a video is displayed can be driven at a high frequency, and a background portion on which a still image is displayed can be driven at a low frequency. Thus, in a display device according to the present disclosure, a portion of a screen can be driven at a low frequency, and another portion can be driven at a high frequency.

[0008] A display device according to the present disclosure may include: a display panel including a plurality of sub-pixels; a data driver configured to output a data voltage and an update voltage to the display panel; a gate driver configured to output a scan signal and an initialization signal to the display panel; and a timing controller configured to output a timing control signal to the data driver and the gate driver, wherein the update voltage may be a signal that swings between an on-level and an off-level, and the data voltage is a signal that is changed to a level corresponding to a grayscale value. Preferably, the update voltage may be applied to an update node, and when the update voltage has an on-level, the sub-pixel may be updated, and when the update voltage has an off-level, the sub-pixel is not updated and may be maintained.

[0009] A display device according to the present disclosure may include: a display panel including a plurality of sub-pixels; a data driver configured to output a data voltage and an update voltage to the sub-pixels of the display panel; and a gate driver configured to control the application of the data voltage to the sub-pixel through a first transistor and a second transistor in a sub-pixel among the plurality of sub-pixels, the first transistor being configured to be turned on or off based on a scan signal, and the second transistor being configured to be turned on or off based on the update voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a view illustrating a display device according to the present disclosure.

[0011] Figure 2 is a circuit diagram illustrating a sub-pixel according to the present disclosure.

[0012] Figure 3 is a view for describing a data driver according to the present disclosure.

[0013] Figure 4 is a view for describing a gate driver according to the present disclosure.

[0014] Figure 5 is a view illustrating an output screen of a display device according to the present disclosure.

[0015] Figure 6 is a timing diagram for describing an update operation and a hold operation of a sub-pixel according to the present disclosure.

[0016] Figure 7 is a timing diagram illustrating update voltages applied to subpixels according to the present disclosure.

[0017] Figure 8 is a timing diagram illustrating data voltages applied to sub-pixels according to the present disclosure.

[0018] Figure 9is a diagram illustrating a timing for updating sub-pixels according to the present disclosure.

[0019] Figures 10 to 13 It shows that according to Figure 9 A view of the timing updates of sub-pixel operations.

[0020] Figure 14 is a diagram illustrating a timing for holding a sub-pixel according to the present disclosure.

[0021] Figures 15 to 18 It shows that according to Figure 14 A view of the timing holding sub-pixel operation. DETAILED DESCRIPTION

[0022] The advantages and features of the present disclosure and the methods for achieving them will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. The embodiments are provided only to make the disclosure of the present disclosure complete and fully inform those skilled in the art to which the present disclosure belongs of the scope of the present disclosure, and the present disclosure is limited only by the scope of the appended claims.

[0023] Since the shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are illustrative, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when describing the present disclosure, when it is determined that the detailed description of the relevant known technology may unnecessarily obscure the main points of the present disclosure, its detailed description will be omitted. When using the terms "including", "having", "consisting of..." etc. described in this specification, other parts may be added unless "only" is used. When a component is represented in the singular, it includes the case where the component is provided as a plurality of components, unless otherwise specifically stated.

[0024] When interpreting a component, the component is interpreted as including the error range even if there is no separate explicit description.

[0025] When describing a positional relationship, for example, when terms "on", "above", "below", "beside", etc. are used to describe the positional relationship between two parts, one or more other parts may be positioned between the two parts unless the terms "immediately" or "directly" are used.

[0026] When an element or layer is described as being “on” another element or layer, it includes both the case where the element or layer is directly on the other element or layer and the case where other layers or elements are interposed therebetween.

[0027] Although terms such as first and second are used to describe various components, the components are not limited by the terms. The terms are only used to distinguish one component from another. Therefore, within the technical spirit of the present disclosure, the first component described below may be the second component.

[0028] Like reference numerals refer to like parts throughout the specification.

[0029] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not necessarily limited to the size and thickness of the components shown.

[0030] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined, and as those skilled in the art will fully appreciate, various technical interconnections and operations are possible, and the embodiments may be implemented independently of each other, and may be implemented in combination therewith.

[0031] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] In the present disclosure, a "display device" in a narrow sense may include display devices such as liquid crystal modules (LCMs), organic light emitting diode (OLED) modules, and quantum dot (QD) modules, which include a display panel and a driver for driving the display panel. In addition, a display device may also include an appliance display device, including a laptop computer, a television, a computer monitor, a car display, or other forms of a vehicle that is a complete product or final product including an LCM, an OLED module, a QD module, etc., as well as a complete electronic device or a complete set of devices, such as a mobile electronic device such as a smartphone or an electronic tablet.

[0033] Therefore, the display device in the present disclosure may include the display device itself in a narrow sense, such as an LCM, OLED module or QD module, as well as a complete set of devices that are application products or end-consumer devices including the LCM, OLED module or QD module.

[0034] Furthermore, in some cases, an LCM, an OLED module, and a QD module consisting of a display panel, a driver, and the like are referred to as a "display device" in a narrow sense, and an electronic device as a final product including the LCM, OLED module, and QD module may be referred to separately as a "complete device." For example, a display device in a narrow sense may be a concept including a display panel of an LCD, OLED, or QD and a source printed circuit board (PCB) as a controller for driving the display panel, the source printed circuit board (PCB) also including a complete PCB, which is a complete controller electrically connected to the source PCB to control the entire complete device.

[0035] The display panel used in this embodiment can use any type of display panel, such as an LCD panel, an OLED display panel, a QD display panel, and an electroluminescent display panel, and is not limited to a specific display panel capable of performing frame bending using the flexible substrate and the backplane support structure thereunder used for the OLED display panel of this embodiment. In addition, the display panel used in the display device according to the embodiment of the present disclosure is not limited to the shape or size of the display panel.

[0036] For example, when the display panel is an OLED display panel, the display panel may include a plurality of gate lines and data lines, as well as pixels formed in the intersection areas of the gate lines and data lines. Furthermore, the display panel may include: an array including thin-film transistors as elements for selectively applying a voltage to each pixel; an OLED layer disposed on the array; an encapsulation substrate or encapsulation layer disposed on the array to cover the OLED layer, etc. The encapsulation layer may protect the thin-film transistors, OLED layer, etc. from external impacts and prevent moisture or oxygen from penetrating the OLED layer. Furthermore, the layer formed on the array may include an inorganic light-emitting layer, such as a nano-sized material layer or quantum dots.

[0037] Figure 1 is a view illustrating a display device according to the present disclosure.

[0038] Reference Figure 1 , the display device 100 includes a display panel 110 , a data driver 120 , a gate driver 130 , a timing controller 140 and a memory 200 .

[0039] The display panel 110 includes a plurality of gate lines GL and a plurality of data lines DL. A plurality of sub-pixels SP are arranged at locations where the gate lines GL and the data lines DL intersect. The display panel 110 receives a data voltage Vdata from the data driver 120 via the data lines DL. In addition, the display panel 110 receives an update voltage Vup from the data driver 120 via the data lines DL. The display panel 110 receives a scan signal SCAN from the gate driver 130 via the gate lines GL. In addition, the display panel 110 receives an initialization signal Ini, an update scan signal UdSC, and an update initialization signal UdIni from the gate driver 130 via the gate lines GL. The gate lines GL may include a plurality of lines, and each line may receive any one of the following: the scan signal SCAN, the initialization signal Ini, the update scan signal UdSC, and the update initialization signal UdIni. Alternatively, the gate lines GL may be configured to asynchronously receive two or more of the scan signal SCAN, the initialization signal Ini, the update scan signal UdSC, and the update initialization signal UdIni as a single line.

[0040] The data driver 120 receives image data Sdata from the timing controller 140. The image data Sdata is serial data and includes information about the grayscale value of the light that each sub-pixel SP should emit. The data driver 120 converts the image data Sdata into (analog) data voltage Vdata and outputs the (analog) data voltage Vdata to the data line DL. In addition, the data driver 120 receives update data Sup from the timing controller 140. The update data Sup is serial data and can control whether each sub-pixel SP should be updated or maintained without updating. The data driver 120 converts the update data Sup (which may also be referred to as an update voltage) into an (analog) update voltage Vup and outputs the (analog) update voltage Vup to the data line DL. The data line DL may include a plurality of lines, and each line may receive the data voltage Vdata and the update voltage Vup. Alternatively, the data line DL may be configured to asynchronously receive the data voltage Vdata and the update voltage Vup as one line. This will be referred to below. Figure 3 The data driver 120 is described.

[0041] The gate driver 130 outputs signals for controlling several transistors provided in the sub-pixels SP to the display panel 110. The gate driver 130 outputs a scan signal SCAN, an initialization signal Ini, an update scan signal UdSC, and an update initialization signal UdIni to the display panel 110. The gate driver 130 may be located at only one side or both sides of the display panel 110 in the form of one or more integrated circuits (ICs). The gate driver 130 may be implemented in the form of a gate in panel (GIP) directly embedded in the non-display area of ​​the display panel 110. Figure 4 The gate driver 130 is described.

[0042] The timing controller 140 controls the operation of the data driver 120 and the gate driver 130 by supplying various signals to the data driver 120 and the gate driver 130. These signals are used to control the operation timing of the data driver 120 and the gate driver 130 and can therefore be referred to as "timing control signals." The timing controller 140 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE from an external device (or a complete system). The vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE are signals used to control the timing of the display panel 110. In addition, the timing controller 140 can receive image data Sdata from an external complete system. The timing controller 140 can write the image data Sdata to the memory 200. The timing controller 140 can read the image data Sdata written in the memory 200 and output the image data Sdata to the data driver 120. The timing controller 140 can output a gate clock GCLK and a gate start pulse GSP to the gate driver 130.

[0043] The memory 200 can receive and store image data Sdata from the timing controller 140. The image data Sdata can be divided based on frames and can be a grayscale value assigned to each sub-pixel within each frame. The memory 200 can be referred to as a "frame memory." The memory 200 can be a NAND type memory. The image data Sdata stored in the memory 200 can be read by the timing controller 140 and output to the data driver 120.

[0044] Figure 2 is a circuit diagram illustrating a sub-pixel according to the present disclosure.

[0045] Reference Figure 2 , the data voltage Vdata and the update voltage Vup are applied to the sub-pixel SP. The data voltage Vdata and the update voltage Vup may be applied through the data line.

[0046] A high voltage EVDD and a low voltage EVSS are applied to the subpixel SP. The high voltage EVDD is a high-level voltage for driving the light-emitting element LD. The low voltage EVSS is a low-level voltage for outputting a current through the light-emitting element LD. The high voltage EVDD and the low voltage EVSS can be applied via a power line.

[0047] A reference voltage Vref is applied to the subpixel SP. The reference voltage Vref is a low-level voltage used to initialize the second node N2, which is the source node of the drive transistor Tdr. The reference voltage Vref may be referred to as an "initialization voltage." In this disclosure, the terms "reference voltage Vref" and "initialization voltage Vref" may be used interchangeably. The reference voltage Vref may be applied via a data line. Alternatively, the reference voltage Vref may be provided to the subpixel SP via a separate power line.

[0048] The scan signal SCAN, the initialization signal Ini, the update scan signal UdSC, and the update initialization signal UdIni are applied to the sub-pixel SP. The signals may be applied through the gate lines.

[0049] The switching transistor Tsw is controlled by a scan signal SCAN to connect the data voltage Vdata to the first node N1. The first node N1 is connected to the gate node of the driving transistor Tdr and to one electrode of the storage capacitor Cst. When the switching transistor Tsw is turned on, the data voltage Vdata is applied to the first node N1 and the storage capacitor Cst.

[0050] The driving transistor Tdr is controlled by the first node N1 to connect the high potential voltage EVDD to the second node N2. The second node N2 is connected to the source node of the driving transistor Tdr and the other electrode of the storage capacitor Cst. The driving transistor Tdr flows a current corresponding to the voltage stored in the storage capacitor Cst. The current passing through the driving transistor Tdr allows the light-emitting element LD to emit light.

[0051] The storage capacitor Cst has one electrode connected to the first node N1 and the other electrode connected to the second node N2. A data voltage is applied to one electrode of the storage capacitor Cst, and a reference voltage (or initialization voltage) Vref is applied to the other electrode.

[0052] The initialization transistor Tini is controlled by the initialization signal Ini to connect the reference voltage Vref to the second node N2. When the initialization transistor Tini is turned on, the reference voltage Vref is applied to the second node N2. When the reference voltage Vref is applied to the second node N2, the other electrode of the storage capacitor Cst is initialized.

[0053] The light emitting element LD is provided between the second node N2 and the low potential voltage EVSS. When current is output from the driving transistor Tdr to the light emitting element LD, the light emitting element LD emits light having brightness corresponding to the current.

[0054] The first transistor T1 is controlled by the update node Nup to connect the switching transistor Tsw to the first node N1. When the first transistor T1 is turned on, the data voltage Vdata output from the switching transistor Tsw can be applied to the first node N1. When the first transistor T1 is turned off, the data voltage Vdata is not applied to the first node N1 and is blocked.

[0055] The second transistor T2 is controlled by the update scan signal UdSC to connect the update voltage Vup to the update node Nup. When the second transistor T2 is turned on, the update voltage Vup can be applied to the update node Nup. When the second transistor T2 is turned off, the update voltage Vup is not applied to the update node Nup and is blocked.

[0056] The third transistor T3 is controlled by the update initialization signal UdIni to connect the update node Nup to the low potential voltage EVSS. When the third transistor T3 is turned on, the update node Nup is connected to the low potential voltage EVSS, and thus the update node Nup is initialized.

[0057] The fourth transistor T4 is controlled by the update node Nup to connect the initialization transistor Tini to the second node N2. When the fourth transistor T4 is turned on, the reference voltage Vref output from the initialization transistor Tini can be output to the second node N2. When the fourth transistor T4 is turned off, the initialization of the second node N2 is prevented.

[0058] The refresh capacitor Cup has one electrode connected to the update node Nup and the other electrode connected to the low potential voltage EVSS. When an on-level voltage is applied to the update node Nup via the second transistor T2, the refresh capacitor Cup maintains the on-level voltage. When an off-level voltage (i.e., the low potential voltage EVSS) is applied to the update node Nup via the third transistor T3, the refresh capacitor Cup maintains the off-level voltage.

[0059] like Figure 2 In the figure, the transistor is shown as an N-type. However, the transistor can also be formed as a P-type.

[0060] Figure 3 is a view for describing a data driver according to the present disclosure.

[0061] Reference Figure 3 , the data driver 120 includes a latch 121 , a converter 122 and a buffer 123 .

[0062] The latch 121 receives digital image data Sdata from the timing controller 140. The image data Sdata may be transmitted in the form of a data packet including a clock. The latch 121 parallelizes the serially input image data Sdata.

[0063] The latch 121 receives digital update data Sup from the timing controller 140. The update data Sup may be transmitted in the form of a data packet including a clock. The latch 121 parallelizes the serially input update data Sup.

[0064] When a source output enable signal is input from the timing controller 140, the latch 121 outputs the image data Sdata or the update data Sup to the converter 122. The source output enable signal is a signal for defining one horizontal line. In other words, when the image data Sdata or the update data Sup corresponding to one horizontal line is applied, the source output enable signal is input. Therefore, the serial data can be parallelized by the source output enable signal.

[0065] The converter 122 is a digital-to-analog converter for converting a digital signal into an analog signal. The converter 122 converts the data Sdata and Sup input from the latch 121 from a digital format to an analog format. The data output from the converter 122 may have a voltage level raised by a gamma converter (not shown) and a level shifter (not shown).

[0066] The buffer 123 outputs the data voltage Vdata to the data line DL via an output buffer provided in each channel of the data driver 120. Furthermore, the buffer 123 outputs the update voltage Vup to the data line DL or a separate signal line via an output buffer provided for each channel of the data driver 120. The separate signal line may be a line connected from the data driver 120 to the display panel 110, such as the data line DL. In some cases, the data voltage Vdata and the update voltage Vup may be output to a single data line DL. The data voltage Vdata and the update voltage Vup are applied to each sub-pixel, which causes an image to be displayed on the screen of the display device.

[0067] Figure 4 is a view for describing a gate driver according to the present disclosure.

[0068] Reference Figure 4 The gate driver 130 includes a shift register 131 and a buffer circuit 132 .

[0069] The gate driver 130 receives a gate start pulse GSP from the timing controller 140. The gate driver 130 receives a gate clock GCLK from the timing controller 140. The signals output from the buffer circuit 132 are output to the gate lines. The signals output to the gate lines include a scan signal SCAN, an initialization signal Ini, an update scan signal UdSC, and an update initialization signal UdIni.

[0070] The scan signal SCAN will be mainly described. When the scan signal SCAN is output to the first gate line GL by the gate start pulse GSP, the next shift register 131 operates through a carry operation. The scan signal SCAN is output to the second gate line GL by the operation of the next shift register 131. Therefore, the scan signals SCAN of all the gate lines GL of the display panel 110 can be sequentially output by the operation of the gate start pulse GSP and the gate clock GCLK.

[0071] Specifically, the shift register 131 can control the Q node and the QB node connected to the buffer circuit 132. The voltage states of the Q node and the QB node change according to the operating state of the shift register 131. According to the states of the Q node and the QB node, the pull-up transistor TU and the pull-down transistor TD are controlled to be turned on and off. According to such control, a high level or low level scan signal SCAN can be output.

[0072] The initialization signal Ini, the update scan signal UdSC, and the update initialization signal UdIni may be output in the same manner as the scan signal SCAN is output.

[0073] Figure 5 is a view illustrating an output screen of a display device according to the present disclosure.

[0074] Figure 6 is a timing diagram for describing an update operation and a hold operation of a sub-pixel according to the present disclosure.

[0075] Figure 7 is a timing diagram illustrating update voltages applied to subpixels according to the present disclosure.

[0076] Figure 8 is a timing diagram illustrating data voltages applied to sub-pixels according to the present disclosure.

[0077] To more clearly describe the technical spirit of the present disclosure, an example in which the display panel 110 includes 5x5 sub-pixels will be described for illustrative purposes. The technical spirit described in the present disclosure can be applied to a display device including a large number of sub-pixels, such as a 3840x2160 display panel 110 that displays UHD quality images in the same manner.

[0078] Furthermore, in order to more clearly describe the technical spirit according to the present disclosure, the frequency is used by replacing it with a term such as refresh rate or update rate.

[0079] In addition, in order to more clearly describe the technical spirit of the present disclosure, an example in which the high frequency and high update rate are 3 Hz and the low frequency and low update rate are 1 Hz will be described. The technical spirit described in the present disclosure can be applied to higher frequencies such as 60 Hz, 120 Hz, 240 Hz, and 480 Hz in the same manner.

[0080] Reference Figure 5 , the display panel 110 includes a total of 25 sub-pixels SP11 to SP55. Among them, some sub-pixels SP22, SP23, SP24, SP32, SP33, and SP34 operate at a high frequency. The remaining sub-pixels SP11 to SP15, SP21, SP25, SP31, SP35, SP41 to SP45, and SP51 to SP55 operate at a low frequency.

[0081] In order to control the high frequency or the low frequency, the update voltages Vup1 to Vup5 are applied to the sub-pixels SP through the data lines. The data voltages Vdata1 to Vdata5 are applied to the sub-pixels SP through the data lines.

[0082] Video can be displayed on sub-pixels SP22, SP23, SP24, SP32, SP33, and SP34, which are driven at a high frequency. Still images can be displayed on sub-pixels SP11 to SP15, SP21, SP25, SP31, SP35, SP41 to SP45, and SP51 to SP55, which are driven at a low frequency. For example, on a computer screen, a video can be displayed in a reduced window of sub-pixels SP22, SP23, SP24, SP32, SP33, and SP34, rather than in full screen. The remaining sub-pixels can display still images, such as a desktop screen.

[0083] Therefore, the display panel 110 can be driven at different frequencies for each section. In other words, some of the plurality of sub-pixels SP, SP11 to SP15, SP21, SP25, SP31, SP35, SP41 to SP45, and SP51 to SP55, can be operated at a first frequency corresponding to a low frequency. Other sub-pixels SP, SP22, SP23, SP24, SP32, SP33, and SP34, can be operated at a second frequency corresponding to a high frequency.

[0084] Reference Figure 6 , showing Figure 5 The update and hold timing of the two sub-pixels SP12 and SP22 are shown. The data voltage Vdata2 is input to Figure 5 Sub-pixels SP12, SP22, SP32, SP42 and SP52 are shown.

[0085] For the purpose of illustration, it is assumed that the sub-pixel SP12 is driven at a low frequency, and the low frequency is 1 Hz. The UP sub-pixel SP12 is updated during the first period P1 of 1 second. During the second period P2 and the third period P3, the sub-pixel SP12 remains HD without being updated.

[0086] Update UP indicates a case where a new data voltage is input to the storage capacitor Cst of the subpixel SP and the subpixel SP emits light with the new data voltage. Hold HD indicates a case where the past data voltage input to the storage capacitor Cst during the previous period remains as it is and the subpixel SP emits light with the past data voltage.

[0087] For illustration purposes, it is assumed that the sub-pixel SP22 is a sub-pixel driven at a high frequency, and the high frequency is 3 Hz. The UP sub-pixel SP22 is updated during the first period P1, the second period P2, and the third period P3 of a period of 1 second.

[0088] Reference Figure 5 , sub-pixels SP12, SP22, SP32, SP42 and SP52 share a data line or a predetermined signal line. The update voltage Vup2 is applied through the shared signal line. Figure 7 , shows the timing of updating the voltage Vup2.

[0089] like Figure 7 As shown, all sub-pixels SP12, SP22, SP32, SP42, and SP52 are updated during the first period P1. Therefore, the update voltage Vup2 transitions a total of five times during the first period P1. The transitions indicate a level change of the update voltage Vup2 from an off level to an on level.

[0090] During the second period P2, some sub-pixels PS12, SP42, and SP52 driven at a low frequency are maintained, and some sub-pixels SP22 and SP32 driven at a high frequency are updated. Therefore, the update voltage Vup2 transitions a total of two times during the second period P2. During the second period P2, the transitioned conduction levels are applied to the sub-pixels SP22 and SP32.

[0091] The driving during the third period P3 is the same as the driving during the second period P2.

[0092] As described above, the update voltage Vup is a voltage that swings between an on-level and an off-level. Figure 2As described above, the update voltage Vup determines whether the voltage applied to the update node Nup is at an on-level or an off-level. When the update voltage Vup is at an on-level, the first transistor T1 and the fourth transistor T4 controlled by the update node Nup are turned on. When the update voltage Vup is at an off-level, the first transistor T1 and the fourth transistor T4 are turned off. Therefore, the update voltage Vup can be implemented as a voltage that swings between two levels.

[0093] Reference Figure 8 , shows the data voltage Vdata2 applied during the first period P1, the second period P2, and the third period P3. Each of the periods P1, P2, and P3 has a duration of approximately 0.33 seconds. The data voltage Vdata2 is a voltage that indicates the grayscale at which each subpixel SP connected to the data line should emit light. Since grayscale has values ​​between 0 grayscale and 255 grayscale, the data voltage Vdata has a voltage level that varies over a wide spectrum corresponding to the entire grayscale. As described above, this differs from the fact that the update voltage Vup swings between two values: an on-level and an off-level.

[0094] Specifically, the first period P1 is a period in which all sub-pixels SP12, SP22, SP32, SP42, and SP52 are updated. The grayscale value of each sub-pixel SP is shown as an example.

[0095] The second period P2 is a period during which subpixels SP22 and SP32 are updated and subpixels SP12, SP42, and SP52 are maintained. Therefore, subpixels SP12, SP42, and SP52 are subpixels driven at a low frequency, while subpixels SP22 and SP32 are subpixels driven at a high frequency. Therefore, the data voltage Vdata2 applied to subpixels SP12, SP42, and SP52, which are driven and maintained at a low frequency, is the same as the data voltage Vdata2 input during the first period P1. For example, the level of data voltage Vdata2 applied to subpixel SP12 during the first and second periods P1 and P2 is level A. The level of data voltage Vdata2 applied to subpixel SP42 during the first and second periods P1 and P2 is level B. The level of data voltage Vdata2 applied to subpixel SP52 during the first and second periods P1 and P2 is level C. In contrast, during the first and second periods P1 and P2, the data voltage Vdata2 applied to subpixels SP22 and SP32, which are driven and updated at a high frequency, are different from each other. Figure 8 The voltage levels shown for sub-pixels SP22 and SP32 are illustrative.

[0096] As with the second period P2, the third period P3 is a period in which the sub-pixels SP22 and SP32 are updated and the sub-pixels SP12, SP42, and SP52 are maintained. The data voltage Vdata2 applied to the sub-pixels SP12, SP42, and SP52 driven and maintained at a low frequency is the same as the data voltage Vdata2 input during the second period P2. During the second period P2 and the third period P3, the data voltage Vdata2 applied to the sub-pixels SP22 and SP32 driven and updated at a high frequency are different from each other. Figure 8 The voltage levels shown for sub-pixels SP22 and SP32 are illustrative.

[0097] Therefore, the data voltage Vdata2 is a voltage changed to a level corresponding to the grayscale value.

[0098] Figure 9 is a diagram illustrating a timing for updating sub-pixels according to the present disclosure.

[0099] Figures 10 to 13 It shows that according to Figure 9 A view of the timing updates of sub-pixel operations.

[0100] For example, Figures 9 to 13 The sub-pixel SP described in the above may be Figure 5 The sub-pixels P22, P23, P24, P32, P33 and P34 are driven at a high frequency and may have Figures 6 to 8 The timing during the first period P1, the second period P2 and the third period P3 of the periods shown in FIG. The update voltage Vup applied to the sub-pixel during such periods is at an on-level.

[0101] In addition, for example, Figures 9 to 13 The sub-pixel SP described in the above may be Figure 5 The sub-pixels SP11, SP12, SP13, SP14, SP15, SP21, SP25, SP31, SP35, SP41, SP42, SP43, SP44, SP45, SP51, SP52, SP53, SP54 and SP55 driven at a low frequency among the sub-pixels shown, and may have Figures 6 to 8 The timing during the first period P1 of the periods shown is shown. The update voltage Vup applied to the sub-pixel during such a period is at an on-level.

[0102] Reference Figure 9 , time periods S110 , S120 , S130 and S140 are shown.

[0103] The first period S110 is a period for initializing the update capacitor Cup, and the state of the sub-pixel SP is between Figure 10 Shown in.

[0104] The second period S120 is a period in which the update voltage Vup is input to the update capacitor Cup, and the state of the sub-pixel SP is between Figure 11 Shown in.

[0105] The third period S130 is a period for initializing the storage capacitor Cst, and the state of the sub-pixel SP is between Figure 12 Shown in.

[0106] The fourth period S140 is a period in which the data voltage Vdata is input to the storage capacitor Cst, and the state of the sub-pixel SP is between Figure 13 Shown in.

[0107] Reference Figure 10 During the first period S110, an update initialization signal UdIni is applied. The initialization signal UdIni turns on the third transistor T3. The low voltage EVSS is applied to the update node Nup via the third transistor T3. Receiving the low voltage EVSS, the update node Nup is turned off. The update capacitor Cup is initialized to an off level.

[0108] Reference Figure 11 During the second period S120, an update scan signal UdSC is applied. The update scan signal UdSC turns on the second transistor T2. The update voltage Vup is applied to the update node Nup via the second transistor T2. The update voltage Vup is at an on-level. Therefore, the update node Nup becomes at an on-level. The on-level voltage is applied to the update capacitor Cup.

[0109] Reference Figure 12 During the third period S130, an initialization signal Ini is applied. The initialization signal Ini turns on the initialization transistor Tini. The update node Nup maintains the on-level voltage stored in the update capacitor Cup. Therefore, the fourth transistor T4 is turned on. As a result, the reference voltage Vref is applied to the second node N2, and the storage capacitor Cst is initialized. Specifically, the past data voltage Vdata N-1 stored in the storage capacitor Cst is initialized.

[0110] Reference Figure 13During the fourth period S140, a scan signal SCAN is applied. The scan signal SCAN turns on the switching transistor Tsw. The update node Nup maintains the on-level voltage stored in the update capacitor Cup. As a result, the first transistor T1 is turned on. Consequently, the data voltage Vdata is applied to the first node N1, and the data voltage Vdata is applied to the storage capacitor Cst. Specifically, the new data voltage Vdata N is stored in the storage capacitor Cst. Since the current Iup passing through the drive transistor Tdr becomes the updated current, an updated image is displayed on the display panel 110.

[0111] Figure 14 is a diagram illustrating a timing for holding a sub-pixel according to the present disclosure.

[0112] Figures 15 to 18 It shows that according to Figure 14 A view of the timing holding sub-pixel operation.

[0113] For example, Figures 14 to 18 The sub-pixel SP described in the above may be Figure 5 The sub-pixels SP11, SP12, SP13, SP14, SP15, SP21, SP25, SP31, SP35, SP41, SP42, SP43, SP44, SP45, SP51, SP52, SP53, SP54 and SP55 driven at a low frequency among the sub-pixels shown, and may have Figures 6 to 8 The timing during the second period P2 and the third period P3 of the periods shown in FIG. The update voltage Vup applied to the sub-pixel during such periods is an off-level.

[0114] Reference Figure 14 , time periods S210 , S220 , S230 and S240 are shown.

[0115] The first period S210 is a period for initializing the update capacitor Cup, and the state of the sub-pixel SP is between Figure 15 Shown in.

[0116] The second period S220 is a period in which the update voltage Vup is input to the update capacitor Cup, and the state of the sub-pixel SP is between Figure 16 Shown in.

[0117] The third period S230 is a period for initializing the storage capacitor Cst, and the state of the sub-pixel SP is between Figure 17 Shown in.

[0118] The fourth period S240 is a period in which the data voltage Vdata is input to the storage capacitor Cst, and the state of the sub-pixel SP is between Figure 18 Shown in.

[0119] Reference Figure 15 During the first period S210, an update initialization signal UdIni is applied. The initialization signal UdIni turns on the third transistor T3. The low voltage EVSS is applied to the update node Nup via the third transistor T3. Receiving the low voltage EVSS, the update node Nup is turned off. The update capacitor Cup is initialized to an off level.

[0120] Reference Figure 16 During the second period S220, an update scan signal UdSC is applied. The update scan signal UdSC turns on the second transistor T2. The update voltage Vup is applied to the update node Nup via the second transistor T2. The update voltage Vup is at an off-level. Therefore, the update node Nup becomes at an off-level. The off-level voltage is applied to the update capacitor Cup.

[0121] Reference Figure 17 During the third period S230, the initialization signal Ini is applied. The initialization signal Ini turns on the initialization transistor Tini. The update node Nup holds the off-level voltage stored in the update capacitor Cup. Therefore, the fourth transistor T4 is turned off. Consequently, the reference voltage Vref is blocked at the second node N2 rather than being applied thereto. The storage capacitor Cst cannot be initialized and holds the previously stored data voltage Vdata N-1.

[0122] Reference Figure 18 , a scan signal SCAN is applied during the fourth period S240. The scan signal SCAN turns on the switching transistor Tsw. The update node Nup maintains the off-level voltage stored in the update capacitor Cup. Therefore, the first transistor T1 is turned off. Therefore, the data voltage Vdata is blocked at the first node N1 instead of being applied to the first node N1. The data voltage Vdata cannot be applied to the storage capacitor Cst. Specifically, the new data voltage Vdata N cannot be stored in the storage capacitor Cst, and the data voltage Vdata N-1 stored in the past is maintained. Since the current Ihold passing through the driving transistor Tdr is not the updated current, but the same current as the current flowing in the past, the maintained image is displayed on the display panel 110.

[0123] According to the present disclosure, a display device is disclosed, which includes: a display panel, which includes a plurality of sub-pixels; a data driver, which is used to output a data voltage and an update voltage to the display panel; a gate driver, which is used to output a scan signal and an initialization signal to the display panel; and a timing controller, which is used to output a timing control signal to the data driver and the gate driver, wherein the update voltage is a signal that swings between an on-level and an off-level.

[0124] The data voltage and the refresh voltage may be output through a plurality of different data lines.

[0125] The data voltage and the refresh voltage can be output asynchronously through the same data line.

[0126] The data voltage may be changed to a level corresponding to a grayscale value.

[0127] The 1 second period may include a first period in which updating is performed and a second period in which maintaining is performed, and subpixels driven at a low frequency during the first and second periods may receive data voltages at the same level during the first and second periods.

[0128] The sub-pixels driven at a high frequency may receive data voltages at different levels during the first period and the second period.

[0129] Some of the plurality of sub-pixels may be updated at a first frequency, and other sub-pixels of the plurality of sub-pixels may be updated at a second frequency.

[0130] The above-mentioned scan signal can be referred to as a first scan signal, and the sub-pixel may further include: a switching transistor, which is used to output a data voltage to a first node; a driving transistor, which is controlled by the voltage at the first node to output a driving current to a second node; a storage capacitor, which is arranged between the first node and the second node; a first transistor, which is controlled by an update node and is arranged between the switching transistor and the first node; a second transistor, which is controlled by an update scan signal and is arranged between the update voltage and the update node; and an update capacitor, which is arranged between the update node and the low potential voltage.

[0131] The second transistor may output a refresh voltage to the refresh node when a refresh scan signal is applied.

[0132] When the refresh voltage becomes a turn-on level, the first transistor may output the data voltage to the first node.

[0133] When the refresh voltage becomes an off level, the first transistor may output the data voltage to the first node.

[0134] The initialization signal may be referred to as a first initialization signal, and the sub-pixel may further include a third transistor controlled by the update initialization signal and disposed between the update node and the low potential voltage.

[0135] When the refresh initialization signal is applied, the third transistor may initialize the refresh node to a low potential voltage.

[0136] The sub-pixel may further include an initialization transistor controlled by the initialization signal and disposed between the reference voltage and the second node; and a fourth transistor controlled by the update node and disposed between the initialization transistor and the second node.

[0137] When the update voltage becomes a turn-on level, the fourth transistor may output the reference voltage to the second node.

[0138] When the update voltage becomes an off level, the fourth transistor may block the reference voltage output to the second node.

[0139] The sub-pixel may also include: a third transistor, which is controlled by the update initialization signal and is set between the update node and the low potential voltage; an initialization transistor, which is controlled by the first initialization signal and is set between the reference voltage and the second node; and a fourth transistor, which is controlled by the update node and is set between the initialization transistor and the second node.

[0140] When the refresh initialization signal is applied, the third transistor may be turned on to initialize the refresh node to a low potential voltage.

[0141] When the update scan signal is applied, the second transistor may be turned on to apply the update voltage at a turn-on level to the update node.

[0142] When the first initialization signal is applied, the initialization transistor may be turned on, and the fourth transistor may be turned on by the update node being at a turn-on level to apply the reference voltage to the second node.

[0143] When the first scan signal is applied, the switching transistor may be turned on, and the first transistor may be turned on by the update node being at a turn-on level to apply the data voltage to the first node.

[0144] The storage capacitor may be refreshed to a new data voltage.

[0145] When the update scan signal is applied, the second transistor may be turned on to apply the update voltage at an off level to the update node.

[0146] When the first initialization signal is applied, the initialization transistor may be turned on, and the fourth transistor may be turned off by the update node being at an off level to block the output of the reference voltage to the second node.

[0147] When the first scan signal is applied, the switching transistor may be turned on, and the first transistor may be turned off by the update node being at an off level to block the output of the data voltage to the first node.

[0148] The storage capacitor can hold the past data voltage.

[0149] According to the present disclosure, an update initialization signal is applied to the sub-pixel. The update initialization signal may initialize the update node, or may not initialize the update node.

[0150] According to the present disclosure, the update scan signal is applied to the sub-pixel. By controlling the second transistor, the update scan signal may apply an update voltage to the update node or may not apply the update voltage to the update node.

[0151] According to the present disclosure, a subpixel includes a refresh capacitor that can maintain a refresh voltage applied to a refresh node.

[0152] According to the present disclosure, a subpixel includes a first transistor. The first transistor can be controlled by an update node to supply a data voltage to a drive transistor or not to supply the data voltage to the drive transistor. When the data voltage is supplied to the drive transistor, the corresponding subpixel is updated. When the data voltage is not supplied to the drive transistor, the corresponding subpixel is not updated to maintain the data voltage of the previous frame.

[0153] According to the present disclosure, sub-pixels may be updated or not. When a sub-pixel is updated, the portion grouped by the corresponding sub-pixel can be driven at a high frequency. When a sub-pixel is not updated, the portion grouped by the corresponding sub-pixel can be driven at a low frequency. Thus, a portion of a screen can be driven at a high frequency, and another portion can be driven at a low frequency. Thus, frequency driving for each portion of the screen is possible.

[0154] According to the present disclosure, a display device is disclosed, which may include: a display panel, which includes a plurality of sub-pixels; a data driver, which is configured to output a data voltage and an update voltage to the sub-pixels of the display panel; and a gate driver, which is configured to control the application of the data voltage to the sub-pixel through a first transistor and a second transistor in a sub-pixel among the plurality of sub-pixels, the first transistor being configured to be turned on or off based on a scan signal, and the second transistor being configured to be turned on or off based on the update voltage.

[0155] The embodiments of the present disclosure have been described above with reference to the accompanying drawings. The present disclosure is not necessarily limited to these embodiments. Various modifications may be made to the present disclosure without departing from the technical spirit of the present disclosure. Therefore, it should be understood that the embodiments of the present disclosure are for illustrative purposes only and do not limit the technical content. The scope of the present disclosure should include those described in the claims. In addition, all technical spirits within the equivalent scope of the claims should be interpreted as included in the technical spirit of the present disclosure.

[0156] The various embodiments described above can be combined to provide other embodiments. If necessary, aspects of the embodiments can be modified to adopt the concepts of the various embodiments to provide further embodiments.

[0157] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: a display panel comprising a plurality of sub-pixels; a data driver configured to output a data voltage and a refresh voltage to the display panel; a gate driver configured to output a scan signal and an initialization signal to the display panel; as well as a timing controller configured to output timing control signals to the data driver and the gate driver, The data voltage is a signal changed to a level corresponding to a grayscale value, and The update voltage is a signal that swings between an on level and an off level.

2. The display device according to claim 1, wherein The data voltage and the refresh voltage are output through a plurality of different data lines.

3. The display device according to claim 1, wherein The data voltage and the refresh voltage are asynchronously outputted through the same data line.

4. The display device according to claim 1, wherein The 1 second period includes a first period for performing update and a second period for performing hold, and The sub-pixels driven at a low frequency during the first period and the second period receive data voltages at the same level during the first period and the second period.

5. The display device according to claim 4, wherein The sub-pixels driven at a high frequency receive data voltages at different levels during the first period and the second period. The display device according to claim 1 , wherein: Some of the plurality of sub-pixels are updated at a first frequency, and Other sub-pixels in the plurality of sub-pixels are updated at a second frequency.

7. The display device according to claim 1, wherein The scanning signal is a first scanning signal, and the sub-pixel includes: a switching transistor configured to output the data voltage to the first node; a driving transistor controlled by the voltage at the first node to output a driving current to a second node; a storage capacitor disposed between the first node and the second node; a first transistor controlled by an update node and disposed between the switch transistor and the first node; a second transistor controlled by a refresh scan signal and disposed between the refresh voltage and the refresh node; and A refresh capacitor is provided between the refresh node and a low potential voltage.

8. The display device according to claim 7, wherein: The first transistor outputs the data voltage to the first node when the update voltage becomes the on-level, and blocks the data voltage from being output to the first node when the update voltage becomes the off-level.

9. The display device according to claim 7, wherein: The initialization signal is a first initialization signal, and the sub-pixel further includes a third transistor, which is controlled by an update initialization signal and is disposed between the update node and the low potential voltage, and When the refresh initialization signal is applied, the third transistor initializes the refresh node to the low potential voltage.

10. The display device according to claim 7, wherein: The sub-pixel further includes: an initialization transistor controlled by the initialization signal and provided between a reference voltage and the second node; and A fourth transistor is controlled by the update node and is provided between the initialization transistor and the second node.

11. The display device according to claim 10, wherein: When the update voltage becomes the on-level, the fourth transistor outputs the reference voltage to the second node, and When the update voltage becomes the off level, the fourth transistor blocks the reference voltage from being output to the second node.

12. The display device according to claim 7, wherein: The initialization signal is a first initialization signal, and the sub-pixel further includes: a third transistor controlled by a refresh initialization signal and disposed between the refresh node and the low potential voltage; an initialization transistor controlled by the first initialization signal and provided between a reference voltage and the second node; and A fourth transistor is controlled by the update node and is provided between the initialization transistor and the second node.

13. The display device according to claim 12, wherein: When the refresh initialization signal is applied, the third transistor is turned on to initialize the refresh node to the low potential voltage.

14. The display device according to claim 13, wherein: When the update scan signal is applied, the second transistor is turned on to apply the update voltage at the on-level to the update node.

15. The display device according to claim 14, wherein When the first initialization signal is applied, the initialization transistor is turned on, and the fourth transistor is turned on by the update node at the on-level to apply the reference voltage to the second node.

16. The display device according to claim 15, wherein When the first scan signal is applied, the switching transistor is turned on, and the first transistor is turned on by the update node at the on level to apply the data voltage to the first node.

17. The display device according to claim 13, wherein: When the update scan signal is applied, the second transistor is turned on to apply the update voltage at an off level to the update node.

18. The display device according to claim 17, wherein: When the first initialization signal is applied, the initialization transistor is turned on, and the fourth transistor is turned off by the update node at the off level to block output of the reference voltage to the second node.

19. The display device according to claim 18, wherein When the first scan signal is applied, the switching transistor is turned on, and the first transistor is turned off by the update node at the off level to block output of the data voltage to the first node.

20. A display device comprising: a display panel comprising a plurality of sub-pixels; a data driver configured to output data voltages and update voltages to sub-pixels of the display panel; as well as a gate driver configured to control application of the data voltage to the sub-pixel through a first transistor and a second transistor in a sub-pixel among the plurality of sub-pixels, the first transistor being configured to be turned on or off based on a scan signal, and the second transistor being configured to be turned on or off based on the update voltage.

Images