Capacitor and electronic device

Abstract

The invention discloses a capacitor and an electronic device. The capacitor comprises a first electrode, a second electrode and a first capacitor dielectric layer. The first capacitor dielectric layer is configured between the first electrode and the second electrode, the first capacitor dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer comprises an inorganic dielectric layer, the second dielectric layer comprises an organic dielectric layer, the first dielectric layer is located between the first electrode and the second dielectric layer, and the second dielectric layer is located between the first electrode and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode.

Description

Technical Field

[0001] The present invention relates to a capacitor, and in particular to a capacitor in an electronic device. Background Art

[0002] In the prior art, passive components, such as multi-layer ceramic capacitors (MLCCs), often have an overly thick overall structure, which often makes it difficult to miniaturize the subsequent integrated circuit packaging. Therefore, technologies have been proposed to integrate passive components into the rewiring structure of the packaging structure through thin film processes. However, the large-area panel-level rewiring process faces high dielectric loss due to poor flatness of the dielectric film, which causes energy loss and heat generation in the capacitor, thereby reducing the overall performance of the passive component. In addition, when the passive component operates at a high frequency, the self-resonance frequency of the capacitor stack layer is easily affected by its size, which causes the capacitance value to deviate from the original design, that is, the capacitance value of the capacitor is unstable, such as the problem of converting from capacitance to inductance. Summary of the Invention

[0003] Embodiments of the present invention provide a capacitor and an electronic device having the capacitor.

[0004] In one embodiment of the present invention, a capacitor includes a first electrode, a second electrode, and a first capacitor dielectric layer. The first capacitor dielectric layer is disposed between the first electrode and the second electrode. The first capacitor dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer includes an inorganic dielectric layer, and the second dielectric layer includes an organic dielectric layer. The first dielectric layer is located between the first electrode and the second dielectric layer, and the second dielectric layer is located between the first dielectric layer and the second electrode.

[0005] In another embodiment of the present invention, an electronic device includes a substrate, a redistribution structure, a capacitor, and a chip. The redistribution structure is configured on the substrate. The capacitor is electrically connected to the redistribution structure, the capacitor includes a first electrode, a second electrode, and a first capacitor dielectric layer, the first capacitor dielectric layer is configured between the first electrode and the second electrode, the first capacitor dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer includes an inorganic dielectric layer, the second dielectric layer includes an organic dielectric layer, wherein the first dielectric layer is located between the first electrode and the second dielectric layer, and the second dielectric layer is located between the first dielectric layer and the second electrode. The chip is configured on the redistribution structure and is electrically connected to the redistribution structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic cross-sectional view of a capacitor according to a first embodiment of the present invention;

[0008] Figure 2 is a schematic cross-sectional view of a capacitor according to a second embodiment of the present invention;

[0009] Figure 3A is a schematic cross-sectional view of a capacitor according to a third embodiment of the present invention;

[0010] Figure 3B is another cross-sectional schematic diagram of a capacitor according to a third embodiment of the present invention;

[0011] Figure 4 is a schematic cross-sectional view of a capacitor according to a fourth embodiment of the present invention;

[0012] Figure 5 is a cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present invention;

[0013] Figure 6 is a cross-sectional schematic diagram of an electronic device according to a sixth embodiment of the present invention;

[0014] Figure 7 is a cross-sectional schematic diagram of an electronic device according to a seventh embodiment of the present invention;

[0015] Figure 8 is a cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present invention;

[0016] Figure 9 is a cross-sectional schematic diagram of an electronic device according to a ninth embodiment of the present invention;

[0017] Figure 10 FIG. 1 is a cross-sectional diagram of an electronic device according to a tenth embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the terms "include", "including", "have", etc. used in the text are all open terms, which means "including but not limited to". Furthermore, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the directions of the drawings, and are not used to limit the present invention. In addition, the quantities and shapes mentioned in the specification are only used to specifically illustrate the present invention in order to facilitate understanding of its content, and are not used to limit the present invention.

[0019] Figure 1is a cross-sectional view of a capacitor according to the first embodiment of the present invention. Figure 1 The capacitor 100 of this embodiment includes a substrate 110 and a capacitor stack layer 120 disposed on the substrate 110. The substrate 110 includes a first material layer 110a and a second material layer 110b disposed on the first material layer 110a. For example, the first material layer 110a of the substrate 110 includes glass, and the second material layer 110b of the substrate 110 includes an organic dielectric material. Figure 1 As shown, substrate 110 has a recess R1. Recess R1 in substrate 110 is distributed only in the second material layer 110b, and capacitor stack layer 120 covers the bottom surface of recess R1, the side surfaces of recess R1, and the top surface of second material layer 110b. In other words, the depth of recess R1 is less than the thickness of second material layer 110b. For example, the bottom area of ​​recess R1 is 20 microns x 20 microns, and the depth of recess R1 is between 10 microns and 20 microns.

[0020] The thin-film capacitor stack layer 120 includes a first electrode 122, a second electrode 124, and a first capacitor dielectric layer 126. The first capacitor dielectric layer 126 is disposed between the first electrode 122 and the second electrode 124. The first capacitor dielectric layer 126 includes a first dielectric layer 126a and a second dielectric layer 126b. The first dielectric layer 126a includes an inorganic dielectric layer, and the second dielectric layer 126b includes an organic dielectric layer. The first dielectric layer 126a is located between the first electrode 122 and the second dielectric layer 126b, and the second dielectric layer 126b is located between the first dielectric layer 126a and the second electrode 124. Furthermore, the thickness of the first dielectric layer 126a is between 180 nanometers and 220 nanometers, and the thickness of the second dielectric layer 126b is between 20 nanometers and 50 nanometers.

[0021] like Figure 1 As shown, the first electrode 122 is disposed on the substrate 110, and the first capacitor dielectric layer 126 and the second electrode 124 are stacked on the first electrode 122. In addition, the first electrode 122, the first capacitor dielectric layer 126, and the second electrode 124 cover the bottom surface of the groove R1, the side surfaces of the groove R1, and the top surface of the second material layer 110b, and the first electrode 122 is in contact with the bottom surface of the groove R1, the side surfaces of the groove R1, and the top surface of the second material layer 110b.

[0022] In this embodiment, the first dielectric layer 126a has a first surface S1, which is covered by the second dielectric layer 126b and in contact with the second dielectric layer 126b. The second dielectric layer 126b has a second surface S2, which is covered by the second electrode 124 and in contact with the second electrode 124. The roughness of the first surface S1 of the first dielectric layer 126a is greater than the roughness of the second surface S2 of the second dielectric layer 126b. In other words, the interface roughness between the first dielectric layer 126a and the second dielectric layer 126b is greater than the interface roughness between the second electrode 124 and the second dielectric layer 126b. For example, the roughness of the first surface S1 of the first dielectric layer 126a is between 30 nanometers and 90 nanometers, and the roughness of the second surface S2 of the second dielectric layer 126b is between 10 nanometers and 40 nanometers. Since the second dielectric layer 126b made of an organic material has good step coverage, the second dielectric layer 126b covering the first surface S1 of the first dielectric layer 126a with higher roughness can provide a second surface S2 with lower roughness.

[0023] In this embodiment, the distribution area of ​​the capacitor stack layer 120 (i.e., the first electrode 122, the second electrode 124, and the first capacitor dielectric layer 126) in the capacitor 100 is less than or equal to 50 microns by 50 microns. When the distribution area of ​​the capacitor 100 is controlled within the range of 50 microns by 50 microns, the self-resonant frequency of the capacitor 100 during high-frequency operation can be well controlled. This control of the distribution area of ​​the capacitor 100 can also improve the dielectric loss problem during high-speed transmission caused by the poor flatness of large-area dielectric films.

[0024] It is worth noting that the capacitance value provided by the thin film type capacitor stack layer 120 can be adjusted by the angle between the side wall and the bottom of the groove R1. In other words, the capacitance value provided by the thin film type capacitor stack layer 120 can be adjusted by the slope of the side wall of the groove R1 and the depth of the groove R1. In some embodiments, the distribution area of ​​the capacitor stack layer 120 covering the groove R1 is preferably between 22.5 microns × 22.5 microns and 35 microns × 35 microns. In some other embodiments, the groove R1 made in the substrate 110 can be omitted. In other words, the capacitor stack layer 120 can be formed directly on the surface of the substrate 110.

[0025] Figure 2 FIG is a cross-sectional view of a capacitor according to a second embodiment of the present invention. Figure 1 and Figure 2The capacitor 200 of this embodiment is similar to the capacitor 100 of the first embodiment, but the main difference between the two is that the substrate 110 in this embodiment is a glass substrate, and the groove R2 is only distributed in the glass substrate 110. In addition, the groove R2 does not penetrate the substrate 110. In other words, the depth of the groove R2 is less than the thickness of the substrate 110. For example, the bottom area of ​​the groove R2 is 20 microns × 20 microns, and the depth of the groove R2 is between 10 microns and 20 microns.

[0026] Figure 3A FIG is a cross-sectional view of a capacitor according to a third embodiment of the present invention. Figure 1 and Figure 3A The capacitor 300 of this embodiment is similar to the capacitor 100 of the first embodiment, but the main difference between the two is that the groove R3 in this embodiment penetrates the second material layer 110b and extends into a portion of the first material layer 110a. In addition, the groove R3 does not penetrate the first material layer 110a of the substrate 110. In other words, the depth of the groove R3 is greater than the thickness of the second material layer 110b, and the depth of the groove R3 is less than the thickness of the substrate 110. For example, the bottom area of ​​the groove R3 is 20 microns x 20 microns, and the depth of the groove R3 is between 10 microns and 20 microns.

[0027] like Figure 3A As shown, the first electrode 122, the first capacitor dielectric layer 126, and the second electrode 124 cover the bottom surface of the groove R3, the side surfaces of the groove R3, and the top surface of the second material layer 110b. In addition, the bottom and the lower half of the sidewall of the groove R3 can be defined by the first material layer 110a, while the upper half of the sidewall of the groove R3 can be defined by the second material layer 110b, and the first electrode 122 is in contact with both the first material layer 110a and the second material layer 110b.

[0028] Figure 3B This is another cross-sectional view of a capacitor according to the third embodiment of the present invention. Figure 3A and Figure 3B , Figure 3B The capacitor 500 is shown with Figure 3AThe capacitor 300 shown is similar, but the main difference between the two is that in this embodiment, the groove R3' that passes through the second material layer 110b and extends into a portion of the first material layer 110a has stepped sidewalls. The lower half sidewall SW1 and the upper half sidewall SW2 of the groove R3' are defined by the first material layer 110a and the second material layer 110b, respectively. Because the first material layer 110a and the second material layer 110b are made of different materials, the slope of the lower half sidewall SW1 is different from the slope of the upper half sidewall SW2. In some embodiments, the slope of the lower half sidewall SW1 is greater than the slope of the upper half sidewall SW2. In some other embodiments, the slope of the lower half sidewall SW1 is less than the slope of the upper half sidewall SW2. It is worth noting that the difference in slope between the lower sidewall SW1 and the upper sidewall SW2 mainly depends on the material selection of the first material layer 110a and the second material layer 110b. For example, the bottom area of ​​the groove R3' is 20 microns x 20 microns, and the depth of the groove R3' is between 10 microns and 20 microns. Figure 3B As shown, the first electrode 122, the first capacitor dielectric layer 126 and the second electrode 124 cover the bottom surface of the groove R3', the local top surface of the first material layer 110a (i.e., the area connected between the side surfaces SW1 and SW2), the side surfaces SW1 and SW2 of the groove R3' and the top surface of the second material layer 110b.

[0029] Figure 4 FIG is a cross-sectional view of a capacitor according to a fourth embodiment of the present invention. Figure 3A and Figure 4 The capacitor 400 of this embodiment is similar to the capacitor 300 of the third embodiment, but the main difference between the two is the capacitor stack layer 120' covering the groove R4. Figure 4 As shown, the capacitor stack layer 120' includes, in addition to the first electrode 122, the second electrode 124 and the first capacitor dielectric layer 126, a third electrode 128 and a second capacitor dielectric layer 129, wherein the second capacitor dielectric layer 129 is disposed on the second electrode 124 and the second capacitor dielectric layer 129 is located between the second electrode 124 and the third electrode 128. In addition, the third electrode 128 and the second capacitor dielectric layer 129 in the capacitor stack layer 120' of this embodiment can also be applied to Figure 1 The capacitor 100 is shown as well as Figure 2 The capacitor 200 is shown.

[0030] In this embodiment, the second capacitor dielectric layer 129 is a single-layer thin film structure, and the material of the second capacitor dielectric layer 129 can be the same as or different from the material of the first dielectric layer 126a. For example, the material of the second capacitor dielectric layer 129 includes an inorganic dielectric material that is the same as or different from the material of the first dielectric layer 126a.

[0031] In other embodiments, the second capacitor dielectric layer 129 may have the same stacked film structure as the first capacitor dielectric layer 126. For example, the second capacitor dielectric layer 129 may include an inorganic dielectric layer and an organic dielectric layer, wherein the inorganic dielectric layer is located between the second electrode 124 and the organic dielectric layer, and the organic dielectric layer is located between the inorganic dielectric layer and the third electrode 128.

[0032] Figure 5 FIG. 5 is a cross-sectional diagram of an electronic device according to a fifth embodiment of the present invention.

[0033] Please refer to Figure 5 The electronic device P1 of this embodiment includes a substrate 510, a redistribution structure 520, a chip 530, and a capacitor 540. For example, the substrate 510 includes a glass substrate, the redistribution structure 520 is disposed on the surface of the substrate 510, and the chip 530 is disposed on the redistribution structure 520 and electrically connected to the redistribution structure 520. In addition, the capacitor 540 is disposed on the surface of the substrate 510 and is embedded or buried in the redistribution structure 520. In this embodiment, before providing the capacitor 540 and forming the redistribution structure 520, a conductive line 512 (e.g., a metal conductive line) may be formed on the surface of the substrate 510, wherein the capacitor 540 is disposed on the conductive line 512 and the capacitor 540 is electrically connected to the conductive line 512.

[0034] In this embodiment, the redistribution structure 520 includes alternately stacked multi-layer dielectric layers 522 and multi-layer redistribution layers 524, wherein the multi-layer dielectric layer 522 includes a bottom dielectric layer 522a covering the substrate 510 and the capacitor 540 and a top dielectric layer 522b disposed on the bottom dielectric layer 522a, and the multi-layer redistribution layer 524 includes a bottom redistribution layer 524a disposed on the bottom dielectric layer 522a and electrically connected to the wire 512, and a top redistribution layer 524b disposed on the bottom redistribution layer 524a. It is worth noting that the individual number of dielectric layers 522 and redistribution layers 524 in the redistribution structure 520 is not limited to 2 layers. In other words, there may be other dielectric layers between the bottom dielectric layer 522a and the top dielectric layer 522b, and there may be other redistribution layers between the bottom redistribution layer 524a and the top redistribution layer 524b. As Figure 5As shown, the conductive line 512 and the capacitor 540 disposed on the surface of the substrate 510 are in contact with the bottom dielectric layer 522a of the multi-layer dielectric layer 522, and the capacitor 540 can be electrically connected to the bottom redistribution layer 524a through the conductive line 512 formed on the substrate 510. Here, the structure of the capacitor 540 can be as shown in FIG. Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B or Figure 4 . Since the thickness of capacitor 540 can be controlled to be in the range of hundreds of nanometers to micrometers, and capacitor 540 is embedded or buried in redistribution structure 520, the overall thickness of electronic device P1 is not affected by the thickness of capacitor 540 and cannot be further reduced.

[0035] Figure 6 FIG. 4 is a cross-sectional diagram of an electronic device according to a sixth embodiment of the present invention.

[0036] Please refer to Figure 5 and Figure 6 The electronic device P2 of this embodiment is similar to the electronic device P1 of the fifth embodiment, but the main difference between the two is the location of the capacitor 540. Figure 6 As shown, the redistribution structure 520 includes alternately stacked multiple dielectric layers 522 and multiple redistribution layers 524, wherein the multiple dielectric layers 522 include a bottommost dielectric layer 522a covering the substrate 510 and a topmost dielectric layer 522b disposed on the bottommost dielectric layer 522a, and the multiple redistribution layers 524 include a bottommost redistribution layer 524a disposed on the bottommost dielectric layer 522a and a topmost redistribution layer 524b disposed on the topmost dielectric layer 522b, and the topmost redistribution layer 524b is electrically connected to the bottommost redistribution layer 524a. It is worth noting that the individual number of dielectric layers 522 and redistribution layers 524 in the redistribution structure 520 is not limited to two layers. In other words, there may be other dielectric layers between the bottommost dielectric layer 522a and the topmost dielectric layer 522b, and there may be other redistribution layers between the bottommost redistribution layer 524a and the topmost redistribution layer 524b. In this embodiment, the capacitor 540 is not disposed on the surface of the substrate 510 . Instead, the capacitor 540 is disposed on and electrically connected to the bottommost redistribution layer 524 a . Furthermore, the capacitor 540 is covered by the topmost dielectric layer 522 b of the redistribution structure 520 .

[0037] Figure 7 FIG is a cross-sectional view of an electronic device according to a seventh embodiment of the present invention. Figure 5 and Figure 7The electronic device P3 of this embodiment is similar to the electronic device P1 of the fifth embodiment, but the main difference between the two is the location of the capacitor 540. Figure 7 As shown, the redistribution structure 520 includes alternately stacked multiple dielectric layers 522 and multiple redistribution layers 524, wherein the multiple dielectric layers 522 include a bottommost dielectric layer 522a covering the substrate 510 and a topmost dielectric layer 522b disposed on the bottommost dielectric layer 522a, and the multiple redistribution layers 524 include a bottommost redistribution layer 524a disposed on the bottommost dielectric layer 522a and a topmost redistribution layer 524b disposed on the topmost dielectric layer 522b, and the topmost redistribution layer 524b is electrically connected to the bottommost redistribution layer 524a. It is worth noting that the individual number of dielectric layers 522 and redistribution layers 524 in the redistribution structure 520 is not limited to two layers. In other words, there may be other dielectric layers between the bottommost dielectric layer 522a and the topmost dielectric layer 522b, and there may be other redistribution layers between the bottommost redistribution layer 524a and the topmost redistribution layer 524b. The capacitor 540 is not disposed on the surface of the substrate 510. Instead, the capacitor 540 is disposed on the surface of the redistribution structure 520 and is electrically connected to the topmost redistribution layer 524b. In this embodiment, the capacitor 540 is a surface mount type passive component.

[0038] Figure 8 FIG is a cross-sectional view of an electronic device according to an eighth embodiment of the present invention. Figure 7 and Figure 8 The electronic device P4 of this embodiment is similar to the electronic device P3 of the seventh embodiment, but the main difference between the two is the electrical connection between the capacitor 540 and the redistribution structure 520. Figure 8 As shown, the capacitor 540 is disposed on the surface of the redistribution structure 520 , and the capacitor 540 is electrically connected to the topmost redistribution layer through a bonding structure 550 . The bonding structure 550 includes a metal material, such as Cu.

[0039] It is worth noting that the number of capacitors 540 in the aforementioned electronic devices P1, P2, P3, and P4 is not limited to one. The capacitors 540 in the electronic devices P1, P2, P3, and P4 may be multiple, and the type of multiple capacitors 540 used in the electronic devices (such as Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B and Figure 4 The capacitors 100, 200, 300, 400, 500 shown in FIG) and various arrangement positions (such as Figures 5 to 8 setting position shown).

[0040] Figure 9 This is a cross-sectional diagram of an electronic device according to a ninth embodiment of the present invention. Figure 9 The electronic device P5 of this embodiment includes a lower electronic device 600A and an upper electronic device 600B configured on the lower electronic device 600A. The lower electronic device 600A includes a first substrate 610A, a first conductive via 620A penetrating the first substrate 610A, a capacitor 640 embedded in the first substrate 610A, and a first bonding structure 630A, wherein the first bonding structure 630A covers the first substrate 610A, the first conductive via 620A, and the capacitor 640, and the first bonding structure 630A is electrically connected to the first conductive via 620A and the capacitor 640. The upper electronic device 600B includes a second substrate 610B, a second conductive via 620B penetrating the second substrate 610B, and a redistribution structure 650, wherein the second bonding structure 630B covers the second substrate 610B and the second conductive via 620B, and the second bonding structure 630B is electrically connected to the second conductive via 620B. In addition, the redistribution structure 650 covers the second substrate 610B and the second conductive via 620B, and the redistribution structure 650 is electrically connected to the second bonding structure 630B through the second conductive via 620B.

[0041] like Figure 9 As shown, the lower electronic device 600A and the upper electronic device 600B can be electrically connected via a first bonding structure 630A and a second bonding structure 630B. The capacitor 640 can be electrically connected to the redistribution structure 650 via the first bonding structure 630A, the second bonding structure 630B, and the second conductive via 620B. The first bonding structure 630A and the second bonding structure 630B include a metal material, such as Cu.

[0042] Here, the structure of the capacitor 640 in the electronic device P5 can be as follows Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B or Figure 4 The structure of the capacitor 100, 200, 300, 400 or 500 shown in FIG.

[0043] Figure 10 FIG is a cross-sectional view of an electronic device according to the tenth embodiment of the present invention. Figure 4 and Figure 10 The capacitor 400' in the electronic device P6 of this embodiment is similar to the capacitor 400 of the fourth embodiment, but the main difference between the two is that the capacitor 400' in this embodiment further includes a conductive via V1 and a conductive via V2, wherein the first electrode 122 is connected to the first portion of the third electrode 128 (for example, Figure 10 The second electrode 124 is electrically connected to the second portion of the third electrode 128 (eg, the right portion of the third electrode 128) through the conductive via V2. Figure 10 The left portion of the third electrode 128 is electrically connected, and the first portion of the third electrode 128 is electrically insulated from the second portion of the third electrode 128. Figure 10 As shown, the electronic device P6 of this embodiment includes a capacitor 400', a rewiring structure 520, and a chip 530, wherein the rewiring structure 520 is disposed on the capacitor 400' and electrically connected to the capacitor 400', and the chip 530 is disposed on the rewiring structure 520 and electrically connected to the capacitor 400' through the rewiring structure 520. For example, the first portion of the third electrode 128 electrically connected to the first electrode 122 is electrically connected to one terminal of the chip 530 through a wire in the rewiring structure 520, while the second portion of the third electrode 128 electrically connected to the second electrode 124 is electrically connected to another terminal of the chip 530 through another wire in the rewiring structure 520. Figure 10 As shown, the dielectric layer in the redistribution structure 520 may be filled into the recess R4 ′ of the capacitor 400 ′.

[0044] In the above embodiment of the present invention, the capacitor dielectric layer having the inorganic dielectric layer and the organic dielectric layer can effectively control the self-resonance frequency of the capacitor during high-frequency operation, thereby improving the dielectric loss problem during high-speed transmission caused by poor dielectric film flatness.

[0045] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the appended claims.

[0046] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A capacitor, characterized in that: include: a first electrode; a second electrode; as well as A first capacitor dielectric layer is disposed between the first electrode and the second electrode. The first capacitor dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer includes an inorganic dielectric layer and the second dielectric layer includes an organic dielectric layer. The first dielectric layer is located between the first electrode and the second dielectric layer, and the second dielectric layer is located between the first dielectric layer and the second electrode.

2. The capacitor according to claim 1, wherein The first dielectric layer has a first surface that contacts the second dielectric layer, the second dielectric layer has a second surface that contacts the second electrode, and the roughness of the first surface is greater than that of the second surface.

3. The capacitor according to claim 1, wherein The distribution area of ​​the first electrode, the second electrode and the first capacitor dielectric layer is less than or equal to 50 micrometers×50 micrometers.

4. The capacitor according to claim 1, wherein Further including: A substrate, wherein the first electrode is configured on the substrate, and the first capacitor dielectric layer and the second electrode are stacked on the first electrode.

5. The capacitor according to claim 4, wherein The substrate has a groove, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

6. The capacitor according to claim 4, wherein The substrate comprises: a first material layer; and The second material layer is disposed on the first material layer.

7. The capacitor according to claim 6, wherein The substrate has a groove, the groove passes through the second material layer and extends into a portion of the first material layer, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

8. The capacitor according to claim 6, wherein The substrate has a groove, the groove is distributed in the second material layer, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

9. The capacitor according to claim 1, wherein Further including: a third electrode; as well as A second capacitor dielectric layer, wherein the second capacitor dielectric layer is configured on the second electrode and located between the second electrode and the third electrode.

10. An electronic device, characterized in that: include: substrate; a redistribution structure, disposed on the substrate; a capacitor electrically connected to the rewiring structure, the capacitor comprising a first electrode, a second electrode, and a first capacitor dielectric layer, the first capacitor dielectric layer being disposed between the first electrode and the second electrode, the first capacitor dielectric layer comprising a first dielectric layer and a second dielectric layer, the first dielectric layer comprising an inorganic dielectric layer, the second dielectric layer comprising an organic dielectric layer, wherein the first dielectric layer is located between the first electrode and the second dielectric layer, and the second dielectric layer is located between the first dielectric layer and the second electrode; and The chip is configured on the redistribution structure and electrically connected to the redistribution structure.

11. The electronic device according to claim 10, wherein: The first dielectric layer has a first surface that contacts the second dielectric layer, the second dielectric layer has a second surface that contacts the second electrode, and the roughness of the first surface is greater than that of the second surface.

12. The electronic device according to claim 10, wherein: The distribution area of ​​the first electrode, the second electrode and the first capacitor dielectric layer is less than or equal to 50 micrometers×50 micrometers.

13. The electronic device according to claim 10, wherein: wherein the capacitor further comprises: A substrate, wherein the first electrode is configured on the substrate, and the first capacitor dielectric layer and the second electrode are stacked on the first electrode.

14. The electronic device according to claim 13, wherein: The substrate has a groove, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

15. The electronic device according to claim 13, wherein: Wherein the substrate comprises: a first material layer; and The second material layer is disposed on the first material layer.

16. The electronic device according to claim 15, wherein: The substrate has a groove, the groove passes through the second material layer and extends into a portion of the first material layer, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

17. The electronic device according to claim 15, wherein: The substrate has a groove, the groove is distributed in the second material layer, and the first electrode, the first capacitor dielectric layer and the second electrode cover the groove.

18. The electronic device according to claim 10, wherein: wherein the capacitor further comprises: a third electrode; and A second capacitor dielectric layer, wherein the second capacitor dielectric layer is configured on the second electrode and located between the second electrode and the third electrode.

19. The electronic device according to claim 10, wherein: The capacitor is embedded in the redistribution structure.

20. The electronic device according to claim 10, wherein: The capacitor is configured on the redistribution structure.

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