Semiconductor packaging structure and preparation method thereof

Abstract

The invention relates to a semiconductor packaging structure and a preparation method thereof. The preparation method comprises the following steps: providing an initial packaging structure; etching and removing part of the first chip along the back surface of the first chip by adopting an etching process to form a groove and expose the through hole connecting structure; a second rewiring layer is formed on the surface, exposed out of the back surface of the first chip, of the first plastic packaging layer and in the groove, and the second rewiring layer is electrically connected with the through hole connecting structure and the metal column; and forming an outer welding bulge on the surface, far away from the first chip, of the second rewiring layer, wherein the outer welding bulge is electrically connected with the second rewiring layer. According to the method, diffusion of metal ions caused by the fact that a grinding process is adopted to grind the back face of the first chip and the metal columns at the same time to remove part of the first chip and the metal columns so as to expose the through hole connecting structure can be avoided, the performance of the packaging structure can be improved, cost can be saved, and meanwhile stress borne by the first chip can be better relieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] Fan-out packaging technology is a packaging method commonly used in integrated circuit design. By connecting multiple chips together to form a small circuit module and encapsulating it in a package, it achieves functional integration and greatly reduces the volume of the package.

[0003] As the number of chips that need to be packaged continues to increase, the lateral area occupied by multiple chips is getting larger and larger. In order to reduce the lateral area occupied by the chips, multiple chips are connected vertically so that more chips can be packaged in the same lateral area. However, the existing packaging process has the problem of copper ion diffusion, which affects the performance of the packaging structure. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor packaging structure and a preparation method thereof, which prevents copper ion diffusion during the packaging process, thereby improving the performance of the packaging structure.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor package structure, comprising:

[0006] An initial packaging structure is provided, comprising a metal pillar, a first chip, a second chip, a first redistribution layer, and a first plastic encapsulation layer, wherein the first chip comprises an active surface and a back surface opposite to each other, the active surface having a connection pad, the first chip comprises a through-hole connection structure, and the back surface does not expose the through-hole connection structure, the first plastic encapsulation layer covers the metal pillar and the side surface of the first chip, and exposes both ends of the metal pillar and the active surface and back surface of the first chip, the first redistribution layer is located on a surface of the first plastic encapsulation layer that exposes the active surface of the first chip, the second chip is attached to a surface of the first redistribution layer away from the first plastic encapsulation layer, and the first redistribution layer is electrically connected to the connection pad, the metal pillar, and the second chip;

[0007] Using an etching process to etch away a portion of the first chip along the back surface of the first chip to form a groove and expose the through-hole connection structure;

[0008] forming a second redistribution layer on the surface of the first plastic packaging layer exposed to the back side of the first chip and in the groove, wherein the second redistribution layer is electrically connected to the through-hole connection structure and the metal pillar;

[0009] An external soldering bump is formed on a surface of the second redistribution layer away from the first chip, and the external soldering bump is electrically connected to the second redistribution layer.

[0010] In some embodiments of the present application, the etching process includes a dry etching process; the first chip includes a silicon substrate, and the through-hole connection structure is located in the silicon substrate.

[0011] In some embodiments of the present application, the dry etching process includes an anisotropic plasma etching process, and the etching gas used in the anisotropic plasma etching process includes Cl2 or HCl, the etching gas flow range is 50sccm~150sccm, the source power range is 300W~1800W, the bias power range is 25W~300W, and the chamber pressure range is 10mTorr~100mTorr.

[0012] In some embodiments of the present application, the second redistribution layer includes an electrically connected first sub-wiring layer and a second sub-wiring layer, the first sub-wiring layer is located in the groove, and the second sub-wiring layer is located on a surface of the first plastic encapsulation layer exposed to the back surface of the first chip and a surface of the first sub-wiring layer away from the first chip; the second redistribution layer is electrically connected to the through-hole connection structure and the metal pillar, including: the first sub-wiring layer is electrically connected to the through-hole connection structure, and the second sub-wiring layer is electrically connected to the metal pillar;

[0013] The process of forming the second redistribution layer includes: forming a first sub-wiring layer in the groove; forming a second sub-wiring layer on the surface of the first plastic packaging layer exposed to the back of the first chip and the surface of the first sub-wiring layer away from the first chip.

[0014] In some embodiments of the present application, the first sub-wiring layer includes a first sub-isolating layer and a first sub-metal layer located in the first sub-isolating layer, and the first sub-wiring layer is electrically connected to the through-hole connection structure, comprising: the first sub-metal layer is electrically connected to the through-hole connection structure;

[0015] The process of forming the first sub-wiring layer includes: forming a first sub-isolating layer that fills the groove; forming a sub-via in the first sub-isolating layer to expose the corresponding via connection structure; and forming a first sub-metal layer in the sub-via.

[0016] In some embodiments of the present application, the thermal expansion coefficient of the first sub-isolation layer is smaller than that of the first plastic encapsulation layer, the material of the first sub-isolation layer is a photosensitive resin, and sub-through holes are formed in the first sub-isolation layer through exposure and development processes.

[0017] In some embodiments of the present application, the second sub-wiring layer includes a second sub-isolating layer and a second sub-metal layer located in the second sub-isolating layer, and the second sub-wiring layer is electrically connected to the first sub-wiring layer and the metal pillar, comprising: the second sub-metal layer is electrically connected to the first sub-metal layer and the metal pillar;

[0018] The process of forming the second sub-wiring layer includes: forming a second sub-isolation layer on the surface of the first plastic packaging layer that exposes the back side of the first chip and on the surface of the first sub-isolation layer that is away from the first chip; forming corresponding first sub-openings and second sub-openings in the second sub-isolation layer that expose the first sub-metal layer and the metal pillar; and forming a second sub-metal layer in the first sub-opening and the second sub-opening.

[0019] In some embodiments of the present application,

[0020] The preparation method further includes: forming a second plastic sealing layer covering the second chip;

[0021] The process of providing an initial package structure includes:

[0022] Providing a carrier plate having raised metal pillars;

[0023] Providing a first chip, and mounting the back side of the first chip on a carrier board;

[0024] forming a first plastic encapsulation layer on the carrier board to cover the first chip and the metal pillar, wherein the first plastic encapsulation layer exposes an end surface of the metal pillar away from the carrier board and an active surface of the first chip;

[0025] forming a first redistribution layer on a surface of the first plastic packaging layer away from the carrier board, wherein the first redistribution layer is electrically connected to the connection pads and the metal pillars;

[0026] Providing a second chip, mounting the second chip on a surface of the first redistribution layer away from the carrier board, and electrically connecting the second chip to the first redistribution layer;

[0027] Remove the carrier board.

[0028] In a second aspect, an embodiment of the present application further provides a semiconductor package structure, including:

[0029] A first chip includes an active surface and a back surface opposite to each other, the active surface having a connection pad, a through-hole connection structure in the first chip, and the back surface exposing the through-hole connection structure;

[0030] a first plastic encapsulation layer covering the metal pillar and the first chip, the first plastic encapsulation layer comprising a first surface and a second surface opposite to each other, the first surface of the first plastic encapsulation layer exposing the active surface of the first chip and one end surface of the metal pillar, and the second surface of the first plastic encapsulation layer exposing the other end surface of the metal pillar;

[0031] a first redistribution layer, located on a first surface of the first plastic packaging layer, the first redistribution layer being electrically connected to the connection pads and the metal pillars;

[0032] A second chip is mounted on a surface of the first redistribution layer away from the first plastic packaging layer, and the second chip is electrically connected to the first redistribution layer;

[0033] a groove penetrating a portion of the second surface of the first plastic packaging layer and exposing the through-hole connection structure on the back side of the first chip;

[0034] a first sub-wiring layer located in the groove, the first sub-wiring layer including a first sub-isolating layer and a first sub-metal layer located in the first sub-isolating layer, the first sub-metal layer being electrically connected to the through-hole connection structure, and the thermal expansion coefficient of the first sub-isolating layer being smaller than the thermal expansion coefficient of the first plastic encapsulation layer;

[0035] a second sub-wiring layer, located on the second surface of the first plastic packaging layer and on the surface of the first sub-wiring layer away from the first chip, the second sub-wiring layer being electrically connected to the first sub-wiring layer;

[0036] The external soldering bump is located on a surface of the second redistribution layer away from the first chip and is electrically connected to the second redistribution layer.

[0037] In some embodiments of the present application, the material of the first sub-isolating layer is a photosensitive resin, and the material of the first plastic encapsulation layer is a plastic encapsulation resin.

[0038] The embodiments of the present application may or at least have the following advantages:

[0039] The semiconductor packaging structure and preparation method thereof in the embodiments of the present application provide an initial packaging structure; an etching process is used to etch and remove a portion of the first chip along the back side of the first chip to form a groove, exposing a through-hole connection structure; a second redistribution layer is formed on the surface of the first plastic encapsulation layer exposed on the back side of the first chip and in the groove, and the second redistribution layer is electrically connected to the through-hole connection structure and the metal column; an external welding protrusion is formed on the surface of the second redistribution layer away from the first chip, and the external welding protrusion is electrically connected to the second redistribution layer. In the present application, a portion of the first chip is etched away along the back side of the first chip through an etching process to expose the through-hole connection structure. On the one hand, the diffusion of metal ions caused by the simultaneous grinding and removing of the back side of the first chip and the metal pillars to expose the through-hole connection structure can be avoided, thereby improving the performance of the packaging structure. On the other hand, compared with the grinding process, the etching process can more simply expose the through-hole connection structure, saving costs, and the etching process will not damage the metal pillars and will not cause the movement or offset of the position of the metal pillars, thereby improving the accuracy of the height and position of the metal pillars, which is conducive to improving the accuracy of the second redistribution layer formed subsequently. On the other hand, the etching process is used to etch away a portion of the first chip along the back side of the first chip to form a groove, and a first sub-isolation layer with a thermal expansion coefficient smaller than that of the first plastic encapsulation layer can be formed in the groove. The first sub-isolation layer serves as a buffer layer, thereby better alleviating the stress on the first chip.

[0040] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of a cross-sectional structure of a carrier board and metal pillars after formation in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0043] Figure 2 A schematic diagram of a cross-sectional structure after mounting a first chip in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0044] Figure 3 A schematic diagram of a cross-sectional structure after forming a first plastic encapsulation layer in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0045] Figure 4 A schematic cross-sectional view of a method for preparing a semiconductor package structure according to some embodiments of the present application after forming a first redistribution layer;

[0046] Figure 5 A schematic diagram of a cross-sectional structure after mounting a second chip in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0047] Figure 6 A schematic diagram of a cross-sectional structure after forming a second plastic encapsulation layer in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0048] Figure 7 A schematic diagram of a cross-sectional structure after removing a carrier board in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0049] Figure 8 A schematic diagram of a cross-sectional structure after a groove is formed in a method for preparing a semiconductor package structure provided in some embodiments of the present application;

[0050] Figure 9 A schematic cross-sectional view of a method for preparing a semiconductor package structure according to some embodiments of the present application after forming a first sub-isolating layer;

[0051] Figure 10 A schematic cross-sectional view of a method for preparing a semiconductor package structure according to some embodiments of the present application after forming a second redistribution layer;

[0052] Figure 11 A schematic diagram of a cross-sectional structure after forming an external welding protrusion in a method for preparing a semiconductor packaging structure provided in some embodiments of the present application.

[0053] Description of reference numerals:

[0054] Carrier 100; seed layer 101; first plastic layer 102; metal pillar 103; first insulating layer 104; first metal line 105; underfill layer 106; second plastic layer 107; groove 108; first sub-isolating layer 109; sub-via 110; first sub-metal layer 111; second sub-isolating layer 112; second sub-metal layer 113; external solder bump 114;

[0055] First chip 201; connection pad 202; through-hole connection structure 203; second chip 204; solder bump 205

[0056] First redistribution layer 11; second redistribution layer 12; active surface 21; back surface 22. DETAILED DESCRIPTION

[0057] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0059] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0060] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0061] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings, but includes shape deviations due to, for example, manufacturing technology.

[0063] It can be understood that in the drawings of the present application, some adjacent film layers made of the same processing film material are drawn as being connected to make them close to the actual structure.

[0064] The present invention first provides a method for preparing a semiconductor structure. Figures 1-11 Schematic diagram of the cross-sectional structure of each stage in the method for preparing the semiconductor structure provided in some embodiments of the present application.

[0065] First, refer to Figure 7 , providing an initial packaging structure, the initial packaging structure includes a metal pillar 103, a first chip 201, a second chip 204, a first redistribution layer 11 and a first plastic layer 102, wherein the first chip 201 includes an active surface 21 and a back surface 22 relative to each other, the active surface 21 has a connecting pad 202, the first chip 201 has a through-hole connection structure 203, and the back surface 22 does not expose the through-hole connection structure 203, the first plastic layer 102 covers the metal pillar 103 and the side of the first chip 201, and exposes both ends of the metal pillar 103 and the active surface 21 and the back surface 22 of the first chip 201, the first redistribution layer 11 is located on the surface of the first plastic layer 102 exposing the active surface 21 of the first chip 201, the second chip 204 is mounted on the surface of the first redistribution layer 11 away from the first plastic layer 102, and the first redistribution layer 11 is electrically connected to the connecting pad 202, the metal pillar 103 and the second chip 204.

[0066] Specifically, metal pillars 103 are electrically connected to first wiring layer 11 and are used to direct some external ports of second chip 204 to a side of the package structure away from second chip 204. In some embodiments, there may be one or more metal pillars 103, which may be distributed on one side, multiple sides, or around first chip 201. In one example, the material of metal pillars 103 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0067] The active surface 21 of the first chip 201 has a connection pad 202, which is electrically connected to the first redistribution layer 11. The first chip 201 has a through-hole connection structure 203 (the through-hole connection structure 203 can be a through-silicon via or TSV). The back surface 22 of the first chip 201 does not expose the through-hole connection structure 203. That is, the back surface 22 of the first chip 201 has not been thinned to expose the through-hole connection structure 203. This allows the first chip 201 to maintain a relatively thick thickness during the formation of the initial package structure, avoiding or reducing the risk of the first chip 201 being broken due to excessive thickness during the formation of the initial package structure. In one example, the material of the connection pad 202 and the through-hole connection structure 203 includes one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0068] In some embodiments, the first chip 201 includes a silicon substrate, and the through-via connection structure 203 is located in the silicon substrate.

[0069] The first chip 201 is electrically connected to the second chip 204. In a specific example, the connection pads 202 on the active surface 21 of the first chip can be electrically connected to the solder bumps 205 on the second chip 204 through the first redistribution layer 11. The number of the first chip 201 is at least one. Specifically, the number of the first chip 201 can be one, two, or more. Figure 7 The package structure has two first chips 201 as an example for description. The number of the second chip 204 is also at least one. Specifically, the number of the second chip 204 can be one, two or more. Figure 7 The description is made by taking a package structure having a second chip 204 as an example.

[0070] In some embodiments, the first chip 201 includes a bridge chip, and the wiring density in the bridge chip is greater than the wiring density in the first redistribution layer 11. In other embodiments, the first chip 201 may also be a signal processing chip, a logic control chip, a memory chip, a sensor chip, a power chip, or a radio frequency chip.

[0071] Second chip 204 includes an active surface and a back surface facing each other. An integrated circuit (e.g., a logic circuit or a memory circuit) is formed in second chip 204. The active surface of second chip 204 includes solder bumps 205, which are electrically connected to the integrated circuit. In some embodiments, solder bumps 205 may include solder bumps or metal bumps and solder caps located on top of the metal bumps. In one example, the metal bumps are made of a metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, or silver. The solder bumps or solder caps are made of tin or a tin alloy, including one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0072] In some embodiments, when the second chip 204 is electrically connected to the first redistribution layer 11, the second chip 204 is flipped on the surface of the first redistribution layer 11 away from the first chip 201. Specifically, the active surface of the second chip 204 faces the surface of the first redistribution layer 11 away from the first chip 201, and the welding protrusions 205 on the active surface of the second chip 204 are welded together with the corresponding pads on the surface of the first redistribution layer 11.

[0073] In some embodiments, the second chip 204 may be a signal processing chip, a logic control chip, a memory chip, a sensor chip, a power chip, or a radio frequency chip. The logic control chip may include, but is not limited to, a gate array, a cell substrate array, an embedded array, a structured application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), or a display driver IC (DDI). The memory chip includes, but is not limited to, a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase-change memory (PRAM), a resistive random access memory (RRAM), a non-volatile memory chip (such as flash memory), or a high-bandwidth memory (HBM).

[0074] The first redistribution layer 11 is used to electrically connect the second chip 204 to the first chip 201 and the metal pillars 103. In some embodiments, the first redistribution layer 11 includes a first insulating layer 104 and first metal traces 105 located within the first insulating layer 104. The first redistribution layer 11 may also include pads located on a surface of the first redistribution layer 11 away from the first chip 201 and electrically connected to the first metal traces 105. In one example, the first insulating layer 104 may be made of polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable polymer-based dielectric materials. The first metal traces 105 or pads may be made of one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0075] The first molding layer 102 is used to protect the first chip 201 and the metal pillars 103. The material of the first molding layer 102 is a molding resin. Specifically, the material of the first molding layer 102 may include epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin with or without fillers; or may include polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol with or without fillers. In one example, the filler may include an inorganic filler or an organic filler.

[0076] In some embodiments, the initial package structure further includes an underfill layer 106 (UF) filling the active surface of the second chip 204 and the surface of the first redistribution layer 11 away from the first chip 201, and a second molding layer 107 encapsulating the second chip 204. Both the underfill layer 106 and the second molding layer 107 are made of resin, and the particle size of the material of the underfill layer 106 is smaller than that of the material of the second molding layer 107. The material of the second molding layer 107 can be the same as that of the first molding layer 102 and will not be further described here.

[0077] In some embodiments below, Figure 1 -Attached Figure 7 A detailed description of the process of providing an initial packaging structure is given.

[0078] The process of providing an initial package structure includes:

[0079] refer to Figure 1 , providing a carrier board 100 having raised metal pillars 103 thereon.

[0080] The material of the carrier 100 can be glass or silicon. The carrier 100 serves as a temporary carrier for forming the initial packaging structure. After the initial packaging structure is formed, the carrier 100 needs to be removed.

[0081] In some embodiments, metal pillars 103 can be formed on carrier 100 via an electroplating process. Prior to forming metal pillars 103, a seed layer 101 can be formed on the surface of carrier 100 via a sputtering process. A patterned mask layer (e.g., a photoresist layer) is then formed on the surface of seed layer 101 facing away from carrier 100. The patterned mask layer includes openings that expose portions of the seed layer surface. Electroplating is then used to form metal pillars 103 in the openings. In other embodiments, existing metal pillars can also be attached to the surface of carrier 100 via an adhesive layer.

[0082] refer to Figure 2 , provide a first chip 201 , and mount the back side 22 of the first chip 201 on the carrier 100 .

[0083] The back surface 22 of the first chip 201 does not expose the through-hole connection structure 203. In one example, the back surface 22 of the first chip 201 is mounted on the carrier 100 via an adhesive layer.

[0084] After the first chip 201 is mounted, the surface of the connection pads 202 of the active surface 21 of the first chip 201 away from the carrier 100 is flush with the surface of the metal pillars 103 away from the carrier 100 .

[0085] refer to Figure 3 A first plastic encapsulation layer 102 covering the first chip 201 and the metal pillar 103 is formed on the carrier 100 , and the first plastic encapsulation layer 102 exposes an end surface of the metal pillar 103 away from the carrier 100 and the active surface 21 of the first chip 201 .

[0086] The process of forming the first plastic encapsulation layer 102 includes compression molding or transfer molding.

[0087] refer to Figure 4 A first redistribution layer 11 is formed on a surface of the first plastic layer 102 away from the carrier 100 . The first redistribution layer 11 is electrically connected to the connection pads 202 and the metal pillars 103 .

[0088] In some embodiments, first redistribution layer 11 includes first insulating layer 104 and first metal line 105 located in first insulating layer 104. Electrically connecting first redistribution layer 11 to connection pad 202 and metal pillar 103 includes: first metal line 105 in first redistribution layer 11 is electrically connected to connection pad 202 and metal pillar 103.

[0089] refer to Figure 4, provide a second chip 204 , and mount the second chip 204 on a surface of the first redistribution layer 11 away from the carrier 100 , so that the second chip 204 is electrically connected to the first redistribution layer 11 .

[0090] In some embodiments, the second chip 204 is flip-chip mounted on a surface of the first redistribution layer 11 away from the carrier 100 . Specifically, the solder bumps 205 on the active surface of the second chip 204 are soldered to corresponding solder pads on the surface of the first redistribution layer 11 .

[0091] refer to Figure 6 An underfill layer 106 is formed between the active surface of the second chip 204 and the first redistribution layer 11 ; and a second plastic encapsulation layer 107 is formed to cover the second chip 204 .

[0092] The process for forming the underfill layer 106 includes a dispensing process, and the process for forming the second plastic encapsulation layer 107 includes a compression molding process or a transfer molding process.

[0093] In some embodiments, the second plastic layer 107 may expose the back of the second chip 204 to facilitate subsequent mounting of a heat sink on the back of the second chip 204. In other embodiments, the second plastic layer 107 may not expose the back of the second chip 204.

[0094] refer to Figure 7 , remove the carrier board 100 .

[0095] In some embodiments, after removing the carrier 100 , the surface of the first plastic layer 102 in contact with the carrier 100 is pre-grinded to remove excess adhesion layer, exposing the back surface of the first chip 201 and one end surface of the second chip 204 on the principle of the metal pillar 103 .

[0096] At this point, the initial packaging structure is complete.

[0097] refer to Figure 8 After providing the initial packaging structure, an etching process is used to etch away a portion of the first chip 201 along the back surface 22 of the first chip 201 to form a groove 108 and expose the through-hole connection structure 203.

[0098] In the present application, a portion of the first chip 201 is etched away along the back side 22 of the first chip 201 to expose the through-hole connection structure 203. On the one hand, the diffusion of metal ions caused by simultaneously grinding and removing the back side 22 of the first chip 201 and the metal pillar 103 to expose the through-hole connection structure 203 can be avoided, thereby improving the performance of the packaging structure. On the other hand, compared with the grinding process, the etching process can more easily expose the through-hole connection structure 203, saving costs, and the etching process can be more convenient. The process will not damage the metal pillar 103 and will not cause the position of the metal pillar 103 to move or shift, thereby improving the accuracy of the height and position of the metal pillar 103, and helping to improve the accuracy of the second redistribution layer formed subsequently; on the other hand, an etching process is adopted to etch and remove part of the first chip 201 along the back side 22 of the first chip 201 to form a groove 108, and subsequently a first sub-isolation layer with a thermal expansion coefficient smaller than that of the first plastic encapsulation layer 102 can be formed in the groove 108. The first sub-isolation layer serves as a buffer layer, thereby better alleviating the stress on the first chip 201.

[0099] In one embodiment, the etching process includes a dry etching process and an anisotropic plasma etching process.

[0100] In one embodiment, the first chip 201 includes a silicon substrate, and when the through-hole connection structure 203 is located in the silicon substrate, the dry etching process includes an anisotropic plasma etching process. The etching gas used in the anisotropic plasma etching process includes Cl2 or HCl, the etching gas flow range is 50sccm~150sccm, the source power range is 300W~1800W, the bias power range is 25W~300W, and the chamber pressure range is 10 mTorr~100 mTorr, thereby improving the etching efficiency on the back side of the first chip 201 while reducing over-etching of the through-hole connection structure 203.

[0101] refer to Figure 9 and Figure 10 A second redistribution layer 12 is formed in the surface of the first plastic layer 102 that exposes the back surface 22 of the first chip 201 and in the groove 108 . The second redistribution layer 12 is electrically connected to the through-hole connection structure 203 and the metal pillar 103 .

[0102] In some embodiments, the second redistribution layer 12 includes an electrically connected first sub-wiring layer and a second sub-wiring layer, the first sub-wiring layer is located in the groove 108, the second sub-wiring layer is located on the surface of the first plastic encapsulation layer 102 exposed to the back side 22 of the first chip 201 and the surface of the first sub-wiring layer away from the first chip 201, and the electrical connection between the second redistribution layer and the through-hole connection structure 203 and the metal pillar 103 includes: the first sub-wiring layer is electrically connected to the through-hole connection structure 203, and the second sub-wiring layer is electrically connected to the metal pillar 103. In some embodiments, the first sub-wiring layer includes a first sub-isolation layer 109 and a first sub-metal layer 111 located in the first sub-isolation layer 109, and the electrical connection between the first sub-wiring layer and the through-hole connection structure 203 includes: the first sub-metal layer 111 is electrically connected to the through-hole connection structure 203; the second sub-wiring layer includes a second sub-isolation layer 112 and a second sub-metal layer 113 located in the second sub-isolation layer 112, and the electrical connection between the second sub-wiring layer and the first sub-wiring layer and the metal pillar 103 includes: the second sub-metal layer 113 is electrically connected to the first sub-metal layer 111 and the metal pillar 103.

[0103] In some embodiments, the process of forming the second redistribution layer 12 includes: forming a first sub-wiring layer in the groove 108; forming a second sub-wiring layer on the surface of the first plastic encapsulation layer 102 exposed to the back surface 22 of the first chip 201 and the surface of the first sub-wiring layer away from the first chip 201. In a specific embodiment, the process of forming the first sub-wiring layer includes: referring to Figure 9 , forming a first sub-isolating layer 109 that fills the groove 108. In a specific example, the thermal expansion coefficient of the first sub-isolating layer 109 is less than the thermal expansion coefficient of the first plastic encapsulation layer 102. The material of the first sub-isolating layer is a photosensitive resin, specifically a photosensitive polyimide (PI), a photosensitive benzocyclobutene (BCB) or a photosensitive polybenzoxazole (PBO), or a photosensitive polymer layer made of other suitable polymer-based dielectric materials. The first sub-isolating layer 109 can act as a buffer layer to effectively buffer the stress on the first chip 201. The first sub-isolating layer 109 can be formed by a spin coating process; continue to refer to Figure 9 , a sub-through hole 110 exposing the corresponding through-hole connection structure 203 is formed in the first sub-isolation layer 109. In one example, the sub-through hole 110 is formed in the first sub-isolation layer 109 by an exposure process and a development process, and a baking process is performed after the development process to solidify the first sub-isolation layer 109; Figure 10 A first sub-metal layer 111 is formed in the sub-through hole, and the material of the first sub-metal layer 111 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0104] In a specific embodiment, reference Figure 10The process of forming the second sub-wiring layer includes: forming a second sub-isolating layer 112 on the surface of the first plastic packaging layer 102 that is exposed to the back surface 22 of the first chip 201 and on the surface of the first sub-isolating layer 109 that is away from the first chip 201. In one example, the material of the second sub-isolating layer 112 can also be a photosensitive polyimide (PI), a photosensitive benzocyclobutene (BCB) or a photosensitive polybenzoxazole (PBO), or a photosensitive polymer layer made of other suitable polymer dielectric materials; forming a corresponding exposed dielectric layer on the second sub-isolating layer 112; The first sub-opening and the second sub-opening of the first sub-metal layer 111 and the metal pillar 103 are formed. In one example, the first sub-opening and the second sub-opening are formed in the second sub-isolation layer 112 through exposure and development processes, and the development process is followed by a baking process to solidify the second sub-isolation layer 112; the second sub-metal layer 113 is formed in the first sub-opening and the second sub-opening, and the material of the second sub-isolation layer 112 includes one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0105] refer to Figure 11 An external solder bump 114 is formed on a surface of the second redistribution layer 12 away from the first chip 201 , and the external solder bump 114 is electrically connected to the second redistribution layer 12 .

[0106] The external welding protrusion 114 may include a solder protrusion or a metal protrusion and a welding cap located on the top surface of the metal protrusion. In one example, the material of the metal protrusion is metal, specifically one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the solder protrusion or welding cap includes tin or a tin alloy, and the tin alloy includes one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0107] In some embodiments, electrically connecting the external solder bump 114 to the second redistribution layer 12 includes electrically connecting the external solder bump to the second sub-metal layer 113 in the second redistribution layer 12 .

[0108] The present application also provides a semiconductor packaging structure. Figure 11 ,include:

[0109] A first chip 201 includes an active surface 21 and a back surface 22 opposite to each other. The active surface 21 has a connection pad 202. The first chip 201 has a through-hole connection structure 203. The back surface 22 exposes the through-hole connection structure 203.

[0110] A first plastic encapsulation layer 102 covers the metal pillar 103 and the first chip 201. The first plastic encapsulation layer 102 includes a first surface and a second surface opposite to each other. The first surface of the first plastic encapsulation layer 102 exposes the active surface 21 of the first chip 201 and one end surface of the metal pillar 103. The second surface of the first plastic encapsulation layer 102 exposes the other end surface of the metal pillar 103.

[0111] A first redistribution layer 11 is located on the first surface of the first plastic layer 102 , and the first redistribution layer 11 is electrically connected to the connection pads 202 and the metal pillars 103 ;

[0112] The second chip 204 is mounted on a surface of the first redistribution layer 11 away from the first plastic packaging layer 102 , and the second chip 204 is electrically connected to the first redistribution layer 11 ;

[0113] The groove 108 penetrates a portion of the second surface of the first plastic packaging layer 102 and exposes the through-hole connection structure 203 on the back surface 22 of the first chip 201;

[0114] A first sub-wiring layer is located in the groove 108. The first sub-wiring layer includes a first sub-isolating layer 109 and a first sub-metal layer 111 located in the first sub-isolating layer 109. The first sub-metal layer 111 is electrically connected to the through-hole connection structure 203. The thermal expansion coefficient of the first sub-isolating layer 109 is smaller than the thermal expansion coefficient of the first plastic encapsulation layer 102.

[0115] A second sub-wiring layer is located on the second surface of the first plastic packaging layer 102 and on the surface of the first sub-wiring layer away from the first chip 201 , and the second sub-wiring layer is electrically connected to the first sub-wiring layer;

[0116] The external solder bump 114 is located on a surface of the second redistribution layer 12 away from the first chip 201 and is electrically connected to the second redistribution layer 12 .

[0117] In some embodiments, the material of the first sub-isolating layer 109 is a photosensitive resin, and the material of the first plastic encapsulation layer 102 is a plastic encapsulation resin.

[0118] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0119] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor packaging structure, characterized in that: include: An initial package structure is provided, comprising a metal pillar, a first chip, a second chip, a first redistribution layer, and a first plastic layer, wherein the first chip comprises an active surface and a back surface opposite to each other, the active surface having connection pads, the first chip comprises a through-hole connection structure, and the back surface does not expose the through-hole connection structure, the first plastic layer covers the metal pillar and the side surfaces of the first chip, and exposes both ends of the metal pillar and the active surface and back surface of the first chip, the first redistribution layer is located on a surface of the first plastic layer that exposes the active surface of the first chip, the second chip is attached to a surface of the first redistribution layer away from the first plastic layer, and the first redistribution layer is electrically connected to the connection pads, the metal pillar, and the second chip; Using an etching process to etch away a portion of the first chip along the back surface of the first chip to form a groove, exposing the through-hole connection structure; forming a second redistribution layer on a surface of the first plastic encapsulation layer exposed to the back side of the first chip and in the groove, wherein the second redistribution layer is electrically connected to the through-hole connection structure and the metal pillar; An external solder bump is formed on a surface of the second redistribution layer away from the first chip, and the external solder bump is electrically connected to the second redistribution layer.

2. The method for preparing a semiconductor package structure according to claim 1, wherein: The etching process includes a dry etching process; the first chip includes a silicon substrate, and the through-hole connection structure is located in the silicon substrate.

3. The method for preparing a semiconductor package structure according to claim 2, wherein: The dry etching process includes an anisotropic plasma etching process. The etching gas used in the anisotropic plasma etching process includes Cl2 or HCl, the etching gas flow range is 50sccm~150sccm, the source power range is 300W~1800W, the bias power range is 25W~300W, and the chamber pressure range is 10 mTorr~100 mTorr.

4. The method for preparing a semiconductor package structure according to claim 1, wherein: The second redistribution layer includes a first sub-wiring layer and a second sub-wiring layer that are electrically connected, the first sub-wiring layer is located in the groove, and the second sub-wiring layer is located on a surface of the first plastic packaging layer exposed to the back of the first chip and a surface of the first sub-wiring layer away from the first chip; The second redistribution layer is electrically connected to the through-hole connection structure and the metal column, comprising: the first sub-wiring layer is electrically connected to the through-hole connection structure, and the second sub-wiring layer is electrically connected to the metal column; The process of forming the second redistribution layer includes: forming the first sub-wiring layer in the groove; forming the second sub-wiring layer on the surface of the first plastic packaging layer exposed to the back of the first chip and the surface of the first sub-wiring layer away from the first chip.

5. The method for preparing a semiconductor package structure according to claim 4, wherein: The first sub-wiring layer includes a first sub-isolating layer and a first sub-metal layer located in the first sub-isolating layer, and the first sub-wiring layer is electrically connected to the through-hole connection structure, comprising: the first sub-metal layer is electrically connected to the through-hole connection structure; The process of forming the first sub-wiring layer includes: forming a first sub-isolating layer that fills the groove; forming a sub-via in the first sub-isolating layer to expose the corresponding via connection structure; and forming the first sub-metal layer in the sub-via.

6. The method for preparing a semiconductor package structure according to claim 5, wherein: The thermal expansion coefficient of the first sub-isolating layer is smaller than the thermal expansion coefficient of the first plastic packaging layer. The material of the first sub-isolating layer is a photosensitive resin. The sub-through hole is formed in the first sub-isolating layer through an exposure process and a development process.

7. The method for preparing a semiconductor package structure according to claim 6, wherein: The second sub-wiring layer includes a second sub-isolating layer and a second sub-metal layer located in the second sub-isolating layer, and the second sub-wiring layer is electrically connected to the first sub-wiring layer and the metal column, comprising: the second sub-metal layer is electrically connected to the first sub-metal layer and the metal column; The process of forming the second sub-wiring layer includes: forming a second sub-isolation layer on the surface of the first plastic packaging layer that exposes the back side of the first chip and the surface of the first sub-isolation layer away from the first chip; forming corresponding first sub-openings and second sub-openings in the second sub-isolation layer that expose the first sub-metal layer and the metal column; and forming the second sub-metal layer in the first sub-opening and the second sub-opening.

8. The method for preparing a semiconductor package structure according to claim 1, wherein: The preparation method further includes: forming a second plastic sealing layer covering the second chip; The process of providing an initial package structure includes: Providing a carrier plate having raised metal pillars; Providing a first chip, and mounting the back surface of the first chip on the carrier; forming a first plastic encapsulation layer on the carrier board to cover the first chip and the metal pillar, wherein the first plastic encapsulation layer exposes an end surface of the metal pillar away from the carrier board and an active surface of the first chip; forming a first redistribution layer on a surface of the first plastic encapsulation layer away from the carrier, wherein the first redistribution layer is electrically connected to the connection pad and the metal column; Providing a second chip, and mounting the second chip on a surface of the first redistribution layer away from the carrier board, wherein the second chip is electrically connected to the first redistribution layer; Remove the carrier board.

9. A semiconductor packaging structure, characterized in that: include: A first chip includes an active surface and a back surface opposite to each other, the active surface having a connection pad, a through-hole connection structure in the first chip, and the back surface exposing the through-hole connection structure; a first plastic encapsulation layer covering the metal pillar and the first chip, the first plastic encapsulation layer comprising a first surface and a second surface opposite to each other, the first surface of the first plastic encapsulation layer exposing the active surface of the first chip and one end surface of the metal pillar, and the second surface of the first plastic encapsulation layer exposing the other end surface of the metal pillar; a first redistribution layer, located on a first surface of the first plastic packaging layer, the first redistribution layer being electrically connected to the connection pad and the metal column; a second chip mounted on a surface of the first redistribution layer away from the first plastic packaging layer, the second chip being electrically connected to the first redistribution layer; a groove penetrating a portion of the second surface of the first plastic packaging layer and exposing the through-hole connection structure on the back side of the first chip; a first sub-wiring layer located in the groove, the first sub-wiring layer comprising a first sub-isolating layer and a first sub-metal layer located in the first sub-isolating layer, the first sub-metal layer being electrically connected to the through-hole connection structure, the thermal expansion coefficient of the first sub-isolating layer being smaller than the thermal expansion coefficient of the first plastic encapsulation layer; a second sub-wiring layer, located on the second surface of the first plastic packaging layer and on the surface of the first sub-wiring layer away from the first chip, the second sub-wiring layer being electrically connected to the first sub-wiring layer; The external soldering bump is located on a surface of the second redistribution layer away from the first chip and is electrically connected to the second redistribution layer.

10. The semiconductor package structure according to claim 9, wherein: The material of the first sub-isolating layer is a photosensitive resin, and the material of the first plastic sealing layer is a plastic sealing resin.

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