Device with integrated deep trench isolation structure and preparation method thereof

Abstract

The present application relates to the field of semiconductor technology, and in particular to a device with an integrated deep trench isolation structure and a method for fabricating the same. The fabrication method may include: providing a semiconductor structure comprising a substrate, a gate material layer stacked on the substrate surface, and a mask layer stacked on the gate material layer, wherein the substrate has functional elements of the semiconductor device formed therein; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates the mask layer, the gate material layer, and extends into the substrate; filling the deep trench to form a deep trench isolation structure, wherein the deep trench isolation structure includes a filling structure, wherein the filling structure is no higher than the substrate surface and the material of the filling structure is a conductive non-metallic material; patterned etching of the gate material layer to form a gate structure; and removing the mask layer. The present application can integrate the fabrication process of the deep trench isolation structure into the standard process for fabricating gate structures of devices such as BCDs, thereby simplifying the integrated process of deep trench isolation and reducing fabrication costs.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a device with an integrated deep trench isolation structure and a method for preparing the same. Background Art

[0002] Deep trench isolation (DTI) is a key three-dimensional isolation structure in semiconductor devices. Its core function is to achieve electrical isolation between devices. It is particularly suitable for device structures with high voltage, high density, and strong anti-interference requirements. The existing DTI integration process mainly involves the preparation of shallow trench isolation (STI) before and after, resulting in a large number of preparation steps, increasing process complexity and manufacturing costs. Summary of the Invention

[0003] To solve the above technical problems, the present application discloses, on one hand, a method for preparing a device with an integrated deep trench isolation structure, which comprises:

[0004] A semiconductor structure is provided, comprising a substrate, a gate material layer stacked on a surface of the substrate, and a mask layer stacked on the gate material layer, wherein functional elements of a semiconductor device are formed in the substrate;

[0005] forming a deep trench in the semiconductor structure, wherein the deep trench penetrates the mask layer, the gate material layer and extends into the substrate;

[0006] Filling the deep trench to form a deep trench isolation structure, wherein the deep trench isolation structure includes a filling structure, and the filling structure is not higher than the surface of the substrate;

[0007] pattern-etching the gate material layer to form a gate structure;

[0008] The mask layer is removed.

[0009] In a possible implementation manner, after removing the mask layer, the preparation method further includes:

[0010] forming an isolation layer stacked on the surface of the substrate and the surface of the deep trench isolation structure and covering the gate structure;

[0011] An interlayer dielectric layer is formed on the isolation layer, and a metal interconnection layer is formed based on the interlayer dielectric layer.

[0012] In a possible implementation manner, forming a metal interconnection layer based on the interlayer dielectric layer includes:

[0013] forming a plurality of contact holes in the interlayer dielectric layer, penetrating the interlayer dielectric layer and the isolation layer, wherein the plurality of contact holes extend to the deep trench isolation structure and the gate structure respectively;

[0014] Filling the plurality of contact holes with a conductive material to form a plurality of contact plug structures;

[0015] A first metal layer is formed above the interlayer dielectric layer and contacts the contact plug structures. The plurality of contact plug structures electrically connect the deep trench isolation structure and the first metal layer, and electrically connect the gate structure and the first metal layer.

[0016] In a possible implementation manner, a shallow trench isolation structure is formed in the substrate, and the deep trench is located at the shallow trench isolation structure and vertically penetrates the shallow trench isolation structure.

[0017] In a possible implementation manner, the substrate comprises a doped buried layer located below the shallow trench isolation structure, the bottom of the deep trench is lower than the doped buried layer, and the deep trench and the doped buried layer are used to isolate adjacent device modules.

[0018] In a possible implementation, forming a deep trench in the semiconductor structure includes:

[0019] forming a first shielding layer stacked on the gate material layer;

[0020] performing patterning on the first shielding layer to expose the mask layer region corresponding to the deep trench;

[0021] The exposed mask layer region, the exposed gate material layer region and the exposed substrate region are etched to form the deep trench.

[0022] In a possible implementation manner, filling the deep trench to form a deep trench isolation structure includes:

[0023] forming an isolation oxide layer covering the deep trench wall and stacked on the mask layer;

[0024] etching back the isolation oxide layer to expose the bottom of the deep trench;

[0025] forming a doped region at the bottom of the deep trench;

[0026] A conductive non-metallic material is deposited to obtain a filling structure filling the deep trench, thereby forming the deep trench isolation structure.

[0027] In a possible implementation manner, depositing a conductive non-metallic material to obtain a filling structure filling the deep trench, and forming the deep trench isolation structure includes:

[0028] Depositing a conductive non-metallic material to form a filling material layer filling the deep trench and stacked on the isolation oxide layer;

[0029] removing the filling material layer region and the isolation oxide layer region on the mask layer;

[0030] The filling material layer region and the isolation oxide layer region in the deep trench are etched back until the remaining filling material layer and the remaining isolation oxide layer are no higher than the surface of the substrate, thereby forming the deep trench isolation structure including the filling structure.

[0031] In a possible implementation manner, the conductive non-metallic material is a gate material.

[0032] In a possible implementation manner, patterning and etching the gate material layer to form a gate structure includes:

[0033] forming a second shielding layer, wherein the second shielding layer shields the surface of the deep trench isolation structure and the mask layer region corresponding to the gate structure;

[0034] Etching the mask layer to remove the mask layer area not masked by the second shielding layer;

[0035] The gate material layer region exposed on the surface of the substrate is etched, and the second shielding layer is removed to form the gate structure.

[0036] In another aspect, the present application further discloses a device with an integrated deep trench isolation structure, comprising:

[0037] a substrate having functional elements of a semiconductor device formed thereon;

[0038] a deep trench in the substrate;

[0039] A deep trench isolation structure, filled in the deep trench, including a filling structure, wherein the filling structure is no higher than the surface of the substrate and the material of the filling structure is a conductive non-metallic material;

[0040] The gate structure is located on the surface of the substrate.

[0041] In another aspect, the present application further discloses an integrated circuit, which includes the device with the above-mentioned integrated deep trench isolation structure.

[0042] In another aspect, the present application further discloses an electronic device, which includes the device with the integrated deep trench isolation structure.

[0043] Based on the above technical solution, this application has the following beneficial effects:

[0044] The technical solution of the present application forms a gate material layer and a mask layer stacked on the gate material layer on a substrate, then performs deep trench etching and conductive non-metallic material filling, and then patterns the gate material layer to form a gate structure, thereby using the mask layer as a barrier layer for deep trench etching and gate structure preparation. This not only integrates the preparation process of the deep trench isolation structure into the standard process for preparing the gate structure of devices such as BCD, but also eliminates the need to introduce additional masking steps required for the preparation of the deep trench isolation structure, thereby simplifying the integration process of deep trench isolation and reducing preparation costs. Furthermore, by integrating the deep trench isolation structure into the front-end-of-line (FEOL) process, the deep trench isolation structure can be prepared using the existing etching and material filling processes of the front-end process without having to change the machine or introduce additional processes. At the same time, the deep trench isolation structure is prepared based on the filling of a conductive non-metallic material, which has a thermal expansion coefficient similar to that of the substrate, reducing the risk of thermal expansion deformation and device damage caused by the heating process. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 A schematic flow chart of a method for fabricating a device with an integrated deep trench isolation structure provided in an embodiment of the present application;

[0047] Figure 2-15 A schematic cross-sectional view of a device during a preparation process provided in an embodiment of the present application;

[0048] The following is a supplementary description of the accompanying drawings:

[0049] 10-semiconductor structure, 100-substrate, 100a-substrate layer, 100b-epitaxial layer, 101-gate material layer, 102-mask layer, 103-deep trench, 104-deep trench isolation structure, 105-gate structure, 106-isolation layer, 107-shallow trench isolation structure, 108-doped buried layer, 109-first shielding layer, 110-isolation oxide layer, 111-doped region, 112-filling material layer, 113-second shielding layer, 114-pad oxide layer, 115-filling structure, 201-interlayer dielectric layer, 202-contact hole, 203-contact plug structure, 204-first metal layer. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0052] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0053] The term "layer" as used in this application refers to a portion of a material that includes an area having a certain thickness. A layer can extend over the entire underlying or superstructure, or can extend over a localized area of ​​the underlying or superstructure. In addition, a layer can be an area of ​​a homogeneous or heterogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a shaped surface. A layer can include multiple layers. For example, the substrate 100 can include multiple sublayers, etc., and can be made of the same or different materials.

[0054] It should be understood that the definitions of “consistent” and “vertical” used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0055] It should be understood that the “surface” used in this application, such as the “first surface”, the “second surface”, etc., refers to the XY plane of the base 100 or the substrate structure, etc., corresponding to the XY plane of the semiconductor structure 10, the “in-plane direction”, the “lateral direction” refers to the direction parallel to the XY plane, the “thickness direction”, the “trench depth direction” or the “longitudinal direction” refers to the Z direction relative to the XY plane.

[0056] The following combination Figure 1-15 The device manufacturing method of the integrated deep trench isolation structure 104 provided in the embodiment of the present application is introduced. Figure 1 1 is a flow chart of a method for preparing a device with an integrated deep trench isolation structure 104. This specification provides method operation steps such as the embodiments or flow charts, but more or fewer operation steps may be included based on conventional or non-creative work. The order of steps listed in the embodiments is only one way of executing the steps among many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order shown in the embodiments or the drawings or in parallel. The preparation method may include S11-S15:

[0057] S11: providing a semiconductor structure 10.

[0058] Specifically, the semiconductor structure 10 includes a substrate 100, a gate material layer 101 stacked on the surface of the substrate 100, and a mask layer 102 stacked on the gate material layer 101. Functional elements of the semiconductor device are formed in the substrate 100, and one or more semiconductor devices can be formed in the semiconductor structure 10.

[0059] In a possible embodiment, the substrate 100 is a semiconductor substrate capable of performing semiconductor device processing. Optionally, the constituent material of the substrate 100 may be at least one of the following: silicon, a material containing silicon (such as a III-V compound semiconductor material of gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0060] In a possible embodiment, the substrate 100 can be a continuous structure, such as a wafer substrate, or can include a substrate layer 100a and an epitaxial layer 100b. Optionally, the epitaxial layer 100b can be formed by an epitaxial growth process. It can be an epitaxial layer 100b of the same nature as the substrate layer 100a, such as being able to continue growing along the lattice direction of the substrate layer 100a to form the epitaxial layer 100b, or it can be a heteroepitaxial layer 100b. The specific process conditions such as the growth temperature can be the same as those of the existing process, or can be adaptively adjusted. Optionally, the epitaxial layer 100b can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. For example, the material of the epitaxial layer 100b may include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), etc., or may be other materials that can be epitaxially grown or deposited on the substrate layer 100a and can be processed in the device region. Figure 2 , the functional elements of the semiconductor device in the substrate 100 are located in the epitaxial layer 100 b.

[0061] Specifically, the functional elements (not shown) in substrate 100 can be prepared and arranged based on the requirements of the semiconductor device. For example, they can be functional elements in the active region of a power transistor device (such as an SGT MOSFET (Shielded Gate Trench MOSFET), such as a shielded gate trench structure, or they can be MOS transistor units of a BCD (Bipolar CMOS DMOS) device. It is understood that the semiconductor device can also be an RF (Radio Frequency) device, etc.

[0062] Specifically, the gate material layer 101 is used to form a continuous film layer of the gate structure 105 and is formed by depositing a gate material. The gate material may include, but is not limited to, polysilicon. Optionally, the deposition process may be implemented using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPECVD), sub-atmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes.

[0063] Specifically, refer to Figure 2 The mask layer 102 at least covers the active area (AA) of the semiconductor device. In some embodiments, the mask layer 102 includes a hard mask layer, which serves as a pattern transfer layer during the subsequent preparation of the gate structure 105, for pattern transfer and improving the accuracy of pattern etching. It can be formed using a deposition process. Optionally, the material of the hard mask layer can include at least one of silicon nitride, titanium nitride, silicon oxynitride, silicon dioxide, etc., or can also be other materials that can achieve pattern transfer. In other embodiments, the mask layer 102 can also include a pad oxide layer 114 (not shown). The pad oxide layer 114 is located between the hard mask layer and the gate material layer 101 and is used to isolate and protect the surface of the gate material layer 101 to avoid surface contamination and reduce the stress of the hard mask layer. The pad oxide can be formed on the gate material layer 101 by thermal oxidation or deposition process. Optionally, the material of the pad oxide layer 114 can include but is not limited to silicon dioxide.

[0064] In a specific embodiment, the hard mask layer of the mask layer 102 includes a first sublayer stacked on the gate material layer 101 and a second sublayer stacked on the first sublayer. The materials of the first sublayer and the second sublayer can be the same or different. The deposition density of the second sublayer is higher than the deposition density of the first sublayer, which is beneficial to improving the density of the surface of the mask layer 102, thereby improving the surface flatness and reducing surface defects, thereby optimizing the preparation process of the deep trench isolation structure 104 and the gate structure 105, and improving the device effect. Preferably, the thickness of the second sublayer is less than the thickness of the first sublayer. Exemplarily, the thickness of the first sublayer is 2500-2800A, preferably 2700A; the thickness of the second sublayer is 300-350A, preferably 320A. The material of the hard mask layer can be silicon oxynitride.

[0065] In some embodiments, the thickness from the top surface of the substrate layer 100 a to the top surface of the mask layer 102 is 8-12 μm.

[0066] S12 : forming a deep trench 103 in the semiconductor structure 10 .

[0067] Specifically, deep trench 103 penetrates mask layer 102, gate material layer 101 and extends into substrate 100. Deep trench 103 is used to isolate device modules of a device with integrated deep trench isolation structure, which may include partial functional modules in a semiconductor device or a complete semiconductor device.

[0068] Specifically, refer to Figure 3 The deep trench 103 may be formed based on a patterned etching process. In a possible embodiment, S12: forming the deep trench 103 in the semiconductor structure 10 may include S121-S123:

[0069] S121: forming a first shielding layer 109 stacked on the gate material layer 101;

[0070] S122: performing patterning on the first shielding layer 109 to expose the mask layer 102 region corresponding to the deep trench 103;

[0071] S123 : etching the exposed mask layer 102 region, the exposed gate material layer region, and the exposed substrate 100 region to form a deep trench 103 .

[0072] Specifically, a photoresist may be coated on the mask layer 102 to cover the first shielding layer 109 of the mask layer 102. The first shielding layer 109 is patterned and exposed to expose the region of the mask layer 102 where deep trench etching is to be performed using the patterned first shielding layer 109. The mask layer 102 is etched using the first shielding layer 109 as an etching barrier to form an etching window. The gate material layer 101 and the underlying substrate structure exposed by the etching window are then etched to form the deep trench 103. The deep trench etching may be performed using a wet etching process, such as using phosphoric acid as an etchant for wet etching, or a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching using a mixture of C4F8 and O2.

[0073] In some embodiments, a shallow trench isolation structure 107 is formed in the substrate 100 , and the deep trench 103 is located at the shallow trench isolation structure 107 and vertically penetrates the shallow trench isolation structure 107 .

[0074] Specifically, the position of the deep trench 103 is located at the shallow trench isolation structure 107. Preferably, referring to Figure 3 The shallow trench isolation structure 107 is wider than the deep trench 103. The deep trench 103 vertically penetrates the shallow trench isolation structure 107 and the epitaxial layer 100b, extending into the substrate 100 layer, thereby achieving effective isolation. In this way, the shallow trench isolation structure 107 in the standard device is combined with conventional isolation, while the deep trench isolation structure 104 is further integrated in locations requiring high voltage resistance or high electrical isolation. This facilitates the positioning of the deep trench 103 and significantly improves device performance.

[0075] In some embodiments, reference Figure 2 The substrate 100 has a doped buried layer 108 located below the shallow trench isolation structure 107. The bottom of the deep trench 103 is lower than the doped buried layer 108. The deep trench 103 and the doped buried layer 108 are used to isolate adjacent device modules, thereby avoiding crosstalk problems between adjacent functional modules or adjacent semiconductor devices.

[0076] In a specific embodiment, referring to Figure 12 , the deep trench isolation structure 104 abuts against the doped buried layer 108 .

[0077] Specifically, based on device requirements, doped buried layer 108 can be an NBL (N-type buried layer) or a PBL (P-type buried layer) to reduce N-region resistance and provide vertical isolation, or to reduce P-region resistance and optimize substrate bias. Doped buried layer 108 is located between the substrate and epitaxial layer 100b and can be formed through ion implantation and high-temperature annealing.

[0078] S13 : filling the deep trench 103 to form a deep trench isolation structure 104 .

[0079] Specifically, the deep trench isolation structure includes a filling structure 115, which is no higher than the surface of the substrate. The material of the filling structure 115 is a conductive non-metallic material, thereby avoiding leakage and being beneficial to the flattening of the device surface, as well as reducing the stress difference with the substrate, avoiding the risk of cracking and deformation of the deep trench isolation structure.

[0080] Specifically, the first shielding layer 109 is removed to expose the mask layer 102, and an isolation material layer is formed on the walls of the deep trench 103 before being filled with a gate material, thereby obtaining the deep trench isolation structure 104. Preferably, the isolation material layer may be an isolation oxide layer 110. The isolation oxide layer 110 isolates the gate material from the substrate material, preventing diffusion of the gate material caused by high-temperature processes. Furthermore, filling the deep trench 103 with the gate material allows the previous deposition process of the gate material layer 101 to be integrated, eliminating the need to switch tools and significantly reducing process complexity.

[0081] In a possible implementation, reference Figure 4-8 S13: Filling the deep trench 103 to form the deep trench isolation structure 104 may include S131-S134:

[0082] S131: forming an isolation oxide layer 110 covering the wall of the deep trench 103 and stacked on the mask layer 102;

[0083] S132: etching back the isolation oxide layer 110 to expose the bottom of the deep trench 103;

[0084] S133: forming a doped region 111 at the bottom of the deep trench 103;

[0085] S134 : depositing a conductive non-metallic material to obtain a filling structure 115 filling the deep trench 103 , thereby forming a deep trench isolation structure 104 .

[0086] Specifically, the isolation oxide layer 110 can be formed based on a thermal oxidation process or a deposition process. Figure 4, an oxide material is deposited through a deposition process to form an isolation oxide layer 110 covering the wall of the deep trench 103 and stacked on the mask layer 102, and then the isolation oxide layer 110 is etched back to remove at least part of the isolation oxide layer area at the bottom of the deep trench 103, and retain the isolation oxide layer area on the sidewall of the deep trench 103, and then ion implantation is performed on the bottom of the deep trench 103 to form a doped region 111. The etch-back process here can be achieved by wet etching or dry etching. The doped region can be used as a grounding electrode, thereby improving the isolation effect of the deep trench isolation structure 104, and the ion implantation process of the bottom doping after the isolation oxide layer 110 is formed can effectively protect the base structure of the deep trench wall, and facilitate the subsequent filling of the conductive non-metallic material and the sufficient contact with the doped region 111. In some embodiments, the thickness of the isolation oxide layer 110 can be 500-1200A.

[0087] In some embodiments, the doped region may be prepared using a rapid thermal annealing (RTA) process, which allows for diffusion of the doped region through instantaneous high-temperature treatment (e.g., 1000-1100°C for a few seconds to tens of seconds) to improve device performance.

[0088] In a possible implementation, reference Figure 5-8 , S134: depositing a conductive non-metallic material to obtain a filling structure 115 filling the deep trench 103. Forming the deep trench isolation structure 104 may include: depositing a conductive non-metallic material to form a filling material layer 112 filling the deep trench 103 and stacked on the isolation oxide layer 110; removing the filling material layer area and the isolation oxide layer area on the mask layer 102; etching back the filling material layer area and the isolation oxide layer area in the deep trench 103 until the remaining filling material layer 112 and the remaining isolation oxide layer 110 are no higher than the surface of the substrate 100, thereby forming a deep trench isolation structure 104 including the filling structure 115.

[0089] Specifically, refer to Figure 5-6 The filling material layer 112 may be subjected to a chemical mechanical polishing (CMP) process to remove the conductive non-metallic material covering the isolation oxide layer 110. Subsequently, the isolation oxide layer 110 may be subjected to a CMP process using the mask layer 102 as a stop layer to remove the filling material layer region and the isolation oxide layer region stacked on the mask layer 102. Figure 7-8The gate material and isolation oxide layer in the deep trench 103 are then etched back using wet or dry etching. The remaining filling material layer 112 after etching back forms a filling structure 115. The filling structure 115 is flush with or lower than the surface of the substrate 100. Specifically, the gate material can be a conductive non-metallic material, including but not limited to polysilicon. In some embodiments, the thickness of the filling material layer 112 stacked on the isolation oxide layer 110 is 0.8-1.3 μm.

[0090] refer to Figure 8 The deep trench isolation structure 104 may include a doped region 111 at the bottom of the deep trench 103, an isolation oxide layer 110 at the sidewall of the deep trench 103, and a filling structure 115 filling the deep trench 103, thereby forming a structure that can be grounded to improve the device isolation effect and voltage resistance performance.

[0091] S14 : pattern-etching the gate material layer 101 to form a gate structure 105 .

[0092] Specifically, after forming the deep trench isolation structure 104 , the gate material layer 101 is pattern-etched using the mask layer 102 as a pattern transfer layer, thereby obtaining the gate structure 105 .

[0093] In a possible implementation, reference Figure 9-12 S14: patterning and etching the gate material layer 101 to form the gate structure 105 may include S141-S143:

[0094] S141: forming a second shielding layer 113 , where the second shielding layer 113 shields the surface of the deep trench isolation structure 104 and the mask layer 102 region corresponding to the gate structure 105 ;

[0095] S142: etching the mask layer 102 to remove the area of ​​the mask layer 102 not masked by the second shielding layer 113;

[0096] S143 : etching the gate material layer region exposed on the surface of the substrate 100 and removing the second shielding layer 113 to form the gate structure 105 .

[0097] Specifically, refer to Figure 9 , a photoresist may be coated on the mask layer 102 to shield the mask layer 102 and the deep trench isolation structure 104, and then patterned exposure processing may be performed on the mask layer 102, referring to Figure 10 , to expose the mask layer 102 corresponding to the gate material layer area to be removed, thereby obtaining a second shielding layer 113 that shields the surface of the deep trench isolation structure 104 and the mask layer 102 area corresponding to the gate structure 105. Figure 11, the exposed mask layer 102 is etched to form an etching window, and then the gate material layer region exposed by the etching window is patterned and etched, and then the second shielding layer 113 is removed, and the remaining gate material layer region forms a gate structure 105, as shown Figure 12 In this way, the deep trench isolation structure 104 and the gate structure 105 are fabricated through the same mask layer 102, simplifying the fabrication process of integrating the deep trench isolation structure 104 into the semiconductor device.

[0098] S15: removing the mask layer 102.

[0099] Specifically, after the gate structure 105 is prepared, the mask layer 102 is removed to enter the back end of line (BEOL) process of the semiconductor device.

[0100] In summary, this embodiment forms a gate material layer 101 and a mask layer 102 stacked on the gate material layer 101 on a substrate 100, then performs deep trench etching and fills with a conductive non-metallic material. The gate material layer 101 is then patterned and etched to form a gate structure 105. The mask layer 102 serves as a barrier layer for the deep trench etching and the fabrication of the gate structure 105. This not only integrates the fabrication process of the deep trench isolation structure 104 into the standard process for fabricating the gate structure 105 of devices such as BCDs, but also eliminates the need for additional masking steps required for fabricating the deep trench isolation structure 104, simplifying the integrated process for deep trench 103 isolation and reducing fabrication costs. Furthermore, by integrating the deep trench isolation structure 104 into the front-end-of-line (FEOL) process, the existing etching and material filling processes of the FEOL process can be utilized to fabricate the deep trench isolation structure 104, eliminating the need for tool replacement or the introduction of additional processes. At the same time, the deep trench isolation structure 104 is filled and prepared based on a conductive non-metallic material, which has a thermal expansion coefficient similar to that of the substrate 100 , thereby reducing the risk of thermal expansion deformation and device damage caused by the heating process.

[0101] Based on some or all of the above embodiments, in a possible embodiment, after removing the mask layer 102 in S15, refer to Figure 13-15 , the preparation method further includes S16-S17:

[0102] S16: forming an isolation layer 106 stacked on the surface of the substrate 100 and the surface of the deep trench isolation structure 104 and covering the gate structure 105;

[0103] S17 : forming an interlayer dielectric layer 201 on the isolation layer 106 , and forming a metal interconnection layer based on the interlayer dielectric layer 201 .

[0104] Specifically, the isolation layer 106 can be formed based on a deposition process. The isolation layer 106 serves as a dielectric layer for electrical isolation. Optionally, the material of the dielectric layer may include one or more of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, etc., or other materials that can be used as dielectric layers. After the isolation layer 106 is formed, an interlayer dielectric layer 201 (ILD) is formed on the isolation layer 106. Optionally, the material of the interlayer dielectric layer 201 may include one or more of silicon dioxide, fluorinated silicate glass (FSG), borophosphosilicate glass (BPSG), carbon-doped oxide (such as SiCOH), etc., or other materials that can be used as interlayer dielectric layer 201.

[0105] In a possible implementation, forming a metal interconnection layer based on the interlayer dielectric layer 201 in S17 may include S171-S173:

[0106] S171: forming a plurality of contact holes 202 in the interlayer dielectric layer 201 penetrating the interlayer dielectric layer 201 and the isolation layer 106;

[0107] S172: Filling the plurality of contact holes 202 with a conductive material to form a plurality of contact plug structures 203;

[0108] S173 : forming a first metal layer 204 on the interlayer dielectric layer 201 and in contact with the contact plug structure 203 .

[0109] Specifically, refer to Figure 14 , a via pattern can be defined by photolithography, and then the interlayer dielectric layer 201 and the isolation layer 106 are etched to form contact holes 202. Multiple contact holes 202 extend to the deep trench isolation structure 104 and the gate structure 105 respectively to expose the areas where the deep trench isolation structure 104 and the gate structure 105 need to be electrically connected. Then, a conductive material is filled to form a contact plug structure 203 as an interconnection structure. Then, refer to Figure 15, forming a first metal layer 204 to electrically connect to the contact plug structure 203. Specifically, the multiple contact plug structures 203 electrically connect the deep trench isolation structure 104 and the first metal layer 204, and electrically connect the gate structure 105 and the first metal layer 204. It can be understood that after preparing the first metal layer 204, subsequent metal inter-dielectric layers (IMD) and second metal layers can also be prepared to complete the preparation of the metal interconnect layer. This embodiment integrates the preparation of the deep trench isolation structure 104 into the front-end process, so that it can be adapted to various back-end process technologies, such as being able to adapt to metal layer preparation processes such as traditional sputtering and stacking etching processes (such as Al processes) and Damascus processes (such as copper processes).

[0110] In summary, the technical solution of the present application integrates the DTI preparation process into the mask layer deposition process of the gate material layer, so as to form DTI in the front-end process of the device, avoiding problems such as high IMD / ILD thickness caused by the integration of DTI preparation in the back-end process, thereby avoiding affecting processes such as CT-ET (Contact Etch, contact hole etching) and through-hole (Via) etching. In addition, the mask layer is used as a hard mask layer for both DTI trench etching and gate structure preparation, and DTI is formed by filling with conductive non-metallic materials, thereby integrating DTI preparation into the standard process of the front-end process of the device, reducing the difficulty of chemical mechanical polishing of DTI, ensuring improved device effects while simplifying the process flow. In addition, the DTI structure introduces doped regions formed by ion implantation to improve the isolation effect.

[0111] The present application also provides a device with an integrated deep trench isolation structure 104, which is prepared based on the above-mentioned preparation method. Figure 12 The device integrating the deep trench isolation structure 104 specifically includes: a substrate 100, a deep trench 103, a deep trench isolation structure 104 and a gate structure 105; the substrate 100 forms a functional element of the semiconductor device; the deep trench 103 is located in the substrate 100; the deep trench isolation structure 104 is filled in the deep trench 103, including a filling structure 115, the filling structure 115 is not higher than the surface of the substrate 100, and the material of the filling structure 115 is a conductive non-metallic material; the gate structure 105 is located on the surface of the substrate 100.

[0112] In a possible implementation, reference Figure 13 The device further includes an isolation layer 106 stacked on the surface of the substrate 100 and the surface of the deep trench isolation structure 104 and covering the gate structure 105; and a metal interconnection layer stacked on the isolation layer 106.

[0113] In some embodiments, reference Figure 15The interlayer dielectric layer 201 has multiple contact holes 202 that penetrate the interlayer dielectric layer 201 and the isolation layer 106. The metal interconnection layer includes multiple contact plug structures 203 and a first metal layer 204. The multiple contact plug structures 203 electrically connect the deep trench isolation structure 104 and the first metal layer 204, and electrically connect the gate structure 105 and the first metal layer 204.

[0114] In some embodiments, reference Figure 12-15 A shallow trench isolation structure 107 is formed in the substrate 100 , and the deep trench 103 is located at the shallow trench isolation structure 107 and vertically penetrates the shallow trench isolation structure 107 .

[0115] In some embodiments, reference Figure 12-15 The substrate 100 has a doped buried layer 108 located below the shallow trench isolation structure 107. The bottom of the deep trench 103 is lower than the doped buried layer 108. The deep trench 103 and the doped buried layer 108 are used to isolate adjacent device modules.

[0116] It should be noted that the device embodiment of the integrated deep trench isolation structure of the present application is implemented based on the device manufacturing method embodiment of the integrated deep trench isolation structure, and both are based on the same inventive concept.

[0117] The embodiment of the present application further provides an electronic device, which includes the above-mentioned semiconductor structure 10. Specifically, the electronic device includes the semiconductor structure 10 and an electronic component connected to the semiconductor structure 10.

[0118] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PlayStation Portable (PSP), etc., and can also be any intermediate product including an electronic device made of the above-mentioned semiconductor structure 10.

[0119] It should be noted that the order of the embodiments of the present application described above is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. The above description is of specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0120] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0121] Those skilled in the art will understand that all or part of the steps of implementing the above embodiments may be accomplished by hardware, or by programs instructing related hardware to accomplish the steps. The programs may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0122] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a device with an integrated deep trench isolation structure, characterized in that: include: A semiconductor structure is provided, comprising a substrate, a gate material layer stacked on a surface of the substrate, and a mask layer stacked on the gate material layer, wherein functional elements of a semiconductor device are formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates the mask layer, the gate material layer and extends into the substrate; Filling the deep trench to form a deep trench isolation structure, wherein the deep trench isolation structure includes a filling structure, the filling structure is no higher than the surface of the substrate, and the material of the filling structure is a conductive non-metallic material; pattern-etching the gate material layer to form a gate structure; The mask layer is removed.

2. The preparation method according to claim 1, characterized in that After removing the mask layer, the preparation method further includes: forming an isolation layer stacked on the surface of the substrate and the surface of the deep trench isolation structure and covering the gate structure; An interlayer dielectric layer is formed on the isolation layer, and a metal interconnection layer is formed based on the interlayer dielectric layer.

3. The preparation method according to claim 2, characterized in that The forming of a metal interconnection layer based on the interlayer dielectric layer comprises: forming a plurality of contact holes in the interlayer dielectric layer, penetrating the interlayer dielectric layer and the isolation layer, wherein the plurality of contact holes extend to the deep trench isolation structure and the gate structure respectively; Filling the plurality of contact holes with a conductive material to form a plurality of contact plug structures; A first metal layer is formed above the interlayer dielectric layer and contacts the contact plug structures. The plurality of contact plug structures electrically connect the deep trench isolation structure and the first metal layer, and electrically connect the gate structure and the first metal layer.

4. The preparation method according to claim 1, characterized in that A shallow trench isolation structure is formed in the substrate, and the deep trench is located at the shallow trench isolation structure and vertically penetrates the shallow trench isolation structure.

5. The preparation method according to claim 4, characterized in that The substrate comprises a doped buried layer located below the shallow trench isolation structure, the bottom of the deep trench is lower than the doped buried layer, and the deep trench and the doped buried layer are used to isolate adjacent device modules.

6. The preparation method according to any one of claims 1 to 5, characterized in that The forming of a deep trench in the semiconductor structure includes: forming a first shielding layer stacked on the gate material layer; performing patterning on the first shielding layer to expose the mask layer region corresponding to the deep trench; The exposed mask layer region, the exposed gate material layer region and the exposed substrate region are etched to form the deep trench.

7. The preparation method according to any one of claims 1 to 5, characterized in that Filling the deep trench to form a deep trench isolation structure includes: forming an isolation oxide layer covering the deep trench wall and stacked on the mask layer; etching back the isolation oxide layer to expose the bottom of the deep trench; forming a doped region at the bottom of the deep trench; A conductive non-metallic material is deposited to obtain a filling structure filling the deep trench, thereby forming the deep trench isolation structure.

8. The preparation method according to claim 7, characterized in that Depositing a conductive non-metallic material to obtain a filling structure filling the deep trench, and forming the deep trench isolation structure includes: Depositing a conductive non-metallic material to form a filling material layer filling the deep trench and stacked on the isolation oxide layer; removing the filling material layer region and the isolation oxide layer region on the mask layer; The filling material layer region and the isolation oxide layer region in the deep trench are etched back until the remaining filling material layer and the remaining isolation oxide layer are no higher than the surface of the substrate, thereby forming the deep trench isolation structure including the filling structure.

9. The preparation method according to any one of claims 1 to 5, characterized in that The patterned etching of the gate material layer to form a gate structure includes: forming a second shielding layer, wherein the second shielding layer shields the surface of the deep trench isolation structure and the mask layer region corresponding to the gate structure; Etching the mask layer to remove the mask layer area not masked by the second shielding layer; The gate material layer region exposed on the surface of the substrate is etched, and the second shielding layer is removed to form the gate structure.

10. A device with an integrated deep trench isolation structure, characterized in that: The device with integrated deep trench isolation structure is manufactured by the manufacturing method according to any one of claims 1 to 9, comprising: a substrate having functional elements of a semiconductor device formed thereon; a deep trench in the substrate; A deep trench isolation structure, filled in the deep trench, including a filling structure, wherein the filling structure is no higher than the surface of the substrate and the material of the filling structure is a conductive non-metallic material; The gate structure is located on the surface of the substrate.

Images