Full-bridge topology staggered BUCK driving control method and system

Abstract

The invention discloses a full-bridge topology staggered BUCK drive control method and system, and the method comprises the steps: carrying out the simulation according to the charging time of a capacitor, and combining the conduction requirements of an upper bridge switch tube of half-bridge drive and the drive overlapping condition of the upper bridge switch tube and the lower bridge switch tube, and determining the optimal value of the duty ratio of the lower bridge switch tube of the half-bridge drive and the position of the optimal value of the duty ratio of the lower bridge switch tube of the half-bridge drive; based on a PWM period and an interlaced BUCK phase shift control principle, according to the optimal value of the duty ratio of the lower bridge switch tube, calculating to obtain an optimal range of the duty ratio of an upper bridge switch tube driven by a half bridge; and according to the optimal value and position of the duty ratio of the lower bridge switch tube and the optimal range of the duty ratio of the upper bridge switch tube, adopting a voltage and current double closed loop and given voltage feedforward control method to realize staggered BUCK driving control. According to the invention, the fixed duty ratio of the lower bridge switch tube and the dynamically adjusted duty ratio of the upper bridge switch tube are adopted to realize the control of the interlaced BUCK, so that the direct connection and oscillation problems of the switch tubes are solved, and the reliability of the system is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of power electronic converter control, and specifically relates to a full-bridge topology interleaved BUCK drive control method and system. Background Art

[0002] In the traditional full-bridge interleaved buck topology, a 180-degree phase shift of the multi-phase drive signals can cause overlapping conduction of the switches, leading to a straight-through of the bridge arms and causing voltage oscillation or current reversal. Furthermore, the half-bridge drive's lower bridge conduction timing lacks coordinated control with the upper bridge's duty cycle, limiting the system's dynamic performance. Summary of the Invention

[0003] In response to the problems mentioned in the background technology, the present application provides a full-bridge topology staggered BUCK drive control method and system, which solves the problems of switch tube direct conduction and oscillation through coordinated control of drive timing constraints and duty cycle, thereby improving system reliability.

[0004] This application is implemented through the following technical solutions: A staggered buck drive control method for a full-bridge topology, comprising: Based on the capacitor charging time, combined with the conduction requirements of the upper-bridge switch of the half-bridge driver and the drive overlap between the upper-bridge switch and the lower-bridge switch, the optimal duty cycle value and position of the lower-bridge switch of the half-bridge driver are determined by simulation. Based on the PWM cycle and staggered buck phase-shift control principle, the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive is calculated according to the optimal value of the duty cycle of the lower bridge switch tube; According to the optimal value and position of the duty cycle of the lower bridge switch tube and the optimal range of the duty cycle of the upper bridge switch tube, a voltage-current dual closed loop and a given voltage feedforward control method are adopted to realize the driving control of the staggered buck.

[0005] In some embodiments, the simulation to determine the optimal duty cycle value and position of the lower bridge switch of the half-bridge driver includes: While keeping other parameters the same, starting from the initial value of the low-bridge switch duty cycle, increase the low-bridge switch duty cycle according to a preset step size, and perform simulation tests to obtain the capacitor charging and the high-bridge switch conduction conditions at each duty cycle. Based on the simulation test results, the low-bridge switch duty cycle range that meets the high-bridge switch conduction performance is obtained; At the same time, in order to avoid overlapping of the driving of the upper and lower bridge switch tubes, the minimum duty cycle value in the duty cycle range of the lower bridge switch tube is taken as its optimal value, and the driving of the lower bridge switch tube is set to the last position in each cycle.

[0006] In some implementations, the initial duty cycle value of the lower bridge switch should be greater than the theoretical value of the capacitor charging time.

[0007] In some embodiments, the step of calculating the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube includes: According to the interleaved buck phase-shift control principle, the total duty cycle of the high-side and low-side switches should be less than or equal to 50%. To avoid overlap with adjacent drivers, the maximum duty cycle of the high-side switch is (50% - the optimal duty cycle of the low-side switch). The duty cycle range of the upper bridge switch tube is obtained to be 0~(50%-optimal value of the duty cycle of the lower bridge switch tube).

[0008] In some embodiments, the staggered buck drive control is implemented by using a voltage-current dual closed-loop and given voltage feedforward control method based on the optimal value and position of the lower bridge switch duty cycle and the optimal range of the upper bridge switch duty cycle, including: Perform voltage outer loop control: Compare the voltage feedback value with the voltage reference value to obtain the voltage error, and dynamically adjust the inductor current reference value based on the voltage error; Performing current inner loop control: using the inductor back-end current as the current feedback value, comparing it with the inductor current reference value to obtain a current error, and adjusting the voltage value according to the current error; Drive control: summing the regulated voltage value and the voltage reference value to obtain a control voltage, dividing the control voltage by the bus voltage to obtain the duty cycle of the upper bridge switch tube, and limiting the duty cycle of the upper bridge switch tube according to the optimal range of the upper bridge switch tube duty cycle; generating a corresponding upper bridge switch tube PWM drive signal according to the upper bridge switch tube duty cycle after limiting adjustment, and generating a corresponding lower bridge switch tube PWM drive signal according to the optimal value of the lower bridge switch tube duty cycle to realize drive control of the staggered buck.

[0009] In a second aspect, the present application proposes a full-bridge topology interleaved BUCK drive control system, comprising: The simulation test module simulates and determines the optimal duty cycle and position of the lower bridge switch of the half-bridge drive based on the capacitor charging time, the conduction requirements of the upper bridge switch of the half-bridge drive, and the drive overlap between the upper bridge switch and the lower bridge switch. A calculation module, based on the PWM cycle and staggered buck phase shift control principle, calculates the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube; Furthermore, the drive control module realizes the drive control of the staggered bucks by adopting the voltage-current dual closed loop and given voltage feedforward control method according to the optimal value and position of the duty cycle of the lower bridge switch tube and the optimal range of the duty cycle of the upper bridge switch tube.

[0010] In some embodiments, the drive control module further includes: The voltage outer loop control unit is used to compare the voltage feedback value with the voltage reference value to obtain a voltage error, and dynamically adjust the inductor current reference value according to the voltage error; A current inner loop control unit is configured to use the current at the rear end of the inductor as a current feedback value, compare it with the inductor current reference value to obtain a current error, and adjust the voltage value according to the current error; an adder, configured to sum the regulated voltage value and the voltage reference value to obtain a control voltage; A duty cycle calculation module, configured to obtain a duty cycle of the upper bridge switch by dividing the control voltage by the bus voltage; A limiter, configured to limit and adjust the duty cycle of the upper bridge switch tube according to an optimal range of the duty cycle of the upper bridge switch tube; The PWM module is used to generate a corresponding PWM drive signal for the upper bridge switch tube according to the duty cycle of the upper bridge switch tube after limit adjustment, and to generate a corresponding PWM drive signal for the lower bridge switch tube according to the optimal value of the duty cycle of the lower bridge switch tube, thereby realizing drive control of the staggered buck.

[0011] In some embodiments, the voltage outer loop control unit includes a first comparator and a PI regulator; And / or, the current inner loop control unit includes a second comparator and a P regulator.

[0012] In a third aspect, the present application proposes an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements any one of the above-mentioned embodiments of the staggered BUCK drive control method when executing the computer program.

[0013] In a fourth aspect, the present application proposes a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any one of the above-mentioned embodiments of the staggered BUCK drive control method.

[0014] This application proposes a staggered buck drive control method for a full-bridge topology, which uses a fixed lower-bridge switch duty cycle and a dynamically adjusted upper-bridge switch duty cycle to achieve staggered buck control, solve the switch shoot-through and oscillation problems, and improve system reliability.

[0015] Accordingly, the present application proposes a full-bridge topology interleaved BUCK drive control system, electronic device, and computer-readable storage medium that achieve the same technical effects as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and do not constitute a limitation of the embodiments of the present application. In the drawings: Figure 1 Schematic diagram of traditional full-bridge topology; Figure 2 for Figure 1 The duty cycle timing diagram of a pair of switching tubes (Q1 and Q2) in the structure shown; Figure 3 for Figure 1 The timing diagram of the phase-shift interleaved control of the two groups of switch tubes in the structure shown; Figure 4 for Figure 1 The control timing diagram of the two groups of switch tubes in the structure shown is when the upper tube duty cycle is 45% and the lower tube duty cycle is 10%; Figure 5 This is a flow chart of the staggered BUCK drive control method proposed in an embodiment of the present application; Figure 6 This is the circuit output effect diagram after the BUCK is stabilized; Figure 7 for Figure 6 A partial enlarged view of the effect diagram shown; Figure 8 This is a block diagram of the principle of the staggered BUCK drive control system proposed in an embodiment of the present application; Figure 9 This is a schematic diagram of the drive control module proposed in an embodiment of the present application; Figure 10 A schematic diagram of an electronic device proposed in an embodiment of the present application; Figure 11 A schematic diagram of a computer-readable storage medium proposed in an embodiment of the present application; Reference numerals and corresponding component names: 200 - interleaved BUCK drive control system, 201 - simulation test module, 202 - computing module, 203 - drive control module, 300 - electronic device, 310 - memory, 320 - processor, 311 - computer program A, 400 - computer-readable storage medium, 411 - computer program B. DETAILED DESCRIPTION

[0017] Hereinafter, the terms "include" or "may include" as used in various embodiments of the present application indicate the presence of an invented function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present application, the terms "include," "have," and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be understood as excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing.

[0018] In order to make the objectives, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with examples and drawings. The schematic implementation methods of this application and their descriptions are only used to explain this application and are not intended to limit this application.

[0019] Figure 1 The figure shows a traditional full-bridge interleaved BUCK circuit (step-down converter circuit). The half-bridge drive circuit selected is a bootstrap circuit. The bootstrap circuit is mainly used to solve the problem of insufficient drive voltage of high-side switching devices (such as MOSFET or IGBT). Its core principle is to increase the low-side power supply voltage to the voltage value required for high-side drive through the dynamic charging and discharging process of the capacitor. It can be simply understood that the turning on of the upper-bridge switch tube requires the turning on of the lower-bridge switch tube first to charge the bootstrap capacitor of the upper tube, so that the upper tube has sufficient turning-on capability.

[0020] The principle of interleaved buck phase shift control is to delay the driving of a group of switch tubes by 180 degrees to achieve interleaved buck. Figure 1 The following figure shows a pair of switch tubes (switch tube Q1 and switch tube Q2) as an example to illustrate their conduction timing. Q1 is turned on to store energy for inductor L1 and charge capacitor C. After charging is completed, the body diode on switch tube Q2 realizes freewheeling for inductor L1 while continuing to charge capacitor C. At the end of the cycle, Q2 is turned on to create conditions for Q1 to turn on again, thus achieving BUCK. The specific timing diagram is shown in the figure. Figure 2 As shown; the conduction of another set of switch tubes Q3 and Q4 is delayed by 180 degrees on this basis to achieve staggered buck. The specific timing diagram is as follows Figure 3 However, through research, it was found that when the duty cycle of the upper bridge switch tube is 45% and the duty cycle of the lower bridge switch tube is 10%, the adjacent switch tubes (Q1, Q4 or Q2, Q3) will overlap and control, which will cause Q1, Q4 and Q2, Q3 to be directly turned on, resulting in output voltage oscillation or even short circuit, as shown in Figure 2. Figure 4 shown.

[0021] To address the above issues, an embodiment of the present application proposes an interleaved BUCK drive control method for a full-bridge topology, which solves the problems of switch tube shoot-through and oscillation through coordinated control of drive timing constraints and duty cycle, thereby improving system reliability.

[0022] like Figure 5 As shown, the staggered BUCK drive control method proposed in the embodiment of the present application includes the following steps: Step 110 , determining the optimal duty cycle and position of the lower bridge switch of the half-bridge drive by simulation based on the capacitor charging time, the conduction requirement of the upper bridge switch of the half-bridge drive, and the drive overlap between the upper bridge switch and the lower bridge switch; Step 120 , based on the PWM cycle and the staggered buck phase-shift control principle, calculate the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube; Step 130 : Based on the optimal duty cycle value and position of the lower bridge switch and the optimal duty cycle range of the upper bridge switch, a voltage-current dual closed loop and a given voltage feedforward control method are used to implement driving control of the interleaved bucks.

[0023] Furthermore, in step 110 of the embodiment of the present application, using simulation software, while keeping other parameters consistent, starting from the initial duty cycle value, the duty cycle of the lower bridge switch tube is increased according to a preset step size, and simulation tests are performed to obtain the capacitor charging situation and the conduction situation of the upper bridge switch tube under each duty cycle. Based on the simulation test results, a duty cycle range that can meet the conduction performance of the upper bridge switch tube is obtained. At the same time, in order to avoid overlapping of the drive of the upper and lower bridge switches, the duty cycle of the lower bridge switch tube needs to be fixed. Based on this, the embodiment of the present application obtains the minimum duty cycle value (i.e.) in the duty cycle range as the optimal duty cycle value, and sets the lower tube drive to the last position of each cycle. It is worth noting that the selection of the initial duty cycle value should be determined based on the theoretical value of the capacitor charging time, that is, the conduction time of the lower bridge switch tube corresponding to the selected initial duty cycle should be greater than the theoretical value of the capacitor charging time.

[0024] The embodiments of this application are Figure 1The above simulation test process is illustrated by taking a specific parameter of the hardware shown as an example (referred to as Example 1). In this example, the bootstrap capacitor is selected to be 100nF, and its series resistance is 2 ohms. According to the theoretical value of RC of 5 times the typical capacitor charging time, the theoretical value of the capacitor charging time t = 1μs is obtained. The PWM frequency was controlled to 20 kHz, or a PWM period of 50 μs. The initial duty cycle of the low-bridge switch was set to 5%, corresponding to an on-time of 2.5 μs (greater than the theoretical capacitor charging time), with a step size of 5%. Simulations were conducted to examine the capacitor charging and the conduction of the high-bridge switch under different low-bridge switch duty cycles: 5% (corresponding to an on-time of 2.5 μs), 10% (corresponding to an on-time of 5 μs), and 15% (corresponding to an on-time of 7.5 μs). The test results show that a low-bridge switch duty cycle less than 10% (i.e., an on-time less than 5 μs) results in a low drive voltage, posing the risk of the high-bridge switch failing to conduct. Therefore, the low-bridge switch duty cycle should be greater than or equal to 10%. To avoid overlap in the drive of the high-bridge and low-bridge switches, the low-bridge switch duty cycle was fixed, with the minimum value (10%) selected as the optimal value for the high-bridge switch. The low-bridge switch drive was set to the last 10% of each cycle.

[0025] Furthermore, in step 120 of the embodiment of the present application, according to the staggered BUCK phase-shift control principle described above: the drive of one group of switch tubes is delayed by 180 degrees (half a cycle). Based on this, the total duty cycle of the upper bridge switch tube and the lower bridge switch tube of the half-bridge drive should be less than or equal to 50%. At the same time, in order to avoid overlapping with adjacent drives, the maximum duty cycle of the upper bridge switch tube should be limited to (50%-the optimal value of the duty cycle of the lower bridge switch tube). The embodiment of the present application still uses the above-mentioned Example 1 as an example to exemplify the above-mentioned step 120. Among them, according to the previous step 110, it can be determined that the optimal value of the duty cycle of the lower bridge switch tube is 10%, then the maximum duty cycle of the upper bridge switch tube is 50%-10%=40%, that is, the optimal range of the duty cycle of the upper bridge switch tube is 0~40%, which can ensure that adjacent drives do not overlap.

[0026] Furthermore, in step 130 of the embodiment of the present application, the current and voltage dual closed-loop and given voltage feedforward control method is adopted, and the specific control process is as follows: Voltage outer loop control: The voltage feedback value (i.e., actual output voltage) is compared with the voltage reference value to obtain the voltage error. The voltage error is dynamically adjusted to the inductor current reference value by the PI regulator, and the integral in the PI regulator is limited. Current inner loop control: The current at the inductor's rear end is used as the current feedback value, which is compared with the inductor current reference value to obtain the current error. The current error is adjusted by the P regulator and the output voltage is adjusted. Drive control: The control voltage is obtained by summing the regulated voltage value and the voltage reference value. The control voltage is then divided by the bus voltage to obtain the duty cycle of the upper bridge switch tube. The calculated duty cycle of the upper bridge switch tube is limited and adjusted according to the optimal range of the upper bridge switch tube duty cycle. The limited-adjusted upper bridge switch tube duty cycle is input into the PWM module to generate the corresponding upper bridge switch tube PWM drive signal. The optimal value of the lower bridge switch tube duty cycle determined by simulation is input into the PWM module to generate the corresponding lower bridge switch tube PWM drive signal, ultimately achieving closed-loop control of the staggered buck. Taking Example 1 above as an example, the embodiment of the present application first generates a control voltage through the above-mentioned voltage-current dual closed-loop control. The actual duty cycle of the upper bridge switch tube can be obtained based on the control voltage and the bus voltage. Then, the upper bridge switch tube duty cycle is limited using the optimal range of the upper bridge switch tube duty cycle determined in step 120. A corresponding upper bridge switch tube PWM drive signal is generated based on the limited upper bridge switch tube duty cycle, and a corresponding lower bridge switch tube PWM drive signal is generated based on the optimal value of the lower bridge switch tube duty cycle determined by simulation in step 110. The corresponding upper bridge switch tube (Q1 or Q3) and lower bridge switch tube (Q2 or Q4) are driven and controlled, and the signal timing of the two groups of upper bridge switch tubes and lower bridge switch tubes differs by half a cycle (i.e., 180 degrees).

[0027] In order to verify the performance of the staggered BUCK drive control method proposed in the embodiment of the present application, the embodiment of the present application uses the staggered BUCK drive control method proposed above to perform staggered BUCK control, and the following is obtained: Figure 6 and Figure 7 The output effect diagram of BUCK after stabilization is shown. Figure 6 and Figure 7 It can be seen that the staggered BUCK drive control method proposed in the embodiment of the present application adopts a fixed lower bridge switch duty cycle and a dynamically adjusted upper bridge switch duty cycle to achieve staggered BUCK control, which solves the problem of switch shoot-through and oscillation, reduces DC output ripple, and improves system reliability. The embodiment of the present application also proposes a staggered BUCK drive control system with a full-bridge topology, such as Figure 8 As shown, the staggered BUCK drive control system 200 includes: The simulation test module 201 simulates and determines the optimal duty cycle value and position of the lower bridge switch tube of the half-bridge drive according to the capacitor charging time, the conduction requirement of the upper bridge switch tube of the half-bridge drive, and the drive overlap between the upper bridge switch tube and the lower bridge switch tube.

[0028] The calculation module 202 calculates the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube based on the PWM cycle and the staggered buck phase shift control principle.

[0029] Furthermore, the drive control module 203 implements drive control of the interleaved bucks using a voltage-current dual closed loop and a given voltage feedforward control method according to the optimal duty cycle value and position of the lower bridge switch and the optimal duty cycle range of the upper bridge switch.

[0030] Further, if Figure 9 As shown, the drive control module 203 of the present application also includes: A voltage outer loop control unit, configured to implement voltage outer loop control; optionally, the voltage outer loop control unit may include a first comparator and a PI regulator (proportional-integral regulator), wherein a voltage reference value and a voltage feedback value (i.e., the actual output voltage) are input into the first comparator for comparison, and a voltage error is output; the voltage error is input into the PI regulator to dynamically adjust the inductor current reference value and to limit the integral in the PI; A current inner loop control unit, configured to implement current inner loop control; optionally, the current inner loop control unit may include a second comparator and a P regulator (proportional regulator), wherein a current reference value and a current feedback value (i.e., the inductor back-end current) are input into the second comparator for comparison, and a current error is output; the current error is input into the P regulator for regulation to output a regulated voltage value; an adder, configured to sum the regulated voltage value output by the current inner loop control unit and the voltage reference value to obtain a control voltage; A duty cycle calculation module is used to divide the control voltage by the bus voltage to obtain the duty cycle of the upper bridge switch; A limiter, which limits the duty cycle of the upper bridge switch tube calculated by the duty cycle calculation module according to the optimal range of the duty cycle of the upper bridge switch tube output by the calculation module 202; The PWM module generates a corresponding PWM drive signal for the upper bridge switch tube according to the duty cycle of the upper bridge switch tube after the limiter adjustment output, and generates a corresponding PWM drive signal for the lower bridge switch tube according to the optimal value of the duty cycle of the lower bridge switch tube output by the simulation test module 201, thereby realizing the drive control of the staggered buck.

[0031] The embodiment of the present application also provides an electronic device 300, such as Figure 10 As shown, the electronic device 300 includes: a memory 310, a processor 320, and a computer program A311 stored in the memory 310 and executable on the processor 320. When the processor 320 executes the computer program A311, the following steps are implemented: Based on the capacitor charging time, combined with the conduction requirements of the upper-bridge switch of the half-bridge driver and the drive overlap between the upper-bridge switch and the lower-bridge switch, the optimal duty cycle value and position of the lower-bridge switch of the half-bridge driver are determined by simulation. Based on the PWM cycle and interleaved buck phase-shift control principle, the optimal duty cycle range of the upper bridge switch of the half-bridge drive is calculated according to the optimal duty cycle value of the lower bridge switch; According to the optimal duty cycle value and position of the lower-bridge switch and the optimal duty cycle range of the upper-bridge switch, the voltage-current dual closed-loop and given voltage feedforward control methods are used to realize the drive control of the interleaved buck.

[0032] Optionally, when the processor 320 executes the computer program A311, any implementation method in the corresponding embodiment of the above-mentioned staggered BUCK drive control method can be implemented.

[0033] It should be noted that the electronic device proposed in this embodiment is a device used to implement the above-mentioned staggered buck drive control method. Therefore, based on the above-mentioned staggered buck drive control method proposed in this embodiment, those skilled in the art can understand the specific implementation methods of the electronic device of this embodiment and its various variations. Therefore, how the electronic device specifically implements the above-mentioned staggered buck drive control method will not be described in detail here. As long as the electronic device used by those skilled in the art to implement the above-mentioned staggered buck drive control method falls within the scope of protection to be protected by this application.

[0034] The present application also provides a computer-readable storage medium. Figure 11 As shown, the computer readable storage medium 400 stores a computer program B411. When the computer program B411 is executed by the processor, the following steps are implemented: Based on the capacitor charging time, combined with the conduction requirements of the upper-bridge switch of the half-bridge driver and the drive overlap between the upper-bridge switch and the lower-bridge switch, the optimal duty cycle value and position of the lower-bridge switch of the half-bridge driver are determined by simulation. Based on the PWM cycle and interleaved buck phase-shift control principle, the optimal duty cycle range of the upper bridge switch of the half-bridge drive is calculated according to the optimal duty cycle value of the lower bridge switch; Based on the optimal duty cycle value and position of the lower-side switch and the optimal duty cycle range of the upper-side switch, a voltage-current dual closed-loop and given voltage feedforward control method is used to realize the drive control of the interleaved buck converter. Optionally, when the computer program B411 is executed by a processor, any implementation method in the embodiments corresponding to the above-mentioned staggered BUCK drive control method can be implemented.

[0035] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0036] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0037] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0038] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0039] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0040] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above description is only the specific implementation methods of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A staggered buck drive control method for a full-bridge topology, characterized in that: include: Based on the capacitor charging time, combined with the conduction requirements of the upper-bridge switch of the half-bridge driver and the drive overlap between the upper-bridge switch and the lower-bridge switch, the optimal duty cycle value and position of the lower-bridge switch of the half-bridge driver are determined by simulation. Based on the PWM cycle and staggered buck phase-shift control principle, the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive is calculated according to the optimal value of the duty cycle of the lower bridge switch tube; According to the optimal value and position of the duty cycle of the lower bridge switch tube and the optimal range of the duty cycle of the upper bridge switch tube, a voltage-current dual closed loop and a given voltage feedforward control method are adopted to realize the driving control of the staggered buck.

2. The interleaved buck drive control method of a full-bridge topology according to claim 1, characterized in that: The simulation determines the optimal duty cycle value and position of the lower bridge switch of the half-bridge driver, including: While keeping other parameters the same, starting from the initial value of the low-bridge switch duty cycle, increase the low-bridge switch duty cycle according to a preset step size, and perform simulation tests to obtain the capacitor charging and the high-bridge switch conduction conditions at each duty cycle. Based on the simulation test results, the low-bridge switch duty cycle range that meets the high-bridge switch conduction performance is obtained; At the same time, in order to avoid overlapping of the driving of the upper and lower bridge switch tubes, the minimum duty cycle value in the duty cycle range of the lower bridge switch tube is taken as its optimal value, and the driving of the lower bridge switch tube is set to the last position in each cycle.

3. The staggered buck drive control method of a full-bridge topology according to claim 2, characterized in that: The initial value of the duty cycle of the lower bridge switch should be greater than the theoretical value of the capacitor charging time.

4. The staggered buck drive control method of a full-bridge topology according to claim 1, characterized in that: The step of calculating the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube includes: According to the interleaved buck phase-shift control principle, the total duty cycle of the high-side and low-side switches should be less than or equal to 50%. To avoid overlap with adjacent drivers, the maximum duty cycle of the high-side switch is (50% - the optimal duty cycle of the low-side switch). The duty cycle range of the upper bridge switch tube is obtained to be 0~(50%-optimal value of the duty cycle of the lower bridge switch tube).

5. The interleaved buck drive control method of a full-bridge topology according to any one of claims 1 to 4, characterized in that: The drive control of the interleaved bucks is achieved by adopting a voltage-current dual closed-loop and given voltage feedforward control method based on the optimal value and position of the duty cycle of the lower bridge switch tube and the optimal range of the duty cycle of the upper bridge switch tube, including: Perform voltage outer loop control: Compare the voltage feedback value with the voltage reference value to obtain the voltage error, and dynamically adjust the inductor current reference value based on the voltage error; Performing current inner loop control: using the inductor back-end current as the current feedback value, comparing it with the inductor current reference value to obtain a current error, and adjusting the voltage value according to the current error; Drive control: summing the regulated voltage value and the voltage reference value to obtain a control voltage, dividing the control voltage by the bus voltage to obtain the duty cycle of the upper bridge switch tube, and limiting the duty cycle of the upper bridge switch tube according to the optimal range of the upper bridge switch tube duty cycle; generating a corresponding upper bridge switch tube PWM drive signal according to the upper bridge switch tube duty cycle after limiting adjustment, and generating a corresponding lower bridge switch tube PWM drive signal according to the optimal value of the lower bridge switch tube duty cycle to realize drive control of the staggered buck.

6. A full-bridge topology interleaved BUCK drive control system, characterized in that: include: The simulation test module simulates and determines the optimal duty cycle and position of the lower bridge switch of the half-bridge drive based on the capacitor charging time, the conduction requirements of the upper bridge switch of the half-bridge drive, and the drive overlap between the upper bridge switch and the lower bridge switch. A calculation module, based on the PWM cycle and staggered buck phase shift control principle, calculates the optimal range of the duty cycle of the upper bridge switch tube of the half-bridge drive according to the optimal value of the duty cycle of the lower bridge switch tube; Furthermore, the drive control module realizes the drive control of the staggered bucks by adopting the voltage-current dual closed loop and given voltage feedforward control method according to the optimal value and position of the duty cycle of the lower bridge switch tube and the optimal range of the duty cycle of the upper bridge switch tube.

7. The full-bridge topology interleaved BUCK drive control system according to claim 6, characterized in that: The drive control module further includes: The voltage outer loop control unit is used to compare the voltage feedback value with the voltage reference value to obtain a voltage error, and dynamically adjust the inductor current reference value according to the voltage error; A current inner loop control unit is configured to use the current at the rear end of the inductor as a current feedback value, compare it with the inductor current reference value to obtain a current error, and adjust the voltage value according to the current error; an adder, configured to sum the regulated voltage value and the voltage reference value to obtain a control voltage; A duty cycle calculation module, configured to obtain a duty cycle of the upper bridge switch by dividing the control voltage by the bus voltage; A limiter, configured to limit and adjust the duty cycle of the upper bridge switch tube according to an optimal range of the duty cycle of the upper bridge switch tube; The PWM module is used to generate a corresponding PWM drive signal for the upper bridge switch tube according to the duty cycle of the upper bridge switch tube after limit adjustment, and to generate a corresponding PWM drive signal for the lower bridge switch tube according to the optimal value of the duty cycle of the lower bridge switch tube, thereby realizing drive control of the staggered buck.

8. The interleaved buck drive control system of full-bridge topology according to claim 7, characterized in that: The voltage outer loop control unit includes a first comparator and a PI regulator; And / or, the current inner loop control unit includes a second comparator and a P regulator.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the interleaved BUCK drive control method according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the staggered BUCK drive control method according to any one of claims 1 to 5 is implemented.

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