Delay circuit of pulse sequence, integrated circuit, interaction system, method and equipment

Abstract

The invention discloses a delay circuit of a pulse sequence, an integrated circuit, an interaction system, a method and equipment, and relates to the field of signal processing. The delay circuit comprises an edge detection module used for receiving an initial pulse sequence, generating an enable signal according to a rising edge and a falling edge of a pulse signal in the initial pulse sequence, and inputting a first numerical value to an FIFO cache module based on the enable signal; the cycle counter is used for cyclically outputting a count value; the FIFO cache module is used for receiving the first numerical value from the data writing port and inputting the first numerical value to the numerical value comparison module after the first numerical value is moved to the data reading port; the numerical value comparison module is used for comparing the first numerical value with a real-time counting value of the cycle counter, and generating a trigger signal when the two values are equal; and the pulse generation module is used for generating a pulse signal according to the trigger signal to obtain a delayed pulse sequence. As a result, the delay circuit can complete the overall delay of the pulse sequence.

Description

Technical Field

[0001] The present invention belongs to the field of signal processing, and in particular relates to a pulse sequence delay circuit, integrated circuit, interactive system, method and device. Background Art

[0002] In the prior art, trigger signals are usually delayed to achieve precise control of electronic devices. In signal delay schemes, in order to expand the scope of application of the scheme and extend the delay time, a counter can be selected to delay the pulse signal.

[0003] However, existing signal delay schemes using counters can only delay a single pulse signal when the interval between pulse signals is less than the delay time. For pulse trains containing multiple consecutive pulse signals, the delay often results in pulse signal loss and a decrease in pulse frequency, making it impossible to delay the entire pulse train. Summary of the Invention

[0004] The present application proposes a pulse sequence delay circuit, integrated circuit, interactive system, method and device to achieve overall delay of the pulse sequence.

[0005] To achieve the above objectives, this application proposes the following technical solutions: In a first aspect of the present application, a pulse sequence delay circuit is provided, comprising: an edge detection module, configured to receive an initial pulse sequence and generate an enable signal based on rising and falling edges of a pulse signal in the initial pulse sequence, so as to input a first value into the FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of the loop counter to a second value; and the second value represents an amount of change in the count value of the loop counter within a preset delay time; A cyclic counter is used to cyclically output a count value, and the time it takes for the count value to cycle through one circle is longer than a preset delay time; a FIFO buffer module, configured to receive a first value from a data write port, and input the first value to a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; a numerical comparison module, configured to compare the first numerical value with the real-time count value of the loop counter and generate a trigger signal when the two values ​​are equal; The pulse generating module is used to receive a trigger signal, generate a pulse signal according to the trigger signal, and obtain a delayed pulse sequence.

[0006] Optionally, the FIFO buffer module includes a rising edge FIFO buffer and a falling edge FIFO buffer; The rising edge FIFO buffer is used to receive the first value from the data write port after the edge detection module generates an enable signal according to the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value is moved to the data read port; The falling edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal according to the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port.

[0007] Optionally, after receiving the trigger signal, the pulse generating module further includes: If the trigger signal is obtained by comparing the first value in the rising edge FIFO buffer, the pulse generation module changes the output signal from a low level to a high level to generate a delayed pulse signal; wherein the initial state of the output signal of the pulse generation module is a low level; If the trigger signal is obtained by comparing with the first value in the falling edge FIFO buffer, the pulse generating module changes the output signal from a high level to a low level to generate a delayed pulse signal.

[0008] Optionally, the delay circuit further includes: an adding module connected to the cycle counter, configured to add the real-time count value of the cycle counter to the second value, and input the added value as the first value to the FIFO buffer module when the edge detection module generates an enable signal; a register module, comprising a pipeline register, configured to receive a pulse sequence when a time for data to be moved from a data write port to a data read port in the FIFO buffer module exceeds a preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain a delayed pulse sequence; A reset module is used to reset the edge detection module, FIFO cache module, numerical comparison module, pulse generation module, addition module and register module in the delay circuit after the delay circuit is initialized or the initial pulse sequence input to the edge detection module changes.

[0009] In a second aspect of the present application, an integrated circuit is provided, comprising a delay circuit as described in any one of the first aspects.

[0010] In a third aspect of the present application, an interactive system is provided, comprising a master device and N slave devices, each slave device comprising the delay circuit described in any one of the first aspect or the integrated circuit described in the second aspect, for receiving an initial pulse sequence emitted by the master device and generating a delayed pulse sequence for triggering based on the delayed pulse signal; wherein N is an integer, and N≥1; in the process of generating the delayed pulse sequence for each slave device, the preset delay time is obtained by calculating the time difference between the moment when the master device emits the initial pulse sequence and the preset trigger moment of the slave device.

[0011] Optionally, the interactive system further includes: N delay circuits described in any one of the first aspects or the integrated circuits described in the second aspect are set in the master device, which are used to output N delayed pulse sequences and send them to corresponding slave devices respectively, so that the slave devices are triggered based on the delayed pulse signals; wherein, during the generation process of the delayed pulse sequence corresponding to each slave device, the preset delay time is obtained by calculating the time difference between the moment when the master device generates the initial pulse sequence and the preset trigger moment of the corresponding slave device.

[0012] In a fourth aspect of the present application, a pulse sequence delay method is provided, the delay method comprising: An edge detection module receives an initial pulse sequence, generates an enable signal according to rising and falling edges of a pulse signal in the initial pulse sequence, and inputs a first value into a FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of a loop counter to a second value; the second value represents a change in the count value in the loop counter within a preset delay time; the loop counter is used to cyclically output the count value, and the time for one cycle of the count value is greater than the preset delay time; receiving a first value from a data write port of a FIFO buffer module, and inputting the first value into a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; comparing the first value with the real-time count value of the loop counter based on the value comparison module, and generating a trigger signal when the two values ​​are equal; The pulse generating module receives a trigger signal and generates a pulse signal according to the trigger signal to obtain a delayed pulse sequence.

[0013] In a fifth aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; Memory for storing computer programs; The processor is used to implement the delay method described in the fourth aspect when executing the program stored in the memory.

[0014] In a sixth aspect of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the delay method described in the fourth aspect is implemented.

[0015] The beneficial effects of this application are as follows: The present application provides a pulse sequence delay circuit, comprising: an edge detection module, configured to receive an initial pulse sequence, generate an enable signal according to a rising edge or a falling edge of each pulse signal in the initial pulse sequence, and input a first value into a FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of a loop counter to a second value; and the second value represents an amount of change in the count value of the loop counter within a preset delay time; A cyclic counter is used to cyclically output a count value, and the time it takes for the count value to cycle through one circle is longer than a preset delay time; a FIFO buffer module, configured to receive a first value from a data write port and input the first value to a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; a numerical comparison module, connected to the cycle counter and the FIFO buffer module, for comparing the first numerical value input from the data reading port with the real-time count value of the cycle counter, so as to generate a trigger signal when the first numerical value and the real-time count value of the cycle counter are equal; The pulse generating module is connected to the numerical comparison module and is used for receiving a trigger signal and generating a pulse signal according to the trigger signal to obtain a delayed pulse sequence.

[0016] Based on the above configuration, the delay circuit provided by the present application uses an edge detection module to identify the edge signals (including rising and falling edges) of the initial pulse sequence. Upon identifying the edge signal, a first value obtained by adding the current count value in the loop counter to the change in the count value corresponding to the delay time is input into the FIFO buffer module. The FIFO buffer module then caches the first value corresponding to the edge signal in the pulse sequence to avoid pulse signal loss. Furthermore, when the first value is set to be the same as the real-time count of the counter, a delayed pulse signal is generated, thereby achieving pulse sequence delay using the loop counter.

[0017] Furthermore, since the first value is obtained by adding the current count value in the loop counter to the second value, this solution uses the current count value in the loop counter to calibrate the entry moments of different edge signals in the pulse sequence, ensuring that the intervals between different edge signals in the pulse sequence remain unchanged before and after the delay. Accordingly, the second value in this solution is used to calibrate the delay time of the pulse sequence, ensuring that any pulse signal is delayed according to the delay time.

[0018] It can be seen that the delay circuit provided in the present application can complete the overall delay of the pulse sequence according to the preset delay time, and use the FIFO cache module to avoid the problem of pulse signal loss during the delay process. Through the combination of the settings of the loop counter, FIFO cache module and numerical comparison module, it is ensured that the pulse frequency does not change before and after the delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 This is a schematic diagram of a device in a detection scenario provided by this application; Figure 2 This is a structural diagram of an existing counter-based delay circuit provided by the present application; Figure 3 This is a delay diagram of an existing pulse sequence provided by the present application; Figure 4 This is a schematic diagram of the structure of a delay circuit provided by this application; Figure 5 This is a schematic diagram of a delayed pulse sequence provided by the present application; Figure 6 is a schematic structural diagram of another delay circuit provided by the present application; Figure 7 It is a flowchart of a delay method provided by this application; Figure 8 This is a structural diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0021] In the field of machine vision, pulse sequence delay is mainly used in equipment collaborative interaction scenarios, such as multi-device control. Typical applications include the mutual control of machine vision cameras with external light sources and motion platforms. A common application scenario is: different equipment is installed along the front and back of the production line. Photoelectric detection equipment is installed near the starting end as a photoelectric detection machine to mark the passing of materials. Multiple machine vision equipment is installed at the back of the production line as high-precision measurement machines for high-precision measurement, as shown below. Figure 1 shown.

[0022] When an object on the production line passes through the photoelectric inspection machine, it generates a pulse signal that is sent to the high-precision measurement machine for inspection. Accordingly, when multiple objects pass through the photoelectric inspection machine in succession, the machine generates a pulse sequence consisting of multiple pulse signals, equivalent to the initial pulse sequence in this application.

[0023] Due to the distance between the two machines, it takes time for the object to travel from the photoelectric inspection machine to the high-precision measurement machine. To enable the high-precision measurement machine to capture the pulse signal synchronously with the arrival of the object, a specific delay is required in the pulse sequence output by the photoelectric inspection equipment.

[0024] like Figure 1 As shown, at time T1, the photoelectric detection system detects the object under test and generates a synchronization signal S (i.e., a pulse signal used to control the triggering of the high-precision measuring system). After the object has moved for a time period t1, it reaches the high-precision measuring system at time T1+t1, at which point the high-precision measuring system needs to synchronize its image capture. Therefore, to account for the time difference between the object's movement and the transmission of the pulse signal, the pulse signal needs to be delayed for a certain period of time so that the high-precision measuring system can synchronize its image capture based on the pulse signal when the object reaches the high-precision measuring system. The delay time is t1-t2, where t2 is the time it takes for the pulse signal to be transmitted from the photoelectric detection system to the high-precision measuring system. In practice, due to the extremely fast signal transmission speed, time t2 can be ignored, and the movement time t1 is used as the delay time. Alternatively, the delay time can be calculated by calculating the time difference between the triggering time of the high-precision measuring system (T1+t1) and the time when the photoelectric detection system generates the initial pulse signal (T1).

[0025] Common signal delay methods include analog and digital methods. Common analog signal delay methods include RC circuits and transmission line delays. However, analog delays require specialized components and are difficult to adjust after device deployment. Digital delays primarily rely on digital processing devices, such as FPGAs. Through the sequential latching of logic gates, they can achieve delays in units as small as gate clock cycles. However, this method cannot be applied to longer delays.

[0026] Therefore, the prior art proposes a solution to delay the pulse signal using a counter, such as Figure 2 As shown, the processing idea of ​​this solution is to first detect the edge signals (rising edge and falling edge) of the digital signal pulse input separately through the edge detection circuit, and then use the digital processing device (including the rising edge delay counter and the falling edge delay counter) to count and delay. After reaching the desired delay time, the pulse generation circuit is used to generate the corresponding rising edge and falling edge, thereby obtaining the delayed pulse signal and outputting it.

[0027] However, when the input pulse frequency is high (the interval time t0 between adjacent pulse signals is less than the delay time t), the aforementioned counter scheme can only achieve accurate delay of a single pulse signal. In the process of delaying the pulse sequence, Figure 3 As shown in the figure, after the first pulse signal (from left to right) is delayed by time t, because the interval t0 between adjacent pulse signals is less than the delay time t, the newly input pulses during the pulse delay process are discarded, which also causes the pulse frequency of the delayed pulse sequence to decrease. The accurate relationship between the output of adjacent pulses cannot be guaranteed, resulting in missed detections in practical application scenarios. This shows that the existing "edge detection + counter" delay method cannot meet the overall pulse sequence delay requirements in some scenarios, and there is a problem of discarding subsequent pulse signals during the delay period.

[0028] In order to solve the above problems, the present application provides a pulse sequence delay circuit, such as Figure 4 As shown, the delay circuit includes: an edge detection module, configured to receive an initial pulse sequence, generate an enable signal based on a rising edge and a falling edge of each pulse signal in the initial pulse sequence, and input a first value into the FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of the loop counter to a second value; and the second value represents an amount of change in the count value of the loop counter within a preset delay time; A cyclic counter is used to cyclically output a count value, and the time it takes for the count value to cycle through one circle is longer than a preset delay time; a FIFO buffer module, configured to receive a first value from a data write port and input the first value to a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; a numerical comparison module, connected to the cycle counter and the FIFO buffer module, for comparing the first numerical value input from the data reading port with the real-time count value of the cycle counter, so as to generate a trigger signal when the first numerical value and the real-time count value of the cycle counter are equal; The pulse generating module is connected to the numerical comparison module and is used for receiving a trigger signal and generating a pulse signal according to the trigger signal to obtain a delayed pulse sequence.

[0029] Based on the above configuration, the delay circuit provided by the present application uses an edge detection module to identify the edge signals (including rising and falling edges) of the initial pulse sequence. Upon identifying the edge signal, a first value obtained by adding the current count value in the loop counter to the change in the count value corresponding to the delay time is input into the FIFO buffer module. The FIFO buffer module then caches the first value corresponding to the edge signal in the pulse sequence to avoid pulse signal loss. Furthermore, when the first value is set to be the same as the real-time count of the counter, a delayed pulse signal is generated, thereby achieving pulse sequence delay using the loop counter.

[0030] Furthermore, since the first value is obtained by adding the current count value in the loop counter to the second value, this solution uses the current count value in the loop counter to calibrate the entry moments of different edge signals in the pulse sequence, ensuring that the intervals between different edge signals in the pulse sequence remain unchanged before and after the delay. Accordingly, the second value in this solution is used to calibrate the delay time of the pulse sequence, ensuring that any pulse signal is delayed according to the delay time.

[0031] It can be seen that the delay circuit provided by the present application can complete the overall delay of the pulse sequence according to the preset delay time, and use the FIFO buffer module to avoid the problem of pulse signal loss during the delay process. Through the combination of the settings of the loop counter, FIFO buffer module and numerical comparison module, it is ensured that the pulse frequency does not change before and after the delay. The pulse sequence after delay in the delay circuit of the present application is as follows Figure 5 shown.

[0032] In the delay circuit provided in the present application, the edge detection module is generally an edge detection circuit, which is used to receive the initial pulse sequence and perform edge recognition on the edge signals (including rising edges and falling edges) of the pulse signals in the initial pulse sequence, thereby generating an enable signal. Specifically, the edge detection module may include a multi-stage trigger. After receiving the edge signal, the multi-stage trigger is used to perform delay in sequence, and the enable signal is generated after the signals of the adjacent stage triggers are passed through the combination logic. Among them, the specific structure of the edge detection module does not need to be limited in the present application. It only needs to have the function of generating an enable signal. For example, it can also be formed by a combination of several registers and a combination logic circuit.

[0033] After the edge detection module detects an edge signal in the pulse sequence, it generates an enable signal. The enable signal is used to input the first value into the FIFO buffer module. It can be understood that the enable signal is a write enable signal for the FIFO buffer module. That is, when the edge detection module detects an edge signal, the first value is written to the data write port of the FIFO buffer module based on the enable signal.

[0034] In some embodiments, the delay circuit provided by the present application further includes an addition module, connected to a cycle counter, for adding the real-time count value of the cycle counter to a second value, and when the edge detection module generates an enable signal, the added value is used as a first value and input into the FIFO buffer module. The addition module is typically a summing circuit, which is used to continuously calculate the sum of the real-time count value of the cycle counter and the second value to generate the first value. The cycle counter continuously inputs its real-time count value into the addition module, and the second value is obtained based on a preset delay time t, which can be set in advance in the delay circuit and the value is changed as the delay time t changes.

[0035] In some embodiments, the delay circuit provided by the present application is disposed in an FPGA (Field Programmable Gate Array). Accordingly, the second value is configured and stored in a register of the FPGA before the delay circuit is initialized, and can be repeatedly modified.

[0036] Regarding the cycle counter, in the delay circuit provided in this application, it is connected to both the addition module and the numerical comparison module. It should be noted that the bit used to represent the first numerical value in this application is consistent with the bit width M of the cycle counter. Therefore, when the sum of the current count value of the cycle counter and the second numerical value is greater than the maximum count value of the cycle counter, based on the aforementioned configuration, since the bit used to represent the first numerical value is fixed, the first numerical value obtained by the addition is like the count value of the cycle counter, and remains within the counting range of the cycle counter. This ensures that the numerical comparison process within the numerical comparison module does not cause errors.

[0037] However, when the second value is greater than or equal to the maximum count value of the loop counter, during the calculation of the first value, due to bit limitations, its value change will "cycle one more" relative to the loop counter. In the subsequent value comparison process within the value comparison module, the first value "advanced" is the same as the real-time count value of the loop counter that "cycles one less", resulting in an error in the comparison process between the first value and the real-time count value of the loop counter, causing the actual delay time of the pulse signal to differ from the preset delay time, resulting in an error in the operation of the delay circuit of the present application. Furthermore, considering that the second value is obtained based on the change in the count value of the loop counter within the preset delay time, the time for the count value to cycle one cycle is limited to be greater than the preset delay time, so that the second value is less than the maximum value of the loop counter.

[0038] The FIFO cache module of the present application can be formed by combining one or more FIFO buffers, and the amount of cache space in the FIFO cache module is not less than the number of edges of the pulse signal within the preset delay time t. The number of edges refers to the number composed of rising edges and falling edges. If the FIFO cache module is composed of two identical FIFO buffers, the depth of a single FIFO buffer must be greater than the number of pulse signals within the preset delay time t. Each pulse signal includes two edges, a rising edge and a falling edge, and the number of edges of the pulse signal within the preset delay time is twice the number of pulse signals. When a FIFO cache module is composed of two identical FIFO buffers, the depth in each buffer only needs to be greater than the number of pulse signals.

[0039] In some embodiments, as Figure 6 As shown, the FIFO buffer module provided by the present application includes two FIFO buffers, namely a rising edge FIFO buffer and a falling edge FIFO buffer. Among them, the rising edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal according to the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value is moved to the data read port.

[0040] The falling edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal according to the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port.

[0041] Considering the first-in, first-out nature of the FIFO buffer, it still takes a certain amount of time for the first value to move from the data write port to the data read port. The time required for this movement is set as the movement time. When the preset delay time is not less than the movement time, the delay circuit provided in the aforementioned application can be directly used to delay the pulse sequence using a loop counter, a FIFO buffer module, and a value comparison module.

[0042] For the case where the preset delay time is lower than the moving time, the delay circuit provided in the present application is also provided with a register module including a pipeline register, which is used to receive a pulse sequence when the time for data to move from the data write port to the data read port in the FIFO cache module is higher than the preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain a delayed pulse sequence.

[0043] For example, the time it takes for data to move from the data write port to the data read port in the FIFO buffer module is three clock cycles. When the preset delay time is less than three clock cycles, the delay circuit provided by this application can be delayed step by step using a pipeline register. The aforementioned pipeline register is a three-level register, and the output of the register at the previous level serves as the input of the register at the next level, thereby achieving a delay of one clock cycle at each level. When the preset delay time is not less than three clock cycles, the delay circuit provided by this application is based on a combination of the aforementioned edge detection module, loop counter, and FIFO buffer module to achieve an overall delay of the pulse sequence.

[0044] In some embodiments, the numerical comparison module provided herein is typically a comparator circuit, which may be a circuit including a comparator, or a circuit having comparator functionality. For example, when the delay circuit provided herein is disposed within an FPGA, the numerical comparison module may be a lookup table within the FPGA, i.e., implementing the comparator functionality through underlying lookup table resources.

[0045] The first value in the value comparison module is read from the data read port of the FIFO buffer module. After the first value is read from the data read port, the remaining first values ​​are updated to the data read port in the order they were written, according to the characteristics of the FIFO buffer. The real-time count value of the loop counter in the value comparison module is continuously read from the loop counter.

[0046] In some embodiments, the pulse generating module is typically a pulse generating circuit. Figure 6In the circuit structure shown, if the trigger signal received by the pulse generation module is obtained by comparing it with the first value in the falling edge FIFO buffer, the pulse generation module will change the output signal from a low level to a high level to generate a delayed pulse signal; wherein the output signal of the pulse generation module is initially at a low level. If the trigger signal received by the pulse generation module is obtained by comparing it with the first value in the falling edge FIFO buffer, the pulse generation module will change the output signal from a high level to a low level to generate a delayed pulse signal.

[0047] Taking the rising edge FIFO buffer as an example, when the first numerical value is equal to the real-time count value of the loop counter, the trigger signal of the rising edge output by the numerical comparison module is transmitted to the pulse generation module, and the signal output by the pulse generation module is changed from a low level to a high level, that is, a rising edge is generated. Since the rising edge and the falling edge appear alternately in the pulse sequence, the trigger signal of the next rising edge must arrive after the trigger signal of the previous falling edge. Therefore, when the initial level of the pulse generation module output signal is determined, the level of the pulse generation module output signal will also change between a low level and a high level in sequence according to the order of the rising edge and the falling edge in the initial pulse sequence, thereby generating a delayed rising edge and a falling edge. Taking into account that in actual work, the pulse signal usually appears first with the rising edge, the initial state of the pulse generation circuit output signal in this application is usually set to a low level to adapt to the order of appearance of the rising edge in the initial pulse sequence.

[0048] In some embodiments, the delay circuit provided herein further includes a reset module configured to reset the edge detection module, FIFO buffer module, value comparison module, pulse generation module, addition module, and register module within the delay circuit after the delay circuit is initialized or the initial pulse sequence input to the edge detection module changes. The loop counter does not require a reset module for processing.

[0049] The reset module of the present application is typically a reset circuit. Specifically, during the initial power-on reset of the delay circuit and during the resetting of the delay circuit according to user requirements, the reset module of the present application can simply input a corresponding specific reset signal. When the reset module performs cross-clock domain and synchronous processing of the reset signal, it can utilize a multi-stage register cascade to complete the processing of the input reset signal.

[0050] Based on the above description, it can be seen that in the delay circuit provided by the present application, the overall delay of the pulse sequence under different pulse frequencies and different delay times can be met by adjusting the bit width of the loop counter and the depth of the FIFO cache module (i.e., the amount of cache space). At the same time, based on the above circuit structure, it can be seen that the delay circuit provided by the present application has a simple composition structure and, on the basis of having a delay function, also has the advantage of low cost. In addition, in the pulse signal generation scheme provided by the patent "CN1125535C", although a technical means of generating pulses by using the counter value to be the same as the target value is disclosed, the purpose of its scheme is to change the interval between adjacent pulse signals, while in the delay circuit scheme provided by the present application, it is necessary to ensure that the interval between adjacent pulse signals remains unchanged to achieve the overall delay of the pulse sequence. It is worth noting that the patent document does not disclose the technical means for achieving the overall delay of the pulse sequence and cannot solve the problems faced by the existing pulse sequence in the overall delay process.

[0051] Based on the same inventive concept, the present application also provides an integrated circuit, which includes the aforementioned delay circuit. Specifically, the integrated circuit can be an FPGA, a chip, etc.

[0052] Based on the same inventive concept, the present application also provides an interactive system comprising a master device and N slave devices, each of which includes the aforementioned delay circuit or integrated circuit, configured to receive an initial pulse sequence transmitted by the master device and generate a delayed pulse sequence for triggering based on the delayed pulse signal. Where N is an integer, and N ≥ 1; in the process of generating the delayed pulse sequence, each slave device uses a preset delay time calculated by calculating the time difference between the time when the master device transmits the initial pulse sequence and the preset triggering time of the slave device.

[0053] Taking the aforementioned machine vision scenario as an example, the master device can be a photoelectric detection device, and the slave device can be a high-precision measurement device. In the interactive system provided by this application, the aforementioned delay circuit or integrated circuit can be deployed on each slave device. The difference in the pulse sequence delay in each slave device lies solely in the delay time. Specifically, the preset delay time for each slave device is calculated by calculating the time difference between the moment the master device sends the initial pulse sequence and the preset trigger time of the slave device.

[0054] In some embodiments, the interactive system provided herein may include N aforementioned delay circuits or integrated circuits in a master device, configured to output N delayed pulse sequences and transmit them to corresponding slave devices, respectively, so that the slave devices are triggered based on the delayed pulse signals. During the generation of the delayed pulse sequence corresponding to each slave device, the preset delay time is determined by calculating the time difference between the time when the master device generates the initial pulse sequence and the preset triggering time of the corresponding slave device.

[0055] In the case where N aforementioned delay circuits or integrated circuits are deployed in a master device, each delay circuit or integrated circuit is architecturally independent and generates a delayed pulse train for its corresponding slave device. During data exchange between the master device and N slave devices, the master device fans out N differently delayed pulse trains and transmits them to the corresponding slave devices.

[0056] Based on the same inventive concept, the present application also provides a pulse sequence delay method, such as Figure 7 As shown, the delay method includes the following steps: S1. An edge detection module receives an initial pulse sequence and generates an enable signal based on the rising and falling edges of each pulse signal in the initial pulse sequence, thereby inputting a first value into a FIFO buffer module based on the enable signal. The first value is obtained by adding a current count value of a loop counter to a second value; the second value represents the amount of change in the count value of the loop counter within a preset delay time; and the loop counter is configured to cyclically output the count value, and the time it takes for the count value to cycle through one cycle is greater than the preset delay time.

[0057] S2. Receive a first value from a data write port of a FIFO buffer module, and after the first value is moved to a data read port, input the first value to a value comparison module, wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time.

[0058] S3. Compare the first value input from the data reading port with the real-time count value of the cycle counter based on the value comparison module, and generate a trigger signal when the two are equal.

[0059] S4. The pulse generating module receives a trigger signal and generates a pulse signal according to the trigger signal to obtain a delayed pulse sequence.

[0060] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, such as Figure 8 As shown, it includes a processor 801, a communication interface 802, a memory 803 and a communication bus 804, wherein the processor 801, the communication interface 802, and the memory 803 communicate with each other through the communication bus 804. Memory 803, used for storing computer programs; The processor 801 is configured to implement the above-mentioned pulse sequence delay method when executing the program stored in the memory 803 .

[0061] The communication bus mentioned in the electronic devices mentioned above may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus. This communication bus can be divided into address buses, data buses, and control buses. For ease of illustration, the figure uses only a single thick line, but this does not mean that there is only one bus or only one type of bus.

[0062] The communication interface is used for communication between the above electronic device and other devices.

[0063] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0064] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0065] In another embodiment provided by the present application, a computer-readable storage medium is further provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned delay method steps is implemented.

[0066] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any one of the delay method steps in the above embodiments.

[0067] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A pulse train delay circuit, characterized in that: include: an edge detection module, configured to receive an initial pulse sequence and generate an enable signal based on rising and falling edges of a pulse signal in the initial pulse sequence, so as to input a first value into the FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of the loop counter to a second value; and the second value represents an amount of change in the count value of the loop counter within a preset delay time; A cyclic counter is used to cyclically output a count value, and the time it takes for the count value to cycle through one circle is longer than a preset delay time; a FIFO buffer module, configured to receive a first value from a data write port, and input the first value to a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; a numerical comparison module, configured to compare the first numerical value with the real-time count value of the loop counter and generate a trigger signal when the two values ​​are equal; The pulse generating module is used to receive a trigger signal, generate a pulse signal according to the trigger signal, and obtain a delayed pulse sequence.

2. The delay circuit according to claim 1, wherein: The FIFO buffer module includes a rising edge FIFO buffer and a falling edge FIFO buffer; The rising edge FIFO buffer is used to receive the first value from the data write port after the edge detection module generates an enable signal according to the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value is moved to the data read port; The falling edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal according to the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port.

3. The delay circuit according to claim 2, wherein: After receiving the trigger signal, the pulse generating module further includes: If the trigger signal is obtained by comparing the first value in the rising edge FIFO buffer, the pulse generation module changes the output signal from a low level to a high level to generate a delayed pulse signal; wherein the initial state of the output signal of the pulse generation module is a low level; If the trigger signal is obtained by comparing with the first value in the falling edge FIFO buffer, the pulse generating module changes the output signal from a high level to a low level to generate a delayed pulse signal.

4. The delay circuit according to claim 1, wherein: The delay circuit further includes: an adding module connected to the cycle counter, configured to add the real-time count value of the cycle counter to the second value, and input the added value as the first value to the FIFO buffer module when the edge detection module generates an enable signal; a register module, comprising a pipeline register, configured to receive a pulse sequence when a time for data to be moved from a data write port to a data read port in the FIFO buffer module exceeds a preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain a delayed pulse sequence; A reset module is used to reset the edge detection module, FIFO cache module, numerical comparison module, pulse generation module, addition module and register module in the delay circuit after the delay circuit is initialized or the initial pulse sequence input to the edge detection module changes.

5. An integrated circuit, characterized in that: The method comprises the delay circuit according to any one of claims 1 to 4.

6. An interactive system comprising a master device and N slave devices, characterized in that: Each slave device includes the delay circuit described in any one of claims 1 to 4 or the integrated circuit described in claim 5, which is used to receive the initial pulse sequence sent by the master device and generate a delayed pulse sequence to trigger based on the delayed pulse signal; wherein N is an integer and N≥1; in the process of generating the delayed pulse sequence by each slave device, the preset delay time is obtained by calculating the time difference between the moment when the master device sends the initial pulse sequence and the preset trigger moment of the slave device.

7. The interactive system according to claim 6, characterized in that: The interactive system further includes: N delay circuits according to any one of claims 1 to 4 or N integrated circuits according to claim 5 are provided in the master device for outputting N delayed pulse sequences and sending them to corresponding slave devices respectively, so that the slave devices are triggered based on the delayed pulse signals; wherein, during the generation process of the delayed pulse sequence corresponding to each slave device, the preset delay time is obtained by calculating the time difference between the moment when the master device generates the initial pulse sequence and the preset triggering moment of the corresponding slave device.

8. A method for delaying a pulse sequence, characterized in that: The delay method includes: An edge detection module receives an initial pulse sequence, generates an enable signal according to rising and falling edges of a pulse signal in the initial pulse sequence, and inputs a first value into a FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of a loop counter to a second value; the second value represents a change in the count value in the loop counter within a preset delay time; the loop counter is used to cyclically output the count value, and the time for one cycle of the count value is greater than the preset delay time; receiving a first value from a data write port of a FIFO buffer module, and inputting the first value into a value comparison module after the first value is moved to a data read port; wherein the amount of buffer space in the FIFO buffer module is not less than the number of edges of the pulse signal within a preset delay time; comparing the first value with the real-time count value of the loop counter based on the value comparison module, and generating a trigger signal when the two values ​​are equal; The pulse generating module receives a trigger signal and generates a pulse signal according to the trigger signal to obtain a delayed pulse sequence.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; The processor is configured to implement the delay method according to claim 8 when executing a program stored in the memory.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the delay method according to claim 8 is implemented.

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