Delay circuit, integrated circuit, interactive system, method and device for pulse sequences

Abstract

The application discloses a delay circuit of pulse sequence, integrated circuit, interactive system, method and equipment, and relates to the field of signal processing.The delay circuit comprises an edge detection module, a cycle counter and a FIFO cache module.The edge detection module is used for receiving an initial pulse sequence, generating an enable signal according to rising edges and falling edges of pulse signals in the initial pulse sequence, and inputting a first value to the FIFO cache module based on the enable signal.The cycle counter is used for cyclically outputting a count value.The FIFO cache module is used for receiving the first value from a data write port and inputting the first value to a value comparison module after the first value moves to a data read port.The value comparison module is used for comparing the first value with a real-time count value of the cycle counter and generating a trigger signal when the two values are equal.The pulse generation module generates a pulse signal according to the trigger signal and obtains a delayed pulse sequence.Therefore, the delay circuit can complete overall delay of the pulse sequence.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of signal processing, and particularly relates to a delay circuit, an integrated circuit, an interactive system, a method and an apparatus for a pulse sequence. BACKGROUND

[0002] In the prior art, a trigger signal is usually delayed to achieve precise control of an electronic device. In a signal delay scheme, a counter can be selected to delay a pulse signal in order to expand the scope of application of the scheme and prolong the delay time.

[0003] However, for the prior signal delay scheme using a counter, when the interval time of the pulse signal is less than the delay time, only the delay of a single pulse signal can be achieved. For a pulse sequence containing multiple continuous pulse signals, there are usually problems of pulse signal loss and pulse frequency reduction after the delay, and the overall delay of the pulse sequence cannot be completed. SUMMARY

[0004] The present application provides a delay circuit, an integrated circuit, an interactive system, a method and an apparatus for a pulse sequence to achieve overall delay of the pulse sequence.

[0005] To achieve the above object, the present application provides the following technical solutions:

[0006] In the first aspect of the present application, a delay circuit for a pulse sequence is provided, comprising:

[0007] an edge detection module, configured to receive an initial pulse sequence, generate an enable signal according to the rising edge and the falling edge of the pulse signal in the initial pulse sequence, and input a first value to a FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of a cyclic counter and a second value; and the second value represents the variation of the count value in the cyclic counter within a preset delay time;

[0008] a cyclic counter, configured to cyclically output a count value, and the time for one cycle of the count value is higher than the preset delay time;

[0009] a FIFO buffer module, configured to receive the first value from a data write port, and input the first value to a value comparison module after the first value moves to a data read port; wherein the number of buffer spaces in the FIFO buffer module is not less than the number of edges of the pulse signal within the preset delay time;

[0010] a value comparison module, configured to compare the first value with a real-time count value of the cyclic counter, and generate a trigger signal when the first value is equal to the real-time count value;

[0011] a pulse generation module, configured to receive the trigger signal, generate a pulse signal according to the trigger signal, and obtain a delayed pulse sequence.

[0012] Optionally, the FIFO cache module comprises a rising edge FIFO cache and a falling edge FIFO cache.

[0013] The rising edge FIFO cache is configured to receive the first value from the data write-in port after the edge detection module generates the enable signal according to the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read-out port.

[0014] The falling edge FIFO cache is configured to receive the first value from the data write-in port after the edge detection module generates the enable signal according to the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read-out port.

[0015] Optionally, the pulse generation module further comprises, after receiving the trigger signal:

[0016] If the trigger signal is obtained by comparing the first value in the rising edge FIFO cache, the pulse generation module converts the output signal from low level to high level to generate the delayed pulse signal; wherein the initial state of the output signal of the pulse generation module is low level.

[0017] If the trigger signal is obtained by comparing the first value in the falling edge FIFO cache, the pulse generation module converts the output signal from high level to low level to generate the delayed pulse signal.

[0018] Optionally, the delay circuit further comprises:

[0019] An addition module connected to the cycle counter, configured to add the real-time count value of the cycle counter and the second value, and input the added value as the first value to the FIFO cache module when the edge detection module generates the enable signal.

[0020] A register module comprising a pipeline register, configured to receive the pulse sequence when the time of data moving from the data write-in port to the data read-out port in the FIFO cache module is higher than the preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain the delayed pulse sequence.

[0021] A reset module configured to reset the edge detection module, the FIFO cache module, the value comparison module, the pulse generation module, the addition module and the register module in the delay circuit after the delay circuit is initialized or the initial pulse sequence input to the edge detection module is changed.

[0022] In the second aspect of the present application, an integrated circuit is provided, comprising the delay circuit according to any one of the first aspect.

[0023] In a third aspect of the present application, an interactive system is provided, comprising one master device and N slave devices, each of the slave devices comprising the delay circuit of any one of the first aspect or the integrated circuit of the second aspect, for receiving an initial pulse sequence sent by the master device and generating a delayed pulse sequence based on the delayed pulse signal for triggering; wherein N is an integer and N≥1; and the preset delay time in the process of generating the delayed pulse sequence by each of the slave devices is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the slave device.

[0024] Optionally, the interactive system further comprises:

[0025] N delay circuits of any one of the first aspect or the integrated circuit of the second aspect are arranged in the master device, for outputting N delayed pulse sequences and sending to the corresponding slave devices respectively, so that the slave devices are triggered based on the delayed pulse signal; wherein the preset delay time in the process of generating the corresponding delayed pulse sequence of each of the slave devices is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the corresponding slave device.

[0026] In a fourth aspect of the present application, a delay method of a pulse sequence is provided, the delay method comprising:

[0027] based on the edge detection module receiving the initial pulse sequence, generating an enable signal according to the rising edge and the falling edge of the pulse signal in the initial pulse sequence, and inputting a first value to the FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a current count value of the cycle counter and a second value; the second value represents the change amount of the count value in the cycle counter within the preset delay time; the cycle counter is used to output the count value cyclically, and the time of one cycle of the count value is higher than the preset delay time;

[0028] receiving the first value from the data write port of the FIFO buffer module, and inputting the first value to the value comparison module after the first value moves to the data read port; wherein the number of the buffer spaces in the FIFO buffer module is not less than the number of edges of the pulse signal within the preset delay time;

[0029] based on the value comparison module comparing the first value with the real-time count value of the cycle counter, and generating a trigger signal when the two values are equal;

[0030] based on the pulse generation module receiving the trigger signal, generating a pulse signal according to the trigger signal, so as to obtain the delayed pulse sequence.

[0031] In a fifth aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;

[0032] The memory is configured to store a computer program.

[0033] The processor is configured to execute the program stored in the memory to implement the delay method of the fourth aspect.

[0034] In a sixth aspect of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the delay method of the fourth aspect.

[0035] The present application has the following beneficial effects:

[0036] The present application provides a delay circuit of a pulse sequence, comprising: an edge detection module, configured to receive an initial pulse sequence, generate an enable signal according to a rising edge or a falling edge of each pulse signal in the initial pulse sequence, and input a first value to a FIFO cache module based on the enable signal; wherein the first value is obtained by adding a current count value of a cycle counter and a second value; the second value represents a change amount of the count value in the cycle counter within a preset delay time;

[0037] The cycle counter is configured to cyclically output the count value, and the time for one cycle of the count value is higher than the preset delay time;

[0038] The FIFO cache module is configured to receive the first value from a data write port, and input to a value comparison module after the first value moves to a data read port; wherein the number of cache spaces in the FIFO cache module is not less than the number of edges of the pulse signal within the preset delay time;

[0039] The value comparison module is connected to the cycle counter and the FIFO cache module, and is configured to compare the first value input from the data read port with the real-time count value of the cycle counter, to generate a trigger signal when the two values are equal;

[0040] The pulse generation module is connected to the value comparison module, configured to receive the trigger signal, generate a pulse signal according to the trigger signal, and obtain a delayed pulse sequence.

[0041] Based on the above setting, the delay circuit provided by the application, through the edge detection module, the edge signals (including rising edge and falling edge) of the initial pulse sequence are identified, and the first value obtained by adding the current count value in the cycle counter and the change amount of the count value corresponding to the delay time is input to the FIFO buffer module. The FIFO buffer module is used to buffer the first value corresponding to the edge signal in the pulse sequence, so as to avoid the phenomenon of pulse signal loss. Moreover, when the first value is equal to the real-time count of the counter, the delayed pulse signal is generated, and the cycle counter is used to realize the delay of the pulse sequence.

[0042] In addition, considering that the first value is obtained by adding the current count value in the cycle counter and the second value, in the present scheme, the current count value in the cycle counter is used to mark the entering time of different edge signals in the pulse sequence, so as to ensure that the interval between different edge signals in the pulse sequence does not change before and after the delay. Correspondingly, the second value in the present scheme is used to mark the delay time of the pulse sequence, so as to realize the delay of any pulse signal according to the delay time.

[0043] It can be seen that the delay circuit provided by the application can complete the overall delay of the pulse sequence according to the preset delay time, and the FIFO buffer module is used to avoid the problem of pulse signal loss in the delay process. Through the combination of the cycle counter, the FIFO buffer module and the value comparison module, it is ensured that the pulse frequency does not change before and after the delay. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the application and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0045] Figure 1 is a schematic diagram of a device provided by the application in a detection scenario;

[0046] Figure 2 is a structure diagram of an existing delay circuit based on a counter provided by the application;

[0047] Figure 3 is a delay schematic diagram of an existing pulse sequence provided by the application;

[0048] Figure 4 is a structure schematic diagram of a delay circuit provided by the application;

[0049] Figure 5 is a schematic diagram of a delayed pulse sequence provided by the application;

[0050] Figure 6is a structural schematic diagram of another delay circuit provided in the present application;

[0051] Figure 7 is a flowchart of a delay method provided in the present application;

[0052] Figure 8 is a structural diagram of an electronic device provided in the present application. DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in a clear and complete manner with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application.

[0054] Pulse sequence delay is mainly applied in the field of machine vision to device cooperative interaction scenes, such as multi-device control, typical applications such as mutual control of machine vision camera and external light source, motion platform. A commonly existing application scene is: different devices are installed along the production line, photoelectric detection devices are installed near the starting end as photoelectric detection machines, used for indicating the passing of materials, and multiple machine vision devices are installed on the back side of the production line as high-precision measurement machines, used for high-precision measurement, as shown in the following figure. Figure 1

[0055] When the measured object passes through the photoelectric detection machine, a pulse signal is generated inside the photoelectric detection machine, which is sent to the high-precision measurement machine to realize the detection of the measured object. Correspondingly, when multiple measured objects pass through the photoelectric detection machine in succession, the photoelectric detection machine generates a pulse sequence containing multiple pulse signals, which is equivalent to the initial pulse sequence of the present application.

[0056] Limited by the distance between the two machines, the measured object needs to spend a certain time from the photoelectric detection machine to the high-precision measurement machine. If the high-precision measurement machine is to realize synchronous shooting based on the pulse signal when the measured object arrives, a specific delay needs to be performed on the pulse sequence output by the photoelectric detection device.

[0057] As Figure 1 ​As shown, at time T1, the photoelectric detection machine detects the passing of the measured object and generates a synchronization signal S (i.e., a pulse signal for triggering the high-precision measurement machine). After the measured object passes through the movement time t1, it reaches the high-precision measurement machine at time T1+t1, at which time the high-precision measurement machine needs to take a synchronous shot. Therefore, considering the time difference between the object movement and the transmission of the pulse signal, the pulse signal needs to be delayed for a certain time, so that the high-precision measurement machine can be triggered to take a shot based on the pulse signal when the measured object reaches the high-precision measurement machine. The delay time is t1-t2, where t2 is the time for the pulse signal to be sent from the photoelectric detection machine to the high-precision measurement machine. In actual work, considering that the signal transmission speed is extremely fast, the time t2 can be ignored, and the movement time t1 is taken as the delay time. Alternatively, the time difference between the triggering time (T1+t1) of the high-precision measurement machine and the time (T1) at which the photoelectric detection machine generates the initial pulse signal can also be obtained.

[0058] Common signal delay schemes include analog method delay and digital method delay. Common schemes for analog signal delay include RC circuits and transmission line delay. Analog delay requires specific devices and is inconvenient to adjust after device arrangement. Digital delay is mainly based on digital processing devices such as FPGAs, and can achieve delay in clock cycles of gate circuits as the smallest unit through logic gate latching. However, this method cannot be applied to long-time delay processing.

[0059] Therefore, the prior art proposes a scheme for delaying the pulse signal using a counter, as shown in Figure 2 The processing idea of this scheme is to first detect the edge signals (rising edge and falling edge) of the digital signal pulse input through an edge detection circuit, then perform counting delay through a digital processing device (including a rising edge delay counter and a falling edge delay counter), generate the corresponding rising edge and falling edge using a pulse generation circuit when the desired delay time is reached, and thus obtain the delayed pulse signal and output it.

[0060] However, when the input pulse frequency is high (the interval time t0 between adjacent pulse signals is less than the delay time t), the foregoing counter scheme can only accurately delay a single pulse signal. In the process of delaying the pulse sequence, as shown in Figure 3As shown, after the first (from left to right) pulse signal is delayed for a time t, because the interval t0 between adjacent pulse signals is less than the delay time t, the newly input pulse during the pulse delay process is discarded, which also causes the pulse frequency of the delayed pulse sequence to decrease, cannot guarantee the accurate relationship between adjacent pulses, and causes missed detection in actual application scenarios. As can be seen, the existing "edge detection + counter" delay method cannot meet the requirements of overall delay of pulse sequence in some scenarios, and there is a problem that subsequent pulse signals during the delay period are discarded.

[0061] To solve the above problems, the present application provides a delay circuit for pulse sequence, as shown in Figure 4 The delay circuit comprises:

[0062] an edge detection module, configured to receive an initial pulse sequence, generate an enable signal according to the rising edge and the falling edge of each pulse signal in the initial pulse sequence, and input a first value to a FIFO cache module based on the enable signal; wherein the first value is obtained by adding a current count value of a cycle counter to a second value; the second value represents the change amount of the count value in the cycle counter within a preset delay time;

[0063] a cycle counter, configured to output the count value cyclically, and the time for one cycle of the count value is higher than the preset delay time;

[0064] a FIFO cache module, configured to receive the first value from a data write port, and input to a value comparison module after the first value moves to a data read port; wherein the number of cache spaces in the FIFO cache module is not less than the number of edges of the pulse signal within the preset delay time;

[0065] a value comparison module, connected to the cycle counter and the FIFO cache module, configured to compare the first value input from the data read port with the real-time count value of the cycle counter, and generate a trigger signal when the two are equal;

[0066] a pulse generation module, connected to the value comparison module, configured to receive the trigger signal, generate a pulse signal according to the trigger signal, and obtain a delayed pulse sequence.

[0067] Based on the above setting, the delay circuit provided in the present application, through the edge detection module, the edge signal (including rising edge and falling edge) of the initial pulse sequence is identified, and at the same time the edge signal is identified, the first value obtained by adding the current count value in the cycle counter and the change amount of the count value corresponding to the delay time is input to the FIFO buffer module, and the first value corresponding to the edge signal in the pulse sequence is buffered by using the FIFO buffer module, so as to avoid the phenomenon of pulse signal loss. Moreover, when the first value is equal to the real-time count of the counter, the delayed pulse signal is generated, and the cycle counter is used to realize the delay of the pulse sequence.

[0068] In addition, considering that the first value is obtained by adding the current count value in the cycle counter and the second value, in the present scheme, the entering time of different edge signals in the pulse sequence is marked by using the current count value in the cycle counter, so as to ensure that the interval between different edge signals in the pulse sequence does not change before and after the delay. Correspondingly, the second value in the present scheme is used to mark the delay time of the pulse sequence, so as to realize the delay of any pulse signal according to the delay time.

[0069] It can be seen that the delay circuit provided in the present application can complete the overall delay of the pulse sequence according to the preset delay time, and the problem of pulse signal loss in the delay process is avoided by using the FIFO buffer module. Through the combination of the cycle counter, the FIFO buffer module and the value comparison module, it is ensured that the pulse frequency does not change before and after the delay. The delayed pulse sequence in the delay circuit of the present application is shown in Figure 5 .

[0070] In the delay circuit provided in the present application, the edge detection module is usually an edge detection circuit, which is used to receive the initial pulse sequence and perform edge recognition on the edge signal (including rising edge and falling edge) of the pulse signal in the initial pulse sequence, thereby generating an enable signal. Specifically, the edge detection module can include multiple flip-flops, which are used to delay in turn after receiving the edge signal, and the signals of adjacent flip-flops are combined by using the logic to generate the enable signal. In the present application, the specific structure of the edge detection module is not limited, as long as it has the function of generating the enable signal, for example, it can also be formed by combining a plurality of registers and a combination logic circuit.

[0071] After the edge detection module detects the edge signal in the pulse sequence, the enable signal is generated. The enable signal is used to input the first value to the FIFO buffer module. It can be understood that the enable signal is a write enable signal of the FIFO buffer module, that is, when the edge detection module detects the edge signal, based on the enable signal, the first value is written to the data write port of the FIFO buffer module.

[0072] In some embodiments, the delay circuit provided by the present application further comprises an addition module connected to the cycle counter, configured to add the real-time count value of the cycle counter and the second value, and input the added value as the first value to the FIFO buffer module when the edge detection module generates the enable signal. The addition module is usually a summation circuit, configured to continuously calculate the sum of the real-time count value of the cycle counter and the second value, and generate the first value. The cycle counter continuously inputs the real-time count value to the addition module, while the second value is obtained based on the change amount of the count value of the cycle counter within the preset delay time t, which can be set in advance in the delay circuit and changed with the change of the delay time t.

[0073] In some embodiments, the delay circuit provided by the present application is arranged in an FPGA (Field Programmable Gate Array). Accordingly, the second value is configured and stored in the register of the FPGA before the delay circuit is initialized, and can be repeatedly changed.

[0074] For the cycle counter, it is connected to the addition module and the value comparison module in the delay circuit provided by the present application. It is noted that the bit used to represent the first value in the present application is consistent with the bit width M of the cycle counter, so that when the current count value of the cycle counter added with the second value is greater than the maximum count value of the cycle counter, based on the foregoing setting, since the bit used to represent the first value is fixed, the first value obtained by addition is like the count value of the cycle counter, which is still within the count range of the cycle counter. Therefore, it can be ensured that the value comparison process in the value comparison module does not occur error.

[0075] However, when the second value is greater than or equal to the maximum count value of the cycle counter, in the calculation process of the first value, limited by the bit, the value change thereof will be more than "one cycle" relative to the cycle counter, and in the subsequent value comparison process in the value comparison module, the first value is "in advance" the same as the real-time count value of the cycle counter "less than one cycle", which causes the first value and the real-time count value of the cycle counter to occur error in the comparison process, so that the actual delay time of the pulse signal is different from the preset delay time, resulting in error in the working of the delay circuit of the present application. Further, considering that the second value is obtained according to the change amount of the count value of the cycle counter within the preset delay time, therefore, the time for one cycle of the count value in the present application is higher than the preset delay time, so that the second value is less than the maximum value of the cycle counter.

[0076] The FIFO cache module of the present application can be formed by one or more FIFO buffers, and the number of cache spaces in the FIFO cache module is not less than the number of edges of the pulse signals within the preset delay time t. The number of edges represents the number of edges composed of rising edges and falling edges. If the FIFO cache module is formed by two identical FIFO buffers, the depth of a single FIFO buffer needs to be greater than the number of pulse signals within the preset delay time t. Each pulse signal includes two edges of rising edge and falling edge, and the number of edges of the pulse signals within the preset delay time is twice the number of pulse signals. When a FIFO cache module is formed by two identical FIFO buffers, the depth in each buffer only needs to be greater than the number of pulse signals.

[0077] In some embodiments, as shown in FIG. 1, the FIFO cache module provided by the present application includes two FIFO buffers, which are a rising edge FIFO buffer and a falling edge FIFO buffer. The rising edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal based on the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port. Figure 6

[0078] The falling edge FIFO buffer is used to receive a first value from the data write port after the edge detection module generates an enable signal based on the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port.

[0079] Considering the first-in-first-out characteristic of the FIFO buffer, it still takes a certain time for the first value to move from the data write port to the data read port. The time required for the movement is set as the movement time. When the preset delay time is not less than the movement time, the delay circuit provided by the present application can be directly used to complete the delay of the pulse sequence by using the cycle counter, the FIFO cache module, and the value comparison module.

[0080] For the case that the preset delay time is less than the movement time, the delay circuit provided by the present application further includes a register module including a pipeline register, which is used to receive a pulse sequence when the time for data to move from the data write port to the data read port in the FIFO cache module is higher than the preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain a delayed pulse sequence.

[0081] ​For example, the time for data moving from the data write port to the data read port in the FIFO cache module is 3 clock cycles, when the preset delay time is lower than 3 clock cycles, the delay circuit provided by the application can delay by using the pipeline registers step by step. Wherein, the aforementioned pipeline registers are 3-stage registers, the output of the previous stage register is taken as the input of the next stage register, thereby realizing 1 clock cycle delay for each stage. When the preset delay time is not lower than 3 clock cycles, the delay circuit provided by the application is based on the combination of the aforementioned edge detection module, the cycle counter and the FIFO cache module, to realize the overall delay of the pulse sequence.

[0082] In some embodiments, the numerical comparison module provided by the application is usually a comparator circuit, which can be a circuit containing a comparator, or can also be a circuit with a comparator function. For example, when the delay circuit provided by the application is arranged in the FPGA, the numerical comparison module can be a lookup table in the FPGA, that is, the comparator function is realized by the underlying lookup table resource.

[0083] The first value in the numerical comparison module is read from the data read port of the FIFO cache module, and after the first value in the data read port is read out, the remaining first values are updated to the data read port according to the writing order according to the FIFO cache characteristics. The real-time count value of the cycle counter in the numerical comparison module is continuously read from the cycle counter.

[0084] In some embodiments, the pulse generation module is usually a pulse generation circuit. As Figure 6 In the circuit structure shown in the figure, if the trigger signal received by the pulse generation module is obtained by comparing the first value in the falling edge FIFO cache, the pulse generation module will convert the output signal from low to high to generate the delayed pulse signal; wherein, the initial state of the output signal of the pulse generation module is low. If the trigger signal received by the pulse generation module is obtained by comparing the first value in the falling edge FIFO cache, the pulse generation module will convert the output signal from high to low to generate the delayed pulse signal.

[0085] Taking the rising edge FIFO buffer as an example, when the first value is equal to the real-time count value of the cycle counter, the value comparison module outputs a rising edge trigger signal to the pulse generation module, and the signal output by the pulse generation module is changed from low level to high level, that is, a rising edge is generated. Since the rising edge and the falling edge in the pulse sequence belong to alternating appearance, the trigger signal of the next rising edge must arrive after the trigger signal of the previous falling edge. Therefore, after the initial level of the signal output by the pulse generation module is determined, the level of the signal output by the pulse generation module will also be converted between low level and high level in sequence according to the order of the rising edge and the falling edge in the initial pulse sequence, thereby generating the delayed rising edge and the delayed falling edge. Considering that the pulse signal usually appears in the rising edge in actual work, the initial state of the signal output by the pulse generation circuit in the present application is usually set to low level to adapt to the order of the rising edge in the initial pulse sequence.

[0086] In some embodiments, the delay circuit provided by the present application further comprises a reset module for resetting the edge detection module, the FIFO buffer module, the value comparison module, the pulse generation module, the addition module and the register module in the delay circuit after the initialization of the delay circuit or the change of the initial pulse sequence input to the edge detection module. The cycle counter does not need to be processed by the reset module.

[0087] The reset module of the present application is usually a reset circuit. Specifically, in the process of initial power-on reset of the delay circuit and reset of the delay circuit according to user demand, the reset module of the present application can be reset by inputting a specific reset signal. When the reset module performs cross-clock domain and synchronous processing of the reset signal, the processing of the input reset signal can be completed by using multi-stage register cascade.

[0088] Based on the foregoing description, it can be known that in the delay circuit provided by the present application, the overall delay of the pulse sequence under different pulse frequencies and different delay times can be satisfied by adjusting the bit width of the cycle counter and the depth (i.e. the number of buffer spaces) of the FIFO buffer module. At the same time, based on the foregoing circuit structure, it can be known that the delay circuit provided by the present application has a simple composition structure and has the advantages of low cost on the basis of having a delay function. In addition, although the patent CN1125535C discloses a technical means for generating a pulse by using a counter value equal to a target value, the purpose of the scheme is to change the interval between adjacent pulse signals, while in the delay circuit scheme provided by the present application, it is necessary to ensure that the interval between adjacent pulse signals is unchanged to achieve the overall delay of the pulse sequence. It should be noted that the patent document does not disclose the technical means for achieving the overall delay of the pulse sequence, and cannot solve the problems faced by the existing pulse sequence in the overall delay process.

[0089] Based on the same inventive concept, the application further provides an integrated circuit comprising the delay circuit or the integrated circuit.

[0090] Based on the same inventive concept, the application further provides an interactive system comprising one master device and N slave devices, each of the slave devices comprising the delay circuit or the integrated circuit, for receiving an initial pulse sequence sent by the master device and generating a delayed pulse sequence to trigger based on the delayed pulse signal. Wherein, N is an integer and N≥1; and the preset delay time in the process of generating the delayed pulse sequence by each of the slave devices is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the slave device.

[0091] Taking the machine vision scene as an example, the master device can be a photoelectric detection device, and the slave device can be a high-precision measurement device. In the interactive system provided by the application, the delay circuit or the integrated circuit can be deployed on each of the slave devices. The difference between the pulse sequence delays in each of the slave devices is only in the different delay times. Specifically, the preset delay time of each of the slave devices is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the slave device.

[0092] In some embodiments, in the interactive system provided by the application, N delay circuits or integrated circuits described above can also be arranged in the master device, for outputting N delayed pulse sequences and sending them to the corresponding slave devices respectively, so that the slave devices trigger based on the delayed pulse signals. Wherein, the preset delay time in the process of generating the corresponding delayed pulse sequence of each of the slave devices is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the corresponding slave device.

[0093] For the case that N delay circuits or integrated circuits described above are arranged in the master device, each of the delay circuits or integrated circuits is independent in architecture and generates the delayed pulse sequence of the corresponding slave device. In the data interaction process between the master device and the N slave devices, the master device fans out N different delayed pulse sequences and transmits them to the corresponding slave devices respectively.

[0094] Based on the same inventive concept, the application further provides a delay method of a pulse sequence, as shown in Figure 7 The delay method comprises the following steps:

[0095] S1. The edge detection module receives the initial pulse sequence and generates an enable signal based on the rising and falling edges of each pulse signal in the initial pulse sequence. The first value is then input to the FIFO buffer module based on the enable signal. The first value is obtained by adding the current count value of the loop counter to a second value. The second value represents the change in the count value in the loop counter within a preset delay time. The loop counter is used to cyclically output the count value, and the time for one complete cycle of the count value is longer than the preset delay time.

[0096] S2. Receive the first value from the data write port of the FIFO buffer module, and input it to the value comparison module after the first value moves to the data read port. The amount of buffer space in the FIFO buffer module is not less than the number of pulse signal edges within a preset delay time.

[0097] S3. The numerical comparison module compares the first value input from the data reading port with the real-time count value of the loop counter, and generates a trigger signal when the two are equal.

[0098] S4. The pulse generation module receives the trigger signal and generates a pulse signal based on the trigger signal to obtain the delayed pulse sequence.

[0099] Based on the same inventive concept, embodiments of this application also provide an electronic device, such as... Figure 8 As shown, it includes a processor 801, a communication interface 802, a memory 803, and a communication bus 804, wherein the processor 801, the communication interface 802, and the memory 803 communicate with each other through the communication bus 804.

[0100] Memory 803 is used to store computer programs;

[0101] The processor 801, when executing the program stored in the memory 803, implements the above-mentioned pulse sequence delay method.

[0102] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0103] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0104] The memory can include a random access memory (RAM) and can also include a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0105] The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0106] In yet another embodiment provided in the present application, a computer readable storage medium is also provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement any of the delay method steps described above.

[0107] In yet another embodiment provided in the present application, a computer program product containing instructions is also provided, and when the computer program product is run on a computer, the computer is caused to execute any of the delay method steps in the above embodiments.

[0108] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A delay circuit for a pulse sequence, characterized by The method comprises the following steps: An edge detection module is configured to receive an initial pulse sequence, generate an enable signal according to rising and falling edges of pulse signals in the initial pulse sequence, and input a first value to a FIFO cache module based on the enable signal; wherein the first value is obtained by adding a current count value of a cycle counter to a second value; and the second value represents a variation of the count value in the cycle counter within a preset delay time; The cycle counter is configured to output the count value cyclically, and the time for one cycle of the count value is higher than the preset delay time; wherein a bit of the first value is consistent with a bit width of the cycle counter; The FIFO cache module is configured to receive the first value from a data write port, and input the first value to a value comparison module after the first value moves to a data read port; wherein a number of cache spaces in the FIFO cache module is not less than a number of edges of the pulse signals within the preset delay time; The value comparison module is configured to compare the first value with a real-time count value of the cycle counter, and generate a trigger signal when the first value is equal to the real-time count value; The pulse generation module is configured to receive the trigger signal, generate a pulse signal based on the trigger signal, and obtain a delayed pulse sequence.

2. The delay circuit of claim 1, wherein The FIFO cache module comprises a rising edge FIFO cache and a falling edge FIFO cache; The rising edge FIFO cache is configured to receive the first value from the data write port after the edge detection module generates the enable signal according to the rising edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port; The falling edge FIFO cache is configured to receive the first value from the data write port after the edge detection module generates the enable signal according to the falling edge of the initial pulse signal, and input the first value to the value comparison module after the first value moves to the data read port.

3. The delay circuit of claim 2, wherein The pulse generation module further comprises the following steps after receiving the trigger signal: If the trigger signal is obtained by comparing the first value in the rising edge FIFO cache, the pulse generation module changes an output signal from a low level to a high level to generate the delayed pulse signal; wherein an initial state of the output signal of the pulse generation module is the low level; If the trigger signal is obtained by comparing the first value in the falling edge FIFO cache, the pulse generation module changes the output signal from the high level to the low level to generate the delayed pulse signal.

4. The delay circuit of claim 1, wherein The delay circuit further comprises: An addition module connected to the cycle counter, configured to add the real-time count value of the cycle counter to the second value, and input the added value as the first value to the FIFO cache module when the edge detection module generates the enable signal; A register module comprising a pipeline register, configured to receive the pulse sequence when the time for data moving from the data write port to the data read port in the FIFO cache module is higher than the preset delay time, and delay the pulse sequence by the preset delay time based on the pipeline register to obtain the delayed pulse sequence. A reset module is configured to reset the edge detection module, the FIFO buffer module, the value comparison module, the pulse generation module, the addition module and the register module in the delay circuit after the delay circuit is initialized or the initial pulse sequence input to the edge detection module is changed.

5. An integrated circuit, characterized by The delay circuit according to any one of claims 1-4.

6. An interactive system comprising a master device and N slave devices, characterized in that, Each slave device comprises the delay circuit according to any one of claims 1-4 or the integrated circuit according to claim 5, and is configured to receive the initial pulse sequence sent by the master device and generate a delayed pulse sequence to be triggered based on the delayed pulse signal; wherein N is an integer and N≥1; and the preset delay time in the generation of the delayed pulse sequence by each slave device is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the slave device.

7. The interactive system of claim 6, wherein, The interaction system further comprises: The master device comprises N delay circuits according to any one of claims 1-4 or the integrated circuit according to claim 5, and is configured to output N delayed pulse sequences and send them to corresponding slave devices respectively, so that the slave devices are triggered based on the delayed pulse signals; wherein the preset delay time in the generation of the corresponding delayed pulse sequence by each slave device is obtained by calculating the time difference between the time when the master device sends the initial pulse sequence and the preset triggering time of the corresponding slave device.

8. A method of delaying a pulse sequence, characterized by, The delay method comprises: The edge detection module receives the initial pulse sequence, and generates an enable signal based on the rising edge and the falling edge of the pulse signal in the initial pulse sequence, so as to input a first value to the FIFO buffer module based on the enable signal; wherein the first value is obtained by adding a second value to the current count value of a cycle counter; the second value represents the change amount of the count value in the cycle counter within the preset delay time; the cycle counter is configured to cyclically output the count value, and the time for one cycle of the count value is higher than the preset delay time; the bit of the first value is consistent with the bit width of the cycle counter; The FIFO buffer module receives the first value from the data write port, and inputs the first value to the value comparison module after the first value moves to the data read port; wherein the number of the buffer spaces in the FIFO buffer module is not less than the number of edges of the pulse signal within the preset delay time; The value comparison module compares the first value with the real-time count value of the cycle counter, and generates a trigger signal when the two values are equal. The pulse generation module receives the trigger signal, and generates a pulse signal based on the trigger signal to obtain the delayed pulse sequence.

9. An electronic device, comprising: The system comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus; The memory is configured to store a computer program; The processor is configured to execute the program stored in the memory, and implement the delay method in claim 8.

10. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and the computer program is executed by the processor to implement the delay method in claim 8.

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