Method for manufacturing a via structure and circuit board
By filling blind vias and stacked vias with conductive dielectric, the problem of delamination and bursting caused by thermal expansion in high-density stacked via structures is solved, ensuring the reliability of the circuit board and the wiring area, and improving circuit performance and durability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENNAN CIRCUITS
- Filing Date
- 2025-05-06
- Publication Date
- 2026-06-19
AI Technical Summary
In high-density stacked via structures, the high CTE value of resin-filled vias leads to expansion at high temperatures, causing delamination and bursting risks, which affect the reliability of the circuit board.
The blind vias and stacked vias are filled with conductive media of the same material to avoid delamination caused by thermal expansion. The internally interconnected stacked via structure is formed by steps such as creating anti-plating ink, copper plating, stripping, filling with conductive media and curing on a multilayer board.
This effectively avoids delamination and bursting caused by thermal expansion of the stacked via structure, ensuring the reliability of the circuit board and the wiring area, and improving circuit performance and durability.
Smart Images
Figure CN120568620B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of printed circuit board technology, and in particular to a method for manufacturing a stacked via structure and a circuit board. Background Technology
[0002] As electronic products pursue ultimate performance, multi-functional miniaturization has become the mainstream design approach for many products. As the basic carrier board for all components to perform their functions, PCBs are constantly increasing their wiring density in order to accommodate more assembly. As a result, high-density interconnect PCB design is becoming one of the ideal solutions.
[0003] One characteristic of high-density vias is the use of multi-level blind vias, buried vias, and stacked via designs. In stacked via designs, through-holes are first fabricated, then filled with resin after electroplating, followed by copper overlay, and finally laser-fabricated blind vias are created on top of the through-holes. This stacked via structure, due to the high CTE value of the resin filling the through-holes, expands under high-temperature operating conditions, ultimately leading to a reliability risk of delamination and bursting at the location where the resin and the copper overlay meet. Summary of the Invention
[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for manufacturing a stacked via structure, in which both the plug vias and the stacked vias are filled with a conductive medium of the same material. This avoids thermal expansion and delamination within the stacked via structure, thus ensuring the reliability of the circuit board and maximizing the wiring area of the circuit board.
[0005] This invention also proposes a circuit board.
[0006] A method for manufacturing a stacked via structure according to a first aspect of the present invention includes the following steps: S1: filling the blind hole locations of a first core board with resist plating ink; S2: laminating the first core board into a multilayer board, wherein the first core board is located on the outermost layer of the multilayer board; S3: fabricating blind holes on the multilayer board, wherein resist plating ink is disposed on the periphery of one end of the blind hole; S4: performing copper plating on the multilayer board, wherein the hole wall of the blind hole and the surface of the resist plating ink are both covered with copper; S5: washing the multilayer board to remove the resist plating ink to obtain plugged vias; S6: filling the plugged vias with a conductive medium; S7: laminating the multilayer board to add layers; S8: forming stacked vias at the locations of the plugged vias on the laminated circuit board; S9: filling the stacked vias with a conductive medium and curing it to obtain an internally interconnected stacked via structure.
[0007] According to the fabrication method of the stacked via structure of the present invention, both the plug via and the stacked via are filled with a conductive medium. The same material can prevent the internal thermal expansion and delamination of the stacked via structure from causing it to burst, thus ensuring the reliability of the circuit board.
[0008] According to some embodiments of the present invention, before step S7, the method further includes: curing the conductive medium within the plug hole and forming an inner layer pattern on the surface of the multilayer board.
[0009] According to some embodiments of the present invention, before step S8, the method further includes: opening a window at the position corresponding to the plug hole in the multilayer board.
[0010] According to some embodiments of the present invention, before step S6, the method further includes: thickening the hole wall of the blind hole with copper plating.
[0011] According to some embodiments of the present invention, the size of the anti-plating ink is larger than the size of the blind hole.
[0012] According to some embodiments of the present invention, the step of filling the blind hole location to be drilled in the first core board with anti-plating ink includes: opening a filling groove at the blind hole location to be drilled in the first core board, and filling the filling groove with anti-plating ink.
[0013] According to some embodiments of the present invention, the step of filling the blind hole location to be drilled in the first core board with anti-plating ink includes: opening a filling hole at the blind hole location to be drilled in the first core board, and filling the filling hole with anti-plating ink.
[0014] According to some embodiments of the present invention, the multilayer board includes: a prepreg, copper foil, a first core board and a second core board, wherein inner layer circuitry is disposed on the first core board and the second core board.
[0015] According to a second aspect of the present invention, a circuit board includes a stacked via structure, wherein the stacked via structure is manufactured using the aforementioned manufacturing method.
[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0018] Figure 1 This is a flowchart of a method for manufacturing a printed circuit board according to an embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of a filling hole being formed in the first core board according to an embodiment of the present invention;
[0020] Figure 3 The first core board according to an embodiment of the present invention is filled with anti-plating ink.
[0021] Figure 4This is a schematic diagram of laminating a first core board into a multilayer board according to an embodiment of the present invention;
[0022] Figure 5 This is a schematic diagram of drilling blind holes in a multilayer board according to an embodiment of the present invention;
[0023] Figure 6 This is a schematic diagram of copper plating on a multilayer board according to an embodiment of the present invention;
[0024] Figure 7 This is a schematic diagram of removing anti-plating ink according to an embodiment of the present invention;
[0025] Figure 8 This is a schematic diagram of thickening the copper plating on the wall of a blind hole according to an embodiment of the present invention;
[0026] Figure 9 This is a schematic diagram of filling a via with a conductive medium according to an embodiment of the present invention;
[0027] Figure 10 This is a schematic diagram of multilayer board lamination according to an embodiment of the present invention;
[0028] Figure 11 This is a schematic diagram of drilling stacked holes in a multilayer board according to an embodiment of the present invention;
[0029] Figure 12 This is a schematic diagram of filling the stacked holes with a conductive medium according to an embodiment of the present invention.
[0030] Figure label:
[0031] 11. First core board; 111. Insulating layer; 112. Copper layer; 113. Filler hole; 12. Anti-plating ink; 13. Multilayer board; 14. Blind hole; 15. Plug hole; 16. Conductive medium; 17. Stacked holes; 18. Stacked hole structure. Detailed Implementation
[0032] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.
[0033] The following is for reference. Figures 1-12 A method for manufacturing a stacked via structure 18 according to an embodiment of the present invention is described, and a circuit board manufactured by the method for manufacturing the stacked via structure 18 is described.
[0034] like Figure 1 As shown, the method for manufacturing the stacked hole structure 18 includes the following steps:
[0035] S1: Fill the blind hole 14 that needs to be drilled in the first core board 11 with anti-plating ink 12.
[0036] like Figure 3As shown, the first core board 11 includes an insulating layer 111 and copper layers 112 on both sides. The upper and lower surfaces of the insulating layer 111 are covered with copper layers 112, that is, the upper and lower surfaces of the insulating layer 111 are covered with copper foil. After determining which locations of the first core board 11 require drilling blind holes 14, grooves or holes are made at the locations of the first core board 11 that require back drilling, and anti-plating ink 12 is filled into the grooves or holes.
[0037] The anti-plating ink 12 exhibits excellent adhesion and corrosion resistance, maintaining stable performance under various electroplating conditions. During the electroplating process, the anti-plating ink 12 forms a stable chemical bond or physical barrier with the metal surface, thereby preventing the electroplating solution from corroding the ink 12.
[0038] S2: The first core board 11 is laminated into a multilayer board 13, and the first core board 11 is located on the outermost layer of the multilayer board 13.
[0039] like Figure 4 As shown, the first core board 11 is laminated with other core boards to form a multilayer board 13. The multilayer board 13 can be laid out in layers, allowing signal traces of different functional modules to be placed on different layers. This can improve circuit performance and reduce signal interference. Through lamination, signal lines, power lines, and ground lines can be laid between different layers to form a good signal loop and improve the rigidity and durability of the circuit board.
[0040] Figures 2-12 In this example, the first core board 11 is located on the top layer of the multilayer board 13.
[0041] S3: A blind hole 14 is made on the multilayer board 13, and an anti-plating ink 12 is provided on the periphery of one end of the blind hole 14.
[0042] like Figure 5 As shown, a blind hole 14 is drilled on the multilayer board 13. The first core board 11 is located on the side of the through hole back drilled, and the anti-plating ink 12 corresponds to the blind hole 14. The size of the anti-plating ink 12 is larger than that of the blind hole 14. Then, a part of the anti-plating ink 12 that is opposite to the through hole is removed, and the remaining part of the anti-plating ink 12 is arranged around one end of the through hole.
[0043] S4: The multilayer board 13 is subjected to copper plating, and the hole walls of the blind hole 14 and the surface of the anti-plating ink 12 are covered with copper.
[0044] like Figure 6 As shown, in step S4, the surface of the multilayer board 13 is subjected to overall copper plating, copper is plated on the inner wall of the blind hole 14, and copper is plated on the surface of the resist ink 12, so that the hole wall of the blind hole 14 and the surface of the resist ink 12 are covered with copper.
[0045] Holes formed by mechanical drilling or laser drilling have walls primarily composed of non-conductive materials. If electroplating is performed directly, current cannot pass through these hole walls, preventing copper plating. Therefore, a copper plating process is required to first deposit copper onto the hole walls of blind via 14, thus enabling the copper plating to adhere.
[0046] S5: The multilayer board 13 is stripped to remove the anti-plating ink 12 in order to obtain the plugged hole 15.
[0047] like Figure 7 As shown, the method for removing the anti-plating ink 12 can be either chemical or physical removal.
[0048] The resist ink 12 can be removed in an alkaline environment. While removing the resist ink 12, the copper on the surface of the resist ink 12 is also removed, thus exposing the position of the first core board 11 filled with the resist ink 12. The plug hole 15 includes the blind hole 14 and the opening portion on the first core board 11.
[0049] S6: Fill the hole 15 with conductive medium 16.
[0050] like Figure 9 As shown, the conductive medium 16 can be conductive ink, conductive copper paste, or other conductive materials with low CTE (coefficient of thermal expansion) fillers. After the conductive medium 16 is filled into the plug hole 15 and cured, the surface of the conductive medium 16 is flush with the surface of the first core board 11.
[0051] A vacuum plugging machine can be used to fill the plugging hole 15 with conductive medium 16. Vacuum filling of conductive medium 16 can prevent air from entering the plugging hole 15 and causing voids, which would affect the tightness of the filling of conductive medium 16.
[0052] S7: Perform lamination on the multilayer board 13.
[0053] like Figure 10 As shown, the two surfaces of the multilayer board 13 are laminated. First, the surface of the first core board 11 is roughened. Then, copper foil is pressed to the multilayer board 13 with an adhesive using a hot press. After pressing, the adhesive serves as a new insulating dielectric layer, and the outer copper foil serves as a new upper copper layer 112.
[0054] The adhesive can be a prepreg or a thermosetting adhesive.
[0055] S8: Create a stacked hole 17 at the position corresponding to the plug hole 15 on the circuit board.
[0056] according to Figure 11As shown, the multilayer board 13 obtained in step S7 is drilled. Laser drilling can be used to drill stacked holes 17 at the positions corresponding to blind holes 14 in the multilayer board 13 after the addition of layers. The opening of the stacked hole 17 is located in the new upper copper layer 112, and the bottom of the hole is the surface of the first core board 11. The bottom of the hole is the conductive medium 16 in the plug hole 15.
[0057] S9: Fill the stacked vias 17 with conductive medium 16 and cure it to obtain an internally interconnected stacked via structure 18.
[0058] like Figure 12 As shown, the same conductive medium 16 as that in the plug hole 15 is filled into the stacked hole 17 and the conductive medium 16 is cured. Then the conductive medium 16 in the stacked hole 17 is electrically connected to the conductive medium 16 in the plug hole 15, thereby obtaining the internally interconnected stacked hole structure 18.
[0059] Because the plug vias 15 and 17 are made of the same material, their coefficients of thermal expansion (CTE) are the same, eliminating the risk of thermal expansion leading to delamination and bursting. Furthermore, air bubbles and voids in the plug via 15 can be ignored because the inner layer has been plated with copper 112, ensuring the foundation for internal interconnection. This allows for the creation of a stacked via structure 18 that saves on wiring and eliminates reliability risks. The non-staggered design of the plug vias 15 and 17 fully preserves the wiring area on the circuit board.
[0060] According to some embodiments of the present invention, before S7, the process further includes: curing the conductive medium 16 within the plug hole 15 and forming an inner layer pattern on the multilayer board 13.
[0061] In other words, in step S6, after filling the via 15 with conductive medium 16, the conductive medium 16 inside the via 15 is cured. The upper surface of the conductive medium 16 is flush with the first core board 11. Inner layer patterns are made on the upper and lower surfaces of the multilayer board 13, and inner layer pads are made at the positions of the via 15. After the inner layer patterns are made, the surface of the inner layer patterns is roughened. Then, copper foil is pressed to the multilayer board 13 with adhesive using a hot press. After pressing, the adhesive serves as a new insulating dielectric layer, and the outer copper foil serves as a new upper copper layer 112.
[0062] According to some embodiments of the present invention, before step S8, a window is made at the position corresponding to the plug hole 15 on the multilayer board 13. Before drilling the stacked hole 17, a window is made at the position opposite to the plug hole 15 on the multilayer board 13 to facilitate subsequent drilling of the stacked hole 17 on the multilayer board 13.
[0063] like Figure 8As shown, before step S6, the process includes thickening the copper plating on the wall of the blind via 14. Before step S6, the wall of the blind via 14 needs to be thickened with copper plating. After copper plating in step S4, a thin copper layer 112 adheres to the wall of the blind via 14, but this can easily cause partial disconnection of the inner layer circuitry of the multilayer board 13. Thickening the copper plating on the wall can improve the reliability of the inner layer interconnection, meet the interlayer interconnection requirements of the circuit board, and greatly increase the flexibility of the interlayer interconnection density. When bubbles and voids exist within the conductive medium 16, the thickened copper layer 112 on the wall of the blind via 14 can avoid the open-circuit reliability risk of the inner layer interconnection.
[0064] Furthermore, the size of the resist ink 12 is larger than the size of the blind via 14. Specifically, the size of the resist ink 12 is the same as the size of the upper surface of the conductive medium 16 filling the via 15. The upper surface of the conductive medium 16 is used to make the inner layer pads. The size of the inner layer pads needs to be larger than the size of the blind via 14 to facilitate the soldering operation.
[0065] In some embodiments, filling the blind hole 14 position of the first core board 11 with anti-plating ink 12 includes: forming a filling groove at the blind hole 14 position of the first core board 11, and filling the filling groove with anti-plating ink 12. Specifically, a filling groove can be formed at the position of the blind hole 14 on the first core board 11. The depth of the filling groove is greater than the copper foil thickness on the surface of the first core board 11 and less than the thickness of the first core board 11. Anti-plating ink 12 is filled into the filling groove and cured. The cured anti-plating ink 12 is approximately flush with the upper surface of the first core board 11, which facilitates the copper plating process of the multilayer board 13.
[0066] Furthermore, the filling groove can be a regular shape or an irregular shape. For ease of manufacturing, the filling groove can be a regular shape, such as a rectangle, a circle, or an ellipse.
[0067] The fill groove is larger than the blind via 14 so that the size of the resist ink 12 is larger than the blind via 14, which facilitates the fabrication of inner layer pads on the conductive medium 16 within the fill groove. The projection of the fill groove onto the first core board 11 can be circular, with a diameter larger than that of the through hole, reducing the amount of resist ink 12 used in the circuit board fabrication process and lowering manufacturing costs.
[0068] In addition, the projection of the filling groove on the first core board 11 can be elliptical. Since the size of the dry film is larger than the through hole and the size of the anti-plating ink 12 is larger than the size of the dry film, the minimum diameter of the ellipse must be larger than the diameter of the through hole to ensure that the etching solution will not enter the through hole and erode the copper during the exposure and development process, thus avoiding open circuits in the inner layer connection of the multilayer board 13.
[0069] like Figure 1As shown, filling the blind hole 14 position of the first core board 11 with anti-plating ink 12 includes: opening a filling hole 113 at the blind hole 14 position of the first core board 11, and filling the filling hole 113 with anti-plating ink 12. Specifically, the filling hole 113 can be opened at the position corresponding to the blind hole 14 on the first core board 11. The depth of the filling hole 113 is greater than the copper foil thickness on the surface of the first core board 11 and less than the thickness of the first core board 11. The anti-plating ink 12 is filled into the filling hole 113 and cured. The cured anti-plating ink 12 is approximately flush with the upper surface of the first core board 11, which facilitates the copper plating process of the multilayer board 13.
[0070] The filling hole 113 can be a regular shape or an irregular shape. For ease of manufacturing, the filling hole 113 can be a regular shape, such as a rectangle, a circle, or an ellipse.
[0071] Combination Figures 2-12 As shown, the multilayer board 13 includes: a prepreg, copper foil, a first core board 11, and a second core board. Inner layer circuitry is provided on the first core board 11 and the second core board. The multilayer board 13 is a multilayer board 13 in which the first core board 11, the second core board, and the copper foil are laminated together by the prepreg, and the first core board 11 and the second core board have already been fabricated with inner layer circuitry before lamination.
[0072] According to a second aspect of the present invention, a circuit board includes a stacked via structure 18, which is manufactured using the above-described manufacturing method.
[0073] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0074] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
[0075] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A method for manufacturing a stacked hole structure, characterized in that, Includes the following steps: S1: Fill the blind hole (14) that needs to be drilled on the first core board (11) with anti-plating ink (12). S2: The first core board (11) is laminated into a multilayer board (13), and the first core board (11) is located on the outermost layer of the multilayer board (13); S3: A blind hole (14) is made on the multilayer board (13), and an anti-plating ink (12) is provided on the periphery of one end of the blind hole (14). S4: The multilayer board (13) is subjected to copper plating, and the hole wall of the blind hole (14) and the surface of the anti-plating ink (12) are covered with copper. S5: The multilayer board (13) is washed to remove the anti-plating ink (12) to obtain a plug (15). S6: Fill the plug hole (15) with a conductive medium (16); S7: Perform lamination on the multilayer board (13); S8: A stacked hole (17) is opened at the position corresponding to the plug hole (15) in the multilayer board (13) after the addition of layers. S9: Fill the stacked holes (17) with a conductive medium (16) and cure it to obtain an internally interconnected stacked hole structure (18).
2. The method of claim 1, wherein Before S7, the process further includes: curing the conductive medium (16) inside the plug hole (15) and creating an inner layer pattern on the surface of the multilayer board (13).
3. The method of claim 1, wherein Before step S8, the method further includes: opening a window at the position of the plug hole (15) on the multilayer board (13).
4. The method of claim 1, wherein Before step S6, the method further includes: The wall of the blind hole (14) is thickened with copper plating.
5. The method of claim 1, wherein The size of the anti-plating ink (12) is larger than the size of the blind hole (14).
6. The method of claim 1, wherein The filling of anti-plating ink (12) at the location of the blind hole (14) to be drilled in the first core board (11) includes: A filling groove is made at the location where a blind hole (14) needs to be drilled on the first core board (11), and anti-plating ink (12) is filled in the filling groove.
7. The method of claim 1, wherein The filling of anti-plating ink (12) at the location of the blind hole (14) to be drilled in the first core board (11) includes: A filling hole (113) is opened at the location where a blind hole (14) needs to be drilled on the first core board (11), and anti-plating ink (12) is filled in the filling hole (113).
8. The method of claim 1, wherein The multilayer board (13) includes: a prepreg, copper foil, a first core board (11) and a second core board, wherein inner layer circuitry is provided on the first core board (11) and the second core board.
9. A circuit board, characterized by include: The stacked hole structure (18) is manufactured by the manufacturing method described in any one of claims 1-8.