Display device

Abstract

A display device includes: a first substrate; a plurality of top pads disposed over the first substrate; a second substrate disposed below the first substrate; a plurality of bottom pads disposed under the second substrate; a plurality of side lines disposed on side surfaces of the first substrate and the second substrate to connect the plurality of top pads and the plurality of bottom pads; and a plurality of ground pads disposed in first edges of the first substrate and the second substrate, the plurality of top pads and the plurality of bottom pads each including: a plurality of first pads disposed in a first pad region of the first edges of the first substrate and the second substrate; and a plurality of second pads disposed in a second pad region of a second edge of the first substrate and the second substrate, the plurality of first pads being applied with a high potential voltage, the plurality of second pads being applied with a low potential voltage, the plurality of ground pads are disposed in the first edge of the first substrate and the first edge of the second substrate to be spaced apart from each other across the plurality of first pads. Therefore, the flow of overcurrent into the display device is suppressed to improve the reliability thereof.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028384 filed on February 27, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0004] As displays used for computers, televisions, mobile phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] Application ranges of display devices include not only monitors of computers and televisions but also personal digital assistants, and display devices having a large display area and reduced size and weight are being studied.

[0006] In addition, display devices including light-emitting diodes (LEDs) have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are highly reliable, resulting in a longer lifespan than liquid crystal display devices or organic light-emitting display devices. In addition, LEDs have a fast response speed, excellent luminous efficiency, and strong impact resistance, resulting in excellent stability and the ability to display images with high brightness. Summary of the Invention

[0007] One object to be achieved by the present disclosure is to provide a display device with improved reliability.

[0008] Another object to be achieved by the present disclosure is to provide a display device that suppresses a short circuit problem by dissipating static electricity.

[0009] Still another object to be achieved by the present disclosure is to provide a display device that grounds static electricity generated on a rear surface.

[0010] The objects of the present disclosure are not limited to the above objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0011] According to one aspect of the present disclosure, a display device is provided. The display device includes: a first substrate; a plurality of top pads arranged above the first substrate; a second substrate arranged below the first substrate; a plurality of bottom pads arranged below the second substrate; a plurality of lateral lines arranged on the side surfaces of the first substrate and the side surfaces of the second substrate to connect the plurality of top pads and the plurality of bottom pads; and a plurality of ground pads arranged in a first edge of the first substrate and a first edge of the second substrate, wherein the plurality of top pads include: a plurality of first pads arranged in a first pad region of the first edge of the first substrate; and a second pad region arranged in a second edge of the first substrate. The plurality of second solder pads in the first edge of the second substrate include: a plurality of first solder pads arranged in a first solder pad area of ​​the first edge of the second substrate; and a plurality of second solder pads arranged in a second solder pad area of ​​the second edge of the second substrate, wherein the plurality of first solder pads of the plurality of top solder pads and the plurality of bottom solder pads are applied with a high potential voltage, the plurality of second solder pads of the plurality of top solder pads and the plurality of bottom solder pads are applied with a low potential voltage, and the plurality of grounding pads are arranged in the first edge of the first substrate and the first edge of the second substrate to be spaced apart from each other by the plurality of first solder pads of the plurality of top solder pads and the plurality of bottom solder pads.

[0012] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0013] According to the present disclosure, the static electricity generation problem can be suppressed by improving the structure of the pad unit.

[0014] According to the present disclosure, an overcurrent is suppressed from flowing into a display device, thereby improving the reliability of the display device.

[0015] According to the present disclosure, an electrostatic discharge path is formed, thereby improving the burn-in phenomenon of a display device.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 3 is an enlarged plan view of a first substrate of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 4 is an enlarged plan view of a second substrate of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 6 is a cross-sectional view of a pad region of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 7A is a cross-sectional view of a top pad of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 7B is a cross-sectional view of a bottom pad of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 8 is a cross-sectional view of a ground pad of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 9 It is along Figure 4 A cross-sectional view of the second substrate taken along line AA';

[0029] Figure 10 It is along Figure 4 sectional views of the second substrate taken along lines BB' and CC'. DETAILED DESCRIPTION

[0030] The advantages and features of the present disclosure and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The exemplary embodiments described in detail below will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example to enable those skilled in the art to fully understand the disclosure of the present invention and the scope of the present disclosure.

[0031] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout the application. In addition, in the description below the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless the term "only" is used in these terms. Any reference in the singular may include the plural, unless otherwise expressly stated.

[0032] Even if not explicitly stated, parts are interpreted as including the usual margin of error.

[0033] When terms such as “on,” “above,” “below,” and “after” are used to describe the positional relationship between two parts, one or more parts may be set between the two parts unless these terms use the terms “immediately” or “directly”.

[0034] When an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on the other element or layer or other elements or layers may be interposed therebetween.

[0035] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, within the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0036] Like reference numbers generally refer to like elements throughout the application.

[0037] The size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown in the drawings.

[0038] The features of the various embodiments of the present disclosure may be combined or coupled with each other in part or in whole, and may be interconnected and operated in various technical ways, and the various embodiments may be implemented independently of each other, or in association with each other.

[0039] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 Schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1Only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device 100 are illustrated.

[0041] Reference Figure 1 The display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD providing various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0042] The gate driver GD provides a plurality of scanning signals to the plurality of scanning lines SL according to a plurality of gate control signals provided from the timing controller TC. Figure 1 4. It is illustrated that one gate driver GD is provided separately from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0043] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0044] The timing controller TC arranges externally input image data and supplies the image data to the data driver DD. The timing controller TC generates gate control signals and data control signals using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0045] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and the plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, although not shown in the figure, each of the plurality of sub-pixels SP can be connected to a high-potential power line, a low-potential power line, a reference line, etc.

[0046] An active area AA and a non-active area NA surrounding the active area AA may be defined in the display panel PN.

[0047] The active area AA is the area of ​​the display device 100 where images are displayed. Multiple sub-pixels SP constituting multiple pixels PX and circuits for driving the multiple sub-pixels SP may be provided in the active area AA. The multiple sub-pixels SP are the smallest unit constituting the active area AA, and n sub-pixels SP may form one pixel PX. Each of the multiple sub-pixels SP may include a light-emitting diode (LED), a thin-film transistor (TFT) for driving the light-emitting diode, and the like. The multiple light-emitting diodes may be defined differently depending on the type of display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diodes may be light-emitting diodes (LEDs) or micro light-emitting diodes (microLEDs).

[0048] A plurality of signal lines are provided in the active area AA to transmit various signals to the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL that respectively provide data voltages to the plurality of sub-pixels SP, a plurality of scan lines SL that respectively provide gate voltages to the plurality of sub-pixels SP, and the like. The plurality of scan lines SL extend in one direction in the active area AA to connect to the plurality of sub-pixels SP, while the plurality of data lines DL extend in a direction different from the one direction in the active area AA to connect to the plurality of sub-pixels SP. Furthermore, low-potential power lines, high-potential power lines, and the like may be further provided in the display area AA. However, the present disclosure is not limited thereto.

[0049] The non-active area NA is an area where no image is displayed, and thus the non-active area NA can be defined as an area extending from the active area AA. Lines, pad electrodes, or driver ICs such as gate driver ICs or data driver ICs that transmit signals to the sub-pixels SP in the active area AA may be disposed in the non-active area NA. The non-active area NA may be located on the rear surface of the display panel PN, i.e., on a surface where no sub-pixels SP are disposed, or may be omitted, without limitation to the example shown in this figure.

[0050] In addition, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active area NA in a gate-in-panel (GIP) manner, or can be installed between multiple sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in a separate flexible film and a printed circuit board, and can be connected to the display panel PN by combining the flexible film and the printed circuit board to the pad electrode formed in the non-active area NA of the display panel PN. When the gate driver GD is installed in a GIP manner and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode in the non-active area NA, it is necessary to ensure the area in the non-active area NA where the gate driver GD and the pad electrode are to be set. In this way, the border will increase.

[0051] In contrast, when the gate driver GD is installed in the active area AA in a GIA manner, and side lines SRL are formed to connect the signal lines on the front surface of the display panel PN with the pad electrodes on the rear surface of the display panel PN to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero border with no border can be substantially achieved, which will be referred to as Figure 2A and Figure 2B Describe in more detail.

[0052] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure.

[0053] A plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are provided in the non-active area NA of the display panel PN. For example, top pads TPAD for transmitting signals to the plurality of sub-pixels SP are provided in the non-active area NA on the front surface of the display panel PN. Bottom pads BPAD for electrically connecting to driving components such as a flexible film and a printed circuit board are provided in the non-active area NA on the rear surface of the display panel PN.

[0054] In this case, although not shown in the drawings, various signal lines connected to the plurality of sub-pixels SP, for example, scan lines SL, data lines DL, etc., extend from the active area AA to the non-active area NA to be electrically connected to the top pad TPAD.

[0055] Side lines SRL are provided along the sides of the display panel PN. The side lines SRL electrically connect top pads TPAD on the front surface of the display panel PN to bottom pads BPAD on the rear surface of the display panel PN. Therefore, signals from driving components on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP via the bottom pads BPAD, the side lines SRL, and the top pads TPAD. This forms a signal transmission path from the front surface of the display panel PN to the rear surface of the display panel PN, thereby minimizing the area of ​​the non-active area NA of the display panel PN.

[0056] Reference Figure 2B By connecting multiple display devices 100, a spliced ​​display device TD with a large screen size can be realized. Figure 2A As shown in , when the spliced ​​display device TD is implemented using the display device 100 with minimized bezels, a seam area between the display devices 100 where no image is displayed is minimized, so that display quality can be improved.

[0057] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in the one display device 100. Therefore, the distance between the pixels PX of the display device 100 is configured to be constant, thereby minimizing a seam area.

[0058] but, Figure 2A and Figure 2B For example, the display device 100 according to the exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0059] In addition, the display panel PN may include a first substrate and a second substrate.

[0060] In the following, reference will be made to Figure 3 and Figure 4 The first substrate and the second substrate are described in detail.

[0061] Figure 3 is an enlarged plan view of a first substrate of a display device according to an exemplary embodiment of the present disclosure.

[0062] First, the display panel PN includes a first substrate 110. The first substrate 110 supports various components disposed above the display device 100 and may be an insulating substrate. A plurality of pixels PX are formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. Furthermore, the first substrate 110 may include a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a flexible plastic material.

[0063] Reference Figure 3 A plurality of pixel areas UPA, a plurality of gate driving areas GA, and a plurality of top pad areas are provided in the first substrate 110. The plurality of pixel areas UPA and the plurality of gate driving areas GA may be included in the active area AA of the display panel PN.

[0064] First, multiple pixel areas UPA are areas where multiple pixels PX are arranged. The multiple pixel areas UPA can be arranged in multiple rows and columns. Each of the multiple pixels PX arranged in the multiple pixel areas UPA includes multiple sub-pixels SP. Each of the multiple sub-pixels SP includes a light-emitting diode LED and a pixel circuit to independently emit light.

[0065] The display panel PN includes a plurality of pixels PX, each formed of a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode LED and a pixel circuit to independently emit light. A pixel may include one or more first sub-pixels, one or more second sub-pixels, and one or more third sub-pixels. For example, a pixel may include two first sub-pixels, two second sub-pixels, and two third sub-pixels. In this case, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel, but the present invention is not limited thereto.

[0066] The plurality of gate drive areas GA are regions where gate drivers GD are disposed. The gate drivers GD may be installed in the active area AA in a gate-in-active-area (GIA) configuration. For example, the gate drive area GA may be formed between the plurality of pixel areas UPA along the row and / or column directions. The gate drivers GD formed in the gate drive area GA may provide scan signals to the plurality of scan lines SL.

[0067] The gate driver GD provided in the gate drive area GA may include a circuit for outputting a scan signal. In this case, for example, the gate driver GD may include a plurality of transistors and / or capacitors. Here, the active layers of the plurality of transistors may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but are not limited thereto. The active layers of the plurality of transistors may be formed of the same or different materials. In addition, the active layers of the transistors of the gate driver may be formed of the same material as the active layers of the respective transistors of the pixel circuit or of different materials.

[0068] The plurality of top pad areas include a first top pad area TPA1 located in the first edge EG1 of the display panel PN, and a second top pad area TPA2 located in the second edge EG2 of the display panel PN.

[0069] The first and second top pad areas TPA1 and TPA2 are areas where a plurality of top pads TPAD are disposed above the first substrate 110. The plurality of top pads TPAD may transmit various signals to various wirings extending in the column direction in the active area AA.

[0070] A plurality of first top pads TPAD1 may be provided in the first top pad area TPA1. The plurality of first top pads TPAD1 may include top pads TPAD to which different signals are applied. For example, the first top pads TPAD1 may include a top data pad TDP for transmitting a data voltage to a top data line TDL; a top gate pad TGP for transmitting a clock signal, a start signal, a gate low voltage, and a gate high voltage for driving the gate driver GD; and a top high potential power pad TVP1 for transmitting a high potential power voltage to a top high potential power line TVL1.

[0071] A plurality of second top pads TPAD2 may be provided in the second top pad area TPA2. In this case, the plurality of second top pads TPAD2 may be different from the plurality of first top pads TPAD1. For example, the plurality of second top pads TPAD2 may include a top low potential power pad TVP2 that transmits a low potential power voltage to the plurality of top low potential power lines TVL2.

[0072] At this time, the plurality of top pads TPAD may be formed to have different sizes. For example, the plurality of top data pads TDP connected one-to-one with the plurality of top data lines TDL among the plurality of first top pads TPAD1 may have a smaller width, and the top high potential power pad TVP1 and the top gate pad TGP may have a larger width. In addition, the top low potential power pad TVP2 as the plurality of second top pads TPAD2 may also have a larger width than the plurality of top data pads TDP, and the top low potential power pads TVP2 may have different widths. However, Figure 3 The widths of the top data pad TDP, the top gate pad TGP, the top high potential power pad TVP1, and the top low potential power pad TVP2 shown in FIG. 8 are exemplary, and thus the top pad TPAD may be configured in various sizes without limitation thereto.

[0073] A plurality of top grounding pads TGNP may be disposed over the first substrate 110 .

[0074] A plurality of top ground pads TGNP may be disposed in the first edge EG1 of the first substrate 110. For example, the plurality of top ground pads TGNP may be disposed in the first top pad area TPA1. Furthermore, the plurality of top ground pads TGNP may be disposed adjacent to the outer peripheral area of ​​the first substrate 110. For example, the plurality of top ground pads TGNP may be disposed so as to be spaced apart from each other via the plurality of first top pads TPAD1.

[0075] The plurality of top ground pads TGNP may be respectively connected to a plurality of bottom ground pads described below.

[0076] In addition, in order to reduce the border of the display panel PN, the edge of the display panel PN may be cut off. A plurality of pixels PX, a plurality of wirings, and a plurality of top pads TPAD are formed on the initial first substrate 110i, and the edge portion of the initial first substrate 110i is ground to reduce the border area. During the grinding process, a portion of the initial first substrate 110i is removed, thereby forming a first substrate 110 with a smaller size. At this time, a portion of the plurality of top pads TPAD and wirings provided in the edge of the first substrate 110 may be removed. Therefore, only a portion of the plurality of top pads TPAD may remain on the first substrate 110.

[0077] A plurality of top data lines TDL extending in a column direction from a plurality of top pads TPAD are disposed in a plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of top data lines TDL may extend from the plurality of top data pads TDP of the first top pad area TPA1 to the plurality of pixel areas UPA. The plurality of top data lines TDL extend in a column direction and may be disposed to overlap the plurality of pixel areas UPA. Thus, the plurality of top data lines TDL may transmit a data voltage to the pixel circuit of each of the plurality of sub-pixels SP.

[0078] A plurality of top high potential power lines TVL1 extending in the column direction are provided in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. A portion of the plurality of top high potential power lines TVL1 extends from the top high potential power pad TVP1 of the first top pad area TPA1 to the plurality of pixel areas UPA to transmit a high potential power voltage to the light emitting diodes LED of the plurality of sub-pixels SP. The remaining portion of the plurality of top high potential power lines TVL1 can be electrically connected to other top high potential power lines TVL1 via the top auxiliary high potential power line TAVL1 described below. Figure 3 In the embodiment, for convenience of description, although one top high potential power supply line TVL1 and one top high potential power supply pad TVP1 are illustrated as being provided, a plurality of top high potential power supply lines TVL1 and a plurality of top high potential power supply pads TVP1 may be provided.

[0079] A plurality of top low-potential power lines TVL2 extending in the column direction are disposed in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. At least a portion of the plurality of top low-potential power lines TVL2 extends from the top low-potential power pad TVP2 of the second top pad area TPA2 to the plurality of pixel areas UPA to transmit a low-potential power supply voltage to the pixel circuit of each of the plurality of sub-pixels SP. Other portions of the plurality of top low-potential power lines TVL2 can be electrically connected to other top low-potential power lines TVL2 via a top auxiliary low-potential power line TAVL2 described below.

[0080] A plurality of top scan lines TSL extending in the row direction are disposed in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of top scan lines TSL extend in the row direction and may be disposed to pass through the plurality of pixel areas UPA and the plurality of gate drive areas GA. The plurality of top scan lines TSL may transmit scan signals from the gate driver GD to the pixel circuits of the plurality of sub-pixels SP.

[0081] A plurality of top auxiliary high-potential power lines TAVL1 extending in the row direction are disposed in a plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of top auxiliary high-potential power lines TAVL1 may be disposed in regions between the plurality of pixel areas UPA. The plurality of top auxiliary high-potential power lines TAVL1 extending in the row direction are electrically connected to the plurality of top high-potential power lines TVL1 extending in the column direction via contact holes, thereby forming a mesh structure. Therefore, the plurality of top auxiliary high-potential power lines TAVL1 and the plurality of top high-potential power lines TVL1 are configured to form a mesh structure to minimize voltage drop and voltage deviation.

[0082] A plurality of top auxiliary low-potential power lines TAVL2 extending in the row direction are arranged in a plurality of pixel areas UPA on the first substrate 110 of the display panel PN. The plurality of top auxiliary low-potential power lines TAVL2 can be arranged in the area between the plurality of pixel areas UPA. The plurality of top auxiliary low-potential power lines TAVL2 extending in the row direction are electrically connected to the plurality of top low-potential power lines TVL2 extending in the column direction through contact holes, thereby forming a mesh structure. Therefore, the plurality of top auxiliary low-potential power lines TAVL2 and the plurality of top low-potential power lines TVL2 are configured to form a mesh structure to reduce wiring resistance and minimize voltage deviation.

[0083] Reference Figure 3A plurality of top gate drive lines TGVL extending in the row and column directions are provided in the plurality of pixel areas UPA on the first substrate 110 of the display panel PN. A portion of the plurality of top gate drive lines TGVL extends from the top gate pads TGP of the first top pad area TPA1 to the gate drive area GA to transmit signals to the gate driver GD. Other portions of the plurality of top gate drive lines TGVL extend in the row direction and can transmit the signals to the gate drivers GD of the plurality of gate drive areas GA. Thus, various signals are transmitted from the top gate drive lines TGVL to the gate driver GD to drive the gate driver GD.

[0084] The plurality of top gate driving lines TGVL may include wirings for transmitting a clock signal, a start signal, a gate high voltage, and a gate low voltage to the gate driver GD. Therefore, various signals are transmitted from the top gate driving lines TGVL to the gate driver GD to drive the gate driver GD.

[0085] For example, the plurality of top gate driving lines TGVL may include a plurality of gate power supply lines that transmit a power supply voltage to the gate driver GD of the gate driving area GA. The plurality of gate power supply lines may include a first gate power supply line that transmits a gate high voltage to the gate driver GD and a second gate power supply line that transmits a gate low voltage to the gate driver GD.

[0086] A plurality of alignment keys AK1 and AK2 are provided in the region between the plurality of pixel areas UPA of the display panel PN. The plurality of alignment keys AK1 and AK2 are used for alignment during the manufacturing process of the display panel PN. The plurality of alignment keys AK1 and AK2 include a first alignment key AK1 and a second alignment key AK2.

[0087] The first alignment key AK1 may be disposed in the gate driving area GA between the plurality of pixel areas UPA. The first alignment key AK1 may be used to check the alignment positions of the plurality of light emitting diodes LED. For example, the first alignment key AK1 may have a cross shape, but is not limited thereto.

[0088] The second alignment key AK2 can be positioned so as to overlap the top high-potential power line TVL1 between the plurality of pixel areas UPA. A hole overlapping the second alignment key AK2 is formed in the top high-potential power line TVL1 to distinguish the second alignment key AK2 from the top high-potential power line TVL1. The second alignment key AK2 can be used to align the display panel PN and the donor. The display panel PN and the donor are aligned using the second alignment key AK2, and the multiple light-emitting diodes (LEDs) of the donor can be transferred to the display panel PN. For example, the second alignment key AK2 can have a circular shape, but is not limited thereto.

[0089] Figure 4is an enlarged plan view of a second substrate of a display device according to an exemplary embodiment of the present disclosure.

[0090] First, the display panel PN includes a second substrate 130. The second substrate 130 supports various components disposed below the display device 100 and may be an insulating substrate. For example, a plurality of flexible films (COFs) and a printed circuit board (PCB) for transmitting signals to the plurality of sub-pixels SP may be disposed below the second substrate 130.

[0091] The second substrate 130 may be formed of glass or resin. In addition, the second substrate 130 may include a polymer or plastic. The second substrate 130 may be formed of the same material as the first substrate 110. In some exemplary embodiments, the second substrate 130 may be formed of a flexible plastic material.

[0092] Reference Figure 4 , the second substrate 130 may include a plurality of bottom pad areas, a COF pad area BPA3 and a plurality of bottom line areas.

[0093] The plurality of bottom pad regions are regions where a plurality of bottom pads BPAD are located below the second substrate 130. For example, the plurality of bottom pad regions may include a first bottom pad region BPA1 located at a first edge EG1 of the display panel PN and a second bottom pad region BPA2 located at a second edge EG2 of the display panel PN. The plurality of bottom pads BPAD may transmit various signals to various wirings located in the plurality of bottom wiring regions.

[0094] Reference Figure 4 A plurality of first bottom pads BPAD1 may be provided in the first bottom pad area BPA1. The plurality of first bottom pads BPAD1 may include a plurality of bottom pads BPAD to which different signals are applied. For example, the plurality of first bottom pads BPAD1 may include a bottom data pad BDP, a bottom gate pad BGP, and a bottom high potential power pad BVP1.

[0095] In addition, the plurality of bottom pads BPAD may be formed to have different sizes. For example, the plurality of first bottom pads BPAD1 may have different sizes. Specifically, the plurality of bottom data pads BDP connected one-to-one with the plurality of bottom data lines BDL may have a smaller width, and the bottom high potential power pad BVP1 and the bottom gate pad BGP may have a larger width. However, Figure 4 The widths of the bottom data pad BDP, the bottom gate pad BGP, and the bottom high potential power pad BVP1 shown in FIG. 5 are exemplary, and the size of the bottom pad BPAD may vary without being limited thereto.

[0096] In the first bottom pad area BPA1, a plurality of bottom ground pads BGNP may be disposed at both sides of the first bottom pad BPAD1 in the first bottom pad area BPA1.

[0097] The plurality of bottom ground pads BGNP may be disposed in the first bottom pad area BPA1 of the first edge EG1 of the second substrate 130. In addition, the plurality of bottom ground pads BGNP may be disposed adjacent to the outer peripheral area of ​​the second substrate 130. For example, the plurality of bottom ground pads BGNP may be disposed to be spaced apart from each other via the plurality of first bottom pads BPAD1.

[0098] The plurality of bottom ground pads BGNP may be respectively connected to the plurality of top ground pads TGNP, and may be electrically connected to a bottom auxiliary low potential power line BAVL2 described below.

[0099] A plurality of second bottom pads BPAD2 may be provided in the second bottom pad area BPA2. In this case, the plurality of second bottom pads BPAD2 may be different from the plurality of first bottom pads BPAD1. For example, the plurality of second bottom pads BPAD2 may include a bottom low potential power pad BVP2 that transmits a low potential power voltage to the bottom low potential power line BVL2.

[0100] In addition, the plurality of second bottom pads BPAD2 may have different sizes. For example, each of the plurality of second bottom pads BPAD2 may have a larger width than the plurality of bottom data pads BDP in the plurality of first bottom pads BPAD1, but is not limited thereto. Figure 4 The width of the bottom low potential power supply pad BVP2 shown in FIG. 1 is exemplary, and the size of the bottom pad BPAD may vary without being limited thereto.

[0101] In addition, to reduce the bezel of the display panel PN, the edges of the display panel PN may be cut away. A plurality of pixels PX, a plurality of wirings, and a plurality of bottom pads BPAD are formed on an initial second substrate 130i, and the edge portion of the initial second substrate 130i is ground to reduce the bezel area. During the grinding process, a portion of the initial second substrate 130i is removed, thereby forming a second substrate 130 having a smaller size. At this time, a portion of the plurality of bottom pads BPAD and wirings provided in the edge of the second substrate 130 may be removed. As a result, only a portion of the plurality of bottom pads BPAD may remain on the second substrate 130.

[0102] The COF pad area BPA3 is disposed between the first and second bottom pad areas BPA1 and BPA2. For example, the COF pad area BPA3 may be disposed adjacent to the first bottom pad area BPA1 between the first and second bottom pad areas BPA1 and BPA2, but is not limited thereto.

[0103] A plurality of COF pads BPAD3 are provided in the COF pad area BPA3.

[0104] The plurality of COF pads BPAD3 may be connected to the plurality of bottom wires disposed in the plurality of bottom wire regions and may electrically connect the plurality of bottom wires with the plurality of flexible films COFs and the printed circuit board PCB.

[0105] For example, the plurality of bottom data link lines BDL may be connected to the plurality of COF pads BPAD3, and the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible films COF. Therefore, the plurality of COF pads BPAD3 may electrically connect the plurality of flexible films COF with the plurality of bottom data link lines BDL.

[0106] Will refer to Figure 9 The plurality of COF pads BPAD3 are described in detail.

[0107] In addition, a plurality of flexible films COF and printed circuit boards PCB may be provided in the COF pad area BPA3.

[0108] The plurality of flexible films COF may be electrically connected to the plurality of COF pads BPAD3. The flexible film COF is a film in which various components are provided on a base film having ductility to provide signals to the sub-pixels SP, and may be electrically connected to the display panel PN.

[0109] Driver ICs, such as gate driver ICs or data driver ICs, can be mounted on multiple flexible film COFs. These ICs process the data used to display images and the drive signals used to process this data. Depending on the mounting method, these ICs can be mounted using chip-on-glass (COG), chip-on-film (COF), or tape carrier packaging (TCP). For ease of description, however, the driver ICs will be described as being mounted on multiple flexible film COFs using chip-on-film technology, but are not limited thereto.

[0110] The printed circuit board PCB is electrically connected to the plurality of flexible films COF. The printed circuit board PCB is a component that provides signals to the driver IC. Various components for providing various signals to the driver IC may be provided on the printed circuit board PCB.

[0111] In addition, although Figure 4 3 , three flexible films COF and one printed circuit board PCB are provided, but the number of the plurality of flexible films COF and the printed circuit board PCB may vary according to design and is not limited thereto.

[0112] The plurality of bottom line areas are areas where a plurality of wirings connected to the plurality of bottom pads BPAD are located. The plurality of bottom line areas may include a first bottom line area BLA1 and a second bottom line area BLA2.

[0113] Reference Figure 4 , the first bottom line area BLA1 and the second bottom line area BLA2 are arranged between the first bottom pad area BPA1 and the second bottom pad area BPA2. The first bottom line area BLA1 and the second bottom line area BLA2 can be arranged to be separated from each other via the COF pad area BPA3. For example, the first bottom line area BLA1 can be arranged between the first bottom pad area BPA1 and the COF pad area BPA3, and the second bottom line area BLA2 can be arranged between the second bottom pad area BPA2 and the COF pad area BPA3. Therefore, the first bottom pad area BPA1, the first bottom line area BLA1, the COF pad area BPA3, the second bottom line area BLA2, and the second bottom pad area BPA2 can be arranged in sequence from the first edge EG1 to the second edge EG2 of the display panel PN.

[0114] The first bottom line area BLA1 may include bottom data lines BDL, bottom gate lines, a bottom high potential power line BVL1, a bottom auxiliary high potential power line BAVL1, a bottom auxiliary low potential power line BAVL2, and a plurality of bottom ground lines BGNL.

[0115] For example, a plurality of bottom data link lines BDL extending from the bottom data pads BDP in the column direction are disposed in a first bottom line area BLA1 on the rear surface of the second substrate 130. The plurality of bottom data link lines BDL extend to the COF pad area BPA3 to connect to the plurality of flexible films COF and the printed circuit board PCB. Furthermore, the plurality of bottom data link lines BDL may be disposed to overlap with the bottom high potential power line BVL1 and the plurality of bottom auxiliary low potential power lines BAVL2.

[0116] A plurality of bottom gate lines extending from the bottom gate pads BGP in a column direction are disposed in a first bottom line area BLA1 of the rear surface of the second substrate 130. The plurality of bottom gate lines extend to the COF pad area BPA3 to be connected to the plurality of COF pads BPAD3.

[0117] A plurality of bottom high potential power connection lines extending from the plurality of bottom high potential power pads BVP1 in a column direction are provided in a first bottom line area BLA1 of the rear surface of the second substrate 130 .

[0118] Each of the plurality of bottom high potential power supply lines extends in the column direction to be connected to the bottom high potential power supply line BVL1 .

[0119] The bottom high-potential power line BVL1 may have a long axis in the row direction. For example, the width of the bottom high-potential power line BVL1 may correspond to the width of the first bottom pad area BPA1. Therefore, the bottom high-potential power line BVL1 may contact each of the plurality of bottom high-potential power connection lines extending in the column direction.

[0120] A plurality of bottom auxiliary high potential power lines BAVL1 may be disposed in the first bottom line area BLA1 . The plurality of bottom auxiliary high potential power lines BAVL1 may be disposed to overlap with the bottom high potential power line BVL1 .

[0121] In addition, the width of each of the plurality of bottom auxiliary high potential power lines BAVL1 decreases as it approaches the first bottom pad area BPA1. For example, the planar shape of each of the plurality of bottom auxiliary high potential power lines BAVL1 may be a triangle.

[0122] A plurality of bottom auxiliary low potential power lines BAVL2 may be disposed in the first bottom line area BLA1 , and the plurality of bottom auxiliary low potential power lines BAVL2 may be disposed to overlap with the bottom high potential power line BVL1 .

[0123] Each of the plurality of bottom auxiliary high potential power lines BAVL1 and each of the plurality of bottom auxiliary low potential power lines BAVL2 may be alternately arranged along the row direction.

[0124] In addition, the width of each of the plurality of bottom auxiliary low potential power lines BAVL2 increases as it is closer to the first bottom pad area BPA1. For example, the planar shape of each of the plurality of bottom auxiliary low potential power lines BAVL2 may be a trapezoid.

[0125] In addition, a plurality of bottom auxiliary low potential power lines BAVL2 can be connected to the bottom low potential power line BVL2. For example, each of the plurality of bottom auxiliary low potential power lines BAVL2 can extend to the second bottom line area BLA2 in the area between the plurality of COF pads BPAD3. Therefore, each of the plurality of bottom auxiliary low potential power lines BAVL2 can be connected to the bottom low potential power line BVL2 provided in the second bottom line area BLA2.

[0126] In addition, the plurality of bottom auxiliary low potential power lines BAVL2 can be connected to the plurality of bottom ground lines BGNL. For example, the bottom auxiliary low potential power lines BAVL2 disposed in the outer peripheral area of ​​the second substrate 130 among the plurality of bottom auxiliary low potential power lines BAVL2 can be connected to the plurality of bottom ground lines BGNL.

[0127] A plurality of bottom ground lines BGNL are disposed in a first bottom line area BLA1 of the rear surface of the second substrate 130. The plurality of bottom ground lines BGNL may be disposed to be spaced apart from each other via bottom data link lines BDL, bottom gate link lines, and bottom high potential power lines BVL1.

[0128] The plurality of bottom ground lines BGNL extend to the first edge EG1 of the second substrate 130 to connect to the plurality of bottom ground pads BGNP. In addition, the plurality of bottom ground lines BGNL extend in a column direction to contact the plurality of bottom auxiliary low potential power lines BAVL2.

[0129] The following will refer to Figure 10 The plurality of bottom auxiliary high potential power lines BAVL1 , the plurality of bottom data link lines BDL, the plurality of bottom auxiliary low potential power lines BAVL2 , and the plurality of bottom ground lines BGNL are described in detail.

[0130] A plurality of bottom low potential power connection lines extending from the plurality of second bottom pads BPAD2 in the column direction are provided in a second bottom line area BLA2 of the rear surface of the second substrate 130 .

[0131] Each of the plurality of bottom low potential power supply lines extends in the column direction to be connected to the bottom low potential power supply line BVL2 .

[0132] The bottom low-potential power line BVL2 may have a long axis in the row direction. For example, the width of the bottom low-potential power line BVL2 may correspond to the width of the second bottom pad area BPA2. Therefore, the bottom low-potential power line BVL2 may contact each of the plurality of bottom low-potential power connection lines extending in the column direction.

[0133] The bottom low potential power line BVL2 may make contact with a plurality of bottom auxiliary low potential power lines BAVL2 extending from the first bottom line area BLA1 .

[0134] In addition, the bottom data line BDL, the bottom gate line, and the bottom high potential power line set in the first bottom line area BLA1 of the second substrate 130 extend to multiple first bottom pads BPAD1 respectively, and can be connected to multiple first top pads TPAD1 set above the first substrate 110 through the side lines SRL described below.

[0135] In addition, the bottom low potential power connection lines set in the second bottom line area BLA2 of the second substrate 130 extend to multiple second bottom pads BPAD2 respectively, and can be connected to multiple second top pads TPAD2 set above the first substrate 110 through the side lines SRL described below.

[0136] In addition, a plurality of bottom ground lines BGNL disposed in the first bottom line area BLA1 of the second substrate 130 extend to the first bottom pad area BPA1 to be connected to a plurality of bottom ground pads BGNP. Furthermore, the plurality of bottom ground pads BGNP can be connected to a plurality of top ground pads TGNP disposed above the first substrate 110 via side ground lines described below.

[0137] The side lines SRL and the side ground lines will be described in detail below with reference to FIG. 7 .

[0138] In the following, reference will be made to Figure 5 The plurality of sub-pixels SP of the pixel area UPA are described in more detail.

[0139] Figure 5 1 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to this exemplary embodiment of the present disclosure, a first substrate 110, a second substrate 130, a bonding layer BL, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarizing layer 115, an adhesive layer 116, a second planarizing layer 117, a third planarizing layer 118, a passivation layer 119, a driving transistor DT, a light-emitting diode LED, a plurality of reflective electrodes RE1 and RE2, a plurality of connecting electrodes CE1 and CE2, a light-shielding layer LS, and an auxiliary electrode LE are provided.

[0140] First, the first substrate 110 is a component for supporting various components included in the display device 100 and can be formed of an insulating material. For example, the first substrate 110 can be formed of glass or resin. In addition, the first substrate 110 can be configured to include a polymer or plastic, or can be formed of a flexible material.

[0141] A light shielding layer LS is provided on the first substrate 110 in each of the plurality of sub-pixels SP. The light shielding layer LS blocks light from being incident on the active layer ACT of the drive transistor DT described below from below the first substrate 110. Light incident on the active layer ACT of the drive transistor DT is blocked by the light shielding layer LS to minimize leakage current. For example, the light shielding layer LS may be formed of molybdenum (Mo), but is not limited thereto.

[0142] A buffer layer 111 is provided on the first substrate 110 and the light shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 can be omitted depending on the type of the first substrate 110 or the type of the transistor, but is not limited thereto.

[0143] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0144] The active layer ACT is disposed on the buffer layer 111. The active layer ACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0145] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE2 and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0146] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0147] A first interlayer insulating layer 113 is provided on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 to connect the source electrode SE and the drain electrode DE to the active layer ACT, respectively. The first interlayer insulating layer 113 is an insulating layer that protects components below the first interlayer insulating layer 113 and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0148] The capacitor electrode C2 is disposed on the first interlayer insulating layer 113. The capacitor electrode C2 may be disposed to overlap the gate electrode GE with the first interlayer insulating layer 113 interposed therebetween.

[0149] A second interlayer insulating layer 114 is provided on the capacitor electrode C2. Contact holes are formed in the second interlayer insulating layer 114 to connect the source electrode SE and the drain electrode DE to the active layer ACT, respectively. The second interlayer insulating layer 114 is an insulating layer that protects components below the second interlayer insulating layer 114 and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0150] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0151] In addition, in the present application, the first interlayer insulating layer 113 and the second interlayer insulating layer 114, that is, multiple insulating layers, are provided between the gate electrode GE and the source electrode SE and the drain electrode DE. However, only one insulating layer may be provided between the gate electrode GE and the source electrode SE and the drain electrode DE, but the present invention is not limited thereto.

[0152] As shown in the figure, when a plurality of insulating layers, such as a first interlayer insulating layer 113 and a second interlayer insulating layer 114, are provided between the gate electrode GE and the source electrode SE and the drain electrode DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor with other structures provided below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0153] An auxiliary electrode LE is provided on the gate insulating layer 112. The auxiliary electrode LE electrically connects the light shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 114. For example, the light shielding layer LS is electrically connected to either the source electrode SE or the drain electrode DE via the auxiliary electrode LE, rather than operating as a floating gate. Therefore, fluctuations in the threshold voltage of the drive transistor DT caused by the floating light shielding layer LS can be minimized. Although the light shielding layer LS is connected to the source electrode SE in the figure, this is not limiting and the light shielding layer LS may also be connected to the drain electrode DE.

[0154] A first planarization layer 115 is provided on the driving transistor DT. The first planarization layer 115 may planarize the upper portion of the first substrate 110 on which the driving transistor DT is provided. The first planarization layer 115 may be composed of a single layer or a double layer, for example, may be formed of a photoresist or an acrylic organic material, but is not limited thereto.

[0155] A plurality of reflective electrodes RE1 and RE2 spaced apart from each other are disposed on the first planarization layer 115. The plurality of reflective electrodes RE1 and RE2 can electrically connect the light emitting diode LED to a power line and the driving transistor DT and can function as reflectors that reflect light emitted from the light emitting diode LED toward the upper portion of the light emitting diode LED. The plurality of reflective electrodes RE1 and RE2 are formed of a conductive material having excellent reflective properties to reflect light emitted from the light emitting diode LED toward the upper portion of the light emitting diode LED.

[0156] For example, the plurality of reflective electrodes RE1, RE2 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0157] The plurality of reflective electrodes RE1 and RE2 include a first reflective electrode RE1 and a second reflective electrode RE2. The second reflective electrode RE2 can electrically connect the driving transistor DT and the light-emitting diode LED. The second reflective electrode RE2 can be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the first planarization layer 115. The second reflective electrode RE2 can be electrically connected to the first electrode 124 of the light-emitting diode LED through a second connection electrode CE2 described below.

[0158] The first reflective electrode RE1 may electrically connect the power line and the light emitting diode LED. The first reflective electrode RE1 may be connected to the power line and may be connected to the second electrode 125 of the light emitting diode LED through a first connection electrode CE1 described below.

[0159] A passivation layer 119 is provided on the plurality of reflective electrodes RE1 and RE2. Contact holes are provided in the passivation layer 119 for connecting the plurality of reflective electrodes RE1 and RE2 to the first connection electrode CE1 and the second connection electrode CE2, respectively. The passivation layer 119 is an insulating layer that protects components below the passivation layer 119 and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0160] The adhesive layer 116 is provided on the passivation layer 119. The adhesive layer 116 is coated on the front surface of the first substrate 110 to fix the light emitting diode LED provided on the adhesive layer 116. For example, the adhesive layer 116 can be selected from any one of adhesive polymer, epoxy resin, UV resin, polyimide, acrylate, urethane and polydimethylsiloxane (PDMS), but is not limited thereto.

[0161] A plurality of light-emitting diodes (LEDs) are disposed in each of the plurality of sub-pixels SP on the adhesive layer 116. The plurality of light-emitting diodes (LEDs) are elements that emit light by current and may include LEDs that emit red, green, and blue light, and may achieve light of various colors, including white, by color mixing. For example, the plurality of light-emitting diodes (LEDs) may be LEDs or micro-LEDs, but are not limited thereto.

[0162] The plurality of LEDs (LEDs) may include a first LED, a second LED, and a third LED. The first LED may be provided in a first sub-pixel, the second LED may be provided in a second sub-pixel, and the third LED may be provided in a third sub-pixel. For example, the first LED may be a red LED, the second LED may be a green LED, and the third LED may be a blue LED.

[0163] Each of the plurality of light emitting diodes LED includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and an encapsulation layer 126 .

[0164] The first semiconductor layer 121 is disposed on the adhesive layer 116, and the second semiconductor layer 123 is disposed above the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type and p-type impurities. The p-type impurity may be magnesium (Mg), zinc (Zn), or beryllium (Be), and the n-type impurity may be silicon (Si), germanium, or tin (Sn), but are not limited thereto.

[0165] The light emitting layer 122 is provided between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 is provided with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light emitting layer 122 may be formed of a single layer or a multiple quantum well (MQW) structure and, for example, may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0166] The first electrode 124 is provided on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. The first electrode 124 may be provided on the top surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0167] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode that electrically connects the power line to the second semiconductor layer 123. The second electrode 125 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO); or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0168] Then, an encapsulation layer 126 is provided surrounding the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation layer 126 is formed of an insulating material to protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the encapsulation layer 126 to expose the first and second electrodes 124 and 125 so as to electrically connect the first and second connection electrodes CE1 and CE2 to the first and second electrodes 124 and 125.

[0169] A second planarization layer 117 and a third planarization layer 118 are provided on the adhesive layer 116. The second planarization layer 117 overlaps a portion of the side surface of the plurality of light emitting diodes LED to fix and protect the plurality of light emitting diodes LED. Figure 5 FIG 2 shows that the encapsulation layer 126 surrounds all side surfaces of the first semiconductor layer 121, but a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation layer 126. The light-emitting diode LED manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light-emitting diode LED from the wafer, a portion of the encapsulation layer 126 may tear. For example, a portion of the encapsulation layer 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting diode LED may tear during the process of separating the light-emitting diode LED from the wafer. Therefore, a portion of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. However, even if the lower portion of the light-emitting diode LED is exposed from the encapsulation layer 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after the second planarization layer 117 covering the side surfaces of the first semiconductor layer 121 is formed. Therefore, short circuit defects can be minimized.

[0170] In addition, the third planarization layer 118 is formed to cover the second planarization layer 117 and the upper portion of the light emitting diode LED, and a contact hole exposing the first electrode 124 and the second electrode 125 of the light emitting diode LED may be formed. The first electrode 124 and the second electrode 125 of the light emitting diode LED are exposed from the third planarization layer 118, and the third planarization layer 118 is partially provided in the region between the first electrode 124 and the second electrode 125, thereby minimizing short circuit defects.

[0171] The second planarization layer 117 and the third planarization layer 118 may be formed of a single layer or a double layer and may be formed of, for example, a photoresist or an acrylic organic material, but are not limited thereto. Although the second planarization layer 117 and the third planarization layer 118 are described in the present application, they are not limited thereto and a single-layer planarization layer may be formed.

[0172] A plurality of connection electrodes CE1, CE2 are disposed on the third planarization layer 118. The plurality of connection electrodes CE1, CE2 include a first connection electrode CE1 and a second connection electrode CE2.

[0173] The second connection electrode CE2 is an electrode provided in each of the plurality of sub-pixels SP to electrically connect the light-emitting diode LED and the driving transistor DT. The second connection electrode CE2 can be connected to the second reflective electrode RE2 via a contact hole formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Therefore, the second connection electrode CE2 can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT via the second reflective electrode RE2. The second connection electrode CE2 can be connected to the first electrodes 124 of the plurality of light-emitting diodes LED via a contact hole formed in the third planarization layer 118. Therefore, the second connection electrode CE2 can electrically connect the driving transistor DT to the first electrodes 124 of the plurality of light-emitting diodes LED.

[0174] The first connection electrode CE1 is an electrode that electrically connects the light-emitting diode (LED) to a power supply line. The first connection electrode CE1 can be connected to the first reflective electrode RE1 via contact holes formed in the third planarization layer 118, the second planarization layer 117, and the adhesive layer 116. Furthermore, the first connection electrode CE1 can be electrically connected to the power supply line via the first reflective electrode RE1. The first connection electrode CE1 can be connected to the second electrodes 125 of the plurality of light-emitting diodes (LED) via contact holes formed in the third planarization layer 118. Therefore, the first connection electrode CE1 can electrically connect the power supply line to the second electrodes 125 of the plurality of light-emitting diodes (LED).

[0175] A bank BB is disposed on the first and second link electrodes CE1 and CE2 and may be spaced apart from the light emitting diode by a predetermined interval.

[0176] The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, for example, may be formed of a black resin, but is not limited thereto.

[0177] A protective layer 190 is provided on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The protective layer 190 is a layer for protecting the structure located below the protective layer 190 and may, for example, cover at least a portion of the light emitting diode LED. The protective layer 190 may be formed of a single layer or multiple layers of a translucent epoxy resin, silicon oxide (SiOx), or silicon nitride (SiNx), but is not limited thereto.

[0178] In addition, the second connection electrode CE2 connecting the driving transistor DT and the light emitting diode LED provided in each of the plurality of sub-pixels SP may be individually provided in each of the plurality of sub-pixels SP.

[0179] In the following, the award is referred to Figures 6 to 7B The plurality of top pads TPAD and the plurality of bottom pads BPAD are described in detail.

[0180] Figure 6 is a cross-sectional view of a pad region of a display device according to an exemplary embodiment of the present disclosure. Figure 7A is a cross-sectional view of a top pad of a display device according to an exemplary embodiment of the present disclosure. Figure 7B : is a cross-sectional view of a bottom pad of a display device according to an exemplary embodiment of the present disclosure. Figure 7B , for convenience of explanation, it is shown that the positions of the second substrate 130 and components disposed below the second substrate 130 are reversed such that the second substrate 130 is disposed at the bottom.

[0181] Reference Figure 6 and Figure 7A Each of the plurality of top pads TPAD may be formed of a plurality of conductive layers. For example, each of the plurality of top pads TPAD may include a first top pad electrode TPEa, a second top pad electrode TPEb, and a third top pad electrode TPEc. That is, each of the plurality of first top pads TPAD1 and the plurality of second top pads TPAD2 may include a first top pad electrode TPEa, a second top pad electrode TPEb, and a third top pad electrode TPEc.

[0182] First, the first top pad electrode TPEa may be provided on the same layer as the driving transistor DT. For example, the first top pad electrode TPEa is provided on the second interlayer insulating layer 114. The first top pad electrode TPEa may be formed of the same conductive material as the source electrode SE and the drain electrode DE, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0183] The second top pad electrode TPEb is disposed on the first top pad electrode TPEa. The second top pad electrode TPEb may be disposed on the same layer as the plurality of reflective electrodes RE1 and RE2, and may be formed of the same conductive material as the plurality of reflective electrodes RE1 and RE2. The second top pad electrode TPEb may be composed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0184] The third top pad electrode TPEc is disposed on the second top pad electrode TPEb. The third top pad electrode TPEc may be disposed on the same layer as the first and second connection electrodes CE1 and CE2, and may be formed of the same conductive material as the first and second connection electrodes CE1 and CE2, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0185] At this time, although not shown in the figure, a portion of the plurality of top pad electrodes of the top pad TPAD is electrically connected to a plurality of wirings on the first substrate 110 to provide various signals to the plurality of wirings and the plurality of sub-pixels SP. For example, the first top pad electrode TPEa and / or the second top pad electrode TPEb of the top pad TPAD is connected to a top data line TDL, a top high potential power line TVL1, and a top low potential power line TVL2 disposed in the active area AA to transmit signals thereto.

[0186] A first metal layer ML1, a second metal layer ML2, and a plurality of insulating layers may be disposed together below the top pad TPAD. The first metal layer ML1, the second metal layer ML2, and the plurality of insulating layers are disposed below the top pad TPAD to adjust the step of the top pad TPAD. For example, a buffer layer 111, a gate insulating layer 112, a first metal layer ML1, a first interlayer insulating layer 113, and a second metal layer ML2 may be disposed in sequence between the top pad TPAD and the first substrate 110. The first metal layer ML1 may be formed of the same conductive material as the gate electrode GE, and the second metal layer ML2 may be formed of the same conductive material as the capacitor electrode C2. However, this is not limiting, and the plurality of insulating layers, the first metal layer ML1, and the second metal layer ML2 may be omitted below the top pad TPAD according to design.

[0187] Also refer to Figure 5 The second substrate 130 is disposed below the first substrate 110. The second substrate 130 supports various components disposed below the display device 100 and may be an insulating substrate. For example, the second substrate 130 may be formed of glass or resin. Furthermore, the second substrate 130 may include a polymer or plastic. The second substrate 130 may be formed of the same material as the first substrate 110. In some exemplary embodiments, the second substrate 130 may be formed of a flexible plastic material.

[0188] Also refer to Figure 5, a bonding layer BL is provided between the first substrate 110 and the second substrate 130. The bonding layer BL may be formed of a material cured by various curing methods to bond the first substrate 110 to the second substrate 130. The bonding layer BL may be provided only in a partial region between the first substrate 110 and the second substrate 130 or may be provided in the entire region therebetween.

[0189] A plurality of bottom pads BPAD are provided on the rear surface of the second substrate 130. The plurality of bottom pads BPAD are electrodes that transmit signals from the driving components provided on the rear surface of the second substrate 130 to the plurality of lateral lines SRL, as well as the plurality of top pads TPAD and the plurality of wirings on the first substrate 110. The plurality of bottom pads BPAD are provided in the end portion of the second substrate 130 in the non-active area NA to be electrically connected to the lateral lines SRL covering the end portion of the second substrate 130.

[0190] At this time, the plurality of bottom pads BPAD may also be arranged corresponding to the plurality of bottom pad regions. Each of the plurality of top pads TPAD may be arranged corresponding to each of the plurality of bottom pads BPAD, and then the top pads TPAD and the bottom pads BPAD that overlap each other may be electrically connected via the side lines SRL.

[0191] Each of the plurality of bottom pads BPAD includes a plurality of pad electrodes. For example, each of the plurality of bottom pads BPAD includes a first bottom pad electrode BPEa, a second bottom pad electrode BPEb, and a third bottom pad electrode BPEc. That is, each of the plurality of first bottom pads BPAD1 and the plurality of second bottom pads BPAD2 includes a first bottom pad electrode BPEa, a second bottom pad electrode BPEb, and a third bottom pad electrode BPEc.

[0192] exist Figure 7B , for convenience of explanation, it is shown that the bottom pad BPAD is disposed over the second substrate 130 , and the first bottom pad electrode BPEa, the second bottom pad electrode BPEb, and the third bottom pad electrode BPEc are sequentially disposed over the second substrate 130 .

[0193] However, Figure 7B The second substrate 130 shown in FIG is to be set upside down to be joined with the first substrate 110. Therefore, in the joined state of the second substrate 130 and the first substrate 110, as shown in FIG. Figure 6 As shown in FIG, a plurality of bottom pads BPAD may be disposed under the second substrate 130. In addition, a first bottom pad electrode BPEa, a second bottom pad electrode BPEb, and a third bottom pad electrode BPEc may be sequentially disposed under the second substrate 130.

[0194] Hereinafter, description will be made based on a state in which the second substrate 130 is bonded to the first substrate 110 , describing that the first bottom pad electrode BPEa, the second bottom pad electrode BPEb, and the third bottom pad electrode BPEc are sequentially disposed under the second substrate 130 .

[0195] First, a first bottom pad electrode BPEa is disposed under the second substrate 130. The first bottom pad electrode BPEa may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0196] A first insulating layer 131 is provided under the first bottom pad electrode BPEa. Figure 7B , the first insulating layer 131 may cover the side surface of the first bottom pad electrode BPEa. In addition, the first insulating layer 131 may include an opening exposing a portion of one surface of the first bottom pad electrode BPEa.

[0197] The first insulating layer 131 may be an inorganic insulating layer. For example, the first insulating layer 131 may be formed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0198] The second bottom pad electrode BPEb is disposed under the first insulating layer 131. Figure 7B , the second bottom pad electrode BPEb may make contact with one surface of the first bottom pad electrode BPEa exposed through the opening of the first insulating layer 131 .

[0199] The second bottom pad electrode BPEb may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0200] A second insulating layer 132 is disposed under the second bottom pad electrode BPEb. The second insulating layer 132 may cover the side surface of the second bottom pad electrode BPEb. In addition, the second insulating layer 132 may include an opening that exposes a portion of one surface of the second bottom pad electrode BPEb.

[0201] The second insulating layer 132 may be an inorganic insulating layer. For example, the second insulating layer 132 may be formed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0202] A third insulating layer 133 is provided under the second insulating layer 132. The third insulating layer 133 may include an opening exposing a portion of the second insulating layer 132. For example, the opening of the third insulating layer 133 is provided to overlap with the opening of the second insulating layer 132 exposing a portion of one surface of the second bottom pad electrode BPEb, so as to expose a portion of one surface of the second bottom pad electrode BPEb.

[0203] The third insulating layer 133 may be an organic insulating layer. For example, the third insulating layer 133 may be formed of a photoresist or an acrylic organic material, but is not limited thereto.

[0204] The third insulating layer 133 may have a thickness greater than that of the first insulating layer 131 and the second insulating layer 132. Therefore, the third insulating layer 133 may form a higher step together with one surface of the second bottom pad electrode BPEb. Therefore, when the plurality of bottom pads BPAD are in contact with the plurality of side lines SRL, the migration of metal ions to the plurality of top pads TPAD, the plurality of bottom pads BPAD, and the plurality of side lines SRL under high current or high humidity conditions may be suppressed.

[0205] The third bottom pad electrode BPEc is disposed under the third insulating layer 133. Figure 7B , the third bottom pad electrode BPEc may make contact with one surface of the second bottom pad electrode BPEb exposed through the opening of the second insulating layer 132 and the opening of the third insulating layer 133 .

[0206] The third bottom pad electrode BPEc may be formed of a material that is hardly corroded even when exposed to air or moisture, thereby suppressing corrosion of the second bottom pad electrode BPEb. For example, the third bottom pad electrode BPEc may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0207] In addition, to increase a contact area with the plurality of side lines SRL, the third bottom pad electrode BPEc extends from one surface of the second bottom pad electrode BPEb to cover a portion of one surface and side surfaces of the third insulating layer 133 , but is not limited thereto.

[0208] In addition, a driving component including multiple flexible films (COFs) and a printed circuit board (PCB) may be disposed on the rear surface of the second substrate 130. The first bottom pad electrode (BPEa) and / or the second bottom pad electrode (BPEb) of the multiple bottom pads (BPAD) extend toward the multiple flexible films (COFs) disposed on the rear surface of the second substrate 130 to be electrically connected to the multiple flexible films (COFs). The multiple flexible films (COFs) can provide various signals to the multiple side lines (SRL), the multiple top pads (TPAD), the multiple wirings, and the multiple sub-pixels (SP) via the multiple bottom pads (BPAD). Therefore, signals from the driving component can be transmitted to the signal lines and the multiple sub-pixels (SP) on the front surface of the first substrate 110 via the multiple bottom pads (BPAD) and the side lines (SRL) of the second substrate 130 and the multiple top pads (TPAD) of the first substrate 110.

[0209] Refer again Figure 6 , a plurality of side lines SRL are provided on the side surfaces of the first substrate 110 and the side surfaces of the second substrate 130. The plurality of side lines SRL may electrically connect a plurality of top pads TPAD formed on the top surface of the first substrate 110 and a plurality of bottom pads BPAD formed on the rear surface of the second substrate 130. The plurality of side lines SRL may be provided to surround the side surfaces of the display device 100. Each of the plurality of side lines SRL may cover a plurality of top pads TPAD at the end of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 130, and the plurality of bottom pads BPAD at the end of the second substrate 130. For example, the plurality of side lines SRL may be formed by a pad printing method using a conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), or chromium (Cr).

[0210] In the following, we will refer to Figure 8 The plurality of top ground pads and the plurality of bottom ground pads are described in detail.

[0211] Figure 8 is a cross-sectional view of a ground pad of a display device according to an exemplary embodiment of the present disclosure.

[0212] Reference Figure 8 The plurality of bottom ground pads BGNP and the plurality of top ground pads TGNP may be connected via a plurality of side ground lines GSRL. Furthermore, the plurality of top ground pads, the plurality of bottom ground pads, and the plurality of side ground lines GSRL may be formed in the same structure as the plurality of top pads TPAD, the plurality of bottom pads BPAD, and the side lines SRL, respectively.

[0213] For example, refer to Figure 8Each of the plurality of top ground pads TGNP may include a first top ground pad electrode TGNPEa, a second top ground pad electrode TGNPEb, and a third top ground pad electrode TGNPEc. The first top ground pad electrode TGNPEa is formed of the same material and on the same layer as the first top pad electrode TPEa. The second top ground pad electrode TGNPEb is formed of the same material and on the same layer as the second top pad electrode TPEb. The third top ground pad electrode TGNPEc is formed of the same material and on the same layer as the third top pad electrode TPEc.

[0214] Although not shown in the drawings, the plurality of top ground pads TGNP are electrically connected to the plurality of wirings on the first substrate 110 to provide ground signals to the plurality of wirings and the plurality of sub-pixels SP.

[0215] A first conductive layer GML1 formed of the same material as the first metal layer ML1 and on the same layer as the first metal layer ML1, a second conductive layer GML2 formed of the same material as the second metal layer ML2 and on the same layer as the second metal layer ML2, and a plurality of insulating layers may be disposed together under the plurality of top ground pads TGNP.

[0216] A plurality of bottom ground pads BGNP are disposed on the rear surface of the second substrate 130. The plurality of bottom ground pads BGNP are electrodes that transmit ground signals to the plurality of sub-pixels SP through the plurality of side ground lines GSRL and the plurality of top ground pads TGNP.

[0217] In this case, a plurality of bottom ground pads BGNP may also be provided corresponding to the first bottom pad area BPA1. Each of the plurality of bottom ground pads BGNP may be provided corresponding to each of the plurality of top ground pads TGNP. Then, the overlapping top ground pads TGNP and bottom ground pads BGNP may be electrically connected via a side ground line GSRL.

[0218] Reference Figure 8Each of the plurality of bottom ground pads BGNP may include a plurality of bottom ground pad electrodes. For example, each of the plurality of bottom ground pads BGNP may include a first bottom ground pad electrode BGNPEa, a second bottom ground pad electrode BGNPEb, and a third bottom ground pad electrode BGNPEc. The first bottom ground pad electrode BGNPEa is formed of the same material and on the same layer as the first bottom pad electrode BPEa. The second bottom ground pad electrode BGNPEb is formed of the same material and on the same layer as the second bottom pad electrode BPEb. The third bottom ground pad electrode BGNPEc is formed of the same material and on the same layer as the third bottom pad electrode BPEc.

[0219] Refer to it together Figure 6 and Figure 8 A lateral insulating layer 150 is provided to cover the plurality of lateral lines SRL and the plurality of lateral ground lines GSRL. The lateral insulating layer 150 may be formed on the top surface of the first substrate 110, the side surfaces of the first substrate 110, the side surfaces of the second substrate 130, and the rear surface of the second substrate 130 to cover the plurality of lateral lines SRL and the plurality of lateral ground lines GSRL. The lateral insulating layer 150 may protect the plurality of lateral lines SRL and the plurality of lateral ground lines GSRL.

[0220] Furthermore, when the plurality of side lines SRL and the plurality of side ground lines GSRL are formed of a metal material, there is a risk that external light may be reflected from the plurality of side lines SRL and the plurality of side ground lines GSRL, or light emitted by the light-emitting diodes (LEDs) may be reflected from the plurality of side lines SRL and the plurality of side ground lines GSRL, thereby being visible to the user. Therefore, the side insulating layer 150 is configured to include a black material to suppress reflection of external light. For example, the side insulating layer 150 can be formed by a pad printing method using an insulating material containing a black material, such as black ink.

[0221] A sealing member 160 is provided to cover the side insulating layer 150, the plurality of side lines SRL, and the plurality of side ground lines GSRL. The sealing member 160 is provided to surround the side surfaces of the display device 100 to protect the display device 100 from external impact, moisture, and oxygen. For example, the sealing member 160 may be formed of polyimide (PI), polyurethane, epoxy resin, or acrylic-based insulating material, but is not limited thereto.

[0222] The optical film MF is disposed on the sealing member 160, the side insulating layer 150, and the protective layer 190. The optical film MF may be a functional film that protects the display device 100 while achieving a higher quality image. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, or a polarizer, but is not limited thereto.

[0223] In addition, although an adhesive layer may be further provided between the optical film MF and the sealing member 160, the side insulating layer 150, and the protective layer 190, Figure 6 and Figure 8 For the sake of convenience, the adhesive layer is not shown. Alternatively, the optical film MF may also be defined as including an adhesive layer disposed thereunder.

[0224] The edges of the sealing member 160 and the edges of the optical film MF can be arranged on the same line. During the manufacturing process of the display device 100, a larger optical film MF is attached above the first substrate 110, and the sealing member 160 can be formed to cover the side insulating layer 150. Afterwards, a laser is irradiated on the sealing member 160 and the optical film MF corresponding to the edge of the display device 100 to cut a portion of the sealing member 160 and the optical film MF. Therefore, the size of the display device 100 is adjusted through the peripheral cutting process of the sealing member 160 and the optical film MF, and the edge of the display device 100 can be formed flat.

[0225] In the following, reference will be made to Figure 9 The COF pad area BPA3 of the display device according to the exemplary embodiment of the present disclosure is described in more detail.

[0226] Figure 9 It is along Figure 4 A cross-sectional view of the second substrate taken along line AA'. Figure 9 In FIG, for the convenience of explanation, the flexible film COF is not shown, but the COF pad BPAD3 is shown. Figure 9 In the figure, for the convenience of explanation, the positions of the second substrate 130 and the COF pad BPAD3 are reversed and the second substrate 130 is disposed at the bottom.

[0227] Reference Figure 9 , a plurality of COF pads BPAD3 are provided in the COF pad area BPA3.

[0228] Each of the plurality of COF pads BPAD3 may be formed of a plurality of conductive layers. For example, each of the plurality of COF pads BPAD3 may include a first COF pad electrode BPE3a, a second COF pad electrode BPE3b, and a third COF pad electrode BPE3c.

[0229] exist Figure 9, for convenience of explanation, it is shown that the COF pad BPAD3 is disposed over the second substrate 130 , and the first COF pad electrode BPE3 a , the second COF pad electrode BPE3 b , and the third COF pad electrode BPE3 c are sequentially disposed over the second substrate 130 .

[0230] However, Figure 9 The second substrate 130 shown in FIG is to be disposed upside down to be bonded to the first substrate 110. Therefore, in a bonded state between the second substrate 130 and the first substrate 110, a plurality of COF pads BPAD3 may be disposed below the second substrate 130. In addition, a first COF pad electrode BPE3a, a second COF pad electrode BPE3b, and a third COF pad electrode BPE3c may be sequentially disposed below the second substrate 130.

[0231] Hereinafter, description will be made based on a state in which the second substrate 130 is bonded to the first substrate 110 , describing that the first COF pad electrode BPE3 a , the second COF pad electrode BPE3 b , and the third COF pad electrode BPE3 c are sequentially disposed under the second substrate 130 .

[0232] The first COF pad electrode BPE3 a is disposed under the second substrate 130 .

[0233] The first COF pad electrode BPE3a may be provided on the same layer as the first bottom pad electrode BPEa, and may be formed of the same material as the first bottom pad electrode BPEa. For example, the first COF pad electrode BPE3a may be made of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0234] The second COF pad electrode BPE3 b is disposed below the first COF pad electrode BPE3 a and may make contact with one surface of the first COF pad electrode BPE3 a exposed through the first insulating layer 131 .

[0235] The second COF pad electrode BPE3b may be provided on the same layer as the second bottom pad electrode BPEb, and the second COF pad electrode BPE3b may be formed of the same material as the second bottom pad electrode BPEb. For example, the second COF pad electrode BPE3b may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0236] The third COF pad electrode BPE3 c is disposed below the second COF pad electrode BPE3 b and may make contact with one surface of the second COF pad electrode BPE3 b exposed by the second insulating layer 132 .

[0237] The third COF pad electrode BPE3c may be formed of the same material as the third bottom pad electrode BPEc. For example, the third COF pad electrode BPE3c may be formed of a material that is hardly corroded even when exposed to air or moisture, thereby suppressing corrosion of the second COF pad electrode BPE3b. For example, the third COF pad electrode BPE3c may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0238] The COF pads BPAD3 can be electrically connected to the flexible films COF through the third COF pad electrodes BPE3c among the conductive layers constituting the COF pads BPAD3. That is, the COF pads BPAD3 can be electrically connected to an external module through the third COF pad electrodes BPE3c.

[0239] The third COF pad electrode BPE3 c extends from one surface of the second COF pad electrode BPE3 b to cover a portion of one surface and a side surface of the second insulating layer 132 .

[0240] Furthermore, the third insulating layer 133 may not be provided between adjacent COF pads BPAD3 within the COF pad area BPA3 to facilitate contact between the COF pads BPAD3 and the flexible film COF. For example, a single flexible film COF may be electrically connected to multiple COF pads BPAD3 via an adhesive layer. However, if a thick insulating layer is provided between adjacent COF pads BPAD3, steps may form between the multiple COF pads BPAD3 and the flexible film COF, resulting in contact failure between the multiple COF pads BPAD3 and the flexible film COF. Therefore, the third insulating layer 133 may not be provided between adjacent COF pads BPAD3 within the COF pad area BPA3.

[0241] Despite Figure 9 Although not shown in the figure, the plurality of COF pads BPAD3 may be electrically connected to the plurality of flexible films COF through the third COF pad electrodes BPE3c among the plurality of conductive layers constituting the plurality of COF pads BPAD3.

[0242] The plurality of COF pads BPAD3 may be connected to the plurality of flexible film COFs via an adhesive layer. For example, the adhesive layer may be an anisotropic conductive film (ACF) or a conductive paste. Furthermore, for example, the plurality of flexible film COFs may be electrically connected to the plurality of COF pads BPAD3 of the second substrate 130 via heat and pressure.

[0243] In the following, reference will be made to Figure 10 Describe the bottom power cable in detail.

[0244] Figure 10 It is along Figure 4 sectional views of the second substrate taken along lines BB' and CC'. Figure 10 : is a cross-sectional view of the first bottom line area BLA1 and the second bottom line area BLA2. Figure 10 , for convenience of explanation, it is shown that the positions of the second substrate 130 and components disposed below the second substrate 130 are reversed such that the second substrate 130 is disposed at the bottom.

[0245] Reference Figure 10 The bottom high potential power line BVL1, the bottom auxiliary high potential power line BAVL1, the bottom auxiliary low potential power line BAVL2 and the plurality of bottom data link lines BDL are arranged in the first bottom line area BLA1.

[0246] exist Figure 10 In the figure, for the convenience of description, it is shown that the bottom high potential power line BVL1 , the bottom auxiliary high potential power line BAVL1 , the bottom auxiliary low potential power line BAVL2 and the plurality of bottom data link lines BDL are disposed above the second substrate 130 .

[0247] However, Figure 10 The second substrate 130 shown in FIG is to be disposed upside down to be bonded to the first substrate 110. Therefore, in a bonded state between the second substrate 130 and the first substrate 110, the bottom high potential power line BVL1, the bottom auxiliary high potential power line BAVL1, the bottom auxiliary low potential power line BAVL2, and the plurality of bottom data link lines BDL may be disposed below the second substrate 130.

[0248] In the following, the description is given based on the state in which the second substrate 130 is bonded to the first substrate 110 , describing that the bottom high potential power line BVL1 , the bottom auxiliary high potential power line BAVL1 , the bottom auxiliary low potential power line BAVL2 and multiple bottom data lines BDL are arranged under the second substrate 130 .

[0249] The bottom high potential power line BVL1 is disposed under the second substrate 130 .

[0250] The bottom high potential power line BVL1 may be provided on the same layer as the first bottom pad electrode BPEa and the first COF pad electrode BPE3a, and may be formed of the same material as the first bottom pad electrode BPEa and the first COF pad electrode BPE3a. For example, the bottom high potential power line BVL1 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0251] A first insulating layer 131 is provided below the bottom high-potential power line BVL1. The first insulating layer 131 may include a plurality of openings provided in positions overlapping with a plurality of bottom auxiliary high-potential power lines BAVL1 described below. Furthermore, the first insulating layer 131 is provided to overlap with the plurality of bottom data lines BDL to insulate the bottom high-potential power line BVL1 from the plurality of bottom data lines BDL.

[0252] A plurality of bottom auxiliary high potential power lines BAVL1 and a plurality of bottom data link lines BDL are disposed under the first insulating layer 131 .

[0253] First, refer to Figure 10 CC′, a plurality of bottom auxiliary high potential power lines BAVL1 are disposed under the first insulating layer 131 .

[0254] The plurality of bottom auxiliary high-potential power lines BAVL1 may contact one surface of the bottom high-potential power line BVL1 exposed by the first insulating layer 131. For example, the plurality of bottom auxiliary high-potential power lines BAVL1 may be spaced apart from one another and arranged between the flexible films COFs, alternating with the flexible films COFs in the row direction. Thus, each of the plurality of bottom auxiliary high-potential power lines BAVL1 may be arranged to overlap with the bottom high-potential power line BVL1 arranged between adjacent flexible films COFs. For example, the first insulating layer 131 and the plurality of bottom auxiliary high-potential power lines BAVL1 may be arranged below the bottom high-potential power line BVL1, and the first insulating layer 131 may be arranged in an area other than between the flexible films COFs. Thus, the plurality of bottom auxiliary high-potential power lines BAVL1 may contact the bottom high-potential power line BVL1 in the area between the flexible films COFs where the first insulating layer 131 is opened.

[0255] Therefore, the plurality of bottom auxiliary high potential power lines BAVL1 are in contact with the bottom high potential power line BVL1 , thereby minimizing voltage drop and voltage deviation.

[0256] The plurality of bottom auxiliary high-potential power lines BAVL1 may be provided on the same layer as the second bottom pad electrode BPEb and the second COF pad electrode BPE3b, and the plurality of bottom auxiliary high-potential power lines BAVL1 may be formed of the same material as the second bottom pad electrode BPEb and the second COF pad electrode BPE3b. For example, the plurality of bottom auxiliary high-potential power lines BAVL1 may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0257] The plurality of bottom data link lines BDL are disposed under the first insulating layer 131. The plurality of bottom data link lines BDL may be disposed on the same layer as the plurality of bottom auxiliary high potential power lines BAVL1.

[0258] In addition, the plurality of bottom data link lines BDL may be arranged to overlap with the bottom high potential power line BVL1 . For example, the plurality of bottom data link lines BDL may be arranged to overlap with the bottom high potential power line BVL1 via the first insulating layer 131 .

[0259] The plurality of bottom data link lines BDL may be provided on the same layer as the plurality of bottom auxiliary high-potential power lines BAVL1, the second bottom pad electrode BPEb, and the second COF pad electrode BPE3b, and the plurality of bottom data link lines BDL may be formed of the same material as the plurality of bottom auxiliary high-potential power lines BAVL1, the second bottom pad electrode BPEb, and the second COF pad electrode BPE3b. For example, the plurality of bottom data link lines BDL may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0260] A second insulating layer 132 and a third insulating layer 133 are disposed under the plurality of bottom data link lines BDL and the plurality of bottom auxiliary high potential power lines BAVL1 .

[0261] The second insulating layer 132 and the third insulating layer 133 are disposed to overlap with a plurality of bottom auxiliary low potential power lines BAVL2 described below to insulate the plurality of bottom data link lines BDL and the plurality of bottom auxiliary high potential power lines BAVL1 from the plurality of bottom auxiliary low potential power lines BAVL2.

[0262] The plurality of bottom auxiliary low potential power lines BAVL2 may be disposed under the third insulating layer 133. The plurality of bottom auxiliary low potential power lines BAVL2 may be disposed on a different layer from the plurality of bottom auxiliary high potential power lines BAVL1 and the plurality of bottom data link lines BDL.

[0263] In addition, each of the plurality of bottom auxiliary low-potential power lines BAVL2 may overlap with the plurality of bottom data lines BDL. Furthermore, the plurality of bottom auxiliary low-potential power lines BAVL2 may be arranged to overlap with a portion of the bottom high-potential power lines BVL1 disposed below the plurality of bottom data lines BDL. For example, the plurality of bottom auxiliary low-potential power lines BAVL2 may be arranged to overlap with the plurality of bottom data lines BDL via the second insulating layer 132 and the third insulating layer 133. The plurality of bottom auxiliary low-potential power lines BAVL2 may also be arranged to overlap with the bottom high-potential power lines BVL1 via the first insulating layer 131, the second insulating layer 132, and the third insulating layer 133.

[0264] In addition, a plurality of bottom auxiliary low potential power lines BAVL2 and a plurality of bottom auxiliary high potential power lines BAVL1 are alternately arranged along the row direction.

[0265] The plurality of bottom auxiliary low potential power lines BAVL2 may be provided on the same layer as the third bottom pad electrode BPEc and the third COF pad electrode BPE3c, and the plurality of bottom auxiliary low potential power lines BAVL2 may be formed of the same material as the third bottom pad electrode BPEc and the third COF pad electrode BPE3c. For example, the plurality of bottom auxiliary low potential power lines BAVL2 may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0266] Reference Figure 10 BB', the bottom low potential power line BVL2 is provided in the second bottom line area BLA2.

[0267] For ease of explanation, Figure 10 FIG shows that the bottom low potential power line BVL2 is disposed above the second substrate 130, but Figure 10 The second substrate 130 shown in FIG. 1 is turned upside down to be bonded to the first substrate 110. Therefore, in a bonded state of the second substrate 130 and the first substrate 110, the bottom low potential power line BVL2 may be provided below the second substrate 130.

[0268] Hereinafter, description will be made based on a state in which the second substrate 130 is bonded to the first substrate 110 , and description will be made that the bottom low potential power line BVL is provided below the second substrate 130 .

[0269] The bottom low potential power line BVL2 includes a first bottom low potential power line BVL2 a , a second bottom low potential power line BVL2 b , and a third bottom low potential power line BVL2 c .

[0270] The first bottom low potential power line BVL2 a is disposed under the second substrate 130 .

[0271] The first bottom low potential power line BVL2a may be provided on the same layer as the first bottom pad electrode BPEa and the first COF pad electrode BPE3a, and may be formed of the same material as the first bottom pad electrode BPEa and the first COF pad electrode BPE3a. For example, the first bottom low potential power line BVL2a may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0272] A first insulating layer 131 is disposed under the first bottom low potential power line BVL2 a and a second bottom low potential power line BVL2 b may be disposed under the first insulating layer 131 .

[0273] The second bottom low-potential power line BVL2b may contact one surface of the first bottom low-potential power line BVL2a exposed by the first insulating layer 131. For example, the first insulating layer 131 and the second bottom low-potential power line BVL2b are disposed below the first bottom low-potential power line BVL2a, and the first insulating layer 131 is disposed in an area other than the second bottom line area BLA2. Thus, the second bottom low-potential power line BVL2b may contact the first bottom low-potential power line BVL2a in the second bottom line area BLA2.

[0274] The second bottom low potential power line BVL2b may be provided on the same layer as the second bottom pad electrode BPEb and the second COF pad electrode BPE3b, and may be formed of the same material as the second bottom pad electrode BPEb and the second COF pad electrode BPE3b. For example, the second bottom low potential power line BVL2b may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0275] A second insulating layer 132 and a third insulating layer 133 are sequentially disposed under the second bottom low potential power line BVL2 b , and a third bottom low potential power line BVL2 c is disposed under the third insulating layer 133 .

[0276] The third bottom low-potential power line BVL2c can contact the second bottom low-potential power line BVL2b exposed through the second insulating layer 132 and the third insulating layer 133. For example, the second insulating layer 132, the third insulating layer 133, and the third bottom low-potential power line BVL2c are sequentially disposed below the second bottom low-potential power line BVL2b, and each of the second insulating layer 132 and the third insulating layer 133 can be disposed in an area other than the second bottom line area BLA2. Therefore, the third bottom low-potential power line BVL2c can contact the second bottom low-potential power line BVL2b in the second bottom line area BLA2.

[0277] The third bottom low potential power line BVL2c may be provided on the same layer as the third bottom pad electrode BPEc, and may be formed of the same material as the third bottom pad electrode BPEc and the third COF pad electrode BPE3c. For example, the third bottom low potential power line BVL2c may be formed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0278] Reference Figure 10 BB', a plurality of bottom ground lines BGNL are disposed in the COF pad area BPA3 and the first bottom line area PLA1. The plurality of bottom ground lines BGNL may contact a plurality of bottom low potential power lines BVL2 disposed in the second bottom line area BLA2.

[0279] For ease of explanation, Figure 10 FIG. 1 shows that the bottom ground line BGNL is disposed above the second substrate 130, but Figure 10 The second substrate 130 shown in FIG. 1 is turned upside down to be bonded with the first substrate 110. Therefore, in a bonded state of the second substrate 130 and the first substrate 110, the bottom ground line BGNL may be disposed under the second substrate 130.

[0280] Hereinafter, description will be made based on a state in which the second substrate 130 is bonded to the first substrate 110 , and description will be made that the bottom ground line BGNL is disposed under the second substrate 130 .

[0281] Each of the plurality of bottom ground lines BGNL includes a first bottom ground line BGNLa, a second bottom ground line BGNLb, and a third bottom ground line BGNLc.

[0282] The first bottom ground line BGNLa is disposed under the second substrate 130 .

[0283] The first bottom ground line BGNLa may be provided on the same layer as the first bottom low-potential power line BVL2a and may be formed of the same material as the first bottom low-potential power line BVL2a. For example, the first bottom ground line BGNLa may be integrally formed with the first bottom low-potential power line BVL2a, but is not limited thereto. The first bottom ground line BGNLa may be composed of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0284] A first insulating layer 131 is disposed under the first bottom ground line BGNLa and a second bottom ground line BGNLb may be disposed under the first insulating layer 131 .

[0285] The second bottom ground line BGNLb may make contact with one surface of the first bottom ground line BGNLa exposed through the first insulating layer 131 .

[0286] The second bottom ground line BGNLb may be provided on the same layer as the second bottom low-potential power line BVL2b and may be formed of the same material as the second bottom low-potential power line BVL2b. For example, the second bottom ground line BGNLb may be integrally formed with the second bottom low-potential power line BVL2b, but is not limited thereto. The second bottom ground line BGNLb may be formed of a conductive material such as, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0287] A third bottom ground line BGNLc may be disposed under the second bottom ground line BGNLb.

[0288] The third bottom ground line BGNLc may make contact with one surface of the second bottom ground line BGNLb exposed through the second and third insulating layers 132 and 133 .

[0289] The third bottom ground line BGNLc may be provided on the same layer as the third bottom low-potential power line BVL2c, and may be formed of the same material as the third bottom low-potential power line BVL2c. For example, the third bottom ground line BGNLc may be integrally formed with the third bottom low-potential power line BVL2c, but the present invention is not limited thereto. For example, the third bottom ground line BGNLc may be formed of a conductive material, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the present invention is not limited thereto.

[0290] A plurality of bottom ground lines BGNL may be connected to a plurality of bottom ground pads BGNP. Figure 10Although not shown, the display device 100 may further include a bottom cover supporting the display panel PN. In this case, the plurality of bottom ground lines BGNL may be grounded to the bottom cover via a conductive tape. For example, a conductive tape may be provided along the first edge EG1 of the first and second substrates 110 and 130, and the plurality of bottom ground lines BGNL may be grounded to a ground voltage.

[0291] In addition, when multiple first pads to which a high potential voltage is applied are provided in the first edge of the display device and multiple second pads to which a low potential voltage is applied are provided in the second edge, a path for discharging static electricity is not formed in the first edge of the display device. Therefore, the first edge of the display device may be affected by static electricity. Specifically, when the data pads among the multiple first pads of the display device are provided in the outermost area, static electricity cannot be discharged due to wiring capacity limitations. Therefore, static electricity generated in the data pads provided in the corners of the first pad area may enter the data line and overcurrent may flow into the data line, causing the data line to short-circuit or open. As a result, a burn-in phenomenon of the display panel may occur.

[0292] Furthermore, when forming a display device by bonding a first substrate to a second substrate, lateral wires are formed on the side surfaces of the first substrate and the second substrate to electrically connect multiple drive transistors above the first substrate with multiple wirings below the second substrate. In this case, when static electricity is generated in the display device, it may enter the lateral wires through the lateral insulating layer. For example, the lateral insulating layer may have a smaller thickness between adjacent pads, allowing static electricity to enter the lateral wires through the thinner lateral insulating layer. Therefore, an anti-static circuit is provided above the first substrate to discharge static electricity entering the display device. However, to reduce the bezel of the display panel, multiple drive transistors for driving the multiple pixels of the display device are provided on the first substrate, and only multiple wirings connected to the multiple drive transistors provided on the first substrate may be provided below the second substrate. In this case, it is difficult to place a separate circuit structure below the second substrate. Therefore, it is difficult to place an anti-static circuit below the second substrate. Consequently, when static electricity is generated on the rear surface of the second substrate, a path for dissipating the static electricity is not formed, resulting in the static electricity being affected. Consequently, static electricity generated on the rear surface of the second substrate can damage the drive transistors provided above the first substrate via the lateral wires, causing defects in the display device.

[0293] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a top ground pad TGNP and a bottom ground pad BGNP are provided in the first top pad area TPA1 of the first substrate 110 and the first bottom pad area BPA1 of the second substrate 130, respectively. Specifically, the top ground pad TGNP and the bottom ground pad BGNP may be provided closer to the periphery of the first substrate 110 and the periphery of the second substrate 130 than the plurality of first top pads TPAD1 and the plurality of first bottom pads BPAD1. Therefore, when static electricity enters the corners of the first top pad area TPA1 and the first bottom pad area BPA1, separate paths are formed that allow the static electricity to flow through the top ground pad TGNP and the bottom ground pad BGNP. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, overcurrent that may be generated in the first top pad area TPA1 and the first bottom pad area BPA1 can be suppressed.

[0294] Furthermore, in the display device 100 according to the exemplary embodiment of the present disclosure, a top ground pad TGNP and a bottom ground pad BGNP are provided in the first top pad area TPA1 and the first bottom pad area BPA1, respectively. Therefore, static electricity can be dissipated without providing a separate anti-static circuit. Consequently, the top ground pad TGNP and the bottom ground pad BGNP discharge static electricity generated by external contact or internally, thereby improving the reliability of the display device 100. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, damage to the multiple driving transistors DT and the light-emitting diodes LED due to static electricity can be suppressed.

[0295] Exemplary embodiments of the present disclosure may also be described as follows:

[0296] According to one aspect of the present disclosure, a display device is provided. The display device includes: a first substrate; a plurality of top pads arranged above the first substrate; a second substrate arranged below the first substrate; a plurality of bottom pads arranged below the second substrate; a plurality of lateral lines that can be arranged on the side surface of the first substrate and the side surface of the second substrate to connect the plurality of top pads and the plurality of bottom pads; and a plurality of ground pads that can be arranged in the first edge of the first substrate and the first edge of the second substrate, wherein the plurality of top pads include: a plurality of first pads arranged in a first pad area of ​​the first edge of the first substrate; and a plurality of second pads arranged in a second pad area of ​​the second edge of the first substrate. A plurality of second solder pads in the domain, the plurality of bottom solder pads include: a plurality of first solder pads arranged in a first solder pad area at the first edge of the second substrate; and a plurality of second solder pads arranged in a second solder pad area at the second edge of the second substrate, wherein the plurality of first solder pads of the plurality of top solder pads and the plurality of bottom solder pads are applied with a high potential voltage, the plurality of second solder pads of the plurality of top solder pads and the plurality of bottom solder pads are applied with a low potential voltage, and the plurality of grounding pads are arranged in the first edge of the first substrate and the first edge of the second substrate to be spaced apart from each other by the plurality of first solder pads of the plurality of top solder pads and the plurality of bottom solder pads.

[0297] The display device may also include: a plurality of side grounding lines arranged on the side surface of the first substrate and the side surface of the second substrate, wherein each of the plurality of grounding pads may include: a top grounding pad that can be arranged above the first substrate and formed with the same structure as the plurality of top pads; and a bottom grounding pad that can be arranged below the second substrate and formed with the same structure as the plurality of bottom pads, and the plurality of side grounding lines can connect the top grounding pad and the bottom grounding pad.

[0298] The display device may further include: a high potential power line and a low potential power line arranged under the second substrate, wherein the second substrate may include: a first pad area which may be arranged in a first edge of the second substrate and in which the plurality of first pads among the plurality of bottom pads are arranged; a second pad area which is arranged in a second edge of the second substrate and in which the plurality of second pads among the plurality of bottom pads are arranged; a line area arranged between the first pad area and the second pad area; and a COF pad area arranged between the first pad area and the second pad area, the line area may include: a first line area arranged between the COF pad area and the first pad area; and a second line area arranged between the COF pad area and the second pad area, the high potential power line may be arranged in the first line area to be connected to the plurality of first pads among the plurality of bottom pads, and the low potential power line may be arranged in the second line area to be connected to the plurality of second pads among the plurality of bottom pads.

[0299] The display device may further include: a plurality of ground lines that may be disposed outside the high potential power line in the first line area, wherein the plurality of ground lines may extend to a first edge of the second substrate to be connected to the plurality of ground pads.

[0300] The plurality of ground lines may be in contact with the low-potential power line.

[0301] The low potential power line may include: a first low potential power line disposed below the second substrate; a second low potential power line disposed below the first low potential power line; and a third low potential power line disposed below the second low potential power line.

[0302] Each of the plurality of ground lines may include: a first ground line arranged on the same layer as the first low-potential power line; a second ground line arranged on the same layer as the second low-potential power line; and a third ground line arranged on the same layer as the third low-potential power line.

[0303] The first ground line may be formed integrally with the first low-potential power line, the second ground line may be formed integrally with the second low-potential power line, and the third ground line may be formed integrally with the third low-potential power line.

[0304] The display device may further include: a plurality of data lines that can be arranged in the first line area to extend to the COF pad area; and a plurality of auxiliary low-potential power lines that can overlap with the plurality of data lines below the plurality of data lines, wherein the plurality of data lines and the plurality of auxiliary low-potential power lines can be arranged below the high-potential power line to overlap with a portion of the high-potential power line.

[0305] The plurality of auxiliary low-potential power lines may extend to the second line region to be electrically connected to the low-potential power lines.

[0306] The display device may further include: a plurality of auxiliary high potential power lines that may be disposed below the high potential power line to contact the high potential power line, wherein the plurality of auxiliary high potential power lines may be alternately disposed with the plurality of auxiliary low potential power lines.

[0307] The plurality of auxiliary high potential power lines and the plurality of auxiliary low potential power lines may be provided on different layers.

[0308] The multiple data lines and the multiple auxiliary high-potential power lines can be arranged on the same layer, the high-potential power lines can be arranged above the multiple data lines and the multiple auxiliary high-potential power lines, and the multiple auxiliary low-potential power lines can be arranged below the multiple data lines and the multiple auxiliary high-potential power lines.

[0309] The display device may further include: an inorganic insulating layer disposed between the plurality of data lines and the high potential power lines; and an organic insulating layer disposed between the plurality of data lines and the plurality of auxiliary high potential power lines and the plurality of auxiliary low potential power lines.

[0310] Each of the plurality of bottom pads may include: a first bottom pad electrode disposed below the second substrate; a second bottom pad electrode disposed below the first bottom pad electrode; and a third bottom pad electrode disposed below the second bottom pad electrode. The high-potential power line may be disposed on the same layer as the first bottom pad electrode, the plurality of data lines and the plurality of auxiliary high-potential power lines may be disposed on the same layer as the second bottom pad electrode, and the plurality of auxiliary low-potential power lines may be disposed on the same layer as the third bottom pad electrode.

[0311] The third bottom pad electrode may be formed of indium tin oxide (ITO).

[0312] The closer the auxiliary high-potential power lines are to the first pad region, the smaller their widths are, and the closer the auxiliary low-potential power lines are to the first pad region, the larger their widths are.

[0313] A width of the low potential power line may correspond to a width of the second pad region, and a width of the high potential power line may correspond to a width of the first pad region.

[0314] The display device may further include: a plurality of transistors arranged on the first substrate; a plurality of reflective electrodes arranged on the plurality of transistors; a plurality of light-emitting diodes arranged on the plurality of reflective electrodes; and a connecting electrode connectable to the plurality of light-emitting diodes, and each of the plurality of top pads may include: a first top pad electrode arranged on the same layer as the plurality of transistors; a second top pad electrode arranged on the same layer as the plurality of reflective electrodes; and a third top pad electrode arranged on the same layer as the connecting electrode.

[0315] The display device may further include: a conductive tape disposed outside the plurality of side ground lines; and a bottom cover contactable with the conductive tape.

[0316] The plurality of ground connection pads may be disposed closer to an outer circumference of the first substrate and an outer circumference of the second substrate than the plurality of first pads of the plurality of top pads and the plurality of bottom pads.

[0317] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for the purpose of illustration and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are merely illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the subsequent claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: a first substrate; a plurality of top pads disposed above the first substrate; a second substrate disposed below the first substrate; a plurality of bottom pads disposed below the second substrate; a plurality of side lines disposed on a side surface of the first substrate and a side surface of the second substrate to connect the plurality of top pads and the plurality of bottom pads; as well as a plurality of ground pads disposed in the first edge of the first substrate and the first edge of the second substrate, wherein the plurality of top pads include: a plurality of first pads disposed in a first pad region of a first edge of the first substrate; and a plurality of second pads arranged in a second pad region at a second edge of the first substrate, The plurality of bottom pads include: a plurality of first pads disposed in a first pad region of a first edge of the second substrate; and a plurality of second pads arranged in a second pad region on a second edge of the second substrate, wherein a high potential voltage is applied to the first plurality of pads of the plurality of top pads and the plurality of bottom pads, a low potential voltage is applied to the second plurality of pads of the plurality of top pads and the plurality of bottom pads, and The plurality of grounding pads are disposed in the first edge of the first substrate and the first edge of the second substrate so as to be spaced apart from each other via the plurality of first pads of the plurality of top pads and the plurality of bottom pads.

2. The display device according to claim 1, further comprising: a plurality of side grounding lines provided on the side surface of the first substrate and the side surface of the second substrate, Each of the plurality of ground pads comprises: a top ground pad disposed over the first substrate and formed in the same structure as the plurality of top pads; and a bottom ground pad disposed under the second substrate and formed in the same structure as the plurality of bottom pads, The plurality of side grounding lines connect the top grounding pad and the bottom grounding pad.

3. The display device according to claim 1, further comprising: a high potential power line and a low potential power line provided below the second substrate; The second substrate comprises: the first pad region disposed in a first edge of the second substrate and in which the plurality of first pads among the plurality of bottom pads are disposed; a second pad region disposed in a second edge of the second substrate and in which the plurality of second pads among the plurality of bottom pads are disposed; a line region disposed between the first pad region and the second pad region; and A COF pad region is provided between the first pad region and the second pad region, The line area includes: A first line region disposed between the COF pad region and the first pad region; and A second line region is provided between the COF pad region and the second pad region, The high potential power line is arranged in the first line area to be connected to the multiple first pads among the multiple bottom pads, and the low potential power line is arranged in the second line area to be connected to the multiple second pads among the multiple bottom pads.

4. The display device according to claim 3, further comprising: a plurality of ground lines arranged outside the high-potential power line in the first line region, The plurality of ground lines extend to the first edge of the second substrate to be connected to the plurality of ground pads. 5 . The display device according to claim 4 , wherein the plurality of ground lines are in contact with the low potential power line.

6. The display device according to claim 4, wherein the low potential power line comprises: a first low-potential power line disposed below the second substrate; a second low-potential power line disposed below the first low-potential power line; and A third low-potential power line is provided below the second low-potential power line.

7. The display device according to claim 6, wherein each of the plurality of ground lines comprises: a first ground line provided on the same layer as the first low-potential power line; a second ground line provided on the same layer as the second low-potential power line; and A third ground line is provided on the same layer as the third low-potential power line. 8 . The display device according to claim 7 , wherein the first ground line is formed integrally with the first low-potential power line, the second ground line is formed integrally with the second low-potential power line, and the third ground line is formed integrally with the third low-potential power line.

9. The display device according to claim 3, further comprising: a plurality of data connection lines disposed in the first line region to extend to the COF pad region; and A plurality of auxiliary low-potential power lines are provided below and overlapping the plurality of data lines. The plurality of data connection lines and the plurality of auxiliary low-potential power lines are arranged below the high-potential power line to overlap with a portion of the high-potential power line. 10 . The display device according to claim 9 , wherein the plurality of auxiliary low potential power lines extend to the second line region to be electrically connected to the low potential power lines.

11. The display device according to claim 9, further comprising: a plurality of auxiliary high-potential power lines disposed below the high-potential power line so as to be in contact with the high-potential power line, The plurality of auxiliary high-potential power lines and the plurality of auxiliary low-potential power lines are arranged alternately. 12 . The display device according to claim 11 , wherein the plurality of auxiliary high potential power supply lines and the plurality of auxiliary low potential power supply lines are provided on different layers.

13. The display device according to claim 11, wherein the plurality of data lines and the plurality of auxiliary high-potential power lines are arranged on the same layer, the high-potential power lines are arranged above the plurality of data lines and the plurality of auxiliary high-potential power lines, and the plurality of auxiliary low-potential power lines are arranged below the plurality of data lines and the plurality of auxiliary high-potential power lines.

14. The display device according to claim 13, further comprising: an inorganic insulating layer disposed between the plurality of data lines and the high-potential power line; and An organic insulating layer is provided between the plurality of data lines and the plurality of auxiliary high potential power lines and the plurality of auxiliary low potential power lines.

15. The display device according to claim 14, wherein each of the plurality of bottom pads comprises: a first bottom pad electrode disposed below the second substrate; a second bottom pad electrode disposed below the first bottom pad electrode; and a third bottom pad electrode disposed below the second bottom pad electrode, The high potential power line and the first bottom pad electrode are arranged on the same layer, the multiple data lines and the multiple auxiliary high potential power lines and the second bottom pad electrode are arranged on the same layer, and the multiple auxiliary low potential power lines and the third bottom pad electrode are arranged on the same layer. 16 . The display device of claim 15 , wherein the third bottom pad electrode is formed of indium tin oxide (ITO). 17 . The display device according to claim 11 , wherein the widths of the auxiliary high potential power lines decrease as they are closer to the first pad region, and the widths of the auxiliary low potential power lines increase as they are closer to the first pad region. 18 . The display device according to claim 3 , wherein a width of the low potential power supply line corresponds to a width of the second pad region, and a width of the high potential power supply line corresponds to a width of the first pad region.

19. The display device according to claim 3, further comprising: a plurality of transistors disposed on the first substrate; a plurality of reflective electrodes disposed on the plurality of transistors; a plurality of light emitting diodes disposed on the plurality of reflective electrodes; and connecting electrodes connected to the plurality of light emitting diodes, Each of the plurality of top pads comprises: a first top pad electrode disposed on a same layer as the plurality of transistors; a second top pad electrode provided on the same layer as the plurality of reflective electrodes; and A third top pad electrode is provided on the same layer as the connection electrode.

20. The display device according to claim 2, further comprising: a conductive tape disposed outside the plurality of side grounding wires; and A bottom cover is in contact with the conductive tape. 21 . The display device of claim 1 , wherein the plurality of ground pads are disposed closer to outer circumferences of the first substrate and the second substrate than the plurality of first pads of the plurality of top pads and the plurality of bottom pads.

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