Display panel and electronic device including the same

Abstract

The invention provides a display panel and an electronic device including the same. The display panel having at least one hole in a display area includes: a substrate; a plurality of display elements arranged in a plane around the at least one hole; and a plurality of signal lines extending in a first direction, in which the at least one hole includes a first hole having a first width in a second direction and having two sides having an asymmetric shape with respect to a first centerline passing through a center of the first width, each of adjacent first and second signal lines of the plurality of signal lines extends in a first direction, the first signal line being wound around a first side of the first hole, the second signal line being wound around a second side of the first hole opposite the first side, the first signal line and the second signal line are asymmetric with respect to a first dummy line therebetween.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 11, 2020, application number "202010953210.8" and invention name "Display panel and electronic device including the display panel". Technical Field

[0002] One or more embodiments relate to a display panel and an electronic device including the display panel. Background Art

[0003] Recently, the purposes of display devices have been diversified. In addition, as display devices have become thinner and lighter, their scope of use has gradually expanded.

[0004] Since display devices are used in various appropriate ways, their shapes can be designed in various appropriate ways. In addition, the functions that can be combined with or associated with display devices are increasing. Summary of the Invention

[0005] Aspects and features of the present disclosure relate to a display device capable of adding functionality that can be combined with or associated with the display device. One or more embodiments of the present disclosure provide a display panel and an electronic device, wherein the display panel includes multiple areas within a display area, and cameras, sensors, etc. can be arranged in the multiple areas. However, in this case, designing the layout of wiring around the multiple areas is difficult.

[0006] One or more embodiments of the present disclosure provide a structure that can prevent or reduce degradation of display quality by properly arranging wiring around multiple areas. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0008] According to one or more embodiments, a display panel having at least one hole in a display area includes: a substrate; a plurality of display elements arranged on the substrate, the plurality of display elements being arranged in a plane around the at least one hole and defining a display area; and a plurality of signal lines electrically connected to the plurality of display elements and extending along a first direction, wherein the at least one hole includes a first hole having a first width along a second direction different from the first direction, and the first hole has two sides, the two sides having an asymmetric shape relative to a first center line passing through the center of the first width, wherein a first signal line among the plurality of signal lines and a second signal line among the plurality of signal lines adjacent to the first signal line each extend along the first direction, the first signal line is arranged around a first side of the first hole, and the second signal line is arranged around a second side of the first hole opposite to the first side, wherein the first signal line and the second signal line are asymmetric relative to a first virtual line between the first signal line and the second signal line.

[0009] The first virtual line may be spaced apart from the first center line along the second direction.

[0010] The display panel may further include an intermediate area between the first hole and the display area, the first signal line may include a first bypass portion located in the intermediate area and bypassing around a first side of the first hole, and the second signal line may include a second bypass portion located in the intermediate area and bypassing around a second side of the first hole.

[0011] The first detour portion and the second detour portion may have asymmetrical shapes with respect to the first imaginary line.

[0012] A first distance between the first signal line and the second signal line in the display area may be greater than a second distance between the first signal line and the second signal line in the middle area.

[0013] One of the first signal line and the second signal line may include a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and the insulating layer is located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to the first conductive layer through a contact hole located in the insulating layer.

[0014] The multiple signal lines may further include a third signal line and a fourth signal line, the third signal line being located on one side of the second signal line, and the first signal line being located between the third signal line and the second signal line; the fourth signal line being located on one side of the first signal line, and the second signal line being located between the fourth signal line and the first signal line, and the third signal line and the fourth signal line may be asymmetric relative to the first virtual line.

[0015] Each of the first signal line and the third signal line may include: an extension portion extending along a first direction; and a bypass portion connected to the extension portion and arranged around a first side of the first hole, and a first connection point between the extension portion of the first signal line and the bypass portion and a second connection point between the extension portion of the third signal line and the bypass portion may be arranged on a first virtual inclined line inclined relative to the first direction and the second direction.

[0016] The plurality of signal lines may include data lines or scan lines.

[0017] Each of the plurality of display elements may include an organic light emitting diode.

[0018] According to one or more embodiments, a display panel having a first hole includes: a plurality of display elements arranged in a plane around the first hole; and a plurality of signal lines electrically connected to the plurality of display elements and extending along a first direction, wherein a first signal line among the plurality of signal lines and each of a second signal line adjacent to the first signal line among the plurality of signal lines extend along the first direction, the first signal line is arranged around a first side of the first hole, and the second signal line is arranged around a second side of the first hole opposite to the first side, wherein the first signal line and the second signal line are asymmetric relative to a first virtual line between the first signal line and the second signal line.

[0019] Each of the first signal line and the second signal line may include: extension portions, both extending in a first direction and spaced apart from each other; and bypass portions connected to each of the extension portions, wherein the bypass portion of the first signal line bypasses around a first side of the first hole, and the bypass portion of the second signal line bypasses around a second side of the first hole, and the bypass portion of the first signal line and the bypass portion of the second signal line may be asymmetric relative to the first virtual line.

[0020] The multiple signal lines may further include: a third signal line, located on one side of the second signal line, and the first signal line is located between the third signal line and the second signal line; and a fourth signal line, located on one side of the first signal line, and the second signal line is located between the fourth signal line and the first signal line, and the third signal line and the fourth signal line may be asymmetric relative to the first virtual line.

[0021] The third signal line may include: an extension portion extending along a first direction; and a bypass portion connected to the extension portion and arranged around a first side of the first hole, a first connection point between one of the extension portions of the first signal line and the bypass portion and a second connection point between the extension portion of the third signal line and the bypass portion may be arranged along a first virtual oblique line inclined relative to the first direction.

[0022] The fourth signal line may include: an extension portion extending along the first direction; and a bypass portion connected to the extension portion and arranged around the second side of the first hole, a third connection point between one of the extension portions of the second signal line and the bypass portion and a fourth connection point between the extension portion of the fourth signal line and the bypass portion may be arranged along a second virtual oblique line inclined relative to the first direction.

[0023] Each of the first signal line and the fourth signal line may include a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and the insulating layer is located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to the first conductive layer through a contact hole located in the insulating layer.

[0024] The detour portion of the first signal line may be spaced a constant distance from the first side of the first hole, and the detour portion of the second signal line may be spaced a constant distance from the second side of the first hole.

[0025] The first hole may have a first width in a second direction different from the first direction, and both sides of the first hole may have asymmetrical shapes with respect to a first center line passing through a center of the first width in the first direction.

[0026] The first virtual line may be spaced apart from the first center line along the second direction.

[0027] The first virtual line and the first center line may be the same line, and the width or thickness of one of the detour portion of the first signal line and the detour portion of the second signal line may be greater than the width or thickness of the other of the detour portion of the first signal line and the second signal line.

[0028] The display panel may include: a substrate; a display layer located on the substrate and including the plurality of display elements; and an encapsulation layer located on the display layer, and the first hole may pass through a stack structure including the substrate, the display layer, and the encapsulation layer.

[0029] According to one or more embodiments, an electronic device includes: a display panel having a first hole; and at least one component corresponding to the first hole of the display panel, wherein the display panel includes: a plurality of display elements arranged around the first hole; and a plurality of signal lines electrically connected to the plurality of display elements and extending along a first direction, wherein a first signal line among the plurality of signal lines and each of a second signal line adjacent to the first signal line among the plurality of signal lines extend along the first direction, the first signal line includes a first bypass portion bypassing around a first side of the first hole, and the second signal line includes a second bypass portion bypassing around a second side of the first hole opposite to the first side, wherein the first bypass portion of the first signal line and the second bypass portion of the second signal line are asymmetric relative to a first virtual line between the first signal line and the second signal line.

[0030] The multiple signal lines may further include: a third signal line located on one side of the second signal line, with the first signal line located between the third signal line and the second signal line, and the third signal line includes a third bypass portion that bypasses around the first side of the first hole; and a fourth signal line located on one side of the first signal line, with the second signal line located between the fourth signal line and the first signal line, and the fourth signal line includes a fourth bypass portion that bypasses around the second side of the first hole, wherein the third bypass portion of the third signal line and the fourth bypass portion of the fourth signal line may be asymmetric relative to the first virtual line.

[0031] The first signal line may include an extension portion extending along the first direction and a first bypass portion connected to the extension portion, the third signal line may include an extension portion extending along the first direction and a third bypass portion connected to the extension portion, and the first connection point between the extension portion of the first signal line and the first bypass portion and the second connection point between the extension portion of the third signal line and the third bypass portion may be arranged along a first virtual oblique line inclined relative to the first direction.

[0032] The first hole may have a first width in a second direction different from the first direction, and both sides of the first hole may have asymmetrical shapes with respect to a first center line passing through a center of the first width.

[0033] The first virtual line may be spaced apart from the first center line along the second direction.

[0034] The first virtual line and the first center line may be the same line, and a width or thickness of one of the first detour portion and the second detour portion may be greater than a width or thickness of the other of the first detour portion and the second detour portion.

[0035] The at least one component may include an electronic element that emits light or receives light through the first aperture.

[0036] The electronic components may include a camera, a sensor for recognizing a part of the human body, or a light.

[0037] The display panel may further have a second hole spaced apart from the first hole, and the display panel may further include an additional component corresponding to the second hole.

[0038] These and other aspects and features will become more apparent and will be more readily understood from the description of the embodiments, the accompanying drawings, and the claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other aspects and features of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1A and Figure 1B Each is a perspective view of an electronic device according to an embodiment;

[0041] Figures 2A to 2C Each is a cross-sectional view of an electronic device according to an embodiment;

[0042] Figure 3A and Figure 3B Each is a cross-sectional view of a display panel according to an embodiment;

[0043] Figure 4A and Figure 4B Each is a cross-sectional view of a display panel according to an embodiment;

[0044] Figure 5A and Figure 5B Each is a plan view of a display panel according to an embodiment;

[0045] Figure 6 is an equivalent circuit diagram of a pixel circuit electrically connected to an organic light emitting diode of a display panel according to an embodiment;

[0046] Figure 7 is a plan view of a portion of a display panel according to an embodiment;

[0047] Figure 8 is a plan view of signal lines arranged around a first region according to an embodiment;

[0048] Figure 9A yes Figure 8 a plan view of four signal lines adjacent to each other among the signal lines;

[0049] Figure 9B and Figure 9C Each is Figure 9A a cross-sectional view of one of the signal lines;

[0050] Figure 10 It is along Figure 8 A cross-sectional view of the signal line taken along lines Xa-Xa' and Xb-Xb';

[0051] Figure 11 is a plan view of a portion of a display panel according to an embodiment;

[0052] Figure 12A is a plan view of signal lines arranged around a first region according to an embodiment;

[0053] Figure 12B yes Figure 12A Extracted plan views of some of the signal lines;

[0054] Figure 13 is a plan view of a portion of a display panel according to an embodiment;

[0055] Figure 14A is a plan view of a portion of a display panel according to an embodiment;

[0056] Figure 14B It is along Figure 14A a cross-sectional view of the display panel taken along line XIV-XIV'; and

[0057] Figure 15 is a plan view of a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0058] With reference now to embodiment, the example of embodiment is shown in the accompanying drawings, wherein the same figure mark represents the same element from time to time.In this regard, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein.Therefore, below only by referring to the accompanying drawings, describe embodiment, to explain aspect and feature of the present disclosure.As used herein, when describing an embodiment of the present invention, the use of term "can" represents "one or more embodiments of the present invention".As used herein, term "and / or" includes any combination and all combinations of one or more of the relevant listed items.Throughout the disclosure, expression "at least one (kind / person) of a, b and c" represents only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variations.

[0059] Since the present disclosure allows for various suitable changes and numerous embodiments, example embodiments will be shown in the accompanying drawings and described in the written description. Aspects and features of the present disclosure and methods of implementing the present disclosure will be apparent when referring to the embodiments described herein below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described herein below and may be implemented in various forms.

[0060] Hereinafter, the disclosed embodiments are described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are given to the same or corresponding elements, and repeated description thereof may not be provided.

[0061] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.

[0062] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0063] It will also be understood that the terms “comprises” and “comprising” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0064] It will be understood that when a layer, region, or component is referred to as being "on" another layer, region, or component, the layer, region, or component can be directly or indirectly on the other layer, region, or component. For example, there may be (multiple) intervening layers, regions, or components. In contrast, when an element or layer is referred to as being "directly on" another layer, region, or component, there are no intervening layers, regions, or components.

[0065] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. For example, the size and thickness of the components in the drawings may be exaggerated for ease of explanation, and the following embodiments are not limited thereto. As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that one of ordinary skill in the art would recognize.

[0066] When the disclosed embodiments can be implemented differently, the order of the disclosed processes can be performed differently from the order described. For example, two consecutively described processes can be performed simultaneously or substantially simultaneously, or can be performed in the reverse order of the described order.

[0067] It will be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, the layer, region, or component may be "directly connected" to the other layer, region, or component, or the layer, region, or component may be "indirectly connected" to the other layer, region, or component with (multiple) other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, the layer, region, or component may be "directly electrically connected" to the other layer, region, or component, or the layer, region, or component may be "indirectly electrically connected" to the other layer, region, or component through (multiple) other layers, regions, and / or components that are electrically interposed therebetween. Furthermore, as used herein, when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, the layer, region, or component may, for example, be electrically connected or electrically coupled to the other layer, region, or component to operate.

[0068] Figure 1A and Figure 1B Each is a perspective view of an electronic device 1 according to an embodiment.

[0069] The electronic device 1 may include at least one component area arranged in the display area DA. Figure 1A As shown in FIG, two component areas (eg, a first area RA1 and a second area RA2) may be arranged within the display area DA. In some embodiments, as shown in FIG. Figure 1BAs shown in FIG, a component area (eg, a first area RA1) may be arranged within the display area DA. The first area RA1 and the second area RA2 are areas in which the following reference Figures 2A to 2C By utilizing these components, the electronic device 1 can have various appropriate functions.

[0070] In the case where the electronic device 1 includes multiple component areas, the first area RA1 and the second area RA2 may have different sizes (e.g., areas) and / or different shapes. The first area RA1 may have an asymmetric, non-typical shape with respect to the horizontal direction (e.g., the x direction) and / or the longitudinal direction (e.g., the y direction). For example, Figure 1A and Figure 1B As shown in , the first region RA1 may have an asymmetrical shape with respect to a line along the longitudinal direction (e.g., the y direction). The second region RA2 may have a symmetrical shape with respect to the horizontal direction (e.g., the x direction) and / or the longitudinal direction (e.g., the y direction). For example, Figure 1A As shown in , the second area RA2 may have a shape such as a circle, a quasi-ellipse (oval), or a quadrangle.

[0071] The display area DA can display a predetermined color or a set image by utilizing light emitted from a plurality of pixels arranged in the display area DA. Each pixel may include a display element for emitting light of a predetermined color or a set color. For example, display elements for emitting red light, green light, or blue light may be arranged two-dimensionally in the x-direction and the y-direction (e.g., arranged in a plane parallel to both the x-direction and the y-direction), and the display area DA in which the image is displayed may be defined (e.g., may be defined by the area including the display elements).

[0072] The middle area MA may be arranged between at least one component area and the display area DA. In some embodiments, the middle area MA may be adjacent to the component area, for example, closely surrounding at least a portion or all of the component area. The display area DA may be surrounded by the peripheral area PA. The middle area MA and the peripheral area PA may be non-display areas in which no pixels are arranged. The middle area MA may be entirely surrounded by the display area DA, and the display area DA may be surrounded by the peripheral area PA.

[0073] The electronic device 1 may include various appropriate types of devices that can provide images, such as a tablet personal computer (PC), a notebook computer, a mobile phone, and a smart band or smart watch that can be worn on a wrist.

[0074] Figures 2A to 2C Each is along Figure 1A sectional view of the electronic device 1 according to the embodiment taken along line II-II′.

[0075] Reference Figures 2A to 2C , the electronic device 1 has a space therein and includes a housing HS having one open side. The one open side of the housing HS may be coupled to a window 60 (e.g., covered by the window 60). A stacked structure may be arranged (e.g., arranged in the housing HS), the stacked structure including the display panel 10, the input sensing layer 40, and the optical functional layer 50. At least one component may be arranged below the back side (e.g., the lower surface) of the display panel 10. Although Figures 2A to 2C A first component 21 , a second component 22 , a third component 23 , a fourth component 24 , and a fifth component 25 are shown, but the number of components and the types of components may be variously and appropriately changed.

[0076] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be arranged within the housing HS and located between the display panel 10 and the bottom surface or bottom of the housing HS. Some of the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be arranged in the first area RA1, and the remaining components of the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may be arranged in the second area RA2. In an embodiment, the first component 21, the second component 22, the third component 23, and the fourth component 24 may be arranged in the first area RA1, and the fifth component 25 may be arranged in the second area RA2.

[0077] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may include electronic components that utilize light and / or sound. The electronic components may include (for example, may be) a sensor for measuring distance (such as a proximity sensor), a sensor for identifying a part of the user's body (for example, a fingerprint, an iris, a face, etc.), a small lamp for outputting light, and / or an image sensor for capturing an image (for example, a camera). The electronic components that utilize light may utilize light in various appropriate wavelengths including visible light, infrared light, and / or ultraviolet light. The electronic components that utilize sound may utilize ultrasound and / or sound in other frequency bands.

[0078] Light and / or sound utilized by the electronic component may proceed to the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 (e.g., may be received by the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25) and / or may be emitted from the first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 through the first area RA1 and the second area RA2. Therefore, the first area RA1 and the second area RA2 may be a type of transmissive area that may transmit light and / or sound.

[0079] The first component 21, the second component 22, the third component 23, the fourth component 24, and the fifth component 25 may include the same type of electronic components or may include different types of electronic components. In an embodiment, the first component 21 and the fifth component 25 may include an image sensor (e.g., a camera), and the second component 22, the third component 23, and the fourth component 24 may include at least one infrared sensor.

[0080] The infrared sensor may include a light emitter and a light receiver. The light emitter and light receiver may be formed as a single unit or may be formed separately as individual components. In an embodiment, the second component 22, the third component 23, and the fourth component 24 may each include a portion of an infrared sensor. For example, some of the second component 22, the third component 23, and the fourth component 24 may include a light emitter that emits light, and the remaining components of the second component 22, the third component 23, and the fourth component 24 may include a light receiver that receives light.

[0081] The display panel 10 may display an image. The display panel 10 may display an image by utilizing a display element (eg, an organic light emitting diode arranged in the display area DA). In an embodiment, the display element may include an inorganic light emitting diode or a quantum dot light emitting diode.

[0082] The input sensing layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input sensing layer 40 includes sensing electrodes (e.g., touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be arranged on the display panel 10. The input sensing layer 40 may sense an external input by utilizing a mutual capacitance method and / or a self-capacitance method.

[0083] like Figures 2A to 2C As shown in , the input sensing layer 40 may be directly formed on the display panel 10. For example, the input sensing layer 40 may be formed sequentially after the process of forming the display panel 10. In some embodiments, the adhesive layer may not be disposed between the input sensing layer 40 and the display panel 10. In some embodiments, the input sensing layer 40 may be formed separately and then bonded to the display panel 10 by using an adhesive layer. The adhesive layer may include (for example, may be) an optically clear adhesive (OCA) (see Figures 2A to 2C Figure 1 shows the OCA in the figure).

[0084] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident on the display panel 10 from the outside through the window 60. In some embodiments, the anti-reflection layer may reduce the amount of light (e.g., external light) incident on the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder (e.g., a film-based retarder) or a liquid crystal retarder (e.g., a liquid crystal-based retarder). The retarder may include a λ / 2 retarder (e.g., a half-wave plate retarder) and / or a λ / 4 retarder (e.g., a quarter-wave plate retarder). The polarizer may include a film-type polarizer (e.g., a film-based polarizer) or a liquid crystal polarizer (e.g., a liquid crystal-based polarizer). The film-type polarizer (e.g., a film-based polarizer) may include a stretchable synthetic resin film, and the liquid crystal polarizer (e.g., a liquid crystal-based polarizer) may include liquid crystals arranged in a predetermined arrangement or set arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and polarizer themselves or the protective films of the retarder and polarizer may be defined as a base layer of the anti-reflection layer.

[0085] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of each beam of light emitted from the pixels of the display panel 10 (e.g., based on the color of the light). For example, a red color filter that filters red light may be arranged to overlap with the pixel emitting red light. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged on different layers. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may destructively interfere, thereby reducing the reflectivity of the external light.

[0086] The optical function layer 50 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or include multiple layers having different refractive indices. The optical function layer 50 may include an anti-reflection layer and / or a lens layer.

[0087] The optical functional layer 50 may be bonded to the window 60 through an adhesive layer such as OCA.

[0088] The display panel 10, the input sensing layer 40 and / or the optical function layer 50 may have holes in the first area RA1 and the second area RA2, respectively. Figure 2AAs shown in , the display panel 10, the input sensing layer 40, and the optical function layer 50 respectively have a first hole 10H, a second hole 40H, and a third hole 50H that overlap each other. The first hole 10H can be formed to penetrate from the top surface of the display panel 10 to the bottom surface of the display panel 10. The second hole 40H can be formed to penetrate from the top surface of the input sensing layer 40 to the bottom surface of the input sensing layer 40. The third hole 50H can be formed to penetrate from the top surface of the optical function layer 50 to the bottom surface of the optical function layer 50. Each of the first hole 10H, the second hole 40H, and the third hole 50H can be positioned to correspond to the first area RA1 and the second area RA2 (for example, overlap with the first area RA1 and the second area RA2). The first area RA1 and the second area RA2 can each be a type of hole area (for example, an area corresponding to (a plurality of) holes (for example, corresponding to the first hole 10H, the second hole 40H, and / or the third hole 50H)). The sizes (eg, diameter, width, or area) of the first hole 10H, the second hole 40H, and the third hole 50H may be equal to or different from each other. Figure 2A It is shown that the OCA may be entirely formed on the back side (eg, bottom side) of the window 60 , but in embodiments, the OCA may include holes in the first area RA1 and / or the second area RA2 .

[0089] In some embodiments, the display panel 10, the input sensing layer 40 and / or the optical functional layer 50 do not include holes. For example, in some embodiments, Figure 2B As shown in , the display panel 10 may include the first hole 10H corresponding to the first area RA1 and the second area RA2, but the input sensing layer 40 and the optical function layer 50 do not include the hole. In some embodiments, when light and / or sound sufficiently passes through the first area RA1 and the second area RA2, each of the display panel 10, the input sensing layer 40, and the optical function layer 50 does not include the hole corresponding to the first area RA1 and the second area RA2, for example, as Figure 2C As shown in .

[0090] Figure 3A and Figure 3B Each is a cross-sectional view of a display panel 10 according to an embodiment.

[0091] Reference Figure 3A The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include (for example, may be) a glass material and / or a polymer resin. The substrate 100 may include a multi-layer structure. For example, Figure 3A As shown in the enlarged view of the substrate 100 in FIG, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103 and a second barrier layer 104.

[0092] Each of the first base layer 101 and the second base layer 103 may include (e.g., may be) a polymer resin. For example, the first base layer 101 and the second base layer 103 may include (e.g., may be) a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate, cellulose triacetate (TAC), and / or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0093] The first and second barrier layers 102 and 104 are barrier layers for preventing or blocking penetration of external foreign substances and may include a single layer structure or a multilayer structure including (eg, being) an inorganic material such as silicon nitride, silicon oxynitride, and / or silicon oxide.

[0094] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A, a pixel circuit layer 200B, and an insulating layer. The display element layer 200A may include a display element arranged for each pixel, and the pixel circuit layer 200B may include a pixel circuit electrically connected to each display element. Each pixel circuit may include a thin film transistor and a storage capacitor, and each display element may include an organic light emitting diode.

[0095] The display element of the display layer 200 may be covered by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin film encapsulation layer 300 may have a structure in which a first inorganic encapsulation layer and a second inorganic encapsulation layer are stacked in sequence. In some embodiments, the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may be stacked in this order. The first inorganic encapsulation layer and the second inorganic encapsulation layer may include (for example, may be) at least one of silicon nitride, silicon oxide, and silicon oxynitride. The organic encapsulation layer may include (for example, may be) a polymer material. The polymer material may include (for example, may be) an acryl resin, an epoxy resin, a polyimide, and / or polyethylene.

[0096] In the case where the display panel 10 includes the substrate 100 and the thin film encapsulation layer 300, which may be a multi-layer structure, the flexibility of the display panel 10 may be improved. The display panel 10 may include a first hole 10H passing through the display panel 10. The first hole 10H may be located in the first area RA1 and the second area RA2, respectively. Figure 3A , it is shown that the substrate 100 , the display layer 200 , and the encapsulation member as the thin film encapsulation layer 300 respectively include through holes 100H, 200H, and 300H each corresponding to the first hole 10H of the display panel 10 .

[0097] In another embodiment, Figure 3B As shown in FIG, the substrate 100 and the thin film encapsulation layer 300 do not include through holes. Because the components are arranged in the first and second regions RA1 and RA2 as described above, the display layer 200 can include through holes 200H in the first and second regions RA1 and RA2, and can ensure that light can pass through the through holes 200H at its transmittance. For example, in some embodiments, even if the substrate 100 and the thin film encapsulation layer 300 do not include through holes, the through holes 200H in the display layer 200 can allow light to pass through the display panel 10.

[0098] Figure 4A and Figure 4B Each is a cross-sectional view of a display panel 10 according to an embodiment.

[0099] Reference Figure 4A and Figure 4B The encapsulation member 300′ includes an encapsulation substrate 340. The encapsulation substrate 340 faces the substrate 100. The display layer 200 is arranged between the encapsulation substrate 340 and the substrate 100. The sealing material 350 is arranged between the encapsulation substrate 340 and the substrate 100. The sealing material 350 may surround the outer surface (e.g., edge or side surface) of the display layer 200. For example, in a plan view, the sealing material 350 may surround the display layer 200 (e.g., the display element layer 200A) in the peripheral area PA and the middle area MA.

[0100] Although in the cross-sectional view Figure 4A , the sealing materials 350 in the middle area MA are shown to be separated from each other (e.g., spaced apart) on both sides of the first hole 10H, but the sealing material 350 in the middle area MA may have an annular shape surrounding each of the first holes 10H in a plan view. The sealing material 350 arranged in the peripheral area PA may be separated from the sealing material 350 arranged in the middle area MA (e.g., spaced apart). Figure 4A As shown in , the first holes 10H may be formed in the first area RA1 and the second area RA2, respectively, and each of the first holes 10H may be surrounded by the sealing material 350. Figure 4A As shown in FIG, the substrate 100, the display layer 200, and the encapsulation substrate 340 respectively include through holes 100H, 200H, and 340H each corresponding to the first hole 10H of the display panel 10.

[0101] In another embodiment, Figure 4BAs shown in FIG, the substrate 100 and the encapsulation substrate 340 may not include through holes. The display layer 200 may include through holes 200H in the first and second areas RA1 and RA2, respectively, and ensure that light can pass through the through holes 200H at its transmittance. For example, the through holes 200H of the display layer 200 may allow light to pass through the display panel 10. In the case where the first holes 10H are not formed in the first and second areas RA1 and RA2 of the substrate 100 and the encapsulation substrate 340, the sealing material 350 may be formed only in the peripheral area PA.

[0102] Figure 5A and Figure 5B Each is a plan view of a display panel 10 according to an embodiment.

[0103] Reference Figure 5A and Figure 5B , the display panel 10 may include at least one area in which components may be arranged. For example, Figure 5A As shown in FIG, the display panel 10 may include a first area RA1, a second area RA2, and a display area DA, or as shown in FIG. Figure 5B As shown in , the display panel 10 may include a first area RA1.

[0104] In the examples, as referenced Figure 2A As described above, the display panel 10 may include first holes 10H corresponding to the first and second areas RA1 and RA2. In this case, Figure 5A and Figure 5B The first area RA1 or the second area RA2 shown in FIG. 1 may correspond to the first hole 10H of the display panel 10 (see FIG. 10 ). Figure 2A In another embodiment, as described above with reference to Figure 2C As described above, the display panel 10 does not include the first holes 10H corresponding to the first area RA1 and the second area RA2 , respectively.

[0105] Reference Figure 5A , the display panel 10 may include a first area RA1, a second area RA2, a display area DA, a middle area MA, and a peripheral area PA. Figure 5A The outer shape of the substrate 100 of the display panel 10 may be shown. For example, the substrate 100 may include a plurality of regions corresponding to the first region RA1, the second region RA2, the display region DA, the middle region MA, and the peripheral region PA. Figure 5B The display panel 10 may include a first area RA1, a display area DA, a middle area MA, and a peripheral area PA. The substrate 100 may include areas corresponding to the first area RA1, the display area DA, the middle area MA, and the peripheral area PA, respectively.

[0106] Each of the plurality of pixels P arranged in the display area DA may include a display element such as an organic light emitting diode. Each pixel P may emit, for example, red light, green light, or blue light from the organic light emitting diode. The first region RA1 and the second region RA2 may be arranged within the display area DA ( Figure 5A ), or the first area RA1 may be arranged within the display area DA ( Figure 5B The middle area MA may be disposed between the first and second areas RA1 and RA2 and the display area DA, or between the first area RA1 and the display area DA.

[0107] The middle area MA is a type of non-display area. Signal lines may be arranged in the middle area MA, and the signal lines may provide signals to the pixels P arranged around the middle area MA.

[0108] The first external driving circuit 110 , the second external driving circuit 120 , the terminal 140 , the first power line 160 , and the second power line 170 may be arranged in the peripheral area PA.

[0109] The first external drive circuit 110 may include a scan drive circuit and a control drive circuit. The first external drive circuit 110 may provide a scan signal and an emission control signal to each pixel P via a scan line SWL and an emission control line EL, respectively. The second external drive circuit 120 may include a scan drive circuit and a control drive circuit. The second external drive circuit 120 may be arranged parallel to (e.g., substantially parallel to) the first external drive circuit 110, with the display area DA located between the second external drive circuit 120 and the first external drive circuit 110. Like the first external drive circuit 110, the second external drive circuit 120 may provide a scan signal and an emission control signal to each pixel P via a scan line SWL and an emission control line EL, respectively.

[0110] The terminal 140 can be arranged at a side of the peripheral area PA (for example, a side of the peripheral area PA that is different from the side of the first external driving circuit 110 and the second external driving circuit 120) (for example, arranged on a side of the peripheral area PA). The terminal 140 can be exposed by not being covered by the insulating layer and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB can be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB is configured to transmit power and / or a signal of the controller to the display panel 10. The control signal generated by the controller can be transmitted to the first external driving circuit 110 and the second external driving circuit 120, respectively, through the printed circuit board PCB. The controller can provide the first power voltage ELVDD and the second power voltage ELVSS to the first power line 160 and the second power line 170, respectively, through the first connection line 161 and the second connection line 171 (see Figure 6, described below). The first power voltage ELVDD may be supplied to each pixel P through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be supplied to the counter electrode of the pixel P connected to the second power line 170.

[0111] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to each pixel P through the connection line 151 and the data line DL, the connection line 151 being connected to the terminal 140 and the data line DL being connected to the connection line 151. Figure 5A and Figure 5B , the data driving circuit 150 is shown to be disposed on the printed circuit board PCB, but in another embodiment, the data driving circuit 150 may be disposed on the substrate 100. For example, the data driving circuit 150 may be disposed between the terminal 140 and the first power line 160.

[0112] The first power line 160 may include a first sub-line 162 and a second sub-line 163 that are parallel to each other (e.g., substantially parallel to each other) and extend along the x-direction, with the display area DA located between the first sub-line 162 and the second sub-line 163. The second power line 170 may have a ring shape having one open side and partially surrounding the display area DA. For example, the second power line 170 may surround the display area DA on three sides of a rectangular or square shape.

[0113] Figure 6 is an equivalent circuit diagram of a pixel circuit PC electrically connected to an organic light emitting diode OLED of the display panel 10 according to an embodiment.

[0114] Reference Figure 6 The organic light emitting diode OLED may be connected to a pixel circuit PC, which may include a plurality of thin film transistors and a storage capacitor. The thin film transistors and the storage capacitor may be connected to the signal lines SL, SL-1, SL+1, EL, and DL, a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL.

[0115] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0116] The signal lines include a scan line SL, a previous scan line SL-1, a next scan line SL+1, an emission control line EL, and a data line DL. The scan line SL is configured to transmit a scan signal Sn (e.g., to the switching thin film transistor T2 and / or to the compensation thin film transistor T3). The previous scan line SL-1 is configured to transmit the previous scan signal Sn-1 to the first initialization thin film transistor T4. The next scan line SL+1 is configured to transmit the scan signal Sn to the second initialization thin film transistor T7. The emission control line EL is configured to transmit the emission control signal En to the operation control thin film transistor T5 and to the emission control thin film transistor T6. The data line DL crosses or intersects the scan line SL in the display panel 10 and is configured to transmit the data signal Dm. The driving voltage line PL can be configured to transmit a first power voltage ELVDD to the driving thin film transistor T1. The first initialization voltage line VL1 can be configured to transmit an initialization voltage Vint to the first initialization thin film transistor T4. The second initialization voltage line VL2 can be configured to transmit an initialization voltage Vint to the second initialization thin film transistor T7.

[0117] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 is configured to receive the data signal Dm according to (for example, according to) the switching operation of the switching thin film transistor T2, and to drive the driving current I OLED Supply to organic light-emitting diodes OLED.

[0118] A switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, a switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and the switching thin film transistor T2 is also connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a scan signal Sn transmitted via the scan line SL and is configured to perform a switching operation to transmit a data signal Dm transmitted via the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0119] A compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line SL. A compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the driving drain electrode D1 of the driving thin-film transistor T1 and is also connected to the pixel electrode of the organic light-emitting diode OLED via the emission control thin-film transistor T6. A compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to a first storage capacitor plate Cst1 of the storage capacitor Cst, a first initialization drain electrode D4 of the first initialization thin-film transistor T4, and a driving gate electrode G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to a scan signal Sn transmitted via the scan line SL and is configured to diode-connect the driving thin-film transistor T1 by electrically connecting the driving gate electrode G1 of the driving thin-film transistor T1 to the driving drain electrode D1 of the driving thin-film transistor T1.

[0120] A first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the first initialization voltage line VL1, and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and is configured to perform an initialization operation to initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0121] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and to the switching drain electrode D2 of the switching thin film transistor T2.

[0122] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and to the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and to the pixel electrode of the organic light emitting diode OLED.

[0123] The operation control thin film transistor T5 and the emission control thin film transistor T6 are concurrently or simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL to allow the first power voltage ELVDD to be transmitted to the organic light emitting diode OLED, thereby allowing the driving current I OLED Flow through the organic light-emitting diode OLED.

[0124] The second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the next scan line SL+1, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and to the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and to the second initialization voltage line VL2.

[0125] Because the scan line SL is electrically connected to the next scan line SL+1, the same scan signal Sn can be applied to the scan line SL and the next scan line SL+1. Therefore, the second initialization thin film transistor T7 can initialize the pixel electrode of the organic light emitting diode OLED by being turned on in response to the scan signal Sn transmitted through the next scan line SL+1.

[0126] The second storage capacitor plate Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the second power voltage ELVSS. Therefore, the organic light emitting diode OLED can be configured to receive the driving current I from the driving thin film transistor T1. OLED And emits light to thereby display an image.

[0127] Although Figure 6 , the compensation thin film transistor T3 and the first initialization thin film transistor T4 both have dual gate electrodes, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may each have one gate electrode.

[0128] Although Figure 6 , the pixel circuit PC includes seven thin film transistors and one storage capacitor, but the embodiments of the present disclosure are not limited thereto. The number of thin film transistors may be six or less, or eight or more, and the number of storage capacitors may be two or more, or may be omitted. The number of thin film transistors and storage capacitors may be variously and appropriately changed (e.g., set) depending on the design of the pixel circuit PC.

[0129] Figure 7 is a plan view of a portion of the display panel 10 according to the embodiment.

[0130] Reference Figure 7 , the display panel 10 may include a first area RA1 arranged in a display area DA in which pixels P are arranged. In an embodiment, as shown in FIG. Figure 2A As described above, the display panel 10 may include a first hole 10H arranged in the first area RA1 (see Figure 2A ).in this case, Figure 7 The first region RA1 shown in FIG. 1 may have a planar shape of (eg, corresponding to) the first hole 10H.

[0131] The first area RA1 may have a first width W1 along the x-direction, and both sides of the first area RA1 may have an asymmetric shape relative to a first center line CL1 that passes through the first center C1 and divides the first width W1 into two halves. The first center line CL1 may be a virtual line. In some embodiments, the first center line CL1 may extend along the y-direction to pass through the first center C1. In an embodiment, the right side of the first center line CL1 (e.g., the right side of the first area RA1 on the right side of the first center line CL1) may have an approximately (or substantially) quadrilateral shape, and the left side of the first center line CL1 (e.g., the left side of the first area RA1 on the left side of the first center line CL1) may have an approximately (or substantially) semi-elliptical shape.

[0132] The middle area MA may have a shape substantially the same as that of the first area RA1. For example, the middle area MA may have a shape in which its two sides are asymmetric with respect to the first center line CL1. In an embodiment, the middle area MA may have a planar shape different from the planar shape of the first area RA1. For example, the middle area MA may have a shape in which its two sides are symmetrical (e.g., substantially symmetrical) with respect to the first center line CL1. As disclosed herein, when two components or regions are referred to as symmetrical or asymmetric, the two components or regions may, for example, have reflection symmetry or reflection asymmetry, respectively.

[0133] Figure 8 is a plan view of signal lines arranged around the first area RA1 according to an embodiment, Figure 9A yes Figure 8 A plan view of four signal lines adjacent to each other among the signal lines, Figure 9B and Figure 9C Each is Figure 9A A cross-sectional view of one of the signal lines, Figure 10 It is along Figure 8 Cross-sectional views of the signal lines taken along lines Xa-Xa' and Xb-Xb'. Figures 8 to 9C An embodiment is shown in which the signal lines extending in one direction include the data lines DL.

[0134] Reference Figure 8The data lines DL may extend in one direction (e.g., the y-direction). When the data lines DL are referred to as extending in one direction (e.g., the y-direction), the data lines DL extend entirely (e.g., generally, substantially, etc.) in one direction (e.g., the y-direction). For example, the data lines DL may extend in one direction (e.g., the y-direction), and a portion of each data line DL may be arranged around the first area RA1. For example, each data line DL may follow a winding path around the first area RA1.

[0135] exist Figure 8 In a plan view, each data line DL extends along the y-direction to provide signals to pixels arranged above and below the first area RA1 and may detour in the middle area MA. For example, each data line DL may include an extension portion DL-L and a detour portion DL-C, the extension portions DL-L being arranged on two opposing sides of the first area RA1 with the first area RA1 positioned therebetween, and the detour portion DL-C connecting the extension portions DL-L. Most of the extension portions DL-L may be positioned in the display area DA, and some portion (e.g., the remaining portion) of the extension portions DL-L may be positioned in the middle area MA. The detour portion DL-C may be positioned in the middle area MA.

[0136] The first spacing Δd1 (or first interval, e.g., distance interval) between portions of the data lines DL located in the display area DA can be greater than the second spacing Δd2 (or second interval, e.g., distance interval) between portions of the data lines DL in the middle area MA. For example, the first spacing Δd1 between the extending portions DL-L of the data lines DL can be greater than the second spacing Δd2 between the detour portions DL-C of the data lines DL. Because the spacing between the data lines DL in the middle area MA is relatively small, the area of ​​the middle area MA (e.g., the area of ​​the non-active region) can be reduced.

[0137] The data lines DL may include a first group DLa and a second group DLb. The first group DLa is included on one side of the first region RA1 (eg, Figure 8 The second group DLb includes the data lines arranged around the left side of the first area RA1 (eg, Figure 8 The data lines are arranged around the right side of the first area RA1 in FIG.

[0138] The data lines DL of the first group DLa and the data lines DL of the second group DLb may extend from the first dividing point DP1 in different directions, respectively. The data lines DL of the first group DLa may extend from the first dividing point DP1 (e.g., away from the first dividing point DP1) along the left side of the first area RA1, and the data lines DL of the second group DLb may extend from the first dividing point DP1 (e.g., away from the first dividing point DP1) along the right side of the first area RA1.

[0139] The data lines DL of the first group DLa may extend along an edge of the first area RA1 and maintain a first distance ds1 from the edge of the first area RA1. In embodiments, the first distance ds1 may have a constant value, and the detour portions DL-C of the data lines DL of the first group DLa may be separated (e.g., spaced apart) from the first area RA1 by a constant interval (e.g., a constant distance interval). In some embodiments, the portion of the innermost data line from the first group DLa extending along the edge of the first area RA1 may be spaced apart from the edge of the first area RA1 by the first distance ds1, and the portion of each of the other data lines of the first group DLa extending along the edge of the first area RA1 may be spaced apart from the edge of the first area RA1 by a distance greater than the first distance ds1.

[0140] Similarly, the data lines DL of the second group DLb may extend along the edge of the first area RA1 and maintain a second distance ds2 from the edge of the first area RA1. In an embodiment, the second distance ds2 may have a constant value, and the detour portions of the data lines DL of the second group DLb may be separated (e.g., spaced apart) from the edge of the first area RA1 by a constant interval (e.g., a constant distance interval). The second distance ds2 may have the same value as the first distance ds1. In some embodiments, the portion of the innermost data line from the second group DLb extending along the edge of the first area RA1 may be spaced apart from the edge of the first area RA1 by the second distance ds2, and the portion of each of the other data lines of the second group DLb extending along the edge of the first area RA1 may be spaced apart from the edge of the first area RA1 by a distance greater than the second distance ds2.

[0141] In some embodiments, the first dividing point DP1 is not located on the same line as the first center line CL1. Figure 8 As shown in , the first dividing point DP1 can be located on a first virtual line DPL1 that is separated (e.g., spaced apart) from the first center line CL1 by a predetermined interval or a set interval (e.g., a distance interval) along a direction (e.g., an x ​​direction) that crosses or intersects the extension direction (e.g., the y direction) of the data line DL.

[0142] In a plan view, the data lines DL of the first group DLa and the data lines DL of the second group DLb may have shapes that are asymmetric to each other. For example, the detour portion DL-C of each of the data lines DL of the first group DLa and the detour portion DL-C of each of the data lines DL of the second group DLb may have an asymmetric shape. In an embodiment, in a plan view, the detour portion DL-C of each of the data lines DL of the first group DLa may have a shape similar to the shape of a portion of an edge of the first area RA1, for example, a semi-elliptical shape as a whole (for example, a basic semi-elliptical shape). In a plan view, the detour portion DL-C of each of the data lines DL of the second group DLb may have a shape similar to the shape of a portion of an edge of the first area RA1, for example, a quadrilateral shape as a whole (for example, a basic quadrilateral shape).

[0143] The connection point between the extension portion DL-L and the detour portion DL-C of each of the data lines DL of the first group DLa can be arranged along an inclined direction inclined relative to the x-direction and the y-direction. The connection point between the extension portion DL-L and the detour portion DL-C of each of the data lines DL of the first group DLa can be placed on a first virtual inclined line VOL1 inclined relative to the x-direction and the y-direction. Similarly, the connection point between the extension portion DL-L and the detour portion DL-C of each of the data lines DL of the second group DLb can be arranged along an inclined direction inclined relative to the x-direction and the y-direction. The connection point between the extension portion DL-L and the detour portion DL-C of each of the data lines DL of the second group DLb can be placed on a second virtual inclined line VOL2 inclined relative to the x-direction and the y-direction. The connection point between the extension portion DL-L and the detour portion DL-C of each data line DL can correspond to the end of the detour portion DL-C.

[0144] Reference Figure 9A The first data line DL1 and the second data line DL2 may extend from the first dividing point DP1 (e.g., away from the first dividing point DP1) in opposite directions. The detour portion DL1-C of the first data line DL1 may be located at one side of the first area RA1 (e.g., on one side of the first area RA1), for example, at the left side of the first area RA1 (e.g., on the left side of the first area RA1), and may extend along a portion of the first area RA1. The detour portion DL2-C of the second data line DL2 may be located at the other side of the first area RA1 (e.g., on the other side of the first area RA1), for example, at the right side of the first area RA1 (e.g., on the right side of the first area RA1), and may extend along another portion of the first area RA1.

[0145] The first data line DL1 may include an extension portion DL1-L extending through the display area DA and a detour portion DL1-C connecting the extension portion DL1-L and located in the middle area MA. The detour portion DL1-C of the first data line DL1 may have a shape substantially the same as a portion (e.g., a left portion) of the first area RA1. For example, in a plan view, the detour portion DL1-C of the first data line DL1 may have a substantially semi-elliptical shape.

[0146] The detour portion DL1-C of the first data line DL1 may include a first detour portion DL1-C1, a third detour portion DL1-C3, and a second detour portion DL1-C2 located between the first detour portion DL1-C1 and the third detour portion DL1-C3. Each of the first detour portion DL1-C1 and the third detour portion DL1-C3 may be connected to the extension portion DL1-L (e.g., each of the first detour portion DL1-C1 and the third detour portion DL1-C3 may be connected to a corresponding extension portion of the extension portion DL1-L) and extend in a direction (e.g., an x-direction) that is different from (e.g., perpendicular or substantially perpendicular to) the direction of the extension portion DL1-L.

[0147] The first detour portion DL1-C1 and the third detour portion DL1-C3 may be substantially straight lines, and the second detour portion DL1-C2 may include a curved line. For example, the second detour portion DL1-C2 may have a substantially semicircular shape with a radius R1 in a plan view.

[0148] The second data line DL2 may include an extension portion DL2-L extending through the display area DA and a detour portion DL2-C connecting the extension portion DL2-L and located in the middle area MA. The detour portion DL2-C of the second data line DL2 may have a shape substantially the same as a portion (e.g., the right portion) of the first area RA1. For example, in a plan view, the detour portion DL2-C of the second data line DL2 may have a substantially quadrilateral shape, e.g., a quadrilateral with rounded corners.

[0149] The detour portion DL2-C of the second data line DL2 may include a first detour portion DL2-C1, a third detour portion DL2-C3, and a second detour portion DL2-C2 located between the first detour portion DL2-C1 and the third detour portion DL2-C3. Each of the first detour portion DL2-C1 and the third detour portion DL2-C3 may be connected to the extension portion DL2-L (e.g., each of the first detour portion DL2-C1 and the third detour portion DL2-C3 may be connected to a corresponding extension portion of the extension portion DL2-L) and extend in a direction (e.g., an x-direction) that is different from (e.g., perpendicular or substantially perpendicular to) the direction of the extension portion DL2-L.

[0150] The first detour portion DL2-C1, the second detour portion DL2-C2, and the third detour portion DL2-C3 of the second data line DL2 can be substantially straight lines. The connecting portion of the second data line DL2 between the first detour portion DL2-C1 and the second detour portion DL2-C2 can include a curved line, and the connecting portion of the second data line DL2 between the third detour portion DL2-C3 and the second detour portion DL2-C2 can include a curved line. For example, in a plan view, the connecting portion of the second data line DL2 between the first detour portion DL2-C1 and the second detour portion DL2-C2 can have an arc shape having a radius R2, and the connecting portion of the second data line DL2 between the third detour portion DL2-C3 and the second detour portion DL2-C2 can have an arc shape having a radius R3. The radius R2 and the radius R3 can be equal to or different from each other.

[0151] The first dividing point DP1 may be located in a first virtual line DPL1 that is separated (e.g., spaced apart) from the first center line CL1 in the x-direction. Therefore, the center angle α1 of the detour portion DL1-C of the first data line DL1 may be different from the center angle β1 of the detour portion DL2-C of the second data line DL2. The center angle represents the angle formed by a virtual arc connecting the first center C1 and the two opposite ends of the detour portion DL-C of each data line DL that detours the first area RA1. In an embodiment, the center angle α1 of the detour portion DL1-C of the first data line DL1 may be greater than the center angle β1 of the detour portion DL2-C of the second data line DL2.

[0152] The length of the detour portion DL1-C of the first data line DL1 may be the same as or substantially the same as the length of the detour portion DL2-C of the second data line DL2. When the length of the detour portion DL1-C of the first data line DL1 is referred to as the same as or substantially the same as the length of the detour portion DL2-C of the second data line DL2, the length deviation between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be within a few μm. For example, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be 80 μm or less, or 70 μm or less. In an embodiment, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 may be in a range of about 0.1 μm to about 70 μm.

[0153] As a comparative example, when the first dividing point DP1 is located on the first center line CL1, the length of the detour portion DL1-C of the first data line DL1 can differ from the length of the detour portion DL2-C of the second data line DL2. For example, the difference between the length of the detour portion DL1-C of the first data line DL1 and the length of the detour portion DL2-C of the second data line DL2 can be approximately one thousand μm to tens of thousands of μm or more. Such length deviation leads to resistance deviation, which can cause brightness differences and / or color deviations, thereby degrading the image quality of the display panel.

[0154] On the contrary, according to the embodiment, as shown in FIG. Figure 8 and Figure 9A As described, the first dividing point DP1 between the first group DLa and the second group DLb can be located on a first virtual line DPL1 that is separated (e.g., spaced apart) from the first center line CL1. Therefore, the length of the detour portion DL1-C of the data line of the first group DLa (e.g., the first data line DL1) and the length of the detour portion DL2-C of the data line of the second group DLb (e.g., the second data line DL2) can be the same or substantially the same, thereby preventing, minimizing, or reducing brightness differences and / or color deviations. For example, the distance between the first virtual line DPL1 and the first center line CL1 can be predetermined or set so that the length of the detour portion DL1-C of the data line of the first group DLa is the same or substantially the same as the length of the detour portion DL2-C of the data line of the second group DLb.

[0155] The third data line DL3 and the fourth data line DL4 can be separated from each other (e.g., spaced apart) so that the first data line DL1 and the second data line DL2 are located between the third data line DL3 and the fourth data line DL4. The third data line DL3 can be located on the opposite side of the second data line DL2 so that the first data line DL1 is located between the third data line DL3 and the second data line DL2, and the fourth data line DL4 can be located on the opposite side of the first data line DL1 so that the second data line DL2 is located between the fourth data line DL4 and the first data line DL1. For example, the third data line DL3, the first data line DL1, the second data line DL2, and the fourth data line DL4 can be arranged in this order from left to right along one direction (e.g., the x-direction).

[0156] The third data line DL3 and the fourth data line DL4 may extend from the first dividing point DP1 in opposite directions, respectively. The detour portion of the third data line DL3 may be located on one side of the first area RA1, for example, on the left side of the first area RA1 and may extend along a portion of the first area RA1, and the detour portion of the fourth data line DL4 may be located on the other side of the first area RA1, for example, on the right side of the first area RA1 and may extend along a portion of the first area RA1.

[0157] The third data line DL3 may have substantially the same characteristics as those of the first data line DL1 (e.g., shape, length, etc.), and the fourth data line DL4 may have substantially the same characteristics as those of the second data line DL2 (e.g., shape, length, etc.). For example, the third data line DL3 and the fourth data line DL4 may have asymmetrical shapes and / or may have different center angles of their winding portions. The third data line DL3 and the fourth data line DL4 may include all the characteristics of the first data line DL1 and the second data line DL2, respectively.

[0158] The connection point between the extended portion and the detour portion of the third data line DL3 and the connection point between the extended portion and the detour portion of the first data line DL1 may be placed (eg, located) as shown in FIG. Figure 8 Similarly, the connection point between the extension portion and the detour portion of the fourth data line DL4 and the connection point between the extension portion and the detour portion of the second data line DL2 can be placed (eg, located) as shown in FIG. Figure 8 The second virtual oblique line VOL2.

[0159] Some of the data lines DL of the first and second groups DLa and DLb may include one integral conductive layer, and others of the data lines DL may include conductive lines on different layers.

[0160] like Figure 9BAs shown in , the first data line DL1 may include a first conductive layer 2155 on the fourth insulating layer 2150. The extending portion DL1-L and the detour portion DL1-C of the first data line DL1 may be formed as a whole. Figure 9B 2 , a first insulating layer 2111 , a second insulating layer 2141 , and a third insulating layer 2143 are disposed between the substrate 100 and the fourth insulating layer 2150 , and a fifth insulating layer 2160 and a sixth insulating layer 2180 are formed on the first data line DL1 .

[0161] On the contrary, Figure 9C As shown in FIG, the second data line DL2 may include a connection structure in which a first conductive layer 2155 on the fourth insulating layer 2150 is connected to a second conductive layer 2165 on the fifth insulating layer 2160. Most of the extended portion of the second data line DL2 may include the first conductive layer 2155, and the detour portion DL2-C may include the second conductive layer 2165. The first conductive layer 2155 may be connected to the second conductive layer 2165 through a contact hole CNT of the fifth insulating layer 2160 (e.g., in the fifth insulating layer 2160) between the first conductive layer 2155 and the second conductive layer 2165.

[0162] The first conductive layer 2155 and the second conductive layer 2165 may include (for example, may be) a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may include (for example, may be) a single-layer structure or a multi-layer structure including the above materials. In an embodiment, the first conductive layer 2155 and / or the second conductive layer 2165 may include (for example, may be) three sublayers of Ti / Al / Ti. The first conductive layer 2155 and the second conductive layer 2165 may include (for example, may be) the same material. In some embodiments, the first conductive layer 2155 and the second conductive layer 2165 may include (for example, may be) different materials.

[0163] Reference Figure 8 as well as Figures 9A to 9C , one of the adjacent data lines DL may have Figure 9B In the structure shown in FIG. 1 , another adjacent data line DL may have Figure 9C In some embodiments, one adjacent data line DL and another adjacent data line DL may be adjacent data lines DL. For example, one of the adjacent data lines DL may have a single body of the first conductive layer 2155 (eg, Figure 9B ), another one of the adjacent data lines DL may have a connection structure of a first conductive layer 2155 and a second conductive layer 2165 arranged on different layers (eg, as shown in FIG. 2 ). Figure 9C ). Therefore, if Figure 8 and Figure 9AAs shown in , the contact holes CNT may be alternately arranged among the data lines DL along the x direction. Figure 10 As shown in , the detour portions of the data lines DL may be arranged alternately up and down with an insulating layer therebetween. As disclosed herein, when a line, component, or region is referred to as being "adjacent" to another line, component, or region, the line, component, or region may be, for example, a line, component, or region that is adjacent to, close to, or closest to the other line, component, or region.

[0164] Reference Figure 8 and Figure 10 , the extension portion DL-L of the data line DL may be arranged on the fourth insulating layer 2150 in the display area DA, but the detour portions DL-C of the data line DL may be alternately arranged up and down in the middle area MA, with the fifth insulating layer 2160 located between the detour portions DL-C of the data line DL. Figure 10 As shown in FIG, a detour portion DL-C of a data line may be on the fourth insulating layer 2150, and another detour portion DL-C of another data line adjacent to the one data line may be on the fifth insulating layer 2160, and the fifth insulating layer 2160 may be between the one detour portion DL-C and the other detour portion DL-C. Because the detour portions DL-C adjacent to each other among the detour portions DL-C of the data line DL are arranged on different layers in the middle area MA, the above reference Figure 8 The described second distance Δd2 may be smaller than the first distance Δd1 .

[0165] Figure 11 is a plan view of a portion of the display panel 10 according to the embodiment.

[0166] Reference Figure 11 , the display panel 10 may include a first area RA1 and a second area RA2 arranged in a display area DA in which pixels P are arranged. Figure 2A As described above, the display panel 10 may include first holes 10H arranged in the first area RA1 and the second area RA2 (see FIG. Figure 2A ).in this case, Figure 11 The first and second regions RA1 and RA2 shown in FIG. 5 may have planar shapes of the first holes 10H corresponding to the first and second regions RA1 and RA2 , respectively.

[0167] The first region RA1 and the second region RA2 may be separated (eg, spaced apart) from each other along one direction (eg, the x direction). Figure 11, the first and second regions RA1 and RA2 are shown to be arranged along the x direction, but the first and second regions RA1 and RA2 may be arranged along the y direction or may be arranged in a direction inclined with respect to the x and y directions. Various appropriate modifications may be made.

[0168] The first and second areas RA1 and RA2 may be surrounded by the middle area MA. Portions of the middle area MA may be disposed between the first area RA1 and the display area DA, between the second area RA2 and the display area DA, and / or between the first and second areas RA1 and RA2, respectively.

[0169] As mentioned above Figure 7 As described above, the first area RA1 may have a first width W1 in the x-direction and have a shape in which two opposite sides (eg, left and right sides) thereof are asymmetrical with respect to a first center line CL1 passing through a first center C1 of the first width W1 .

[0170] The second area RA2 may have a second width W2 along the x-direction and have a shape in which its two opposite sides (e.g., left and right sides) are symmetrical with respect to a second center line CL2 passing through a second center C2 of the second width W2. For example, the second area RA2 may have a circular shape in which its two opposite sides are symmetrical with respect to the second center line CL2 passing through the second center C2. In some embodiments, the second area RA2 may have a shape such as a quadrilateral or an elliptical shape in which its two opposite sides are symmetrical with respect to the second center line CL2 passing through the second center C2. In another embodiment, like the first area RA1, the second area RA2 may have a shape in which its two opposite sides are asymmetrical with respect to the second center line CL2 passing through the second center C2.

[0171] Figure 12A is a plan view of signal lines arranged around the first area RA1 according to an embodiment, Figure 12B yes Figure 12A Extracted plan views of some of the signal lines. Figure 12A and Figure 12B A case is shown where the signal lines include data lines DL.

[0172] Reference Figure 12A The data lines DL may extend along the y direction, some of the data lines DL may surround the first area RA1 in the middle area MA, and some of the data lines DL may surround the second area RA2 in the middle area MA.

[0173] Because the characteristics (eg, shape, length, etc.) of the data lines DL arranged around the first area RA1 (eg, the data lines DL of the first group DLa and the data lines DL of the second group DLb) are similar to those described above with reference to FIG. Figures 8 to 10The characteristics of the described data lines DL are the same, so a repeated description thereof may not be provided.

[0174] The data lines DL may include a third group DLc and a fourth group DLd. The third group DLc is included on one side of the second area RA2 (eg, Figure 12A The fourth group DLd includes the data lines DL arranged around the left side of the second area RA2 (eg, Figure 12A The data lines DL are arranged around the right side of the second area RA2 in FIG.

[0175] In a plan view, the data lines DL of the third group DLc and the data lines DL of the fourth group DLd may have shapes symmetrical to each other. For example, the detour portion DL-C of each of the data lines DL of the third group DLc and the detour portion DL-C of each of the data lines DL of the fourth group DLd may have shapes symmetrical to each other.

[0176] The data lines DL of the third group DLc and the data lines DL of the fourth group DLd may extend from the second dividing point DP2 (e.g., away from the second dividing point DP2) in different directions, respectively. The data lines DL of the third group DLc may extend from the second dividing point DP2 (e.g., away from the second dividing point DP2) around the left edge of the second area RA2, and the data lines DL of the fourth group DLd may extend from the second dividing point DP2 (e.g., away from the second dividing point DP2) around the right edge of the second area RA2.

[0177] The second dividing point DP2 may be located on the same line as the second center line CL2. For example, the second dividing point DP2 may be located on the second virtual line DPL2, which may be the second center line CL2.

[0178] Reference Figure 12B The fifth data line DL5 and the sixth data line DL6 may extend from the second dividing point DP2 (e.g., away from the second dividing point DP2) in opposite directions, respectively. The detour portion DL5-C of the fifth data line DL5 may be located on one side of the second area RA2 (e.g., the left side of the second area RA2) and may extend around a portion of the second area RA2. The detour portion DL6-C of the sixth data line DL6 may be located on the other side of the second area RA2 (e.g., the right side of the second area RA2) and may extend around a portion of the second area RA2.

[0179] The fifth data line DL5 may include an extension portion DL5-L extending through the display area DA and a detour portion DL5-C connected to the extension portion DL5-L and located in the middle area MA. The detour portion DL5-C of the fifth data line DL5 may have a shape substantially the same as that of a portion of the second area RA2. For example, in a plan view, the detour portion DL5-C of the fifth data line DL5 may have a substantially semicircular shape.

[0180] The sixth data line DL6 may include an extension portion DL6-L extending through the display area DA and a detour portion DL6-C connecting the extension portion DL6-L and located in the middle area MA. The detour portion DL6-C of the sixth data line DL6 may have a shape substantially the same as that of a portion of the second area RA2. For example, in a plan view, the detour portion DL6-C of the sixth data line DL6 may have a substantially semicircular shape.

[0181] The detour portion DL5-C of the fifth data line DL5 and the detour portion DL6-C of the sixth data line DL6 may have substantially the same length. The center angle α2 of the detour portion DL5-C of the fifth data line DL5 may be equal to the center angle β2 of the detour portion DL6-C of the sixth data line DL6. The center angle (e.g., center angle α2 or β2) represents the angle formed by a virtual arc connecting the second center C2 and two opposite ends (e.g., two opposite ends of the detour portion DL5-C or DL6-C) of each data line DL (e.g., the fifth data line DL5 or the sixth data line DL6) that detours around the second area RA2.

[0182] Although according to the reference Figures 7 to 12B In the embodiment described above, the signal line along the y direction (e.g., extending along the y direction or passing along the y direction) includes the data line DL, and the data line DL has an asymmetric shape with respect to the first virtual line DPL1, but the embodiments of the present disclosure are not limited thereto. In another embodiment, the above structure can be applied to the signal line along the x direction (e.g., extending along the x direction or passing along the x direction). For example, referring to Figure 6 The described scan line SL, the previous scan line SL-1, the next scan line SL+1, and / or the emission control line EL may extend along the x-direction.

[0183] Figure 13 is a plan view of a portion of the display panel 10 according to the embodiment. Figure 13 Schematic diagram showing signal lines arranged around the first and second regions RA1 and RA2 including scan lines SL.

[0184] Reference Figure 13, the scan line SL may extend along one direction (e.g., the x-direction). When the scan line SL extends along one direction (e.g., the x-direction), the scan line SL may extend along one direction (e.g., the x-direction) as a whole (e.g., may extend entirely or substantially along the x-direction). For example, the scan line SL may extend along one direction (e.g., the x-direction) and partially surround the first area RA1.

[0185] Each scan line SL may include an extension portion SL-L passing through the display area DA and a detour portion SL-C located in the middle area MA and connected to the extension portion SL-L. The detour portion SL-C may extend around a portion of the first area RA1 in the middle area MA.

[0186] The scan lines SL may include a first group SLa including scan lines and a second group SLb including scan lines, the first group SLa and the second group SLb being arranged on two opposite sides (e.g., top and bottom sides) of a first virtual line DPL1', respectively. The scan lines SL of the first group SLa and the scan lines SL of the second group SLb may be arranged asymmetrically with respect to the first virtual line DPL1'. For example, the planar shape of the detour portion SL-C of each of the scan lines SL of the first group SLa may be different from the planar shape of the detour portion SL-C of each of the scan lines SL of the second group SLb with respect to the first virtual line DPL1'.

[0187] The first scan line SL1 as one of the scan lines SL of the first group SLa and the second scan line SL2 as one of the scan lines SL of the second group SLb may extend in opposite directions from the first dividing point DP1' (e.g., away from the first dividing point DP1'). The detour portion of the first scan line SL1 may be on one side of the first area RA1 (e.g., Figure 13 The detour portion of the second scan line SL2 may extend around the top side of the first region RA1 (eg, Figure 13 In an embodiment, the detour portion of the first scan line SL1 may have a semicircular shape, and the detour portion of the second scan line SL2 may have a quadrilateral shape, for example, a quadrilateral shape with rounded corners.

[0188] In a plan view, the first area RA1 may have a first width W1' in the y direction and an asymmetric shape with respect to a first center line CL1' passing through a first center C1 of the first width W1' and extending in the x direction. One side of the first area RA1 may have an approximately (or substantially) semi-elliptical shape with respect to the first center line CL1', and the other side of the first area RA1 may have an approximately (or substantially) quadrilateral shape (e.g., a quadrilateral shape with rounded corners) with respect to the first center line CL1'. In an embodiment, as shown in FIG. Figure 2A As described above, the display panel 10 may include a first hole 10H arranged in the first area RA1 (see Figure 2A ).in this case, Figure 13 The first region RA1 shown in FIG. 1 may have the same planar shape as the first hole 10H.

[0189] The scan lines SL of the first group SLa may extend around the edge of the first area RA1 and maintain a first distance ds1' from the edge of the first area RA1. The first distance ds1' may have a constant value. For example, the detour portion of the first scan line SL1 may be separated (e.g., spaced apart) from the edge of the first area RA1 by a constant interval. In some embodiments, the detour portion of the innermost scan line of the scan lines of the first group SLa may be spaced apart from the edge of the first area RA1 by the first distance ds1' as the detour portion extends around the first area RA1, and the detour portions of the other scan lines of the first group SLa may be spaced apart from the edge of the first area RA1 by at least the first distance ds1' as the detour portion extends around the first area RA1.

[0190] Similarly, the scan lines SL of the second group SLb may extend around the edge of the first area RA1 and maintain a second distance ds2' from the edge of the first area RA1. The second distance ds2' may have a constant value. For example, the detour portion of the second scan line SL2 may be separated (e.g., spaced apart) from the edge of the first area RA1 by a constant interval. The second distance ds2' may have the same value as the first distance ds1'. For example, in some embodiments, the detour portion of the innermost scan line of the scan lines of the second group SLb may be spaced apart from the edge of the first area RA1 by the second distance ds2' as the detour portion extends around the first area RA1, and the detour portions of the other scan lines of the second group SLb may be spaced apart from the edge of the first area RA1 by at least the second distance ds2' as the detour portion extends around the first area RA1.

[0191] The first dividing point DP1' may be located on a first virtual line DPL1', which may be separated (e.g., spaced apart) from the first center line CL1' along the y-direction. The detour portion of the first scan line SL1 and the detour portion of the second scan line SL2 may have substantially the same length. Thus, as described above, the resistance difference between the scan lines may be reduced or minimized, and the corresponding degradation in display quality may be reduced or minimized.

[0192] The display panel 10 may include a second area RA2 adjacent to the first area RA1. Figure 13 As shown in FIG, the second area RA2 may have a symmetrical shape with respect to a second center line CL2 ′ passing through a second center C2 of the second area RA2 and extending in the x-direction.

[0193] The scan lines SL may include a third group SLc including scan lines and a fourth group SLd including scan lines. The third group SLc is located on one side of the second area RA2 (eg, Figure 13 The fourth group SLd is arranged around the top side of the second area RA2 in FIG. Figure 13 The bottom side of the second area RA2 in the embodiment of the present invention is arranged around the bottom side of the second area RA2 in

[0194] In a plan view, the scan lines SL of the third group SLc and the scan lines SL of the fourth group SLd may have symmetrical shapes. For example, the detour portion SL-C of each of the scan lines SL of the third group SLc may have a shape symmetrical to the shape of the detour portion SL-C of each (or a corresponding one) of the scan lines SL of the fourth group SLd.

[0195] The scan lines SL of the third group SLc and the scan lines SL of the fourth group SLd may extend from the second dividing point DP2' (e.g., away from the second dividing point DP2') in different directions, respectively. The scan lines SL of the third group SLc may extend from the second dividing point DP2' (e.g., away from the second dividing point DP2') around the top edge of the second area RA2, and the scan lines SL of the fourth group SLd may extend from the second dividing point DP2' (e.g., away from the second dividing point DP2') around the bottom edge of the second area RA2.

[0196] The second dividing point DP2' may be located on the same line as the second center line CL2'. For example, the second dividing point DP2' may be located on the second virtual line DPL2', which may be the second center line CL2'.

[0197] Figure 14A is a plan view of a portion of the display panel 10 according to the embodiment, Figure 14B The display panel 10 is along Figure 14AA sectional view taken along line XIV-XIV'. Figure 14A The case where the signal lines running around the first area RA1 are data lines DL is shown.

[0198] Reference Figure 14A The data lines DL may include a first group DLa and a second group DLb, the first group DLa including the data lines DL arranged on the left side of the first virtual line DPL1, and the second group DLb including the data lines DL arranged on the right side of the first virtual line DPL1. The data lines DL of the first group DLa and the data lines DL of the second group DLb may be arranged asymmetrically with respect to the first virtual line DPL1. For example, in a plan view, the detour portions DL-C of the data lines DL of the first group DLa and the detour portions DL-C of the data lines DL of the second group DLb may have an asymmetrical shape with respect to the first virtual line DPL1.

[0199] As above (for example, see Figure 7 As described above, the first area RA1 may have an asymmetric shape with respect to the first center line CL1. The detour portions DL-C of the data lines DL of the first group DLa may maintain a constant interval (e.g., a first distance ds1) from the edge of the first area RA1. Similarly, the detour portions DL-C of the data lines DL of the second group DLb may maintain a constant interval (e.g., a second distance ds2) from the edge of the first area RA1.

[0200] The first center line CL1 may be the same as the first virtual line DPL1. In this case, the detour portion DL-C of the data line DL of the first group DLa and the detour portion DL-C of the data line DL of the second group DLb may have different lengths. In this case, a reduction in brightness and / or color deviation may result, but the width or thickness of at least a portion of each data line DL of the first group DLa may be different from the width or thickness of at least a portion of each data line DL of the second group DLb, respectively. For example, the width or thickness of one of the detour portion DL-C of the data line DL of the first group DLa and the detour portion DL-C of the data line DL of the second group DLb may be greater than the width or thickness of the other of the detour portion DL-C of the data line DL of the first group DLa and the detour portion DL-C of the data line DL of the second group DLb. In an embodiment, as Figure 14A and Figure 14B As shown in FIG, a width of at least a portion of each data line DL of the first group DLa may be smaller than a width of at least a portion of each data line DL of the second group DLb.

[0201] Reference Figure 14B, the width dw1 of at least a portion of the first data line DL1 of the first group DLa may be smaller than the width dw2 of at least a portion of the second data line DL2 of the second group DLb. In an embodiment, the width dw2 of the portion of the second data line DL2 of the data lines DL of the second group DLb located in the middle area MA may be greater than the width dw1 of the portion of the first data line DL1 of the data lines DL of the first group DLa located in the middle area MA. In an embodiment, the length of the detour portion of the second data line DL2 may be greater than the length of the detour portion of the first data line DL1, and the width dw2 of the detour portion of the second data line DL2 may be greater than the width dw1 of the detour portion of the first data line DL1.

[0202] With this structure, the resistance deviation between the first data line DL1 and the second data line DL2 may be reduced, and thus a brightness reduction and / or a color deviation may be prevented, minimized, or reduced.

[0203] Figure 15 is a plan view of a portion of the display panel 10 according to the embodiment. Figure 15 The case where the signal lines running around the first area RA1 are data lines DL is shown.

[0204] Reference Figure 15 , the data lines DL may be arranged around the first area RA1. The data lines DL may be arranged symmetrically with respect to the first virtual line DPL1 on which the first dividing point DP1 is located. The data lines DL may include a first group DLa and a second group DLb, the first group DLa including the data lines DL arranged on one side (e.g., the left side) of the first virtual line DPL1, and the second group DLb including the data lines DL arranged on the other side (e.g., the right side) of the first virtual line DPL1. The data lines DL of the first group DLa and the data lines DL of the second group DLb may be arranged symmetrically with respect to the first virtual line DPL1. For example, in a plan view, the detour portion DL-C of the data lines DL of the first group DLa and the detour portion DL-C of the data lines DL of the second group DLb may have a symmetrical shape with respect to the first virtual line DPL1.

[0205] As above (for example, see Figure 7), the first area RA1 may have an asymmetric shape relative to the first center line CL1. In a plan view, the shape of the first area RA1 may be different from the shape of the detour portions DL-C of the data lines DL of the first group DLa and / or the shape of the detour portions DL-C of the data lines DL of the second group DLb. For example, in some embodiments, the shapes of the detour portions DL-C of the data lines DL of the first group DLa may have a shape substantially the same as the shape of the portion of the first area RA1 around which they extend, and the shapes of the detour portions DL-C of the data lines DL of the second group DLb may have a shape substantially the same as the shape of the portion of the first area RA1 around which they extend. Therefore, the detour portions DL-C of the data lines DL of the first group DLa may have a first distance ds1" from the edge of the first area RA1 (e.g., may be spaced apart from the first area RA1 by the first distance ds1"), and the first distance ds1" may have a variable value depending on the measurement point. For example, the first distance ds1" may vary as the detour portions DL-C of the data lines DL of the first group DLa extend around a portion of the first area RA1. In contrast, the detour portion DL-C of the data lines DL of the second group DLb may have a second distance ds2″ from the edge of the first area RA1 (eg, may be spaced apart from the first area RA1 by the second distance ds2″), and the second distance ds2″ may have a constant value.

[0206] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display panel, comprising: a substrate having an upper surface and a lower surface opposite to the upper surface, wherein the substrate has a first hole and a second hole both extending from the upper surface through the lower surface; a plurality of display elements, the plurality of display elements being two-dimensionally arranged around the first hole and the second hole on the upper surface of the substrate; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, wherein the first hole has a first width in a second direction intersecting the first direction, the first width being between a first portion of an outer edge of the first hole and a second portion of the outer edge of the first hole, and the first hole includes a first side and a second side that are asymmetric with respect to a first centerline passing through a center of the first width along the first direction, The plurality of signal lines include a first signal line arranged around the first side of the first hole and a second signal line arranged around the second side of the first hole, A first distance between the first portion of the outer edge of the first hole and the detour portion of the first signal line is the same as a second distance between the second portion of the outer edge of the first hole and the detour portion of the second signal line.

2. The display panel according to claim 1, wherein: A portion of the first side of the first hole has a first radius of curvature, and a portion of the second side of the first hole has a second radius of curvature different from the first radius of curvature.

3. The display panel according to claim 2, wherein: The first radius of curvature is greater than the second radius of curvature.

4. The display panel according to claim 1, wherein: The second hole has a second width in the second direction, and the second hole has two sides symmetrical with respect to a second center line passing through a center of the second width along the first direction.

5. The display panel according to claim 4, wherein: The first width is greater than the second width. The display panel according to claim 1 , wherein: The shape of the first hole and the shape of the second hole are different from each other.

7. The display panel according to claim 1, wherein: The first width is a maximum width of the first hole along the second direction, the first signal line is closest to the first side of the first hole among the plurality of signal lines, and the second signal line is closest to the second side of the first hole among the plurality of signal lines.

8. The display panel according to claim 1, wherein: The plurality of signal lines further include: a third signal line running around the first side of the second hole; and A fourth signal line is arranged around a second side of the second hole opposite to the first side of the second hole.

9. The display panel according to claim 8, wherein: A third distance between the first side of the second hole and the detour portion of the third signal line is the same as a fourth distance between the second side of the second hole and the detour portion of the fourth signal line.

10. A display panel, comprising: a substrate having an upper surface and a lower surface opposite to the upper surface, wherein the substrate has a first hole and a second hole both extending from the upper surface through the lower surface; a plurality of display elements, the plurality of display elements being two-dimensionally arranged around the first hole and the second hole on the upper surface of the substrate; and a plurality of signal lines electrically connected to the plurality of display elements and extending in a first direction, at least one signal line of the plurality of signal lines being arranged around the first hole, wherein the first hole has a first width in a second direction intersecting the first direction, the second hole has a second width in the second direction, and the first width is greater than the second width, wherein the first hole includes a first side and a second side opposite to the first side relative to a first centerline passing through the center of the first width along the first direction, a first portion of the first side of the first hole has a first radius of curvature, and a second portion of the second side of the first hole has a second radius of curvature different from the first radius of curvature, The plurality of signal lines include a first signal line arranged around the first side of the first hole and a second signal line arranged around the second side of the first hole, The portion of the first signal line extending around the first portion of the first side of the first hole and the portion of the second signal line extending around the second portion of the second side of the first hole are asymmetric with respect to the first center line.

11. The display panel according to claim 10, wherein: The shape of the first hole and the shape of the second hole are different from each other.

12. The display panel according to claim 10, wherein: The first side and the second side of the first hole are asymmetric with respect to the first centerline.

13. The display panel according to claim 10, wherein: The first radius of curvature is greater than the second radius of curvature.

14. The display panel according to claim 10, wherein: The second hole has two sides symmetrical with respect to a second center line passing through the center of the second width along the first direction.

15. The display panel according to claim 10, wherein: A first distance between the first side of the first hole and the detour portion of the first signal line is the same as a second distance between the second side of the first hole and the detour portion of the second signal line.

16. The display panel according to claim 1 or 10, wherein: The plurality of signal lines include a plurality of data lines.

17. An electronic device, comprising: The display panel according to any one of claims 1 to 16; as well as at least one component corresponding to at least one of the first hole and the second hole of the display panel, Wherein, the at least one component includes a camera or a sensor.

18. The electronic device according to claim 17, wherein: The at least one component includes a first component corresponding to the first hole of the display panel and a second component corresponding to the second hole of the display panel, and The first component includes electronic components that are different from electronic components of the second component.

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