Display device

Abstract

A display panel includes: first and second substrates including a display area having a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor and a light emitting element disposed in each of the plurality of sub-pixels; a barrier disposed between the first substrate and the second substrate at an end portion of the display area and the non-display area; and a protective layer formed on a side surface of the non-display area and a side surface of an end portion of the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0027727 filed in Korea on February 27, 2024, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] The present invention relates to a display device that can have various sizes and shapes. Background Art

[0004] Recently, with the development of multimedia, the importance of display devices is increasing. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic electroluminescent display devices are being commercialized. Among these display devices, organic electroluminescent display devices are currently widely used because they have high response speed, high brightness, and good viewing angle.

[0005] Meanwhile, as the application range of display devices increases, demand for large-area display devices and display devices of various shapes that can be applied to various electronic devices is increasing, but there are limitations in actually manufacturing such display devices. Summary of the Invention

[0006] An advantage of the present invention is to provide a display panel that can be manufactured in various sizes through a simplified manufacturing process.

[0007] Another advantage of the present invention is to provide a tiled display device including display panels of various sizes.

[0008] Additional features and advantages of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be understood through practice of the present invention. These and other advantages of the present invention will be realized and obtained through the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0009] To achieve these and other advantages and in accordance with the purposes of the present invention, as embodied and broadly described herein, a display panel includes: a first substrate and a second substrate, including a display area having a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor and a light-emitting element arranged in each of the plurality of sub-pixels; a barrier arranged between the first substrate and the second substrate at an end portion of the display area and the non-display area; and a protective layer formed on side surfaces of the non-display area and side surfaces of the end portion of the display area.

[0010] In another aspect, a display device includes: a support substrate; and a plurality of display panels mounted on the support substrate, one of the plurality of display panels being the above-described display panel.

[0011] It is to be understood that both the foregoing summary and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0013] Figure 1 is a diagram showing a display device according to the present invention;

[0014] Figure 2 is a schematic block diagram of a sub-pixel of a display device according to the present invention;

[0015] Figure 3 is a circuit diagram showing a sub-pixel of a display device according to the present invention;

[0016] Figure 4 is a diagram schematically showing a display panel according to the present invention;

[0017] Figure 5A and Figure 5B is a diagram specifically showing the structure of a display panel according to the present invention;

[0018] Figures 6A to 6G are diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The advantages and features of the present invention and methods for achieving them will be apparent from the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms, and only these embodiments allow the present invention to be completed. The present invention is provided to fully inform those skilled in the art of the scope of the invention, and the present invention may be limited by the scope of the claims.

[0020] The shapes, sizes, proportions, angles, quantities, etc. disclosed in the accompanying drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the contents shown. Throughout the specification, the same reference numerals represent the same components. In addition, when describing the present invention, if it is determined that the detailed description of the relevant known technology does not necessarily make the subject matter of the present invention difficult to understand, its detailed description may be omitted. When "including", "comprising", "having", "consisting of..." and the like are used in the present invention, other parts may be added unless "only" is used. When a component is represented in the singular, the plural case is included unless a specific statement is described.

[0021] When interpreting a component, it is interpreted as including a margin range even if there is no separate explicit description.

[0022] When describing a positional relationship, for example, when the positional relationship of two parts is described as "on", "above", "below", "beside", "below", etc., one or more other parts may be positioned between the two parts, unless "just" or "directly" is used.

[0023] In the case of describing a temporal relationship, for example, when describing a temporal priority order as "after," "subsequently," "before," and the like, discontinuous cases may be included unless "directly" or "immediately" is used.

[0024] The various features of the various embodiments of the present invention may be partially or completely connected or combined with each other, may be technically interlocked and driven in various ways, and the various embodiments may be implemented independently of each other, or may be implemented together in a related relationship.

[0025] When describing components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are used solely to distinguish a component from other components and do not limit the nature, order, sequence, or number of the components. Furthermore, when a component is described as being "connected," "coupled," or "in contact with" another component, the component may be directly connected or in contact with the other component, but it should be understood that other components may be "interposed" between the components, or that the component may be "connected," "coupled," or "in contact with" the other component.

[0026] In the present invention, the term "display device" may include a display device in a narrow sense, such as a display module, which includes a display panel and a driving portion for driving the display panel. In addition, the term "display device" may include a complete product or final product, which is a notebook computer, a television, a computer monitor, an automotive device or device display (including other types of vehicles), or a complete set of electronic equipment or equipment or equipment including a display module, such as a mobile electronic device such as a smart phone or electronic tablet.

[0027] Therefore, the display device of the present invention may include a display device in a narrow sense such as a display module, and / or an application product or complete set of equipment as an end-user device including the display module.

[0028] Hereinafter, embodiments of the present invention are described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a diagram showing a display device according to the present invention.

[0030] like Figure 1 As shown, the display device 100 of the present invention is a tiled display device in which a plurality of display panels 110 are tiled. The tiled display device 100 is configured such that the plurality of display panels 110 are arranged on a large-area support substrate 120 and electrically connected via signal lines SL to operate as a single display device.

[0031] The display panels 110 disposed on the support substrate 120 can have various sizes. For example, the plurality of first display panels 110a can have a first area, and the second display panel 110b and the third display panel 110c can have a second area smaller than the first area. In this case, the first to third display panels 110a to 110c can be display panels having the same structure formed by the same process. For example, the first to third display panels 110a to 110c can be configured by forming thin film transistors, various lines, and light-emitting elements on substrates of the same area using the same process.

[0032] The second display panel 110b may be formed by forming a display panel having the same area as the first display panel 110a and then cutting and removing some areas of the display panel, for example, in a horizontal direction. Alternatively, the third display panel 110c may be formed by forming a display panel having the same area as the first display panel 110a and then cutting and removing some areas of the display panel, for example, in a vertical direction.

[0033] One end of a plurality of flexible circuit boards (FPCs) is attached to the support substrate 120, and the other end of the printed circuit board (PCB) is attached to the flexible circuit boards. The flexible circuit boards (FPCs) are flexible base films that can supply power voltage and data voltage to the first to third display panels 110a to 110c. The number of flexible circuit boards (FPCs) can vary depending on the design, but is not limited thereto.

[0034] The printed circuit board PCB may be placed on the other end of the corresponding flexible circuit board FPC and electrically connected to the flexible circuit board FPC.

[0035] An IC that generates various signals and provides them to the first to third display panels 110a to 110c may be mounted on a printed circuit board PCB. For example, an image processing part, a timing control part, a power supply part, etc. may be placed on the printed circuit board PCB.

[0036] The image processing part outputs image data provided from the outside and driving signals for driving various components. For example, the driving signals output from the image processing part may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0037] The timing control section receives image data and a driving signal from the image processing section. Based on the driving signal from the image processing section, the timing control section generates and outputs a gate control signal (or gate timing control signal) for controlling the operation timing of the gate driving section and a data control signal (or data timing control signal) for controlling the operation timing of the data driving section.

[0038] The power supply part outputs a high potential voltage and a low potential voltage and supplies them to the first to third display panels 110 a to 110 c .

[0039] Driving signals such as a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, control signals such as a gate control signal and a data control signal, and a power supply voltage are supplied from the printed circuit board PCB to the first to third display panels 110 a to 110 c through the flexible circuit board FPC and the signal lines SL.

[0040] Each of the first to third display panels 110a to 110c includes a plurality of sub-pixels and displays an image. The sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In this case, the white, red, green, and blue sub-pixels SP may all be formed with the same area, but may also be formed with different areas.

[0041] Hereinafter, the first to third display panels 110 a to 110 c are mainly described as organic light emitting display panels, but are not limited thereto and may also be liquid crystal display panels, micro LED display panels, or mini LED display panels.

[0042] Figure 2 is a schematic block diagram of sub-pixels of first to third display panels of a display device according to the present invention.

[0043] like Figure 2As shown, a subpixel SP can be connected to a gate line GL, a data line DL, a first power line PL providing a high potential voltage EVDD, and a second power line providing a low potential voltage EVSS. The subpixel SP can include multiple thin film transistors and storage capacitors depending on the configuration of the pixel circuit. For example, the subpixel SP can be configured using a 2T1C structure with two transistors and one capacitor formed in the subpixel SP, but the present invention is not limited thereto. The subpixel SP can also be configured using 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, 8T2C, and the like.

[0044] Figure 3 is a circuit diagram showing sub-pixels of first to third display panels of a display device according to the present invention.

[0045] like Figure 3 As shown, the first to third display panels 110 a to 110 c of the display device according to the present invention each include a gate line GL, a data line DL, and a power line PL that cross each other to define a sub-pixel SP.

[0046] A switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and an organic light emitting element (or organic light emitting diode) D are provided in the subpixel SP. The switching transistor Ts is connected to the gate line GL and the data line DL, the driving transistor Td and the storage capacitor Cst are connected between the switching transistor Ts and the power line PL, and the organic light emitting element D is connected to the driving transistor Td.

[0047] In the above configuration, when the switching transistor Ts is turned on according to the scan signal (or gate signal) applied to the gate line GL, the data signal applied to the data line DL is supplied to the gate electrode of the driving transistor Td and one electrode of the storage capacitor Cst through the switching transistor Ts.

[0048] The driving transistor Td is turned on according to the data signal applied to its gate electrode, and as a result, a current proportional to the data signal flows from the power line PL through the driving transistor Td to the organic light emitting element D, and the organic light emitting element D emits light with a brightness proportional to the current flowing through the driving transistor Td.

[0049] At this time, the storage capacitor Cst is charged with a voltage proportional to the data signal so that the gate electrode voltage of the driving transistor Td is maintained constant during one frame.

[0050] In the drawings, only two transistors Td and Ts and one capacitor Cst are provided in the sub-pixel SP, but the present invention is not limited thereto, and three or more transistors and two or more capacitors may be provided.

[0051] Figure 41 is a diagram schematically illustrating a display panel according to the present invention, and shows the display panel 110 formed into various shapes through a cutting process.

[0052] like Figure 4 As shown, the display panel 110 according to the present invention includes a display area AA displaying an actual image and a non-display area NA.

[0053] A plurality of sub-pixels SP are arranged in the display area AA. The sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In addition, the sub-pixels SP may further include a white sub-pixel.

[0054] A plurality of gate lines and data lines are arranged in the display area AA, and sub-pixels SP are arranged at intersections of the gate lines and the data lines. In each sub-pixel SP, a thin film transistor as a switching element and a display element for realizing an actual image are arranged.

[0055] The display element may include one of various display elements. For example, the display element may be an organic light emitting display element, a liquid crystal display element, a quantum dot display element, a micro LED display element, or a mini LED display element.

[0056] A gate driver and a data driver, which apply various signals to the subpixels SP, can be located in the non-display area NA. The gate driver applies scan signals to the subpixels SP via gate lines, while the data driver applies image signals to the subpixels SP via data lines. Furthermore, a plurality of pads PAD are located in the non-display area NA below the display panel AA.

[0057] Figure 1 The display device 100 according to the present invention is a display device in which a plurality of display panels 110a, 110b and 110c are spliced. Figure 4 The display panel 110 shown in FIG. 1 is used to form first to third display panels 110a to 110c of different sizes. That is, in the present invention, after forming a display panel 110 of a specific size, any one of the display panels 110a, 110b, and 110c of various sizes can be manufactured by selectively cutting the display panel 110 along a plurality of cutting lines A, B, C, D, and E.

[0058] like Figure 4 As shown, during manufacture, the display panel 110 can be spliced ​​and used on the display device 100. In addition, the display panel 110 can be cut along any one of the horizontal cutting lines A, B, and C and spliced ​​on the display device 100, or can be cut along any one of the vertical cutting lines D and E and spliced ​​on the display device 100.

[0059] For example, Figure 1 The first display panel 110a of the display device 100 shown can be used without cutting the display panel 110. Figure 4 display panel 110. In addition, Figure 1 The second display panel 110 b of the display device 100 shown may use the display panel 110 cut along the horizontal cutting line A, B, or C, and the third display panel 110 c may use the display panel 110 cut along the vertical cutting line D or E.

[0060] The pads PAD of the display panel 110 spliced ​​on the supporting substrate 120 electrically contact the signal lines SL formed on the supporting substrate 120 to apply driving signals such as data enable signals, vertical synchronization signals, horizontal synchronization signals and clock signals, control signals such as gate control signals and data control signals, and power supply voltages to the display panel 110.

[0061] In addition, the display panels 110 cut along the cutting lines A, B, C, D, or E can be used in a display device without being spliced, and the display panels 110 cut once can be used as a display device. In this case, since the display panels 110 of various sizes can be formed by the same manufacturing line, the display panels 110 of various sizes can be manufactured at a low manufacturing cost. In addition, since the display panels 110 with defects can be recycled, the yield rate can be significantly improved. In the case where the defect is located in a specific area of ​​the display panel 110, for example, between the cutting lines B and C, the display panel 110 can be recycled by cutting the display panel 110 along the cutting lines C, D, or E.

[0062] Therefore, in the display panel 110 of the present invention, the cut and removed area is also the area displaying the image, so the same sub-pixels SP and circuits are formed on the entire display area AA of the display panel 110 including the cutting lines A, B, C, D and E.

[0063] Meanwhile, in the display device 100 according to the present invention, due to the cutting of the display panel 110, a portion of the subpixel SP is directly exposed to the outside, thus causing defects due to moisture penetration. In the present invention, to prevent moisture from penetrating the exposed side surfaces, before cutting the display panel 110, the organic layer and cathode of the display area AA inside the cut line A, B, C, D, or E are selectively removed by laser ablation, and then the removed area is filled with a barrier containing a getter component. This is described in detail below.

[0064] Figure 5A and Figure 5B FIG. 1 is a diagram specifically showing the structure of a display panel according to the present invention. Figure 5A It is along Figure 1 A cross-sectional view taken along line II' of Figure 5B It is along Figure 1 Here, for the convenience of explanation, some sub-pixels SP of the display area AA and the non-display area NA of the third display panel 110c are shown. Figure 5A The display area AA and the non-display area NA with a pad PAD formed on the lower side of the display area AA are included. Figure 5B The display area AA is included and cut along the vertical cutting line D or E so that the right side has a cutting surface.

[0065] like Figure 5A and Figure 5B As shown, a buffer layer 142 is formed on the first substrate 140. The first substrate 140 may be formed of a rigid material such as glass, or may be formed of a plastic material such as polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate, but is not limited thereto.

[0066] For example, when the first substrate 140 is formed of polyimide, it may be configured with a plurality of polyimide layers, and an inorganic layer may be further disposed between the polyimide layers, but is not limited thereto.

[0067] The buffer layer 142 is formed over the entire first substrate 140. The buffer layer 142 may serve to improve the adhesive strength between layers formed thereon and the first substrate 140 and to block various types of defects, such as alkaline components, from leaking from the first substrate 140. In addition, the buffer layer 142 may delay the diffusion of moisture or oxygen that has penetrated the first substrate 140.

[0068] The buffer layer 142 may be formed of a single layer of SiNx or SiOx, or a multilayer using at least one of SiNx or SiOx. When the buffer layer 142 is formed of multiple layers, SiOx and SiNx may be alternately formed. The buffer layer 142 may be omitted depending on the type and material of the first substrate 140, the structure and type of the thin film transistor T, and the like.

[0069] Thin film transistors T are formed on the buffer layer 142 in the display area AA. For ease of illustration, only a driving thin film transistor is shown among the various thin film transistors that can be arranged, but other thin film transistors such as a switching thin film transistor may also be included. In addition, although the thin film transistors T are shown as having a top-gate structure in the figure, thin film transistors are not limited to this structure and may also be implemented using other structures such as a bottom-gate structure.

[0070] The thin film transistor T includes a semiconductor layer 112 disposed on the buffer layer 142, a gate insulating layer 144 formed on the semiconductor layer 112, a gate electrode 114 disposed on the gate insulating layer 144, an interlayer insulating layer 146 formed on the gate electrode 114, and a source electrode 115 and a drain electrode 116 disposed on the interlayer insulating layer 146.

[0071] The semiconductor layer 112 may be formed of a polycrystalline semiconductor. For example, the polycrystalline semiconductor may be formed of low temperature polysilicon (LTPS) having high mobility, but is not limited thereto.

[0072] In addition, the semiconductor layer 112 may be formed of an oxide semiconductor. For example, it may be formed of one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), and IGO (indium gallium oxide), but is not limited thereto. The semiconductor layer 112 includes a channel region 112a in the center region and source and drain regions 112b and 112c on both sides as doped regions.

[0073] The gate insulating layer 144 may be formed over the entire first substrate 140, or may be formed only in some regions, for example, under the gate electrode 114. The gate insulating layer 144 may be formed as a single layer or multiple layers using an inorganic material such as SiOx and / or SiNx, but is not limited thereto.

[0074] The gate electrode 114 is formed of a metal. For example, the gate electrode 114 may be formed of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof in a single layer or multiple layers, but is not limited thereto.

[0075] The interlayer insulating layer 146 may be formed over the entire first substrate 140 or may be formed only in some areas. The interlayer insulating layer 146 may be formed as a single layer or multiple layers using an organic material such as photo acrylic or an inorganic material such as SiNx or SiOx. In addition, the interlayer insulating layer 146 may be formed of multiple layers including an organic layer and an inorganic layer, but is not limited thereto.

[0076] The source electrode 115 and the drain electrode 116 may be formed as a single layer or multiple layers using at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof, but are not limited thereto. The source electrode 115 and the drain electrode 116 may contact the source region 112 b and the drain region 112 c of the semiconductor layer 112 through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146, respectively.

[0077] A bottom shield metal layer may be disposed on the first substrate 140 and below the semiconductor layer 112. The bottom shield metal layer may serve to minimize a back channel phenomenon caused by charges trapped in the first substrate 140 and prevent afterimages or transistor performance degradation, and may be formed as a single layer or multiple layers using titanium (Ti), molybdenum (Mo), and / or alloys thereof, but is not limited thereto.

[0078] A first planarization layer 148 is formed over the first substrate 140 formed with the thin film transistor T. The first planarization layer 148 may be formed of an organic material such as photo acrylic, but is not limited thereto, and may be formed of multiple layers including an inorganic layer and an organic layer.

[0079] The connection electrode 154 is formed on the first planarization layer 148 of the display area AA and is electrically connected to the drain electrode 116 of the thin film transistor T through a contact hole formed in the first planarization layer 148 .

[0080] A second planarization layer 150 is formed over the first planarization layer 148 having the connection electrode 154 formed thereon. The second planarization layer 150 may be formed of an organic material such as photoacrylic, but is not limited thereto, and may be formed of multiple layers including an inorganic layer and an organic layer. Furthermore, the second planarization layer 150 may be formed of the same material as the first planarization layer 148, but may also be formed of a different material from the first planarization layer 148.

[0081] Thus, in the present invention, by forming the two-layer structure of planarization layers 148 and 150, various electrodes and lines can be formed between the first planarization layer 148 and the second planarization layer 150. Accordingly, since the electrodes can be arranged vertically, the area of ​​the electrodes and lines in the sub-pixel can be reduced. As a result, the area of ​​the sub-pixel can be reduced, thereby manufacturing a high-resolution display device 100.

[0082] Of course, the planarization layer may be configured as a single layer depending on the type, area, resolution, etc. of the display device 100. In this case, the connection electrode 154 may be omitted.

[0083] The light emitting element D is disposed in the display area AA on the second planarization layer 150. The light emitting element D includes a first electrode 132, a light emitting layer 134, and a second electrode 136.

[0084] The first electrode 132 is provided on the second planarization layer 150 and is connected to the connection electrode 154 through a contact hole formed in the second planarization layer 150. The connection electrode 154 is connected to the drain electrode 116 of the thin film transistor T through a contact hole formed in the first planarization layer 148, so that the first electrode 132 is electrically connected to the drain electrode 116 through the connection electrode 154. The first electrode 132 can be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and alloys thereof. In addition, the first electrode 132 can be formed of a transparent metal oxide layer such as ITO (indium tin oxide) or IZO (indium zinc oxide).

[0085] When the planarization layer is formed of a single layer and the connection electrode 154 is omitted, the first electrode 132 is provided on the first planarization layer 148 and is directly connected to the drain electrode 116 of the thin film transistor T through a contact hole formed in the first planarization layer 148 .

[0086] When the display device 100 is a top-emission display device, the first electrode 132 may include an opaque conductive material to serve as a reflective electrode that reflects light. When the display device 100 is a bottom-emission display device, the first electrode 132 may be formed using a transparent conductive material that transmits light, such as ITO (indium tin oxide) or IZO (indium zinc oxide).

[0087] The bank layer BNK forms a boundary of each sub-pixel on the second planarization layer 150. The bank layer BNK may be a partition wall defining the sub-pixels. The bank layer BNK may separate the sub-pixels and prevent light of a specific color outputted from adjacent sub-pixels from being mixed and outputted.

[0088] The bank layer BNK may be formed of at least one of an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, and a photosensitive material including a black pigment, but is not limited thereto.

[0089] The light emitting layer 134 is formed on an upper surface (or top surface) of the first electrode 132 surrounded by the bank layer BNK. The light emitting layer 134 may be formed to extend to a portion of a side surface and an upper surface of the bank layer BNK.

[0090] The light-emitting layer 134 may include an R light-emitting layer formed in a red sub-pixel and emitting red light, a G light-emitting layer formed in a green sub-pixel and emitting green light, and a B light-emitting layer formed in a blue sub-pixel and emitting blue light. The light-emitting layer 134 may include an organic light-emitting layer or an inorganic light-emitting layer, such as a nanomaterial layer, a quantum dot light-emitting layer, a micro-LED light-emitting layer, or a mini-LED light-emitting layer, but is not limited thereto.

[0091] The light-emitting layer 134 may include not only an organic light-emitting layer, but also an electron injection layer and a hole injection layer for injecting electrons and holes into the organic light-emitting layer, and an electron transport layer, a hole blocking layer, an electron blocking layer and a hole transport layer for transporting the injected electrons and holes into the organic light-emitting layer, but is not limited thereto.

[0092] The second electrode 136 is provided on the light emitting layer 134 and may be formed as a single layer or multiple layers using metal and / or its alloy. In addition, the second electrode 136 may be formed of a transparent metal oxide such as ITO (indium tin oxide) or IZO (indium zinc oxide), but is not limited thereto.

[0093] When the display device 100 is a top emission type, the second electrode 136 may be formed using a semi-transparent conductive material that transmits light. For example, the second electrode 136 may be formed using at least one of an alloy such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and LiF / Ca:Ag.

[0094] When the display device 100 is a bottom emission type, the second electrode 136 can be formed as a reflective electrode that reflects light using an opaque conductive material. For example, the second electrode 136 can be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and alloys thereof.

[0095] In addition, the light-emitting element D can be configured as a series structure. The series structure may include multiple light-emitting layers, and the charge generation layer may be provided between the light-emitting layers. The charge generation layer is used to control the charge balance between the multiple organic layers and can be configured as a multilayer including a first charge generation layer and a second charge generation layer. The charge generation layer may include an N-type charge generation layer and a P-type charge generation layer, and may be formed of a light-emitting layer doped with an alkali metal (e.g., Li, Na, K, or Cs) or an alkaline earth metal (e.g., Mg, Sr, Ba, or Ra), but is not limited thereto.

[0096] Encapsulation layer 182 is formed on light-emitting element D to encapsulate light-emitting element D. If light-emitting element D is exposed to moisture or oxygen, pixel shrinkage, where the light-emitting area is reduced, or defects, where dark spots form in the light-emitting area, may occur. Furthermore, moisture or oxygen oxidizes metal electrodes. Encapsulation layer 182 blocks moisture and oxygen from penetrating from the outside, thereby preventing defects in light-emitting element D and various electrodes.

[0097] The DAM is provided in the non-display area NA below the display area AA and on the cut surface on one side of the display area AA. The DAM may be formed along the entire periphery of the display panel 110 to bond the first and second substrates 140 and 190 while preventing moisture from penetrating into the interior of the display panel 110. The DAM is formed of, but is not limited to, an organic material.

[0098] Filler 184 is disposed between first substrate 140 and second substrate 190 and is surrounded by a barrier DAM. Filler 184 may be an adhesive layer adhering encapsulation layer 182 and second substrate 190. Filler 184 may be formed of a thermosetting adhesive resin, a light-curing adhesive resin, or a naturally curing adhesive resin.

[0099] The filler 184 may be a barrier layer for preventing moisture and oxygen from penetrating into the display panel 110. When the first substrate 140 and the second substrate 190 are bonded together, if a separate material is not filled into the space between the first substrate 140 and the second substrate 190, the display panel 110 may be relatively susceptible to moisture and oxygen penetrating from the outside. Therefore, by filling the space between the first substrate 140 and the second substrate 190 with a moisture-proof layer that inhibits the penetration of moisture and oxygen, moisture and oxygen can be effectively prevented from penetrating into the display panel 110. In this case, the filler 184 may be configured to include a moisture absorbent or a moisture and oxygen barrier. For example, a getter may be included in the filler 184.

[0100] In addition, the filler 184 may be configured to include an adhesive resin that bonds the encapsulation layer 182 and the second substrate 190 , and a moisture and oxygen barrier.

[0101] The filler 184 may have a function of maintaining a constant gap between the first substrate 140 and the second substrate 190 .

[0102] Since the filler 184 is filled inside the display panel 110 via the dam DAM, the dam DAM serves as a sealant for sealing the filler 184 .

[0103] In the non-display area NA below the display area AA, blocking banks BDAM may be provided inside and outside the barrier DAM. The blocking banks BDAM may be formed of two layers. In this case, the lower layer of the blocking banks BDAM may be formed of the same material as the second planarization layer 150, and the upper layer of the blocking banks BDAM may be formed of the same material as the bank layer BNK, but is not limited thereto.

[0104] In the drawing, the blocking bank BDAM is formed inside and outside the barrier DAM. Alternatively, the blocking bank BDAM may be formed only on one of the inside and outside of the barrier DAM, or may be omitted according to the structure of the display panel 110.

[0105] The DAM is disposed on the first planarization layer 148. Specifically, the second planarization layer 150 and the light-emitting layer 134 are removed from the non-display area NA, and the DAM is formed in the removed area. This prevents moisture from penetrating the second planarization layer 150 and the light-emitting layer 134 because the second planarization layer 150 and the light-emitting layer 134 below the DAM are removed.

[0106] The second planarization layer 150 and the light emitting layer 134 under the stopper DAM may be removed in various ways. For example, the second planarization layer 150 and the light emitting layer 134 under the stopper DAM may be removed during an etching process when the second planarization layer 150 and the light emitting layer 134 are formed.

[0107] However, in the case of manufacturing the display panel 110 of various sizes by cutting the display panel 110 as in the present invention, the display panel 110 is formed through the same process up to the light emitting element D, and then the display panel 110 is cut into various sizes. After the display panel 110 is cut, the dam DAM and the filler 184 are formed and bonded to the second substrate 190.

[0108] Therefore, since the formation position of the barrier DAM varies depending on the area of ​​the display panel 110 to be cut, after forming the light-emitting element D, a process of removing the second planarization layer 150 and the light-emitting layer 134 is performed in the area where the barrier DAM is to be formed. In the present invention, the second planarization layer 150 and the light-emitting layer 134 can be removed using a laser. When the second planarization layer 150 and the light-emitting layer 134 are removed using a laser, they can be removed quickly and precisely at the desired location. However, the second planarization layer 150 and the light-emitting layer 134 can be removed not only using a laser process but also using other processes.

[0109] Meanwhile, the stopper DAM may be disposed on the interlayer insulating layer 146. In this case, before forming the stopper DAM, the first planarization layer 148, the second planarization layer 150, and the light emitting layer 134 in regions corresponding to the stopper DAM may be removed by a laser process or the like.

[0110] The pad PAD is provided at the edge of the non-display area NA. The pad PAD may be formed on the first planarization layer 148 and may be formed of the same metal as the connection electrode 154 through the same process, but is not limited thereto. Alternatively, the pad PAD may be formed on the interlayer insulating layer 146 and may be formed of the same metal as the source electrode 115 and the drain electrode 116 through the same process, but is not limited thereto.

[0111] Connection line 162 is provided on first planarization layer 148 of non-display area NA. Connection line 162 contacts corresponding pad PAD and is electrically connected to pad PAD. In the figure, connection line 162 is formed to completely cover pad PAD, but connection line 162 may also be formed to cover a portion of pad PAD. In addition, an insulating layer may be formed on pad PAD, and connection line 162 may be provided on the insulating layer so that pad PAD and connection line 162 can be electrically connected through a contact hole formed in the insulating layer.

[0112] The connection line 162 may be formed as a single layer or multiple layers using at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof, but is not limited thereto.

[0113] The connection line 162 extends from the upper surface of the pad PAD to the lower surface (or bottom surface) of the first substrate 140 through the side surface of the first substrate 140. A protective layer 164 is formed on the connection line 162. The protective layer 164 seals the connection line 162 to prevent the connection line 162 from being corroded by external moisture or the like.

[0114] The protective layer 164 may be formed of an inorganic material or an organic material, and may be formed of a double layer including an inorganic layer and an organic layer.

[0115] A protective layer 164 is also formed on the cut surface CF of the display area AA. Because the cut surface CF is directly exposed to the outside, moisture can penetrate this area from the outside. Therefore, by forming the protective layer 164 on the cut surface CF, moisture is prevented from penetrating this area. The protective layer 164 extends from the upper surface of the second substrate 190 to the cut surface CF and the lower surface of the first substrate 140, so that the entire cut surface CF is sealed by the protective layer 164.

[0116] Meanwhile, the support substrate 120 is disposed on a lower surface of the first substrate 140 , and the first substrate 140 and the support substrate 120 are bonded together by an adhesive 170 .

[0117] The signal line SL is provided on the upper surface of the support substrate 120, that is, on one surface of the support substrate 120 facing the first substrate 140. Figure 1As shown, the signal line SL is electrically connected to the printed circuit board PCB through the flexible circuit board FPC.

[0118] The signal lines SL are electrically connected to the connection lines 162 of the first substrate 140 through contact holes formed in the protective layer 164 to apply various signals provided from an image processing section, a timing control section, a power supply section, etc. arranged on the printed circuit board PCB to various electrodes on the first substrate 140. The signal lines SL may be connected to the connection lines 162 by connection members such as solder balls or bumps, but are not limited thereto.

[0119] As described above, in the display device 100 according to the present invention, since the display panel 110 is manufactured through the same process and then the display panels 110 of various sizes are manufactured through a cutting process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0120] In addition, in the display device 100 according to the present invention, the second planarization layer 150 and the bank layer BNK of the cut region are removed, and the barrier DAM is formed in the removed region, thereby preventing moisture from penetrating the cut surface.

[0121] Furthermore, in the display device 100 according to the present invention, since the protective layer 164 is formed on the side surfaces of the non-display area NA and the cut surface CF of the display area AA, moisture may be more effectively prevented from penetrating into the display device 100 .

[0122] In addition, in the display device 100 according to the present invention, the connecting line 162 connected to the pad PAD of the non-display area NA extends along the side surface of the first substrate 140 to the rear side of the first substrate 140 and is electrically connected to the signal line SL of the supporting substrate 120, so that the area occupied by the connecting device connecting the display panel 110 and the supporting substrate 120 can be minimized, thereby minimizing the seam of the spliced ​​display device 100.

[0123] Hereinafter, a method of manufacturing the display device 100 according to the present invention is described in detail with reference to the accompanying drawings.

[0124] Figures 6A to 6G are diagrams illustrating a method of manufacturing a display device according to an embodiment of the present invention. Figures 6A to 6G Shows the manufacturing Figure 5B The structural method.

[0125] First, if Figure 6AAs shown, a buffer layer 142 is formed over the entire first substrate 140. The first substrate 140 can be formed of a rigid material such as glass or a plastic material such as polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate. The buffer layer 142 can be formed by stacking a single layer or multiple layers of SiNx or SiOx.

[0126] Then, a polycrystalline semiconductor such as polysilicon or an oxide semiconductor such as IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), or IGO (indium gallium oxide) is stacked on the buffer layer 142 and etched to form a semiconductor layer 112 in each subpixel SP. In addition, by doping impurities on both sides of the semiconductor layer 112, a channel region 112a, a source region 112b, and a drain region 112c are formed.

[0127] Then, an inorganic material such as SiOx or SiNx is stacked to form a gate insulating layer 144. Then, a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu) is stacked by a sputtering method and etched by a wet etching method to form a gate electrode 114 in each sub-pixel SP. Then, an organic material such as photo acrylic or an inorganic material such as SiNx or SiOx is stacked on the gate electrode 114 to form an interlayer insulating layer 146, and then the interlayer insulating layer 146 on each of the source region 112b and the drain region 112c of the semiconductor layer 112 is dry-etched to form a contact hole.

[0128] Next, a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy is stacked by sputtering and then etched to form a source electrode 115 and a drain electrode 116 in each sub-pixel SP that are in ohmic contact with the source region 112 b and the drain region 112 c of the semiconductor layer 112 through corresponding contact holes, thereby forming a thin film transistor T.

[0129] Then, an organic material such as photo acrylic is stacked on the source electrode 115 and the drain electrode 116 to form a first planarization layer 148 , and then the first planarization layer 148 on the drain electrode 116 is dry-etched to form a contact hole.

[0130] Next, a metal layer such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr) or an alloy thereof is stacked on the first planarization layer 148 by sputtering and etched to form a connecting electrode 154 on the first planarization layer 148.

[0131] Then, an organic material such as photo acrylic is stacked on the first planarization layer 148 to form a second planarization layer 150 , and then the second planarization layer 150 on the connection electrode 154 is etched to form a contact hole.

[0132] Next, a metal such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof, or a metal oxide such as ITO or IZO is stacked by a sputtering method and etched to form the first electrode 132 on the second planarization layer 150. At this time, the first electrode 132 is connected to the connection electrode 154 through a contact hole formed in the second planarization layer 150, and the connection electrode 154 is connected to the drain electrode 116 of the thin film transistor T through a contact hole formed in the first planarization layer 148, so that the first electrode 132 is connected to the drain electrode 116 of the thin film transistor T.

[0133] Then, at least one of an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as BCB (benzocyclobutene), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin or a polyimide resin, or a photosensitive material including a black pigment is stacked on the second planarization layer 150 and the first electrode 132, and etched by a dry etching method to form a bank layer BNK on the edges of the second planarization layer 150 and the first electrode 132.

[0134] Then, a light-emitting material is stacked and patterned on the display area AA to form a light-emitting layer 134, and then a metal or its alloy or metal oxide is stacked and etched to form a second electrode 136 on the side surface and upper surface of the light-emitting layer 134 and the partition layer BNK, thereby forming a light-emitting element D.

[0135] Then, if Figure 6B As shown, laser light is irradiated on the laser irradiation area LA in the first substrate 140. Figure 6C As shown, the light emitting element D, the bank layer BNK, the second planarization layer 150 and the first planarization layer 148 in the laser irradiation area LA are removed.

[0136] Then, if Figure 6D As shown, an organic material is stacked and patterned to form a barrier DAM in the laser irradiation area LA where the light emitting element D, the bank layer BNK, the second planarization layer 150, and the first planarization layer 148 are removed. Meanwhile, the barrier DAM may be formed along the periphery on other sides of the first substrate 140 than the side corresponding to the laser irradiation area LA.

[0137] Afterwards, if Figure 6EAs shown, filler 184 is applied to the inner side of the outer periphery of first substrate 140, and then second substrate 190 is placed on filler 184, and then filler 184 is cured to attach second substrate 190. Filler 184 can be formed of a heat-curing adhesive resin, a light-curing adhesive resin, or a natural curing adhesive resin, but is not limited thereto. In addition, filler 184 can include a moisture-proof material such as a getter.

[0138] The filler 184 may be placed between the first substrate 140 and the second substrate 190 outside the barrier DAM. In this case, when cutting the display panel, the cutting efficiency may be reduced due to the filler 184, and the filler 184 may not be applied between the first substrate 140 and the second substrate 190 outside the barrier DAM.

[0139] Then, the display panel is cut along a cutting line spaced a certain distance from the blocker DAM by a cutting wheel or laser. Figure 6F As shown, the cut surface is polished by a polishing device 195 to complete a display panel of a desired size.

[0140] Then, if Figure 6G As shown, a protective layer 164 is formed on the cut surface of the display panel to seal the cut surface, and then the manufactured display panel is attached to the support substrate 120. Figure 5A In the non-display area NA where the pad PAD is placed, before forming the protective layer 164, a connecting line 162 electrically connected to the pad PAD can be formed, and the connecting line 162 extends from the upper surface of the first planarization layer 148 to the rear surface of the first substrate 140, and the protective layer 164 can be configured to seal the connecting line 162.

[0141] As described above, in the display device according to the present invention, since the display panel is manufactured through the same process and then the display panels of various sizes are manufactured through a cutting process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0142] In the display device according to the present invention, the planarization layer and the bank layer of the cut region are removed, and a barrier is formed in the removed region, thereby preventing moisture from penetrating the cut surface.

[0143] In the display device according to the present invention, since the protective layer is formed on the side surfaces of the non-display area and the cut surface of the display area, it is possible to more effectively prevent moisture from penetrating into the display device.

[0144] In the display device according to the present invention, the connection lines connected to the pads of the non-display area extend along the side surface of the first substrate to the rear surface and are electrically connected to the signal lines of the support substrate. Therefore, the area occupied by the connection device connecting the display panel and the support substrate can be minimized, thereby minimizing the seam of the tiled display device.

[0145] In the display device according to the present invention, display panels of various sizes can be manufactured through the same process, so that production energy consumption can be reduced due to process optimization.

[0146] It will be apparent to those skilled in the art that various modifications and variations may be made in the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display panel, comprising: The first substrate and the second substrate include a display area having a plurality of sub-pixels and a non-display area outside the display area; a thin film transistor and a light emitting element, arranged in each of the plurality of sub-pixels; a barrier disposed between the first substrate and the second substrate at an end portion of the display area and the non-display area; as well as A protective layer is provided on the side surface of the non-display area and the side surface of the end portion of the display area.

2. The display panel according to claim 1, wherein The organic layer below the barrier is removed.

3. The display panel according to claim 2, further comprising: at least one planarization layer covering the thin film transistor; as well as A bank layer is provided between the plurality of sub-pixels.

4. The display panel according to claim 3, wherein: The organic layer below the stopper includes the planarization layer and the bank layer.

5. The display panel according to claim 4, wherein: The organic layer below the stopper is removed by laser.

6. The display panel according to claim 1, further comprising: a solder pad, arranged on the first substrate in the non-display area; a connecting line electrically connected to the pad and extending to the lower surface of the first substrate through the side surface of the first substrate, Wherein, the connecting line is covered by the protective layer.

7. The display panel according to claim 6, wherein: The connecting wire completely covers the pad.

8. The display panel according to claim 6, further comprising an insulating layer located on the pad, in, The pad is electrically connected to the connection line through a first contact hole formed in the insulating layer.

9. The display panel according to claim 1, wherein: The end portion of the display area has a cut surface. 10 . The display panel of claim 1 , further comprising a filler placed between the first substrate and the second substrate at an inner side of the barrier.

11. The display panel according to claim 10, wherein: The filler includes a binding resin.

12. The display panel according to claim 11, wherein: The adhesive resin includes a moisture-proofing agent.

13. A display device comprising: a supporting substrate; as well as A plurality of display panels mounted on the support substrate include the display panel according to claim 1.

14. The display device according to claim 13, wherein: The plurality of display panels include display panels cut along horizontal cutting lines and / or vertical cutting lines and having different sizes. 15 . The display device according to claim 13 , further comprising a signal line provided on an upper surface of the support substrate.

16. The display device according to claim 15, wherein The signal lines are electrically connected to the connection lines of the display panel. 17 . The display device according to claim 13 , further comprising an adhesive layer disposed between the support substrate and the display panel.

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