Display device

Abstract

The embodiment of the invention relates to a display device. A first metal layer having an opening is in an intermediate region between the display region and the opening region, and an organic encapsulation layer overlaps the opening of the first metal layer in at least a partial region. Accordingly, it is possible to provide a display device capable of reducing foreign matter generated during a process and improving reliability.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0029461, filed on February 29, 2024, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device. Background Art

[0004] With the advancement of technology, in addition to the image display function, the display device can also provide a shooting function and various detection functions.

[0005] To this end, the display device should include an optoelectronic device (also called a light receiving device or sensor), such as a camera and a detection sensor.

[0006] Since the optoelectronic device should receive light from the front surface of the display device, the optoelectronic device should be installed at a position that is conducive to receiving light.

[0007] Therefore, the camera (camera lens) and the detection sensor have to be mounted on the front surface of the display device so as to be exposed to the outside.

[0008] Due to this fact, the bezel of the display panel is widened, or a notch or a physical hole is formed in the display area of ​​the display panel and a camera or a detection sensor is installed therein.

[0009] Therefore, since an optoelectronic device (eg, a camera and a detection sensor) that performs a predetermined function by receiving light from a front surface is provided in the display device, the display device may be required to have high transmittance. Summary of the Invention

[0010] In the prior art, attempts have been made to ensure reliability by forming an undercut structure around a channel hole at a camera mounting position in a display panel to cut the light emitting layer and by contacting an encapsulation layer to prevent penetration of moisture particles.

[0011] However, there is a problem that an additional process is required to form the undercut structure. Therefore, the inventors of the present disclosure have invented a display device that can ensure reliability by reducing foreign matter generated during the process while achieving process optimization.

[0012] Embodiments of the present disclosure are intended to provide a display device capable of reducing foreign matter generated during a process.

[0013] The embodiments of the present disclosure are directed to providing a display device that can achieve process optimization while ensuring the reliability of a display panel.

[0014] According to an embodiment of the present disclosure, a display device may include: a substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the intermediate area on the substrate; a first metal layer located on the insulating layer and including at least one first opening, the at least one first opening being located in the intermediate area; a second metal layer located on the first metal layer in the intermediate area and including at least one second opening, the at least one second opening being located in an area including an area overlapping with the at least one first opening; and an organic encapsulation layer located on the insulating layer and at least partially overlapping with the first opening.

[0015] According to an embodiment of the present disclosure, a display device may include: a substrate, which includes an opening area, a display area surrounding the opening area, an intermediate area between the opening area and the display area, and an external area surrounding the outside of the display area; at least one first dam portion, which is located on the substrate and is arranged in the external area; at least one second dam portion, which is located on the substrate, is arranged in the intermediate area, and includes a dummy electrode located on the same layer as a cathode electrode arranged in the display area.

[0016] According to an embodiment of the present disclosure, a display device may include: a substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the intermediate area on the substrate; an encapsulation layer located on the insulating layer, located in the intermediate area, and including a first part and a second part, the first part including an organic encapsulation layer, and the second part not including an organic encapsulation layer; a first metal layer located in the first part and between the insulating layer and the organic encapsulation layer; and a second metal layer located in the first part and between the first metal layer and the organic encapsulation layer.

[0017] According to an embodiment of the present disclosure, a display device capable of reducing foreign matter generated during a process can be provided.

[0018] According to the embodiments of the present disclosure, by reducing foreign matter generated during a process, a display device capable of achieving process optimization while ensuring the reliability of a display panel can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a plan view of a display device according to an embodiment of the present disclosure.

[0020] Figure 2 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0021] Figure 3is an equivalent circuit diagram of a sub-pixel in a display device according to an embodiment of the present disclosure.

[0022] Figure 4A and Figure 4B is a plan view illustrating a portion of a display panel according to an embodiment of the present disclosure.

[0023] 5A to 5D It is along Figure 4A A cross-sectional view taken along line II'.

[0024] Figure 6 It is along Figure 4B A cross-sectional view taken along line II-II'.

[0025] Figure 7 It is along Figure 4A A cross-sectional view taken along line III-III'.

[0026] Figure 8 yes Figure 5A An enlarged cross-sectional view of portion A.

[0027] Figures 9A to 9C It shows Figure 4A A plan view of at least one dam portion shown in FIG.

[0028] 10A to 10C is a cross-sectional view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0029] Figures 11A to 11C is a plan view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0030] 12A to 12D is a cross-sectional view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, which show by way of example specific examples or embodiments that may be implemented, and in which the same reference numerals and symbols may be used to represent the same or similar parts, even if they are shown in different drawings from one another. In addition, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter of some embodiments of the present disclosure less clear. Terms such as "including," "having," "comprising," "consisting of," and "formed of" used herein are generally intended to allow for the addition of other parts unless these terms are used with the term "only." As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0032] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, order, sequence, quantity, etc. of the elements, but is only used to distinguish the corresponding element from other elements.

[0033] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be understood that the first element may not only be “directly connected or coupled to” the second element, or “directly contact or overlap” the second element, but also that a third element may be “interposed” between the first and second elements, or that the first and second elements may be “connected or coupled to”, “contacts or overlaps” each other via a fourth element, etc. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., each other.

[0034] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or arrangement, or a procedure or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0035] Furthermore, when referring to any dimension, relative size, etc., even if no relevant description is specified, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can."

[0036] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 is a plan view of a display device 100 according to an embodiment of the present disclosure.

[0038] refer to Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 displaying an image and at least one channel hole CH.

[0039] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0040] In the display area DA, a plurality of sub-pixels may be provided, and various signal lines for driving the plurality of sub-pixels may be provided.

[0041] The non-display area NDA may be an area outside the display area DA.

[0042] In the non-display area NDA, various signal lines may be provided and various driving circuits may be connected.

[0043] The non-display area NDA may be curved so as not to be visible on the front surface, or may be covered by a case (not shown).

[0044] The non-display area NDA may be referred to as a bezel or a bezel area.

[0045] refer to Figure 1 , in the display device 100 according to an embodiment of the present disclosure, the channel hole CH may be formed by cutting along the cutting line TML.

[0046] Light may enter the front surface (or viewing surface) of the display panel 110 and may be transmitted through the channel hole CH of the display panel 110 to at least one optoelectronic device located below the display panel 110 (or a surface opposite to the viewing surface).

[0047] The at least one optoelectronic device may be a device that receives light transmitted through the display panel 110 and performs a predetermined function according to the received light.

[0048] For example, the at least one optoelectronic device may include at least one of a photographing device such as a camera (image sensor) and a detection sensor such as a proximity sensor and an illumination sensor.

[0049] The illumination sensor may be an ambient light sensor, but is not limited thereto.

[0050] When the display device 100 is turned off, the ambient light of the display device 100 may be detected by the illumination sensor, and the brightness of the screen output through the display panel 110 may be adjusted according to the brightness of the ambient light.

[0051] Although the channel hole CH is depicted as having a circular structure, according to an embodiment of the present disclosure, the shape of the channel hole CH is not limited thereto.

[0052] The channel hole CH may have various shapes such as a circle, an ellipse, a quadrangle, a hexagon, and an octagon.

[0053] Figure 2 is a system configuration diagram of the display device 100 according to an embodiment of the present disclosure.

[0054] refer to Figure 2 , the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image.

[0055] The display driving circuit, as a circuit for driving the display panel 110 , may include a data driving circuit 220 , a gate driving circuit 230 , and a display controller 240 .

[0056] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0057] The non-display area NDA may be an area outside the display area DA, and may also be referred to as a frame area.

[0058] All or part of the non-display area NDA may be an area visible on the front surface of the display device 100 , or an area that is curved and thus not visible on the front surface of the display device 100 .

[0059] The display panel 110 may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB.

[0060] In order to drive the plurality of sub-pixels SP, the display panel 110 may further include various types of signal lines.

[0061] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device, etc., or may be a self-luminous display device in which the display panel 110 emits light by itself.

[0062] When the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0063] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light emitting display device in which a light emitting element is implemented using an organic light emitting diode (OLED).

[0064] For another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light emitting display device in which the light emitting elements are implemented using inorganic-based light emitting diodes.

[0065] For another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light emitting elements are implemented by quantum dots, which are self-luminous semiconductor crystals.

[0066] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100 .

[0067] For example, when the display device 100 is a self-luminous display device in which each sub-pixel SP emits self-light, each sub-pixel SP may include a self-luminous element, at least one transistor, and at least one capacitor.

[0068] For example, the various types of signal lines may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0069] The plurality of data lines DL and the plurality of gate lines GL may intersect each other.

[0070] Each of the plurality of data lines DL may be disposed to extend in a first direction.

[0071] Each of the plurality of gate lines GL may be disposed to extend in the second direction.

[0072] The first direction may be a column direction, and the second direction may be a row direction.

[0073] Alternatively, the first direction may be a row direction, and the second direction may be a column direction.

[0074] The data driving circuit 220 , which is a circuit for driving the plurality of data lines DL, may output data signals to the plurality of data lines DL.

[0075] The gate driving circuit 230 , which is a circuit for driving the plurality of gate lines GL, may output gate signals to the plurality of gate lines GL.

[0076] The display controller 240 , which is a device for controlling the data driving circuit 220 and the gate driving circuit 230 , may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

[0077] The display controller 240 may provide the data driving circuit 220 with a data driving control signal DCS for controlling the data driving circuit 220 , and may provide the gate driving control signal GCS for controlling the gate driving circuit 230 with the gate driving circuit 230 .

[0078] The display controller 240 may receive input image data from the host system 250 and may provide image data data to the data driving circuit 220 based on the input image data.

[0079] The data driving circuit 220 may provide data signals to the plurality of data lines DL according to driving timing control of the display controller 240 .

[0080] The data driving circuit 220 may receive digital-type image data Data from the display controller 240 , may convert the received image data Data into analog-type data signals, and may output the data signals to a plurality of data lines DL.

[0081] The gate driving circuit 230 may provide gate signals to the plurality of gate lines GL according to the timing control of the display controller 240 .

[0082] The gate driving circuit 230 may be provided with a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage, as well as various gate driving control signals GCS, may generate gate signals, and may provide the generated gate signals to a plurality of gate lines GL.

[0083] For example, the data driving circuit 220 can be connected to the display panel 110 in a tape automated bonding (TAB) method, can be connected to the bonding pads of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or can be connected to the display panel 110 by being implemented in a chip on film (COF) method.

[0084] The gate driving circuit 230 can be connected to the display panel 110 in a tape automated bonding (TAB) method, can be connected to the bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or can be connected to the display panel 110 according to a chip on film (COF) method.

[0085] Alternatively, the gate driving circuit 230 may be formed in the non-display area NDA of the display panel 110 in a gate-in-panel (GIP) type.

[0086] The gate driving circuit 230 may be provided on the substrate or may be connected to the substrate.

[0087] That is, in the case of the GIP type, the gate driving circuit 230 may be disposed in the non-display area NDA of the substrate.

[0088] In case of a chip on glass (COG) type or a chip on film (COF) type, the gate driving circuit 230 may be connected to the substrate.

[0089] At least one driving circuit of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110 .

[0090] For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed so as not to overlap with the sub-pixel SP, or may be disposed so as to partially or completely overlap with the sub-pixel SP.

[0091] The data driving circuit 220 may be connected to one side (eg, an upper side or a lower side) of the display panel 110 .

[0092] The data driving circuit 220 may be connected to both sides (eg, upper and lower sides) of the display panel 110 , or may be connected to at least two of four sides of the display panel 110 , depending on a driving method, a panel design method, etc.

[0093] The gate driving circuit 230 may be connected to one side (eg, left or right) of the display panel 110 .

[0094] The gate driving circuit 230 may be connected to both sides (eg, left and right sides) of the display panel 110 , or may be connected to at least two of four sides of the display panel 110 , depending on a driving method, a panel design method, etc.

[0095] The display controller 240 may be implemented as a component separate from the data driving circuit 220 , or may be implemented as an integrated circuit by being integrated with the data driving circuit 220 .

[0096] The display controller 240 may be a timing controller used in general display technology, a control device including a timing controller and capable of further performing other control functions, a control device different from a timing controller, or a circuit in a control device.

[0097] The display controller 240 may be implemented by various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and a processor.

[0098] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 220 and the gate driving circuit 230 through the printed circuit board, the flexible printed circuit, or the like.

[0099] The display controller 240 may transmit and receive signals to and from the data driving circuit 220 according to at least one predetermined interface.

[0100] For example, the interface may include a low voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral (SP) interface, and the like.

[0101] In order to further provide touch sensing functions as well as image display functions, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, which detects whether a touch event occurs through a touch object such as a finger or a pen or detects a touch position by sensing the touch sensor.

[0102] The touch sensing circuit may include a touch driving circuit 260 and a touch controller 270 . The touch driving circuit 260 generates and outputs touch sensing data by driving and sensing the touch sensor. The touch controller 270 can use the touch sensing data to detect the occurrence of a touch event or detect a touch position.

[0103] The touch sensor may include a plurality of touch electrodes.

[0104] The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit 260 .

[0105] The touch sensor may be located outside the display panel 110 in the form of a touch panel, or may be located inside the display panel 110 .

[0106] In the case where the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type.

[0107] When the touch sensor is of an external type, the touch panel and the display panel 110 may be manufactured separately and coupled during an assembly process.

[0108] The external type touch panel may include a substrate for a touch panel and a plurality of touch electrodes on the substrate for the touch panel.

[0109] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during a process of manufacturing the display panel 110 .

[0110] The touch driving circuit 260 may provide a touch driving signal to at least one of the plurality of touch electrodes and may generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0111] The touch sensing circuit may perform touch sensing in a self-capacitance sensing method or a mutual capacitance sensing method.

[0112] In the case where the touch sensing circuit performs touch sensing in a self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0113] According to the self-capacitance sensing method, each of the plurality of touch electrodes may function as both a driving touch electrode and a sensing touch electrode.

[0114] The touch driving circuit 260 may drive all or some of the plurality of touch electrodes and may sense all or some of the plurality of touch electrodes.

[0115] In the case where the touch sensing circuit performs touch sensing in a mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0116] According to the mutual capacitance sensing method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes.

[0117] The touch driving circuit 260 may drive the touch electrodes and sense the touch electrodes.

[0118] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented as separate devices or as a single device.

[0119] Furthermore, the touch driving circuit 260 and the data driving circuit 220 may be implemented as separate devices or as a single device.

[0120] The display device 100 may further include a power supply circuit that provides various types of power to the display driving circuit and / or the touch sensing circuit.

[0121] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone and a tablet computer, or a monitor or television (TV) of various sizes. However, the display device 100 according to an embodiment of the present disclosure is not limited thereto and may be a display of various types and sizes capable of displaying information or images.

[0122] The display area DA in the display panel 110 may include a normal area NA and at least one channel hole CH.

[0123] Figure 3 is an equivalent circuit diagram of a sub-pixel SP in the display device 110 according to an embodiment of the present disclosure.

[0124] Each subpixel SP included in the display area DA of the display panel 110 may include a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, a scan transistor SCT for transmitting a data voltage Vdata to a first node N1 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0125] The driving transistor DRT may include a first node N1 to which the data voltage Vdata may be applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which the driving voltage ELVDD from the driving voltage line DVL is applied.

[0126] In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0127] The light emitting element ED may include a first electrode layer AE, a light emitting layer EL, and a second electrode layer CE.

[0128] The first electrode layer AE may be a pixel electrode provided in each sub-pixel SP and may be electrically connected to the second node N2 of the driving transistor DRT of each sub-pixel SP.

[0129] The second electrode layer CE may be a common electrode, which is commonly provided in the plurality of sub-pixels SP, and to which a base voltage ELVSS may be applied.

[0130] For example, the first electrode layer AE may be a pixel electrode, and the second electrode layer CE may be a common electrode.

[0131] On the contrary, the first electrode layer AE may be a common electrode, and the second electrode layer CE may be a pixel electrode.

[0132] Hereinafter, for the convenience of description, it is assumed that the first electrode layer AE is a pixel electrode, and the second electrode layer CE is a common electrode.

[0133] The light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode, or a quantum dot (QD) light emitting element.

[0134] When the light emitting element ED is an organic light emitting diode, the light emitting layer EL in the light emitting element ED may include an organic light emitting layer including an organic material.

[0135] The scan transistor SCT may be turned on-off by a scan signal SCAN, which is a gate signal applied through the gate line GL, and may be electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

[0136] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0137] like Figure 3 As shown, each sub-pixel SP may have a 2T (transistor) 1C (capacitor) structure including two transistors DRT and SCT and one capacitor Cst. Depending on the specific situation, the sub-pixel SP may further include at least one transistor or at least one capacitor.

[0138] The storage capacitor Cst may not be a parasitic capacitor (eg, Cgs or Cgd), which is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DRT, but may be an external capacitor intentionally designed outside the driving transistor DRT.

[0139] Each of the driving transistor DRT and the scanning transistor SCT may be an n-type transistor or a p-type transistor.

[0140] Each of the driving transistor DRT and the scanning transistor SCT may be configured with a low temperature polysilicon transistor.

[0141] However, the present disclosure is not limited thereto, and at least one of the driving transistor DRT and the scanning transistor SCT may be formed of an oxide thin film transistor.

[0142] Since the circuit elements (especially the light emitting element ED) in each sub-pixel SP are susceptible to external moisture or oxygen, an encapsulation layer ENCAP for preventing external moisture or oxygen from penetrating into the circuit elements (especially the light emitting element ED) may be provided to cover the light emitting element ED.

[0143] Figure 4A and Figure 4B is a plan view illustrating a portion of a display panel according to an embodiment of the present disclosure.

[0144] exist Figure 4A and Figure 4B In FIG. 1 , only one channel hole CH is shown. However, this is for the sake of convenience of explanation, and the present disclosure is not necessarily limited thereto. There may be a plurality of channel holes CH, and the channel hole CH may correspond to at least a portion of the opening area OA.

[0145] For the convenience of explanation, Figure 4A and Figure 4B In the embodiment, the opening area OA may be referred to as a channel hole CH, but the opening area OA is not necessarily limited to the one-to-one corresponding channel hole CH.

[0146] refer to Figure 4A and Figure 4B , the sub-pixel SP is disposed in the display area DA, and the intermediate area IA may be located between the sub-pixel SP and the channel hole CH.

[0147] When viewed on a plane, the sub-pixels SP adjacent to the channel hole CH may be disposed to be spaced apart from each other around the channel hole CH.

[0148] like Figure 4A and Figure 4BAs shown in the plan view of FIG, the sub-pixels SP may be disposed to be spaced apart up and down around the channel hole CH, or may be disposed to be spaced apart left and right around the channel hole CH.

[0149] Each sub-pixel SP uses red light, green light or blue light emitted by a light emitting element, and Figure 4A and Figure 4B The positions of the sub-pixels SP shown in correspond to the positions of the light emitting elements, respectively.

[0150] Therefore, the fact that the sub-pixels SP are disposed to be spaced apart from each other around the channel hole CH when viewed on a plane may indicate that the light emitting elements are disposed to be spaced apart from each other around the channel hole CH when viewed on a plane.

[0151] Among the gate lines GL and the data lines DL connected to the light emitting elements of the corresponding sub-pixels SP, the gate lines GL and the data lines DL adjacent to the channel hole CH may detour the cutting line TML that is the edge of the channel hole CH.

[0152] Some of the data lines DL passing through the display area DA extend in the y direction to transmit data signals to the sub-pixels SP disposed above and below with the channel holes CH interposed therebetween, but may be as shown in FIG. Figure 4A As shown, the channel hole CH may be bypassed along the edges of the first dam portion PW1 and the second dam portion PW2 in the middle area IA, or may be as shown. Figure 4B The cutting line TML as the edge of the channel hole CH in the intermediate area IA is shown to go around the channel hole CH.

[0153] In addition, some of the gate lines GL passing through the display area DA extend in the x direction to transmit gate signals to the sub-pixels SP disposed on the left and right sides with the channel holes CH interposed therebetween, but may be as shown in FIG. Figure 4A As shown, the channel hole CH may be bypassed along the edges of the first dam portion PW1 and the second dam portion PW2 in the middle area IA, or may be as shown. Figure 4B The cutting line TML as the edge of the channel hole CH in the intermediate area IA is shown to go around the channel hole CH.

[0154] Although Figure 4A and Figure 4B The display gate line GL bypasses the channel hole CH in the intermediate area IA, but this is just an example and the present disclosure is not limited thereto.

[0155] refer to Figure 4A and Figure 4B , an outer dam OPW surrounding the display area DA may be provided in the non-display area NDA.

[0156] Figure 4A and Figure 4BThe outer side dam OPW shows an example in which the number of partition walls is two, but the number is not necessarily limited to this.

[0157] refer to Figure 4A In the intermediate area IA, at least one dam may be provided, the dam being disposed closer to the channel hole CH than the bypass portion of the data line DL.

[0158] in this regard, Figure 4A A first dam portion PW1 and a second dam portion PW2 are shown.

[0159] The first and second dam portions PW1 and PW2 may be provided to be spaced apart from each other in the intermediate area IA in a simple closed curve shape surrounding the channel hole CH.

[0160] exist Figure 4A Hereinafter, description will be made taking as an example a case where the first dam portion PW1 and the second dam portion PW2 have annular shapes.

[0161] At the same time, reference Figure 4B ,and Figure 4A Different, since there is no dam portion provided near the channel hole CH, Figure 4B The data lines DL and gate lines GL can be compared Figure 4A The data line DL and the gate line GL are disposed closer to the channel hole CH.

[0162] Since the data lines DL and the gate lines GL are disposed closer to the channel hole CH, the area of ​​the display area DA can be increased by the reduced area of ​​the intermediate area IA.

[0163] Therefore, as the display area DA increases, a larger number of sub-pixels SP may be provided.

[0164] 5A to 5D It is along Figure 4A A cross-sectional view taken along line II'.

[0165] refer to 5A to 5D , light emitting elements and transistors may be disposed on substrates PI1 and PI2 in the active area AA.

[0166] The substrates PI1 and PI2 may include a first substrate PI1 and a second substrate PI2.

[0167] The substrate light emitting layer IPD may be located between the first substrate PI1 and the second substrate PI2.

[0168] The substrate light emitting layer IPD can prevent moisture from penetrating.

[0169] A first buffer layer BUF1 may be formed on the second substrate PI2.

[0170] A light blocking layer LSL may be formed on the first buffer layer BUF1 , and a second buffer layer BUF2 may be formed on the light blocking layer LSL.

[0171] Each of the first buffer layer BUF1 and the second buffer layer BUF2 may be formed of an inorganic insulating material and may be composed of at least one insulating layer.

[0172] The light blocking layer LSL may be patterned in a photolithography process.

[0173] The light blocking layer LSL may include a light blocking pattern.

[0174] The light blocking pattern may block external light from being irradiated onto the active layer of the thin film transistor, thereby preventing photocurrent of the thin film transistor from being generated in the active region.

[0175] The active layer ACT may be formed of a semiconductor material on the second buffer layer BUF2 and may be patterned through a photolithography process.

[0176] The active layer ACT may be partially metallized by ion doping.

[0177] The metallization may be used as a jumper pattern that connects metal layers at some nodes of the circuit, thereby connecting components of the circuit.

[0178] A gate insulating layer GI may be formed on the second buffer layer BUF2 to cover the active layer ACT.

[0179] The gate insulating layer GI may be made of an inorganic insulating material.

[0180] A first storage capacitor electrode layer CAPE1 may be formed on the gate insulating layer GI.

[0181] The first storage capacitor electrode layer CAPE1 may be patterned through a photolithography process.

[0182] The first storage capacitor electrode layer CAPE1 may serve as a jumping pattern connecting the gate line, the gate electrode, the bottom electrode of the storage capacitor, the light blocking layer LSL, and the pattern of the second storage capacitor electrode layer CAPE2.

[0183] A first interlayer insulating layer ILD1 may be formed on the gate insulating layer GI to cover the first storage capacitor electrode layer CAPE1.

[0184] The second storage capacitor electrode layer CAPE2 may be formed on the first interlayer insulating layer ILD2 , and the second interlayer insulating layer ILD2 may cover the second storage capacitor electrode layer CAPE2 .

[0185] The second storage capacitor electrode layer CAPE2 may be patterned by a photolithography process.

[0186] The second storage capacitor electrode layer CAPE2 may include a metal pattern, eg, a top electrode of the storage capacitor.

[0187] The first and second interlayer insulating layers ILD1 and ILD2 may include an inorganic insulating material.

[0188] A first source drain electrode layer SD1 may be formed on the second interlayer insulating layer ILD2 , and an inorganic insulating layer PAS1 and a first planarization layer PLN1 may be stacked on the first source drain electrode layer SD1 .

[0189] The second source drain electrode layer SD2 may be formed on the first planarization layer PLN1 .

[0190] The first and second planarization layers PLN1 and PLN2 may be made of an organic insulating material that planarizes a surface.

[0191] The first source drain electrode layer SD1 may include a first electrode and a second electrode of a thin film transistor, which are connected to an active pattern of the thin film transistor through a contact hole passing through the second interlayer insulating layer ILD2 .

[0192] The data line DL and the power wiring may be implemented using the first source-drain electrode layer SD1 or the second source-drain electrode layer SD2 .

[0193] The anode electrode AND is a first electrode layer of the light emitting element ED and can be formed on the second planarization layer PLN2.

[0194] The anode electrode AND may be connected to the electrode of the driving thin film transistor through a contact hole passing through the second planarization layer PLN2 .

[0195] The anode electrode AND may be made of a transparent or semi-transparent electrode material.

[0196] The bank layer BNK may cover the anode electrode AND of the light emitting element ED.

[0197] The bank layer BNK may be formed in a pattern defining a light emitting area through which light is transferred from each sub-pixel to the outside.

[0198] The light emitting layer EL may be formed in a light emitting region of each sub-pixel defined by the bank layer BNK.

[0199] The cathode electrode CAT is a second electrode layer of the light emitting element ED, and may be formed on the entire surface of the display device 100 to cover the bank layer BNK and the light emitting layer EL.

[0200] The encapsulation layer may include inorganic encapsulation layers PAS2 and PAS3 and an organic encapsulation layer PCL therebetween.

[0201] The first inorganic encapsulating layer PAS2 may cover the cathode electrode CAT, and the organic encapsulating layer PCL may be formed on the first inorganic encapsulating layer PAS2.

[0202] The second inorganic encapsulation layer PAS3 may be formed on the organic encapsulation layer PCL.

[0203] refer to 5A to 5D In the intermediate area IA, a dummy metal layer DM having openings OPN1 and OPN3 may be formed on the inorganic insulating layer PAS1.

[0204] In the intermediate area IA, a light emitting layer EL having an opening may be formed on the dummy metal layer DM.

[0205] In the intermediate area IA, a cathode electrode CAT having openings OPN2 and OPN4 may be formed on the light emitting layer EL.

[0206] refer to Figures 5A to 5C , the openings OPN1 and OPN3 of the dummy metal layer DM may be referred to as first openings OPN1 and third openings OPN3 , and the openings OPN2 and OPN4 of the cathode electrode CAT may be referred to as second openings OPN2 and fourth openings OPN4 .

[0207] The second opening OPN2 may overlap with the first opening OPN1 , and the fourth opening OPN4 may overlap with the third opening OPN3 .

[0208] The first opening OPN1 and the third opening OPN3 may be covered by the first and second inorganic encapsulation layers PAS2 and PAS3 .

[0209] Since the formation of burrs on the cathode electrode CAT is prevented, the reliability of the display device 100 can be improved.

[0210] The organic encapsulation layer PCL may be located on the first opening OPN1 .

[0211] The first dam PW1 may be disposed between the first opening OPN1 and the third opening OPN3 .

[0212] The second dam PW2 may be disposed between the third opening OPN3 and the transmission area TA.

[0213] refer to Figures 5A to 5C , the first dam PW1 and the second dam PW2 may be located on the inorganic insulating layer PAS1 .

[0214] The first and second dams PW1 and PW2 may include a first planarization layer PLN1 on the inorganic insulating layer PAS1 , a second planarization layer PLN2 on the first planarization layer PLN1 , and a bank layer BNK on the second planarization layer PLN2 .

[0215] The first and second dams PW1 and PW2 may be covered by encapsulation layers PAS2 , PAS3 and PCL.

[0216] refer to Figure 5A As an embodiment, the dummy metal layer DM including the first opening OPN1 and the dummy metal layer DM including the third opening OPN3 may be disposed to be spaced apart from each other.

[0217] However, the present disclosure is not necessarily limited thereto. As another embodiment, refer to Figure 5B The dummy metal layer DM including the first opening OPN1 may extend in the direction of the channel hole CH to be disposed along the upper surface of the second planarization layer PLN2 and may include a third opening OPN3 between the first dam PW1 and the second dam PW2.

[0218] As another example, refer to Figure 5C , the first dam PW1 may be located in the first opening OPN1 of the dummy metal layer DM.

[0219] Since the first dam PW1 is located in the first opening OPN1 , the organic encapsulation layer PCL may overlap only a partial area of ​​the first opening OPN1 .

[0220] The dummy metal layer DM may include at least one of Ti, Al, Ag, Mg, or ITO.

[0221] As another example, refer to Figure 5D , when cutting is performed between the first dam portion PW1 and the second dam portion PW2 , the second dam portion PW2 may be removed, and only the first dam portion PW1 may remain.

[0222] That is, no additional dam portion may be provided between the first dam portion PW1 and the cutting line TML.

[0223] refer to Figures 5A to 5C The channel hole CH can be formed by cutting the first substrate PI1, the second substrate PI2, the substrate light-emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the inorganic insulating layer PAS1, the light-emitting layer EL, the cathode electrode CAT, the first inorganic encapsulation layer PAS2 and the second inorganic encapsulation layer PAS3 along the cutting line TML.

[0224] refer to Figure 5D, a channel hole CH can be formed by cutting the first substrate PI1, the second substrate PI2, the substrate light emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the inorganic insulating layer PAS1, the first inorganic encapsulation layer PAS2 and the second inorganic encapsulation layer PAS3 along the cutting line TML.

[0225] Figure 6 It is along Figure 4B A cross-sectional view taken along line II-II'.

[0226] Figure 6 The light blocking layer LSL, the first substrate PI1, the second substrate PI2, the substrate light emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the active layer ACT, the first storage capacitor electrode layer CAPE1, the second storage capacitor electrode layer CAPE2, the inorganic insulating layer PAS1, the first source drain electrode layer SD1, the second source drain electrode layer SD2, the first planarizing layer PLN1, the second planarizing layer PLN2, the anode electrode AND, the light emitting layer EL, the cathode electrode CAT, the bank layer BNK, the first inorganic encapsulation layer PAS2, the second inorganic encapsulation layer PAS3 and the organic encapsulation layer PCL can be the same as those described above. Figure 5A and Figure 5B The described light blocking layer LSL, first substrate PI1, second substrate PI2, substrate light emitting layer IPD, first buffer layer BUF1, second buffer layer BUF2, gate insulating layer GI, first interlayer insulating layer ILD1, second interlayer insulating layer ILD2, active layer ACT, first storage capacitor electrode layer CAPE1, second storage capacitor electrode layer CAPE2, inorganic insulating layer PAS1, first source drain electrode layer SD1, second source drain electrode layer SD2, first planarization layer PLN1, second planarization layer PLN2, anode electrode AND, light emitting layer EL, cathode electrode CAT, embankment layer BNK, first inorganic encapsulation layer PAS2, second inorganic encapsulation layer PAS3 and organic encapsulation layer PCL are basically the same.

[0227] refer to Figure 6 , in the intermediate area IA, the dummy metal layer DM may be located on the inorganic insulating layer PAS1 .

[0228] The light emitting layer EL may cover a region where the dummy metal layer DM overlaps with the organic encapsulation layer PCL.

[0229] In other words, the light emitting layer EL may not cover the region of the dummy metal layer DM that does not overlap with the organic encapsulation layer PCL.

[0230] The cathode electrode CAT may be disposed on a region of the dummy metal layer DM overlapping the organic encapsulation layer PCL, and the encapsulation layers PAS2 , PAS3 , and PCL may be disposed on the cathode electrode CAT.

[0231] refer to Figure 6 The second inorganic encapsulation layer PAS3 among the encapsulation layers PAS2 , PAS3 , and PCL may cover a boundary between a region of the dummy metal layer DM overlapping with the organic encapsulation layer PCL and a region of the dummy metal layer DM not overlapping with the organic encapsulation layer PCL.

[0232] When the second inorganic encapsulation layer PAS3 is designed to have a structure covering the boundary between the area where the dummy metal layer DM overlaps with the organic encapsulation layer PCL and the area where the dummy metal layer DM does not overlap with the organic encapsulation layer PCL, the area of ​​the intermediate area IA can be reduced since the dam portion in the intermediate area IA is removed, and therefore, the area of ​​the active area AA can be relatively increased.

[0233] As the area of ​​the active area AA increases, more sub-pixels SP may be disposed in the active area AA.

[0234] The dummy metal layer DM may include at least one of Ti, Al, Ag, Mg, or ITO.

[0235] refer to Figure 6 , a channel hole CH can be formed by cutting the first substrate PI1, the second substrate PI2, the substrate light emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the inorganic insulating layer PAS1 and the second inorganic encapsulation layer PAS3 along the cutting line TML.

[0236] Figure 7 It is along Figure 4A A cross-sectional view taken along line III-III'.

[0237] Figure 7 The light blocking layer LSL, the first substrate PI1, the second substrate PI2, the substrate light emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the active layer ACT, the first storage capacitor electrode layer CAPE1, the second storage capacitor electrode layer CAPE2, the inorganic insulating layer PAS1, the first source drain electrode layer SD1, the second source drain electrode layer SD2, the first planarizing layer PLN1, the second planarizing layer PLN2, the anode electrode AND, the light emitting layer EL, the cathode electrode CAT, the bank layer BNK, the first inorganic encapsulation layer PAS2, the second inorganic encapsulation layer PAS3 and the organic encapsulation layer PCL can be the same as those described above. Figure 5Aand Figure 5B The described light blocking layer LSL, first substrate PI1, second substrate PI2, substrate light emitting layer IPD, first buffer layer BUF1, second buffer layer BUF2, gate insulating layer GI, first interlayer insulating layer ILD1, second interlayer insulating layer ILD2, active layer ACT, first storage capacitor electrode layer CAPE1, second storage capacitor electrode layer CAPE2, inorganic insulating layer PAS1, first source drain electrode layer SD1, second source drain electrode layer SD2, first planarization layer PLN1, second planarization layer PLN2, anode electrode AND, light emitting layer EL, cathode electrode CAT, embankment layer BNK, first inorganic encapsulation layer PAS2, second inorganic encapsulation layer PAS3 and organic encapsulation layer PCL are basically the same.

[0238] refer to Figure 7 , a third buffer layer BUF3 may be provided on the second inorganic encapsulation layer PAS3.

[0239] A plurality of touch electrodes TE may be included on the third buffer layer BUF3 and may include a sensor metal TSM and a bridge metal BRG to form the plurality of touch electrodes TE.

[0240] In the embodiment of the present disclosure, the sensor metal TSM is also referred to as a sensor metal layer TSM, and the bridge metal BRG is also referred to as a bridge metal layer BRG.

[0241] refer to Figure 7 , a third interlayer insulating layer ILD3 may be disposed on the third buffer layer BUF3 , and a capping layer OC may be disposed on the third interlayer insulating layer ILD3 .

[0242] The bridge metal BRG may be disposed between the third buffer layer BUF3 and the third interlayer insulating layer ILD3 , and the sensor metal TSM may be disposed between the third interlayer insulating layer ILD3 and the overcoat layer OC.

[0243] Each of the plurality of touch electrodes TE may be configured with a sensor metal TSM.

[0244] Each of the plurality of touch electrodes TE may be a mesh electrode having a plurality of openings.

[0245] The plurality of touch electrodes TE may include first touch electrodes TE1 and second touch electrodes TE2.

[0246] The sensor metal TSM included in the first touch electrode TE1 may be electrically connected through the bridge metal BRG.

[0247] That is, the sensor metals TSM spaced apart from each other may be electrically connected by the bridge metal BRG to constitute one first touch electrode TE1.

[0248] A bridge metal BRG may be disposed on the third buffer layer BUF3 , and a third interlayer insulating layer ILD3 may be disposed on the bridge metal BRG.

[0249] The sensor metal TSM may be disposed on the third interlayer insulating layer ILD3 .

[0250] A portion of the sensor metal TSM may be connected to the corresponding bridge metal BRG through the hole of the third interlayer insulating layer ILD3 .

[0251] refer to Figure 7 , the sensor metal TSM and the bridge metal BRG can be set not to overlap with the light emitting element ED.

[0252] The sensor metal TSM and the bridge metal BRG may overlap with the bank layer BNK.

[0253] A plurality of sensor metals TSM may constitute a touch electrode TE, may be arranged in a grid form, and may be electrically connected.

[0254] A portion of the sensor metal TSM and another portion of the sensor metal TSM may be electrically connected through the bridge metal BRG to constitute one touch electrode TE.

[0255] The cover layer OC may be provided to cover the sensor metal TSM and the bridge metal BRG.

[0256] refer to Figure 7 , the touch line TL may electrically connect the touch electrode TE and the touch pad TP.

[0257] The touch line TL may include at least one of a sensor metal TSM and a bridge metal BRG.

[0258] When the display panel 110 is a type including a touch sensor, the touch line TL may extend along the outer inclined surface SLP_ENCAP of the second inorganic encapsulation layer PAS3 and may extend over the outer dam OPW to the touch pad TP provided in the non-display area NDA.

[0259] The outer dam OPW may include two partition walls surrounding the outside of the display area DA, but is not limited thereto.

[0260] The outer dam OPW is provided in the non-display area NDA.

[0261] refer to Figure 7 ,because 5A to 5D The dummy metal layer DM is disposed between the display area DA and the outer dam portion OPW, and thus a structure in which the light emitting layer EL is cut using a laser may be formed, thereby ensuring reliability, but the present disclosure is not limited thereto.

[0262] Alternatively, refer to Figure 7 ,because Figure 6 The dummy metal layer DM is disposed under the outer dam OPW, and thus all or a portion of the outer dam OPW may be removed using a laser, thereby reducing the area of ​​the non-display area NDA and increasing the area of ​​the display area DA.

[0263] As the area of ​​the display area DA increases, more sub-pixels SP may be disposed in the display area DA.

[0264] Figure 8 yes Figure 5A An enlarged cross-sectional view of portion A.

[0265] Figure 8 The first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the first planarization layer PLN1, the second planarization layer PLN2, the bank layer BNK, the dummy metal layer DM, the light emitting layer EL, the cathode electrode CAT, the first inorganic encapsulation layer PAS2 and the organic encapsulation layer PCL may be the same as those described above. Figure 5A The described first interlayer insulating layer ILD1, second interlayer insulating layer ILD2, first planarization layer PLN1, second planarization layer PLN2, bank layer BNK, dummy metal layer DM, light emitting layer EL, cathode electrode CAT, first inorganic encapsulation layer PAS2 and organic encapsulation layer PCL are basically the same.

[0266] refer to Figure 8 , the light emitting layer EL may include a fifth opening OPN5 overlapping the first opening OPN1 .

[0267] The cathode electrode CAT may include a second opening OPN2 overlapping with the fifth opening OPN5 .

[0268] Figures 9A to 9C It shows Figure 4A A plan view of at least one dam portion shown in FIG.

[0269] Figures 9A to 9C The first dam portion PW1 and the second dam portion PW2 can be the same as those in the reference Figure 4A The first dam portion PW1 and the second dam portion PW2 described are substantially identical.

[0270] also, Figures 9A to 9C The dummy metal layer DM can be used with the reference Figure 5A The described dummy metal layers DM are basically the same.

[0271] refer to Figures 9A to 9C , the first dam portion PW1 and the second dam portion PW2 may be provided in a simple closed curve shape surrounding the channel hole CH to be spaced apart from each other in the intermediate area IA.

[0272] Figure 9A and Figure 9C It is shown that the first dam portion PW1 and the second dam portion PW2 are provided to be spaced apart from each other in an annular shape surrounding the annular channel hole CH.

[0273] Figure 9B It is shown that the first dam portion PW1 and the second dam portion PW2 are provided to be spaced apart from each other in a simple closed curve shape, which surround the channel hole CH having a simple closed curve shape.

[0274] refer to Figure 9A and Figure 9B , the first opening OPN1 may be located between the first dam portion PW1 and the second dam portion PW2 .

[0275] The second dam PW2 may be located between the first opening OPN1 and the third opening OPN3 .

[0276] refer to Figure 9C , the second dam portion PW2 may be located within the first opening OPN1 .

[0277] 10A to 10C is a cross-sectional view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0278] 10A to 10C As an example, a method for forming Figure 5A The process of local area of ​​the display panel.

[0279] refer to Figure 10A , in the intermediate area IA, the dummy metal layer DM may be disposed between the inorganic insulating layer PAS1 and the light emitting layer EL.

[0280] The dummy metal layer DM may be disposed between the active area AA and the first dam PW1 , or between the first dam PW1 and the second dam PW2 .

[0281] refer to Figure 10B , a laser having a pulse width smaller than the width of the dummy metal layer DM may be irradiated to the lower side of the dummy metal layer DM.

[0282] The width of the dummy metal layer DM should be greater than the pulse width of the laser so that the dummy metal layer DM suppresses the reaction between the laser and the cathode electrode CAT, thereby reducing foreign matter generated during processing of the cathode electrode CAT and suppressing burrs formed on the cathode electrode CAT.

[0283] refer to Figure 10C , when irradiating laser, a display panel can be manufactured without forming burrs on the cathode electrode CAT, as Figure 5A shown.

[0284] Figures 11A to 11C is a plan view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0285] refer to Figure 11A , the dummy metal layer DM may be provided in a ring shape along the first dam portion PW1 and the second dam portion PW2 .

[0286] When a laser having a pulse width smaller than the width of the dummy metal layer DM is irradiated, the dummy metal layer DM having the first opening OPN1 and the third opening OPN3 may be formed.

[0287] refer to Figure 11B , the dummy metal layer DM may be disposed in a ring shape along the first dam PW1 and the second dam PW, and at least one ring-shaped dummy metal layer DM may be disposed to be spaced apart from the dummy metal layer DM.

[0288] That is, the at least one dummy metal layer DM may be island-shaped and have a ring shape.

[0289] refer to Figure 11B By irradiating laser light along at least one island-shaped and ring-shaped dummy metal layer DM, the dummy metal layer DM having the first opening OPN1 and the third opening OPN3 may be formed.

[0290] However, the arrangement of the island-shaped and ring-shaped dummy metal layer DM is not limited thereto, and as shown in FIG. Figure 11C As shown, at least one dummy metal layer DM may be disposed to be spaced apart from the dummy metal layer DM and the first dam PW1 .

[0291] 12A to 12D is a cross-sectional view simply illustrating a process for forming a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0292] 12A to 12D It can be shown that the Figure 6 The process of local area of ​​the display panel.

[0293] refer to Figure 12A , the dummy metal layer DM may be located between the first planarization layer PLN1 of the first dam PW1 and the inorganic insulating layer PAS1 .

[0294] refer to Figure 12B , the organic encapsulation layer PCL may be formed on the first inorganic encapsulation layer PAS2 to overlap with at least a portion of the dummy metal layer DM.

[0295] refer to Figure 12CAfter forming the organic encapsulation layer PCL, laser may be irradiated to the lower side of the dummy metal layer DM before forming the second inorganic encapsulation layer PAS3 to remove the first dam PW1 on the dummy metal layer DM.

[0296] refer to Figure 12D After removing the first dam PW1 on the dummy metal layer DM using laser, a second inorganic encapsulation layer PAS3 may be formed to cover a boundary between an area where the dummy metal layer DM overlaps with the organic encapsulation layer PCL and an area where the dummy metal layer DM does not overlap with the organic encapsulation layer PCL.

[0297] After forming the second inorganic encapsulation layer PAS3, in order to form the channel hole CH, the first substrate PI1, the second substrate PI2, the substrate light-emitting layer IPD, the first buffer layer BUF1, the second buffer layer BUF2, the gate insulating layer GI, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the inorganic insulating layer PAS1 and the second inorganic encapsulation layer PAS3 can be cut along the cutting line TML.

[0298] refer to 12A to 12D Since the first dam portion PW1 in the intermediate area IA is removed, the area of ​​the intermediate area IA may be reduced, and thus the area of ​​the active area AA may be relatively increased.

[0299] A brief description of the embodiments of the present disclosure described above is as follows.

[0300] According to an embodiment of the present disclosure, a display device may include: a substrate, the substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the intermediate area on the substrate; a first metal layer located on the insulating layer and including at least one first opening, the at least one first opening being located in the intermediate area; a second metal layer located on the first metal layer in the intermediate area and including at least one second opening, the at least one second opening being arranged in an area including an area overlapping with the at least one first opening; and an organic encapsulation layer located on the insulating layer and at least partially overlapping with the first opening.

[0301] In a display device according to an embodiment of the present disclosure, an inorganic encapsulation layer may be located on an organic encapsulation layer, the intermediate region may include a first intermediate region overlapping with the organic encapsulation layer and a second intermediate region not overlapping with the organic encapsulation layer, and the display device may further include a first metal layer located on the insulating layer and including at least one third opening, the at least one third opening being located in the second intermediate region; and a second metal layer located on the first metal layer in the second intermediate region and including at least one fourth opening, the at least one fourth opening being arranged in an area including an area overlapping with the at least one third opening.

[0302] In a display device according to an embodiment of the present disclosure, the display device may further include a dam layer located on the insulating layer and the first metal layer and covering at least a portion of the first metal layer; and a light-emitting layer located on the dam layer and the first metal layer and including at least one fifth opening, wherein the at least one fifth opening is located in an area including an area overlapping with the at least one first opening.

[0303] In the display device according to the embodiment of the present disclosure, the display device may further include a dam portion located between the first opening and the third opening, the dam portion being located on the insulating layer and including a planarization layer.

[0304] In the display device according to the embodiment of the present disclosure, the first metal layer may cover the planarization layer.

[0305] In the display device according to the embodiment of the present disclosure, the organic encapsulation layer may overlap with a portion of the first opening.

[0306] In the display device according to the embodiment of the present disclosure, the first metal layer may include at least one of Ti, Al, Ag, Mg, or ITO.

[0307] In the display device according to the embodiment of the present disclosure, the second metal layer may include at least one of a transparent conductive oxide or a semi-transparent metal.

[0308] According to an embodiment of the present disclosure, a display device may include: a substrate including an opening area, a display area surrounding the opening area, an intermediate area between the opening area and the display area, and an external area surrounding the outside of the display area; at least one first dam portion located on the substrate and arranged in the external area; and at least one second dam portion located on the substrate and arranged in the intermediate area, the at least one second dam portion including a dummy electrode located on the same layer as a cathode electrode arranged in the display area.

[0309] In a display device according to an embodiment of the present disclosure, the display device may further include: an encapsulation layer, which is located on a substrate and includes a first inorganic encapsulation layer located on the substrate, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer, wherein the intermediate area includes a first part located between the display area and the second dam portion and a second part located between the second dam portion and the opening area, and wherein the organic encapsulation layer covers at least a part of the first part and does not cover the second part.

[0310] In the display device according to the embodiment of the present disclosure, the third dam may be provided in the first portion, and the organic encapsulating layer may cover between the display area and the third dam, and not cover between the third dam and the second dam.

[0311] In the display device according to the embodiment of the present disclosure, the second dam may have a simple closed curve shape.

[0312] In the display device according to the embodiment of the present disclosure, the second dam may have a ring shape.

[0313] According to an embodiment of the present disclosure, a display device may include: a substrate including an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the intermediate area on the substrate; an encapsulation layer located on the insulating layer, located in the intermediate area, and including a first portion including an organic encapsulation layer and a second portion not including an organic encapsulation layer; a first metal layer located in the first portion and between the insulating layer and the organic encapsulation layer; and a second metal layer located in the first portion and between the first metal layer and the organic encapsulation layer.

[0314] In the display device according to the embodiment of the present disclosure, the display device may further include a light emitting layer located in the first portion, on the insulating layer, and covering the first metal layer.

[0315] In the display device according to an embodiment of the present disclosure, the display device may further include an inorganic encapsulation layer located in the first portion and on the organic encapsulation layer, wherein the inorganic encapsulation layer covers the organic encapsulation layer located in the first portion and a boundary between the first portion and the second portion.

[0316] In the display device according to the embodiment of the present disclosure, the first metal layer may include at least one of Ti, Al, Ag, Mg, or ITO.

[0317] The above description is provided to enable those skilled in the art to make and use the technical concepts of the present disclosure, and is provided in the context of specific applications and their requirements. Those skilled in the art will readily appreciate various modifications, additions, and substitutions to the described embodiments, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

Claims

1. A display device comprising: a substrate comprising an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the middle region on the substrate; a first metal layer located on the insulating layer and comprising at least one first opening, wherein the at least one first opening is located in the middle region; a second metal layer located on the first metal layer in the middle region and including at least one second opening disposed in a region including a region overlapping the at least one first opening; as well as An organic encapsulation layer is located on the insulating layer and at least partially overlaps the at least one first opening.

2. The display device according to claim 1, in, The inorganic encapsulation layer is located on the organic encapsulation layer, The middle region includes a first middle region overlapping with the organic encapsulation layer and a second middle region not overlapping with the organic encapsulation layer, and in, The first metal layer further includes at least one third opening, the at least one third opening being located in the second middle region; and The second metal layer further includes at least one fourth opening in the second middle region, the at least one fourth opening being disposed in a region including a region overlapping with the at least one third opening.

3. The display device according to claim 1, further comprising: a bank layer located on the insulating layer and the first metal layer and covering at least a portion of the first metal layer; as well as A light emitting layer is located on the bank layer and the first metal layer and includes at least one fifth opening located in a region including a region overlapping the at least one first opening.

4. The display device according to claim 2, further comprising: The dam portion is located between the at least one first opening and the at least one third opening, is located on the insulating layer, and includes a planarization layer.

5. The display device according to claim 4, wherein The first metal layer covers the planarization layer. The display device according to claim 1 , wherein: The organic encapsulating layer overlaps a portion of the at least one first opening.

7. The display device according to claim 1, wherein The first metal layer includes at least one of Ti, Al, Ag, Mg or ITO.

8. The display device according to claim 1, wherein The second metal layer includes at least one of a transparent conductive oxide or a semi-transparent metal.

9. A display device comprising: a substrate comprising an opening area, a display area surrounding the opening area, an intermediate area between the opening area and the display area, and an outer area surrounding an outer side of the display area; at least one first dam portion located on the substrate and disposed in the outer region; as well as At least one second dam is located on the substrate, is disposed in the middle region, and includes a dummy electrode located in the same layer as a cathode electrode disposed in the display region.

10. The display device according to claim 9, further comprising: an encapsulation layer located on the substrate and comprising a first inorganic encapsulation layer located on the substrate, an organic encapsulation layer located on the first inorganic encapsulation layer, and a second inorganic encapsulation layer located on the organic encapsulation layer, The middle area includes a first portion located between the display area and the second dam portion and a second portion located between the second dam portion and the opening area. The organic encapsulation layer covers at least a portion of the first portion and does not cover the second portion.

11. The display device according to claim 10, wherein: A third dam portion is provided in the first portion, and The organic encapsulating layer covers a portion between the display region and the third dam portion, and does not cover a portion between the third dam portion and the at least one second dam portion.

12. The display device according to claim 10, wherein: The at least one second dam portion has a closed curve shape.

13. The display device according to claim 12, wherein: The at least one second dam has a ring shape.

14. A display device comprising: a substrate comprising an opening area, a display area surrounding the opening area, and an intermediate area between the opening area and the display area; an insulating layer located in the middle region on the substrate; an encapsulation layer located on the insulating layer and in the middle region, and including a first portion and a second portion, wherein the first portion includes an organic encapsulation layer, and the second portion does not include the organic encapsulation layer; a first metal layer located in the first portion and between the insulating layer and the organic encapsulation layer; as well as A second metal layer is located in the first portion and between the first metal layer and the organic encapsulation layer.

15. The display device according to claim 14, further comprising: The light emitting layer is located in the first portion, on the insulating layer, and covers the first metal layer.

16. The display device according to claim 15, further comprising: an inorganic encapsulation layer located in the first portion and on the organic encapsulation layer, The inorganic encapsulation layer covers the organic encapsulation layer in the first portion and a boundary between the first portion and the second portion.

17. The display device according to claim 14, wherein: The first metal layer includes at least one of Ti, Al, Ag, Mg or ITO.

Images