Floating point atoms using integer hardware

Abstract

This disclosure provides systems, apparatus, apparatuses, and methods, including computer programs encoded on a storage medium, for floating point number minimum / maximum atoms using integer hardware. A data processor may obtain a first indication of a floating-point number associated with a floating-point operation. The data processor may select a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating-point number or the floating-point operation, where the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional patent application serial number 18 / 162,660, entitled “FLOATING POINT ATOMICS USING INTEGER HARDWARE,” filed on January 31, 2023, which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates generally to processing systems and, more particularly, to one or more techniques for data processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize the GPU during execution. The display processor can be configured to convert digital information received from the CPU into analog values ​​and can issue commands to the display panel to display visual content. A device that provides content for visual presentation on a display can utilize a CPU, a GPU, and / or a display processor.

[0005] Current hardware may not include support for floating-point atomics. Improved techniques for floating-point atomic support are needed. Summary of the Invention

[0006] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects and is neither intended to identify key or critical elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be presented later.

[0007] In one aspect of the present disclosure, a method, computer-readable medium, and apparatus for data processing are provided. The apparatus includes a memory; and at least one processor coupled to the memory and configured, based at least in part on information stored in the memory, to: obtain a first indication of a floating-point number associated with a floating-point operation; and select a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating-point number or the floating-point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

[0008] To accomplish the foregoing and related objectives, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of but a few of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0010] Figure 2 An example graphics processor (eg, a graphics processing unit (GPU)) in accordance with one or more techniques of this disclosure is illustrated.

[0011] Figure 3 Example images or surfaces are illustrated in accordance with one or more techniques of this disclosure.

[0012] Figure 4 is a diagram illustrating example aspects of signed integers, unsigned integers, and floating-point numbers in accordance with one or more techniques of this disclosure.

[0013] Figure 5 is a diagram illustrating example aspects of an atomic swap operation and an atomic compare-and-swap operation in accordance with one or more techniques of this disclosure.

[0014] Figure 6 is a diagram illustrating an example atomic unit in a GPU, in accordance with one or more techniques of this disclosure.

[0015] Figure 7 is a diagram illustrating example aspects of atomic maximum and atomic minimum operations in accordance with one or more techniques of this disclosure.

[0016] Figure 8 is a diagram illustrating example aspects of a floating-point atomic maximum operation and a floating-point atomic minimum operation, in accordance with one or more techniques of this disclosure.

[0017] Figure 9 is a call flow diagram illustrating example communications between a graphics processor and graphics processor components in accordance with one or more techniques of this disclosure.

[0018] Figure 10 is a flowchart of an example method of data processing according to one or more techniques of this disclosure.

[0019] Figure 11 is a flowchart of an example method of data processing according to one or more techniques of this disclosure. DETAILED DESCRIPTION

[0020] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings of this article, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functionality, or structure and functionality in addition to or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0021] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of various aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or objective. On the contrary, various aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and drawings merely illustrate and do not limit this disclosure, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0022] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SOCs), baseband processors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described in this disclosure. One or more processors in a processing system may execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software may be broadly understood to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc.

[0024] The term "application" may refer to software. As described herein, one or more technologies may refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute the application. For example, an application may be described as including code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0025] In one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented in software, the functions can be stored or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, a combination of the above-mentioned types of computer-readable media, or any other medium that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0026] As used herein, instances of the term "content" may refer to "graphics content," "image," and the like, regardless of whether the term is used as an adjective, noun, or other part of speech. In some examples, as used herein, the term "graphics content" may refer to content generated by one or more processes of a graphics processing pipeline. In other examples, as used herein, the term "graphics content" may refer to content generated by a processing unit configured to perform graphics processing. In yet other examples, as used herein, the term "graphics content" may refer to content generated by a graphics processing unit.

[0027] The GPU may utilize floating-point atomic operations (e.g., a minimum / maximum function for emulating depth comparisons with a floating-point frame buffer) to facilitate the display of graphical content. For example, the GPU may be configured to access and / or modify shared data simultaneously via different threads. In one example, a first thread of the GPU may read a 32-bit integer at a first time instance and update the 32-bit integer with an incrementing (or decrementing) value at a second time instance occurring after the first time instance. However, a second thread of the GPU may read the 32-bit integer at a third time instance occurring between the first time instance and the second time instance and then update the 32-bit integer with an incrementing (or decrementing) value at a fourth time instance after the second time instance. Since the 32-bit integer has not yet been updated at the third time instance, the second thread may only see the initial value of the 32-bit integer, resulting in the final value being incremented only once, rather than twice as expected. To solve this problem, the GPU can utilize atomic operations so that the 32-bit integer cannot be read between the first time instance (i.e., the time when the modification of the 32-bit integer begins) and the second time instance (i.e., the time when the modification of the 32-bit integer ends). The second thread can also utilize atomic operations so that the 32-bit integer cannot be read between the third time instance and the fourth time instance. Therefore, regardless of the order in which the threads execute, the initial value can be incremented twice. Some GPUs may not be configured with hardware support for floating-point atomic operations. In contrast, some GPUs may be configured with hardware support for signed integer atomic operations and unsigned integer atomic operations.

[0028] Various techniques related to emulating floating-point atomic operations using integer hardware are described herein. In one example, a device (e.g., a GPU) obtains a first indication of a floating-point number associated with a floating-point operation. The device selects a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating-point number or the floating-point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition. With respect to the above-mentioned features, the device can use integer hardware to emulate support for floating-point maximum / minimum operations. Furthermore, the above-mentioned features can accommodate non-monotonicity of floating-point numbers at zero crossings.

[0029] The examples described herein may relate to the use and functionality of a graphics processing unit (GPU). As used herein, a GPU may be any type of graphics processor, and a graphics processor may be any type of processor designed or configured to process graphical content. For example, a graphics processor or GPU may be a specialized electronic circuit designed to process graphical content. As an additional example, a graphics processor or GPU may be a general-purpose processor configured to process graphical content.

[0030] Figure 11 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. Content generation system 100 includes device 104. Device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a system-on-chip (SoC). Device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, device 104 may include multiple components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). Display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays, which may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In yet another example, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to the other device. In some aspects, this is referred to as split rendering.

[0031] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing using graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a processor that may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120 and then display these frames via one or more displays 131. While the processor in example content generation system 100 is configured as display processor 127, it should be understood that display processor 127 is one example of a processor and that other types of processors, controllers, etc. may be used in place of display processor 127. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0032] Memory external to processing unit 120 and content encoder / decoder 122, such as system memory 124, can be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 can be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 can be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 can be communicatively coupled to internal memory 121 via the bus or via a different connection.

[0033] The content encoder / decoder 122 can be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 can be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 can be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 can be configured to encode or decode any graphics content.

[0034] The internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, the internal memory 121 or system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, magnetic data media, optical storage media, or any other type of memory. According to some examples, the internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier or propagating signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0035] The processing unit 120 may be a CPU, a GPU, a GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In another example, the processing unit 120 may be present on a graphics card installed in a port of the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic elements, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute the instructions in the hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123) and may use one or more processors to execute the instructions in the hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0037] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to the device 104. In addition, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, and / or position information. The transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which information may include a request for content. The receiver 128 and transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any of the receiving functions and / or transmitting functions described herein with respect to the device 104.

[0038] Reference again Figure 1 In some aspects, the processing unit 120 may include an atomic simulator 198 configured to: obtain a first indication of a floating point number associated with a floating point operation; and select a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating point number or the floating point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition. Although the following description may focus on data processing, the concepts described herein may be applicable to other similar processing techniques.

[0039] Devices such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, base station, user equipment, client device, station, access point, computer (such as, personal computer, desktop computer, laptop computer, tablet computer, computer workstation or mainframe computer), final product, device, phone, smart phone, server, video game platform or console, handheld device (such as, portable video game device or personal digital assistant (PDA)), wearable computing device (such as, smart watch, augmented reality device or virtual reality device), non-wearable device, display or display device, TV, TV set-top box, intermediate network device, digital media player, video streaming device, content streaming device, vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., GPU), but in other embodiments, other components (e.g., CPU) that conform to the disclosed embodiments may be used to perform.

[0040] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shader programs, or constant data, which can adjust how the graphics context is processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, there may be one or more bits that indicate which workload belongs to the context register. In addition, multiple functions or programs can be run simultaneously and / or in parallel. For example, a function or program can describe an operation, such as a color mode or color format. Thus, the context register can define multiple states of the GPU.

[0041] Context states can be used to determine how individual processing units (e.g., vertex fetchers (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate and / or in which mode a processing unit operates. To do this, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline based on context register definitions of the mode or state, such as vertex or pixel workloads. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to aggregate vertices. Because these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changed mode or state.

[0042] Figure 2 An exemplary GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, the GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache memory (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, an L2 cache memory (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 through 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 through 238 are merely examples, and any combination or order of processing units may be used by the GPU in accordance with the present disclosure. GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0043] like Figure 2 As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to parse the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then transmit context register packet 260 or draw call packet 212 to a processing unit or block in the GPU via separate paths. Furthermore, command buffer 250 can alternate between different states of context registers and draw calls. For example, the command buffer can simultaneously store the following information: context registers for context N, draw calls for context N, context registers for context N+1, and draw calls for context N+1.

[0044] A GPU can render an image in a variety of different ways. In some cases, a GPU may use direct rendering and / or tile rendering to render an image. In a tile rendering GPU, an image can be divided or separated into different parts or tiles. After the image is divided, each part or tile can be rendered separately. A tile rendering GPU can divide a computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects of tile rendering, the image can be divided into different bins or tiles during a binning pass. In some aspects, during the binning pass, a visibility stream can be constructed, in which visible primitives or draw calls can be identified. A rendering pass can be performed after the binning pass. In contrast to tile rendering, direct rendering does not divide the frame into smaller bins or tiles. In contrast, in direct rendering, the entire frame is rendered at once (i.e., there is no binning pass). Additionally, some types of GPUs may allow both tile rendering and direct rendering (e.g., flexible rendering).

[0045] In some aspects, the GPU can apply a drawing or rendering process to different bins or tiles. For example, the GPU can render for a bin and perform all drawing for the primitives or pixels within the bin. During the bin-based rendering process, a render target can be located in the GPU's internal memory (GMEM). In some cases, after rendering for a bin, the contents of the render target can be moved to system memory, and the GMEM can be freed to render the next bin. Additionally, the GPU can render for another bin and perform drawing for the primitives or pixels within that bin. Thus, in some aspects, there may be a small number of bins (e.g., four bins) that cover all drawing in a surface. Furthermore, the GPU can loop through all drawing within a bin but only perform drawing for visible draw calls, i.e., draw calls that contain visible geometry. In some aspects, a visibility stream can be generated, for example, during the binning process, to determine visibility information for each primitive in an image or scene. For example, this visibility stream can identify whether a primitive is visible. In some aspects, this information can be used to remove invisible primitives, such that, for example, they are not rendered in a rendering pass. Additionally, at least some of the primitives identified as visible may be rendered during the rendering process.

[0046] In some aspects of tile rendering, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, such as a binning, visibility or bin visibility pass and a rendering or bin rendering pass. During the visibility pass, the GPU can input the rendering workload, record the position of the primitives or triangles, and then determine which primitives or triangles fall into which bin or region. In some aspects of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pass, the GPU can input the visibility stream and process one bin or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. Therefore, the visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce unnecessary workload of processing or rendering invisible primitives or triangles.

[0047] In some aspects, during the visibility process, certain types of primitive geometry may be processed, such as only positioned geometry. Additionally, primitives or triangles may be sorted into different bins or regions based on their position or positioning. In some cases, sorting primitives or triangles into different bins may be performed by determining visibility information for those primitives or triangles. For example, the GPU may determine visibility information for each primitive in each bin or region or write it to, for example, system memory. This visibility information may be used to determine or generate a visibility stream. During rendering, the primitives in each bin may be rendered separately. In these cases, the visibility stream may be retrieved from memory and used to remove primitives that are not visible to that bin.

[0048] Some aspects of the GPU or GPU architecture may provide a number of different options for rendering (e.g., software rendering and hardware rendering). In software rendering, the driver or CPU may process each viewport by Figure 1 times to copy the entire frame geometry. Additionally, some different states may change depending on the view. Thus, in software rendering, the software may copy the entire workload by changing some of the states that may be used to render for each viewpoint in the image. In some aspects, there may be an increased amount of overhead because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for copying or processing the geometry for each viewpoint in the image. Thus, the hardware may manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0049] Figure 3 An image or surface 300 is illustrated, including a plurality of primitives divided into a plurality of bins, in accordance with one or more techniques of this disclosure. Figure 3As shown, image or surface 300 includes region 302, which includes primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided or placed into different bins, such as bins 310, 311, 312, 313, 314, and 315. Figure 3 An example of using multiple viewpoints for tile rendering of primitives 321-324 is shown. For example, primitives 321-324 are in a first viewpoint 350 and a second viewpoint 351. Therefore, GPU processing or rendering of image or surface 300 including region 302 may utilize multi-viewpoint or multi-view rendering.

[0050] As indicated herein, a GPU or graphics processor can use a tile rendering architecture to reduce power consumption or save memory bandwidth. As further described above, this rendering method can divide a scene into multiple bins and include a visibility pass that identifies visible triangles in each bin. Thus, in tile rendering, the entire screen can be divided into multiple bins or tiles. The scene can then be rendered multiple times, for example, once or multiple times for each bin.

[0051] In various aspects of graphics rendering, some graphics applications may render to a single target (i.e., a render target) one or more times. For example, in graphics rendering, a frame buffer on system memory may be updated multiple times. A frame buffer may be a portion of memory or random access memory (RAM) (e.g., containing a bitmap or storage) that helps store display data for the GPU. A frame buffer may also be a memory buffer that contains a complete frame of data. Additionally, a frame buffer may be a logical buffer. In some aspects, updating the frame buffer may be performed in bin or tile rendering, where, as described above, a surface is divided into multiple bins or tiles, and each bin or tile may then be rendered separately. Furthermore, in tile rendering, the frame buffer may be divided into multiple bins or tiles.

[0052] As indicated herein, in some aspects, such as in bin or tile rendering architectures, frame buffers may have data stored or written to them repeatedly, for example, when rendering from different types of memory. This may be referred to as resolving and unresolving frame buffers or system memory. For example, when storing or writing to one frame buffer and then switching to another frame buffer, the data or information on the frame buffer may be resolved from GMEM at the GPU to system memory, i.e., memory in double data rate (DDR) RAM or dynamic RAM (DRAM).

[0053] In some aspects, system memory can also be system-on-chip (SoC) memory or another chip-based memory for storing data or information, such as on a device or smartphone. System memory can also be physical data storage shared by the CPU and / or GPU. In some aspects, system memory can be, for example, a DRAM chip on a device or smartphone. Thus, SoC memory can be a chip-based way to store data.

[0054] In some aspects, GMEM can be on-chip memory at the GPU, which can be implemented by static RAM (SRAM). In addition, GMEM can be stored on a device (e.g., a smartphone). As indicated herein, data or information can be transferred between system memory or DRAM and GMEM, for example, at the device. In some aspects, system memory or DRAM can be located at the CPU or GPU. In addition, data can be stored in DDR or DRAM. In some aspects, such as in box or tile rendering, a small portion of memory can be stored at the GPU, for example, in GMEM. In some cases, storing data at GMEM may utilize a larger processing workload and / or consume more power than storing data at the frame buffer or system memory.

[0055] Figure 4 4 is a diagram illustrating example aspects of signed integers, unsigned integers, and floating-point numbers. A GPU (or another device) may store data as signed integers 402, unsigned integers 408, and / or floating-point numbers 412. In one example, memory or registers of the GPU may store signed integers 402, unsigned integers 408, and / or floating-point numbers 412. Furthermore, the GPU's hardware may be configured to perform operations on signed integers 402, unsigned integers 408, and / or floating-point numbers 412.

[0056] Signed integer 402 may represent a negative integer, a zero integer, or a positive integer. Thus, signed integer 402 may include a sign bit 404 and data bits 406, where sign bit 404 may indicate whether signed integer 402 is positive or negative. For example, if signed integer 402 is positive, sign bit 404 may be "0," and if signed integer 402 is negative, sign bit 404 may be "1."

[0057] Signed integers 402 can be represented using two's complement notation. In this scheme, a positive number of bit length (n-1) can be represented by adding a 0 as the new most significant bit (MSB) and creating a multi-bit length of n. An equivalent negative number can be created by adding a 0 as the new MSB and creating a multi-bit length of n, reversing each of the n bits, and adding a 1 bit to the resulting number and truncating it to the bit length of n. In this scheme, the MSB can be 0 for positive numbers and 1 for negative numbers, so the MSB can be used as a sign bit 404. In this scheme, an encoding in which a 1 bit is followed by a 0 bit of the MSB (an encoding that is not otherwise used) can be used to encode a negative number of (2**n). Positive values ​​of (2**n) may not be encodable.

[0058] Unsigned integer 408 may represent a zero integer or a positive integer. Unsigned integer 408 may include data bits 410 representing a zero integer or a positive integer. In one example, data bits 410 may include 32 bits. In this example, data bits 410 may represent an integer in the range of [0 to 4,294,967,295].

[0059] Floating point number 412 may be associated with a decimal point that can be moved (ie, "floated"). Floating point number 412 may include mantissa 414, sign 416, and exponent 418. Generally speaking, floating point number 412 may be generated by s*1.ax base b-offset , where s is the sign 416 (0 represents +1.0 and 1 represents -1.0), "a" is the mantissa 414, and "b" is the exponent 418. In one example, the mantissa 414 and the exponent 418 may be unsigned integers, the base may be assumed to be fixed at "2", and the offset may be assumed to be fixed at "127". In one example, +1.0*1.a×2 b-127 It can be encoded by concatenating the bits of "s", "b" and "a". If "b" is "0", a number can be represented by 0.a*2 -127 , there is no leading '1' before 'a'. This may be called a "denormalized number". Note that if a and b are both '0', this may represent the value 0.0. Since 's' may still be '0' or '1', both '+0.0' and '-0.0' may be encoded in this case. In one example, the floating point number 412 may be between + / - (2–2 -23 )×2 127 The range is approximately equal to + / -3.4028235×10 38 .

[0060] Figure 55 is a diagram 500 illustrating example aspects of an atomic swap operation 502 and an atomic compare-and-swap operation 504. A GPU (or another device) may be configured to access and / or modify shared data simultaneously via different threads. In one example, a first thread of a GPU may update (i.e., change bits) the first sixteen bits of a 32-bit integer at a first time instance, and update the last sixteen bits of the 32-bit integer at a second time instance that occurs after the first time instance. However, a second thread of the GPU may read the 32-bit integer at a third time instance that occurs between the first and second time instances. Because the 32-bit integer has not yet been fully updated at the third time instance, the second thread may obtain an incorrect value for the 32-bit integer.

[0061] To address the above issues, a GPU (or another device) may be configured with support for atomic operations. Generally speaking, an atomic operation may refer to an operation that reads a value from memory, and the value is not modified by an assignment or another atomic operation between the time the value is read from memory and the time the new value is written to memory. Atomic operations can be thread-safe. Atomic swap operation 502 and atomic compare-and-exchange operation 504 can be examples of atomic operations. A GPU (or another device) may be configured with hardware support for atomic operations on integers (e.g., signed integers 402, unsigned integers 408, etc.); however, a GPU may not be configured with hardware support for atomic operations on floating-point numbers (e.g., floating-point numbers 412).

[0062] In atomic swap operation 502, the GPU (or another device) may obtain integer data 506. Memory 508 associated with the GPU may include integer content 510. In one example, integer data 506 and integer content 510 may be signed integers (e.g., signed integer 402). In another example, integer data 506 and integer content 510 may be unsigned integers (e.g., unsigned integer 408). In atomic swap operation 502, the GPU may swap integer data 506 with integer content 510 in memory 508. More specifically, in atomic swap operation 502, integer data 506 may be written to memory 508, and the original contents of memory 508 (i.e., integer content 510) may be returned. Between the time integer content 510 is read and the time integer data 506 is written to memory 508, integer content 510 may not be modified by a dispatch in a shader invocation or another atomic operation.

[0063] In atomic compare-and-swap operation 504, the GPU (or another device) may obtain integer data 506. Memory 508 associated with the GPU may include integer content 510. The GPU may also obtain comparison integer 512. In one example, integer content 510 may be a signed integer (e.g., signed integer 402), and integer data 506 and comparison integer 512 may be unsigned integers (e.g., unsigned integer 408). In another example, integer content 510, integer data 506, and comparison integer 512 may be unsigned integers (e.g., unsigned integer 408). In atomic compare-and-swap operation 504, at 514, the GPU may compare comparison integer 512 with integer content 510. If comparison integer 512 is equal to integer content 510, the GPU may write integer data 506 to memory 508. Otherwise, integer content 510 may remain in memory 508. In either case, the original contents of memory 508 (i.e., integer content 510) may be returned. Between the time integer content 510 is read and the time integer data 506 is written to memory 508 , integer content 510 may not be modified by an assignment or another atomic operation in a shader invocation.

[0064] In one aspect, a graphics processor or GPU (or another device) may utilize atomic swap operation 502 and atomic compare-and-swap operation 504 to emulate support for floating-point atomics.

[0065] Figure 6 6 is a diagram illustrating an example atomic unit in a GPU 602 (or graphics processor). In one example, GPU 602 may be or include GPU 200. In one example, GPU 602 may be included in device 104. For example, GPU 602 may be processing unit 120. GPU 602 may include atomic simulator 198. In one example, GPU 602 may not include hardware support for floating-point atomic operations.

[0066] The GPU 602 may include a command processor 604. The command processor 604 may receive commands and, based on the commands, distribute work between a first shader processor 606 and an Nth shader processor 608, where N is a positive integer greater than one. In one example, the work may be associated with rendering graphics content. The first shader processor 606 and the Nth shader processor 608 may be collectively referred to as "a plurality of shader processors 606 to 608." The first shader processor 606 and the Nth shader processor 608 may execute shader code (e.g., a vertex shader, a fragment shader, a compute shader, etc.). The first shader processor 606 and the Nth shader processor 608 may also be referred to as shader cores. Shader code may also be referred to as a shader and may refer to a user-defined program configured to run in a level of the GPU 602. In one example, the shader code may be associated with rendering graphics content.

[0067] The first shader processor 606 may include a first arithmetic logic unit (ALU) 610, and the Nth shader processor 608 may include an Nth ALU 612. The number of ALUs in the first ALU 610 may be the same as or different from the number of ALUs in the Nth ALU 612. The number of ALUs in the first ALU 610 and the number of ALUs in the Nth ALU 612 may be a number different from N. The first ALU 610 and the Nth ALU 612 may be collectively referred to as "plurality of ALUs 610-612." The ALUs may be combinational digital circuits that perform arithmetic and bitwise operations on integer binary numbers (e.g., signed integers 402, unsigned integers 408, etc.).

[0068] The first shader processor 606 may include a first general purpose register (GPR) 614, and the Nth shader processor 608 may include an Nth GPR 616. The number of GPRs in the first GPR 614 may be the same as or different from the number of ALUs in the Nth GPR 616. The number of GPRs in the first GPR 614 and the number of GPRs in the Nth GPR 616 may be a number different from N. The first GPR 614 and the Nth GPR 616 may be collectively referred to as "a plurality of GPRs 614-616." A GPR may be a register that stores both data and addresses, i.e., a GPR may be a combined data / address register. A register may refer to a location accessible by a processor. A register may include a small amount of relatively quickly accessible storage.

[0069] The first shader processor 606 may include a first local memory 618, and the Nth shader processor 608 may include an Nth local memory 620. The first local memory 618 may include a first local memory atomic unit 622, and the Nth local memory 620 may include an Nth local memory atomic unit 624. The first local memory atomic unit 622 may perform atomic operations on data stored in the first local memory 618 and / or the first GPR 614, and the Nth local memory atomic unit 624 may perform atomic operations on data stored in the Nth local memory 620 and / or the Nth local memory atomic unit 624. The first local memory atomic unit 622 and the Nth local memory atomic unit 624 may be hardware that does not include support for floating-point atomic operations.

[0070] The GPU 602 may include a level 2 (L2) cache 626 accessible by multiple shader processors 606 through 608. The L2 cache 626 may also be referred to as a unified cache. The L2 cache 626 may include a tag RAM 628. The tag RAM 628 may identify data from other memory within a cache line of the L2 cache 626. The data itself may be stored in a separate portion of the L2 cache 626 from the tag RAM 628. The value stored in the tag RAM 628 may determine whether a cache lookup results in a hit or a miss. The L2 cache 626 may include a global atomic unit 630. The global atomic unit 630 may perform atomic operations on data stored in the L2 cache 626. The global atomic unit 630 may be hardware that does not include support for floating-point atomic operations.

[0071] Figure 7 700 is a diagram illustrating example aspects of an atomic maximum integer operation 702 and an atomic minimum integer operation 704. The atomic maximum integer operation 702 can be a signed atomic integer maximum operation or an unsigned atomic integer maximum operation. The atomic minimum integer operation 704 can be a signed atomic integer minimum operation or an unsigned atomic integer minimum operation. As will be described in detail below, a GPU (e.g., GPU 602 or GPU 200) can perform the atomic maximum integer operation 702 or the atomic minimum integer operation 704 on floating-point numbers (or interpreted integers generated from floating-point numbers) to emulate floating-point atomic operations, even when the GPU does not include hardware support for floating-point atomic operations.

[0072] In the atomic maximum integer operation 702, the GPU or graphics processor (or a component thereof or another device) may obtain integer data 706. In one example, the first local memory atomic unit 622 may obtain the integer data 706 from the command processor 604. In another example, the global atomic unit 630 may obtain the integer data 706 from a shader processor in the plurality of shader processors 606 through 608. In one example, the integer data 706 may be a signed integer (e.g., the signed integer 402). In another example, the integer data 706 may be an unsigned integer (e.g., the unsigned integer 408). The memory 708 may store integer content 710. The memory 708 may be or include the first local memory 618, the Nth local memory 620, or the L2 cache 626. In one example, the integer content 710 may be a signed integer (e.g., the signed integer 402). In another example, the integer content 710 may be an unsigned integer (e.g., the unsigned integer 408). In atomic maximum integer operation 702, the GPU or graphics processor may perform an atomic comparison of integer data 706 and the contents of memory 708 (i.e., integer content 710), write the larger of integer data 706 and integer content 710 to memory 708, and return the (original) contents of memory 708 (i.e., integer content 710) before the atomic comparison. The contents of memory 708 (i.e., integer content 710) updated during atomic maximum integer operation 702 may not be modified by a dispatch or another atomic operation in a shader invocation between the time the contents of memory 708 (i.e., integer content 710) are read and the time a new value (e.g., integer data 706 or integer content 710) is written.

[0073] In the atomic minimum integer operation 704, the GPU or graphics processor (or a component thereof or another device) may obtain integer data 706. In one example, the first local memory atomic unit 622 may obtain the integer data 706 from the command processor 604. In another example, the global atomic unit 630 may obtain the integer data 706 from a shader processor in the plurality of shader processors 606 through 608. In one example, the integer data 706 may be a signed integer (e.g., the signed integer 402). In another example, the integer data 706 may be an unsigned integer (e.g., the unsigned integer 408). The memory 708 may store integer content 710. In one example, the integer content 710 may be a signed integer (e.g., the signed integer 402). In another example, the integer content 710 may be an unsigned integer (e.g., the unsigned integer 408). In atomic minimum integer operation 704, the GPU or graphics processor may perform an atomic comparison of integer data 706 and the contents of memory 708 (i.e., integer content 710), write the smaller of integer data 706 and integer content 710 to memory 708, and return the (original) contents of memory 708 (i.e., integer content 710) before the atomic comparison. The contents of memory 708 (i.e., integer content 710) updated during atomic maximum integer operation 702 may not be modified by a dispatch or another atomic operation in a shader invocation between the time the contents of memory 708 (i.e., integer content 710) are read and the time the new value (integer data 706 or integer content 710) is written.

[0074] Figure 8 800 is a diagram illustrating example aspects of a floating-point atomic maximum operation 802 and a floating-point atomic minimum operation 816. A GPU or graphics processor (or a component or device thereof) may perform the floating-point atomic maximum operation 802 and / or the floating-point atomic minimum operation 816. The GPU or graphics processor (or a component or device thereof) may not include hardware supporting floating-point atomic operations; however, as will be described in more detail below, the floating-point atomic maximum operation 802 and the floating-point atomic minimum operation 816 may emulate support for floating-point atomic operations on hardware supporting atomic integer operations. In one example, the floating-point atomic maximum operation 802 and / or the floating-point atomic minimum operation 816 may be performed by the first local memory atomic unit 622, the Nth local memory atomic unit 624, and / or the global atomic unit 630.

[0075] In floating-point atomic maximum operation 802, a GPU (or graphics processor) (or a component or device thereof) may obtain a floating-point number 804. In one example, floating-point number 804 may be floating-point number 412. In one example, first local memory atomic unit 622 may obtain floating-point number 804 from command processor 604. In another example, global atomic unit 630 may obtain floating-point number 804 from one of multiple shader processors 606-608. At 806, the GPU (or graphics processor) may determine whether floating-point number 804 is less than 0.0. In other words, the GPU (or graphics processor) may determine whether a condition is satisfied (i.e., whether the condition is not satisfied). If floating point number 804 is less than 0.0, then at 808, the GPU (or graphics processor) may interpret the floating point bit pattern of floating point number 804 as a signed integer (e.g., signed integer 402), and at 810, the GPU (or graphics processor) may perform a signed atomic maximum operation (e.g., a signed variant of atomic maximum integer operation 702) on the interpreted integer (e.g., integer data 706 may be an integer interpreted from the floating point bit pattern of floating point number 804). In one example, interpreting the floating point bit pattern of floating point number 804 as a signed integer may be performed via a union operation. If floating point number 804 is greater than or equal to 0.0, then at 812, the GPU may interpret the floating point bit pattern of floating point number 804 as an unsigned integer (e.g., unsigned integer 408), and at 814, the GPU (or graphics processor) may perform an unsigned atomic minimum operation (e.g., an unsigned variant of atomic minimum integer operation 704) on the interpreted integer (e.g., integer data 706 may be an integer interpreted from the floating point bit pattern of floating point number 804). In one example, interpreting the floating point bit pattern of floating point number 804 as an unsigned integer may be performed via a union operation.

[0076] The following describes an example of interpreting an integer from a floating-point bit pattern. The floating-point number "1.0" can be stored in binary format, where the hexadecimal representation of the floating-point number "1.0" can be "0x3f80000". The floating-point number "1.0" can be interpreted as the integer value "1065353216" (which is the decimal equivalent of "0x3f80000").

[0077] The floating point atomic maximum operation 802 may be represented by the pseudo code listed below.

[0078] FLOAT_ATOMIC_MAX:if(X<0.0)SIGNED_INT_ATOMIC_MAX(X); else UNSIGNED_INT_ATOMIC_MIN(X).

[0079] In the pseudocode listed above, “X” may be a floating point number (or an integer interpreted from a floating point bit pattern of a floating point number), “SIGNED_INT_ATOMIC_MAX” may refer to the signed variant of the atomic maximum integer operation 702, and “UNSIGNED_INT_ATOMIC_MIN” may refer to the unsigned variant of the atomic minimum integer operation 704.

[0080] In one aspect with respect to the pseudo-code listed above, the current data at the atomic position (e.g., integer content 710) may be "+0.0", and "X" may be "-0.0". In this aspect, when a signed integer comparison is performed, SIGNED_INT_ATOMIC_MAX(0x80000000) may be utilized and the atomic position may remain at "+0.0" (because 0x0>0x80000000). In another aspect with respect to the pseudo-code listed above, the current data at the atomic position (e.g., integer content 710) may be "-0.0", and "X" may be "+0.0". In this aspect, when an unsigned integer comparison is performed, UNSIGNED_INT_ATOMIC_MIN(0x0) may be utilized to correctly update the atomic position to "+0.0" (because 0x0<0x80000000).

[0081] In a floating-point atomic minimum operation 816, the GPU or graphics processor (or a component or device thereof) may obtain a floating-point number 804. In one example, the floating-point number 804 may be the floating-point number 412. In one example, the first local memory atomic unit 622 may obtain the floating-point number 804 from the command processor 604. In another example, the global atomic unit 630 may obtain the floating-point number 804 from one of the plurality of shader processors 606 through 608. At 806, the GPU (or graphics processor) may determine whether the floating-point number 804 is less than 0.0. If floating point number 804 is less than 0.0, then at 818, the GPU (or graphics processor) may interpret the floating point bit pattern of floating point number 804 as a signed integer (e.g., signed integer 402), and at 820, the GPU (or graphics processor) may perform a signed atomic minimum operation (e.g., a signed variant of atomic minimum integer operation 704) on the interpreted integer (e.g., integer data 706 may be an integer interpreted from the floating point bit pattern of floating point number 804). In one example, interpreting the floating point bit pattern of floating point number 804 as a signed integer may be performed via a union operation. If floating point number 804 is greater than or equal to 0.0, then at 822, the GPU (or graphics processor) may interpret the floating point bit pattern of the floating point number as an unsigned integer (e.g., unsigned integer 408), and at 824, the GPU (or graphics processor) may perform an unsigned atomic maximum operation (e.g., an unsigned variant of atomic maximum integer operation 702) on the interpreted integer (e.g., integer data 706 may be an integer interpreted from the floating point bit pattern of floating point number 804). In one example, interpreting the floating point bit pattern of floating point number 804 as an unsigned integer may be performed via a union operation.

[0082] The floating point atomic minimum operation 816 may be represented by the pseudo code listed below.

[0083] FLOAT_ATOMIC_MIN:if(X<0.0)SIGNED_INT_ATOMIC_MIN(X); else UNSIGNED_INT_ATOMIC_MAX(X).

[0084] In the pseudocode listed above, “X” may be a floating point number (or an integer interpreted from a floating point bit pattern of a floating point number), “SIGNED_INT_ATOMIC_MIN” may refer to the signed variant of the atomic minimum integer operation 704 , and “UNSIGNED_INT_ATOMIC_MAX” may refer to the unsigned variant of the atomic maximum integer operation 702 .

[0085] The GPU (or graphics processor) may utilize the results of floating-point atomic maximum operation 802 and / or floating-point atomic minimum operation 816 to perform further processing steps associated with rendering graphics data (or for other purposes). In one example, the GPU may utilize floating-point number 804 in an operation depending on whether floating-point number 804 is greater than or less than a specific value stored in a memory or register of the GPU. In another example, the GPU may utilize the value written to memory 708 (e.g., an integer interpreted from the floating-point bit pattern of floating-point number 804) for subsequent processing.

[0086] In one aspect, the GPU may utilize the atomic swap operation 502 and the atomic compare-and-swap operation 504 to emulate floating-point maximum / minimum atomic operations on integer hardware. For the purpose of emulating floating-point maximum / minimum operations on integer hardware, the floating-point atomic maximum operation 802 and the floating-point atomic minimum operation 816 may be more computationally efficient than the atomic swap operation 502 and the atomic compare-and-swap operation 504.

[0087] Figure 9 9 is a call flow diagram 900 illustrating example communications between a graphics processor 902 and a graphics processor component 904, in accordance with one or more techniques of this disclosure. In one example, graphics processor 902 and / or graphics processor component 904 may be or include GPU 200 or GPU 602. In another example, graphics processor 902 and / or graphics processor component 904 may be included in device 104. In one example, graphics processor 902 and graphics processor component 904 may not include hardware support for floating-point atomic operations.

[0088] At 906, graphics processor 902 may obtain an indication of a floating-point (FP) number associated with a FP operation. In one example, the FP number may be floating-point number 412. At 908, graphics processor 902 may obtain an indication of whether an atomic minimum operation or an atomic maximum operation is to be applied to the FP number. In one example, the indication may be an indication of floating-point atomic maximum operation 802 or an indication of floating-point atomic minimum operation 816. At 909, graphics processor 902 may determine whether a condition regarding the FP number is satisfied. In one example, if the FP number is less than 0.0, the condition may be satisfied, and if the FP number is greater than or equal to 0.0, the condition may not be satisfied.

[0089] At 910, the graphics processor 902 may select a signed atomic integer operation or an unsigned atomic integer operation based on the FP number and / or the FP operation. For example, if the FP number is less than 0.0, the graphics processor 902 may select a signed atomic integer operation, or if the FP number is greater than or equal to 0.0, the graphics processor 902 may select an unsigned atomic integer operation. At 912, the graphics processor 902 may send an indication of the selected signed atomic integer operation or unsigned atomic integer operation to the graphics processor component 904. At 914, the graphics processor 902 may perform the selected signed atomic integer operation or unsigned atomic integer operation, as described above in Figure 8 As described in the description.

[0090] Figure 10 1000 is a flowchart of an example method of data processing according to one or more techniques of the present disclosure. The method may be performed by a device such as a device for graphics processing, a graphics processor (e.g., a GPU), a CPU, a wireless communication device, etc., such as in combination with Figures 1 to 9 The method may be used in various aspects of the graphics processor. The method may be associated with various technical advantages at the graphics processor, such as emulating floating-point atomic operations on hardware that supports integer atomic operations instead of floating-point atomic operations. In one example, the method may be performed by the atomic simulator 198.

[0091] At 1002, a device (e.g., a graphics processor) may obtain a first indication of a floating point number associated with a floating point operation. For example, Figure 9 At 906, graphics processor 902 may obtain an indication of an FP number associated with an FP operation. In one example, the floating point number may be floating point number 412. In another example, the floating point number may be floating point number 804. In another example, the floating point operation may be a maximum operation or a minimum operation. In one example, 1002 may be performed by atomic simulator 198.

[0092] At 1004, a device (e.g., a graphics processor) selects a signed atomic integer operation or an unsigned atomic integer operation based on at least one of a floating point number or a floating point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition. For example, Figure 9At 910, it is shown that the graphics processor 902 can select a signed atomic integer operation or an unsigned atomic integer operation based on the FP number and / or the FP operation. In one example, the signed atomic integer operation can be a signed version of the atomic maximum integer operation 702 or a signed version of the atomic minimum integer operation 704. In one example, the unsigned atomic integer operation can be an unsigned version of the atomic maximum integer operation 702 or an unsigned version of the atomic minimum integer operation 704. In one example, the condition can include the floating point number being less than a number (e.g., 0.0), and the condition can include the floating point number being greater than or equal to the number. In another example, selecting a signed atomic integer operation or an unsigned atomic integer operation can include the above description of the conditions. Figure 8 In one example, 1004 may be performed by the atom simulator 198 .

[0093] Figure 11 1100 is a flowchart of an example method of data processing according to one or more techniques of the present disclosure. The method may be performed by a device such as a device for graphics processing, a graphics processor (e.g., a GPU), a CPU, a wireless communication device, etc., such as in combination with Figures 1 to 9 The method may be associated with various technical advantages at a graphics processor, such as emulating floating-point atomic operations on hardware that supports integer atomic operations instead of floating-point atomic operations. In one example, the method (including various aspects described in detail below) may be performed by an atomic simulator 198.

[0094] At 1102, a device (e.g., a graphics processor) obtains a first indication of a floating point number associated with a floating point operation. For example, Figure 9 At 906, graphics processor 902 may obtain an indication of an FP number associated with an FP operation. In one example, the floating point number may be floating point number 412. In another example, the floating point number may be floating point number 804. In another example, the floating point operation may be a maximum operation or a minimum operation. In one example, 1102 may be performed by atomic simulator 198.

[0095] At 1108, the device (e.g., a graphics processor) selects a signed atomic integer operation or an unsigned atomic integer operation based on at least one of a floating point number or a floating point operation, wherein the signed atomic integer operation is associated with satisfying the condition and the unsigned atomic integer operation is associated with not satisfying the condition. For example, Figure 9At 910, it is shown that the graphics processor 902 can select a signed atomic integer operation or an unsigned atomic integer operation based on the FP number and / or the FP operation. In one example, the signed atomic integer operation can be a signed version of the atomic maximum integer operation 702 or a signed version of the atomic minimum integer operation 704. In one example, the unsigned atomic integer operation can be an unsigned version of the atomic maximum integer operation 702 or an unsigned version of the atomic minimum integer operation 704. In one example, the condition can include the floating point number being less than a number (e.g., 0.0), and the condition can include the floating point number being greater than or equal to the number. In another example, selecting a signed atomic integer operation or an unsigned atomic integer operation can include the above description of the conditions. Figure 8 In one example, 1108 may be performed by the atom simulator 198 .

[0096] In one aspect, at 1110, a device (eg, a graphics processor) may send a second indication of a selected signed atomic integer operation or a selected unsigned atomic integer operation. For example, Figure 9 At 912, it is shown that the graphics processor 902 may send an indication of the selected signed or unsigned atomic integer operation to the graphics processor component 904. In one example, 1110 may be performed by the atomic simulator 198.

[0097] In one aspect, at 1112, the device (eg, a graphics processor) may perform the selected signed atomic integer operation or the selected unsigned atomic integer operation after sending the second indication. For example, Figure 9 At 914 it is shown that graphics processor 902 may perform the selected signed or unsigned atomic integer operation after sending the indication of the selected signed or unsigned integer operation at 912. In one example, 1112 may be performed by atomic simulator 198.

[0098] In one aspect, the selected signed atomic integer operation or the selected unsigned atomic integer operation can be associated with at least one compare-and-exchange operation. For example, the selected signed atomic integer operation or the selected unsigned atomic integer operation can be associated with atomic compare-and-exchange operation 504 or atomic exchange operation 502.

[0099] In one aspect, the selected signed atomic integer operation or the selected unsigned atomic integer operation may correspond to a one-to-one replacement of a floating-point operation. For example, the selected signed atomic integer operation or the selected unsigned atomic integer operation may correspond to a one-to-one replacement of a maximum or minimum floating-point operation.

[0100] In one aspect, at 1106, the device (e.g., a graphics processor) may determine whether a condition is satisfied based on the first indication of the floating point number, and a signed atomic integer operation or an unsigned atomic integer operation may be selected based on the determination. For example, Figure 9 At 909, the graphics processor 902 may determine whether a condition regarding the number of FPs is satisfied. Figure 9 The selection of a signed atomic integer operation or an unsigned atomic integer operation may be based on the satisfaction or non-satisfaction of a condition, as shown at 910. In one example, 1106 may be performed by the atomic simulator 198.

[0101] In one aspect, the condition may be satisfied if the floating point number is less than 0.0, and may not be satisfied if the floating point number is greater than or equal to 0.0. For example, the condition at 909 may include the FP number being less than 0.0. In another example, the condition may include the above regarding Figure 8 All aspects described in 806.

[0102] In one aspect, at 1104, a device (e.g., a graphics processor) may obtain a second indication of whether an atomic maximum operation or an atomic minimum operation is to be applied to the floating point number, wherein selecting a signed atomic integer operation or an unsigned atomic integer operation may be based on the second indication. For example, Figure 9 At 908, graphics processor 902 may obtain an indication of whether an atomic minimum operation or an atomic maximum operation is to be applied to the FP number. In one example, the atomic maximum operation may be a floating-point atomic maximum operation 802, and the atomic minimum operation may be a floating-point atomic minimum operation 816. Additionally, the signed atomic integer operation or the unsigned atomic integer operation selected at 910 may be a maximum operation or a minimum operation. In one example, 1104 may be performed by atomic simulator 198.

[0103] In one aspect, the second indication may indicate that an atomic maximum operation is to be applied to a floating point number, and selecting a signed atomic integer operation may include applying a signed atomic integer maximum operation to the floating point number. For example, the second indication may indicate that the floating point atomic maximum operation 802 is to be applied to the floating point number 804. Additionally, selecting a signed atomic integer operation may include the above description of Figure 8 Furthermore, applying the signed atomic integer maximum operation to the floating point number may include applying a signed version of the atomic maximum integer operation 702.

[0104] In one aspect, the second indication may indicate that an atomic maximum operation is to be applied to a floating point number, and selecting an unsigned atomic integer operation may include applying an unsigned atomic integer minimum operation to the floating point number. For example, the second indication may indicate that the floating point atomic maximum operation 802 is to be applied to the floating point number 804. Additionally, selecting an unsigned atomic integer operation may include the above description of Figure 8 Furthermore, applying the unsigned atomic integer minimum operation to the floating point number may include applying the unsigned version of the atomic minimum integer operation 704.

[0105] In one aspect, the second indication may indicate that an atomic minimum operation is to be applied to a floating point number, and selecting a signed atomic integer operation may include applying a signed atomic integer minimum operation to the floating point number. For example, the second indication may indicate that the floating point atomic minimum operation 816 is to be applied to the floating point number 804. Additionally, selecting a signed atomic integer operation may include the above description of Figure 8 Furthermore, applying the signed atomic integer minimum operation to the floating point number may include applying a signed version of the atomic minimum integer operation 704.

[0106] In one aspect, the second indication may indicate that an atomic minimum operation is to be applied to a floating point number, and selecting an unsigned atomic integer operation may include applying an unsigned atomic integer maximum operation to the floating point number. For example, the second indication may indicate that the floating point atomic minimum operation 816 is to be applied to the floating point number 804. Additionally, selecting an unsigned atomic integer operation may include the above description of Figure 8 Furthermore, applying the unsigned atomic integer maximum operation to the floating point number may include applying an unsigned version of the atomic maximum integer operation 702.

[0107] In one aspect, signed atomic integer operations or unsigned atomic integer operations can be associated with shader code at a graphics processor. For example, signed atomic integer operations or unsigned atomic integer operations can be associated with code associated with multiple shader processors 606 to 608 of GPU 602.

[0108] In one aspect, signed atomic integer operations or unsigned atomic integer operations can be associated with an L2 cache at a graphics processor. For example, signed atomic integer operations or unsigned atomic integer operations can be associated with an L2 cache 626 of a GPU 602.

[0109] In one aspect, the signed atomic integer operation or the unsigned atomic integer operation can be associated with at least one thread at the graphics processor. For example, the signed atomic integer operation or the unsigned atomic integer operation can be associated with a thread associated with GPU 602.

[0110] In a configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a CPU, or some other processor that can perform graphics processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within the device 104 or another device. The apparatus may include means for obtaining a first indication of a floating-point number associated with a floating-point operation. The apparatus may also include means for selecting a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating-point number or the floating-point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition. The apparatus may also include means for sending a second indication of the selected signed atomic integer operation or the selected unsigned atomic integer operation. The apparatus may also include means for executing the selected signed atomic integer operation or the selected unsigned atomic integer operation after sending the second indication. The apparatus may also include means for determining whether the condition is satisfied based on the first indication of the floating-point number, wherein the signed atomic integer operation or the unsigned atomic integer operation is selected based on the determination. The apparatus may further include means for obtaining a second indication of whether an atomic maximum operation or an atomic minimum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation or the unsigned atomic integer operation is based on the second indication.

[0111] It should be understood that the specific order or hierarchy of blocks / steps in the processes, flowcharts, and / or call flow diagrams disclosed herein is merely illustrative of example methods. It should be understood that the specific order or hierarchy of blocks / steps in these processes, flowcharts, and / or call flow diagrams may be rearranged based on design preferences. In addition, some blocks / steps may be combined or omitted. Other blocks / steps may also be added. The accompanying method claims provide elements of various blocks / steps in a sample order, but are not intended to be limited to the specific order or hierarchy provided.

[0112] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein, unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as being preferred or having advantages over other aspects.

[0113] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” can be interpreted as “and / or” unless the context dictates otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, which may include multiple As, multiple Bs, or multiple Cs. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A, B, and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. Words such as "module," "mechanism," "element," and "device" are not intended to be substituted for the word "component." Therefore, no claim element is to be construed as part-plus-function unless the element is explicitly recited using the phrase "means for..."

[0114] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, the functionality, processing unit, technique, or other module described herein may be stored or transmitted as one or more instructions or codes on a computer-readable medium.

[0115] Computer-readable media may include computer data storage media and communication media, including any media that facilitate the transfer of a computer program from one place to another. In this manner, a computer-readable medium may generally correspond to: (1) a non-transitory, tangible computer-readable storage medium; or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to extract instructions, codes, and / or data structures for implementing the techniques described in this disclosure. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, or other magnetic storage devices. As used herein, magnetic disks and optical disks include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include computer-readable media.

[0116] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or groups of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize the functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units may be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0117] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0118] Aspect 1 is a data processing method, the method comprising: obtaining a first indication of a floating-point number associated with a floating-point operation; and selecting a signed atomic integer operation or an unsigned atomic integer operation based on at least one of the floating-point number or the floating-point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

[0119] Aspect 2 may be combined with Aspect 1 and further include sending a second indication of the selected signed atomic integer operation or the selected unsigned atomic integer operation.

[0120] Aspect 3 may be combined with Aspect 2 and further include: performing the selected signed atomic integer operation or the selected unsigned atomic integer operation after sending the second indication.

[0121] Aspect 4 may be combined with any one of aspects 1 to 3 and includes: the selected signed atomic integer operation or the selected unsigned atomic integer operation being associated with at least one compare-and-exchange operation.

[0122] Aspect 5 may be combined with any one of aspects 1 to 4 and includes: the selected signed atomic integer operation or the selected unsigned atomic integer operation corresponding to a one-to-one replacement of the floating-point operation.

[0123] Aspect 6 can be combined with any one of aspects 1 to 5 and further include: determining whether the condition is met based on the first indication of the floating point number, wherein the signed atomic integer operation or the unsigned atomic integer operation is selected based on the determination.

[0124] Aspect 7 can be combined with Aspect 6 and includes: if the floating point number is less than 0.0, the condition is satisfied; and includes: if the floating point number is greater than or equal to 0.0, the condition is not satisfied.

[0125] Aspect 8 can be combined with any one of aspects 1 to 7 and further includes: obtaining a second indication of whether an atomic maximum operation or an atomic minimum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation or the unsigned atomic integer operation is based on the second indication.

[0126] Aspect 9 may be combined with Aspect 8 and include: the second indication indicating that the atomic maximum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation includes applying the signed atomic integer maximum operation to the floating point number.

[0127] Aspect 10 may be combined with aspect 8 and include: the second indication indicating that the atomic maximum operation is to be applied to the floating point number, wherein selecting the unsigned atomic integer operation comprises applying an unsigned atomic integer minimum operation to the floating point number.

[0128] Aspect 11 may be combined with Aspect 8 and include: the second indication indicating that the atomic minimum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation comprises applying the signed atomic integer minimum operation to the floating point number.

[0129] Aspect 12 may be combined with aspect 8 and include: the second indication indicating that the atomic minimum operation is to be applied to the floating point number, wherein selecting the unsigned atomic integer operation comprises applying an unsigned atomic integer maximum operation to the floating point number.

[0130] Aspect 13 may be combined with any one of aspects 1 to 12 and includes: the signed atomic integer operation or the unsigned atomic integer operation being associated with shader code at a graphics processor.

[0131] Aspect 14 may be combined with any one of aspects 1 to 13 and includes: the signed atomic integer operation or the unsigned atomic integer operation being associated with a level 2 (L2) cache at a graphics processor.

[0132] Aspect 15 may be combined with any one of aspects 1 to 14 and include: the signed atomic integer operation or the unsigned atomic integer operation being associated with at least one thread at a graphics processor.

[0133] Aspect 16 is an apparatus for data processing, the apparatus comprising at least one processor coupled to a memory and configured to implement the method according to any one of aspects 1 to 15.

[0134] Aspect 17 may be combined with Aspect 16 and include: the apparatus is a wireless communication device, the wireless communication device comprising at least one of a transceiver or an antenna coupled to the at least one processor, wherein in order to obtain the first indication, the at least one processor is configured to obtain the first indication via at least one of the transceiver or the antenna.

[0135] Aspect 18 is an apparatus for data processing, the apparatus comprising means for implementing the method according to any one of aspects 1 to 15.

[0136] Aspect 19 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement the method according to any one of aspects 1 to 15.

[0137] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

1. A device for data processing, comprising: Memory; and at least one processor coupled to the memory and, based at least in part on information stored in the memory, configured to: obtaining a first indication of a floating point number associated with a floating point operation; and A signed atomic integer operation or an unsigned atomic integer operation is selected based on at least one of the floating point number or the floating point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

2. The apparatus of claim 1 , wherein the at least one processor is further configured to: A second indication of the selected signed atomic integer operation or the selected unsigned atomic integer operation is sent.

3. The apparatus of claim 2, wherein the at least one processor is further configured to: The at least one processor is configured to perform the selected signed atomic integer operation or the selected unsigned atomic integer operation after sending the second indication. 4 . The apparatus of claim 1 , wherein the selected signed atomic integer operation or the selected unsigned atomic integer operation is associated with at least one compare-and-exchange operation.

5. The apparatus of claim 1, wherein the selected signed atomic integer operation or the selected unsigned atomic integer operation corresponds to a one-to-one replacement of the floating-point operation.

6. The apparatus of claim 1 , wherein the at least one processor is further configured to: A determination is made based on the first indication of the floating-point number as to whether the condition is satisfied, wherein to select the signed atomic integer operation or the unsigned atomic integer operation, the at least one processor is configured to select the signed atomic integer operation or the unsigned atomic integer operation based on the determination.

7. The apparatus of claim 6, wherein the condition is satisfied if the floating point number is less than 0.0, and wherein the condition is not satisfied if the floating point number is greater than or equal to 0.

0.

8. The apparatus of claim 1 , wherein the at least one processor is further configured to: A second indication is obtained as to whether an atomic maximum operation or an atomic minimum operation is to be applied to the floating-point number, wherein to select the signed atomic integer operation or the unsigned atomic integer operation, the at least one processor is configured to select the signed atomic integer operation or the unsigned atomic integer operation based on the second indication.

9. The apparatus of claim 8, wherein the second indication indicates that the atomic maximum operation is to be applied to the floating point number, wherein to select the signed atomic integer operation, the at least one processor is configured to apply the signed atomic integer maximum operation to the floating point number.

10. The apparatus of claim 8, wherein the second indication indicates that the atomic maximum operation is to be applied to the floating point number, wherein to select the unsigned atomic integer operation, the at least one processor is configured to apply an unsigned atomic integer minimum operation to the floating point number.

11. The apparatus of claim 8, wherein the second indication indicates that the atomic minimum operation is to be applied to the floating point number, wherein to select the signed atomic integer operation, the at least one processor is configured to apply the signed atomic integer minimum operation to the floating point number.

12. The apparatus of claim 8, wherein the second indication indicates that the atomic minimum operation is to be applied to the floating point number, wherein to select the unsigned atomic integer operation, the at least one processor is configured to apply an unsigned atomic integer maximum operation to the floating point number.

13. The apparatus of claim 1, wherein the signed atomic integer operation or the unsigned atomic integer operation is associated with shader code at a graphics processor.

14. The apparatus of claim 1, wherein the signed atomic integer operation or the unsigned atomic integer operation is associated with a level 2 (L2) cache at a graphics processor.

15. The apparatus of claim 1, wherein the signed atomic integer operation or the unsigned atomic integer operation is associated with at least one thread at a graphics processor.

16. The apparatus of claim 1 , wherein the apparatus is a wireless communication device comprising at least one of a transceiver or an antenna coupled to the at least one processor, wherein to obtain the first indication, the at least one processor is configured to obtain the first indication via at least one of the transceiver or the antenna.

17. A method for data processing, the method comprising: obtaining a first indication of a floating point number associated with a floating point operation; as well as A signed atomic integer operation or an unsigned atomic integer operation is selected based on at least one of the floating point number or the floating point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

18. The method according to claim 17, further comprising: A second indication of the selected signed atomic integer operation or the selected unsigned atomic integer operation is sent.

19. The method according to claim 18, further comprising: The selected signed atomic integer operation or the selected unsigned atomic integer operation is performed after sending the second indication.

20. The method of claim 17, wherein the selected signed atomic integer operation or the selected unsigned atomic integer operation is associated with at least one compare-and-exchange operation.

21. The method of claim 17, wherein the selected signed atomic integer operation or the selected unsigned atomic integer operation corresponds to a one-to-one replacement of the floating-point operation.

22. The method according to claim 17, further comprising: A determination is made based on the first indication of the floating point number whether the condition is satisfied, wherein the signed atomic integer operation or the unsigned atomic integer operation is selected based on the determination.

23. The method of claim 22, wherein the condition is satisfied if the floating point number is less than 0.0, and wherein the condition is not satisfied if the floating point number is greater than or equal to 0.

0.

24. The method according to claim 17, further comprising: A second indication of whether an atomic maximum operation or an atomic minimum operation is to be applied to the floating point number is obtained, wherein selecting the signed atomic integer operation or the unsigned atomic integer operation is based on the second indication.

25. The method of claim 24, wherein the second indication indicates that the atomic maximum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation comprises applying a signed atomic integer maximum operation to the floating point number.

26. The method of claim 24, wherein the second indication indicates that the atomic maximum operation is to be applied to the floating point number, wherein selecting the unsigned atomic integer operation comprises applying an unsigned atomic integer minimum operation to the floating point number.

27. The method of claim 24, wherein the second indication indicates that the atomic minimum operation is to be applied to the floating point number, wherein selecting the signed atomic integer operation comprises applying a signed atomic integer minimum operation to the floating point number.

28. The method of claim 24, wherein the second indication indicates that the atomic minimum operation is to be applied to the floating point number, wherein selecting the unsigned atomic integer operation comprises applying an unsigned atomic integer maximum operation to the floating point number.

29. The method of claim 17, wherein the signed atomic integer operation or the unsigned atomic integer operation is associated with shader code at a graphics processor.

30. A computer-readable medium storing computer-executable code that, when executed by at least one processor, causes the at least one processor to: obtaining a first indication of a floating point number associated with a floating point operation; and A signed atomic integer operation or an unsigned atomic integer operation is selected based on at least one of the floating point number or the floating point operation, wherein the signed atomic integer operation is associated with satisfying a condition and the unsigned atomic integer operation is associated with not satisfying the condition.

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