Efficient tensor recalculation for neural networks

Abstract

A processor-implemented method for re-computation of an artificial neural network (ANN) includes receiving a graph representing the ANN. The graph includes a plurality of nodes connected by edges, and each node represents an operation. A retention interval for the nodes is determined based on priority constraints for the nodes. These hold intervals correspond to time intervals for holding each node output in the local memory. A node of the nodes to be recalculated is determined based on the hold intervals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 18 / 353,637, filed on July 17, 2023, entitled “EFFICIENT TENSORREMATERIALIZATION FOR NEURAL NETWORKS,” which claims the benefit of U.S. provisional patent application No. 63 / 441,150, filed on January 25, 2023, entitled “EFFICIENT TENSOR REMATERIALIZATION FOR NEURAL NETWORKS,” the disclosures of which are expressly incorporated by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure generally relate to efficient tensor rematerialization for neural networks. Background Art

[0004] An artificial neural network may include an interconnected set of artificial neurons (e.g., a neuron model). An artificial neural network may be a computing device or represented as a method to be executed by a computing device. A convolutional neural network (CNN) is a type of feedforward artificial neural network. A convolutional neural network may include a collection of neurons, each of which has a receptive field and collectively spells out an input space. CNNs, such as deep convolutional neural networks (DCNs), have numerous applications. Specifically, these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword detection, autonomous driving, and other classification tasks.

[0005] Given the many useful applications of neural networks, there is an increasing demand for using them on edge devices such as smartphones. However, edge devices have limited computational resources, and generalized models can utilize more complex networks and more computation. Consequently, the memory footprint and high latency of neural networks make their use challenging, especially for efficient deployment and inference on resource-constrained devices.

[0006] One way to reduce memory usage is to recompute. Recomputation involves recomputing certain operations instead of keeping the outputs of such operations in memory. However, determining the outputs of the operations to recompute (which can be represented as nodes in a graph) is a combinatorial optimization problem that can be difficult to solve. Summary of the Invention

[0007] The present disclosure is set out in the independent claims. Some aspects of the present disclosure are described in the dependent claims.

[0008] In some aspects of the present disclosure, a processor-implemented method performed by at least one processor includes receiving a graph representing an artificial neural network (ANN). The graph includes a plurality of nodes connected by edges, and each node represents an operation. The processor-implemented method also includes determining, by the at least one processor, retention intervals for the nodes based on precedence constraints for the nodes. The retention intervals correspond to time intervals for retaining each node output in local memory. The processor-implemented method also includes determining, by the at least one processor, nodes to be recomputed from the plurality of nodes based on the retention intervals.

[0009] Some aspects of the present disclosure relate to an apparatus comprising a component for receiving a graph representing an artificial neural network (ANN). The graph comprises a plurality of nodes connected by edges, and each node represents an operation. The apparatus further comprises a component for determining a retention interval for the nodes based on precedence constraints for the nodes. The retention intervals correspond to time intervals for retaining each node output in a local memory. The apparatus further comprises a component for determining, based on the retention intervals, which nodes of the plurality of nodes to recompute.

[0010] In some aspects of the present disclosure, a non-transitory computer-readable medium having program code recorded thereon is disclosed. The program code is executed by a processor and includes program code for receiving a graph representing an artificial neural network (ANN). The graph includes a plurality of nodes connected by edges, and each node represents an operation. The program code also includes program code for determining a retention interval for a node based on a priority constraint for the node. These retention intervals correspond to time intervals for maintaining each node output in a local memory. The program code also includes program code for determining a node to be recalculated among the plurality of nodes based on the retention interval.

[0011] Some aspects of the present disclosure relate to a device having a global memory and one or more processors coupled to the global memory. The processor is configured to receive a graph representing an artificial neural network (ANN). The graph includes a plurality of nodes connected by edges, and each node represents an operation. The processor is further configured to determine retention intervals for the plurality of nodes based on precedence constraints for the plurality of nodes. The retention intervals correspond to time intervals for retaining each node output in a local memory. The processor is further configured to determine, based on the retention intervals, which nodes in the plurality of nodes to recalculate.

[0012] Additional features and advantages of the present disclosure are described below. It will be understood by those skilled in the art that the present disclosure can be readily used as a basis for modifying or designing other structures for carrying out the same purposes as the present disclosure. It will also be recognized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the present disclosure, both in its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the figures is provided for illustration and description purposes only and is not intended to be a definition of limitations of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The features, nature and advantages of the present disclosure will become more apparent when the detailed description set forth below is read in conjunction with the accompanying drawings, in which like reference numerals are correspondingly identified throughout.

[0014] Figure 1 An example implementation of a neural network using a system on a chip (SOC) including a general-purpose processor in accordance with certain aspects of the present disclosure is illustrated.

[0015] Figure 2A 、 Figure 2B and Figure 2C is a diagram illustrating a neural network according to various aspects of the present disclosure.

[0016] Figure 2D is a diagram illustrating an exemplary deep convolutional network (DCN) according to various aspects of the present disclosure.

[0017] Figure 3 is a block diagram illustrating an exemplary deep convolutional network (DCN) according to various aspects of the present disclosure.

[0018] Figure 4 is a block diagram illustrating an exemplary software architecture that can modularize artificial intelligence (AI) functionality according to various aspects of the present disclosure.

[0019] Figure 5 is an example diagram illustrating the tradeoff between memory utilization and computation time according to various aspects of the present disclosure.

[0020] Figure 6A is an example computational graph according to various aspects of the present disclosure.

[0021] Figure 6B is an example of a method for performing various aspects of the present disclosure. Figure 6A An example computation graph for

[0054] shows an example of a graph preserving intervals.

[0022] Figure 7is a flow chart illustrating a processor-implemented method for efficient tensor recomputation for artificial neural networks according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the described concepts may be practiced. The detailed description includes specific details to provide a comprehensive understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0024] Based on the teachings, it will be appreciated by those skilled in the art that the scope of the present disclosure is intended to encompass any aspect of the present disclosure, regardless of whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect. For example, a device or method may be implemented using any number of aspects set forth. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functionality, or structure and functionality that are supplementary to or different from the various aspects of the present disclosure set forth. It should be understood that any aspect of the present disclosure disclosed may be embodied by one or more elements of a claim.

[0025] The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] Although specific aspects have been described, numerous variations and permutations of these aspects fall within the scope of this disclosure. Although some benefits and advantages of preferred aspects have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or purpose. On the contrary, various aspects of this disclosure are intended to be broadly applicable to different technologies, system configurations, networks, and protocols, some of which are illustrated as examples in the accompanying drawings and the following description of preferred aspects. The detailed description and drawings are merely illustrative of the present disclosure and are not limiting, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0027] Deploying and training neural networks on computing devices presents many challenges. The low memory constraints of edge devices are often one of the biggest limiting factors encountered in the deployment of large neural network models. Tensor recomputation (also known as recalculation) can address the higher memory requirements of neural network training and inference.

[0028] Many computer architectures for deep neural networks (DNNs) utilize a limited amount of fast local cache memory (e.g., tightly coupled memory) in combination with a larger amount of external memory (e.g., global memory or system memory) that has significantly slower access speeds. For example, today's accelerators for mobile devices may allocate several megabytes of local cache per core for storing intermediate output sensors, rather than using the mobile device's main memory directly. In addition, large DNNs can be trained primarily on the GPU's local graphics double data rate (GDDR) memory before offloading tensors to the DDR memory on the mobile device's motherboard. However, in practice, there are many DNNs where the amount of memory is insufficient to store all intermediate outputs. On-device training on resource-constrained devices can further exacerbate the shortcomings.

[0029] One approach to addressing this problem is recomputation. When input data is used for a computational operation, the data can be read from memory, or alternatively, the data can be discarded and recomputed (recalculated) when it is to be used. This additional computation can be advantageous over using data to occupy valuable local cache memory until it is ready to be used. However, deciding which operations (nodes) in a DNN to recompute or not to recompute in order to improve or optimize latency and memory usage can be a difficult combinatorial problem.

[0030] Some conventional methods formulate mixed integer linear programs (MILPs) with Boolean variables for each use of the output of a compute node (read from memory or recompute). 2 ) Boolean variables (where n is the number of nodes in the computation graph), this formulation has limitations when trying to scale to large graphs. While linear relaxation followed by rounding is an approximation utilized in such conventional methods, these rounded solutions can be far from optimal, limiting the applicability of such methods.

[0031] Aspects of the present disclosure relate to efficient tensor recomputation for artificial neural networks. Certain aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques (such as determining a hold interval for the plurality of nodes and determining nodes in the plurality of nodes to recompute based on the hold interval) can reduce peak memory utilization and memory footprint.

[0032] Figure 1An example implementation of a system on a chip (SOC) 100 is illustrated, which may include a central processing unit (CPU) 102 or a multi-core CPU configured for tensor recomputation of an artificial neural network. Variables (e.g., neural signals and synaptic weights), system parameters associated with a computational device (e.g., a neural network with weights), latency, frequency bin information, and task information may be stored in a memory block associated with a neural processing unit (NPU) 108, in a memory block associated with CPU 102, in a memory block associated with a graphics processing unit (GPU) 104, in a memory block associated with a digital signal processor (DSP) 106, in a memory block 118, or may be distributed across multiple blocks. Instructions executed at CPU 102 may be loaded from a program memory associated with CPU 102 or may be loaded from memory block 118.

[0033] The SOC 100 may also include additional processing blocks tailored for specific functions, such as a GPU 104, a DSP 106, a connectivity block 110 (which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, etc.), and a multimedia processor 112 that may, for example, detect and recognize gestures. In one specific implementation, the NPU 108 is implemented in the CPU 102, the DSP 106, and / or the GPU 104. The SOC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, and / or a navigation module 120, which may include a global positioning system.

[0034] SOC 100 may be based on the ARM instruction set. In one aspect of the present disclosure, the instructions loaded into the general purpose processor 102 may include code for receiving a graph representing an artificial neural network (ANN) by at least one processor. The graph includes a plurality of nodes connected by edges, and each node represents an operation. The general purpose processor 102 may also include code for determining, by the at least one processor, a retention interval for a node based on a priority constraint for the node. These retention intervals correspond to time intervals for maintaining each node output in a local memory. The general purpose processor 102 may also include code for determining, by the at least one processor, a node to be recalculated among the plurality of nodes based on the retention interval.

[0035] Deep learning architectures can perform object recognition tasks by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building useful feature representations of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Before the advent of deep learning, machine learning approaches to object recognition problems could rely heavily on human-designed features, perhaps combined with shallow classifiers. A shallow classifier could be a two-class linear classifier, for example, where the weighted sum of the feature vector components is compared to a threshold to predict which class the input belongs to. Human-designed features can be templates or kernels customized for a specific problem domain by engineers with domain expertise. In contrast, while deep learning architectures can learn to represent features similar to those that a human engineer might design, they do so through training. Furthermore, deep networks can learn to represent and recognize new types of features that humans may not have considered.

[0036] Deep learning architectures can learn hierarchies of features. For example, if presented with visual data, the first layer might learn to recognize relatively simple features in the input stream, such as edges. In another example, if presented with auditory data, the first layer might learn to recognize spectral power at specific frequencies. The second layer, taking the output of the first layer as input, might learn to recognize combinations of features, such as simple shapes in visual data or combinations of sounds in auditory data. For example, higher layers might learn to represent complex shapes in visual data or words in auditory data. Even higher layers might learn to recognize common visual objects or spoken phrases.

[0037] Deep learning architectures perform particularly well when applied to problems with a natural hierarchical structure. For example, the classification of motorized vehicles can benefit from first learning to recognize wheels, windshields, and other features. These features can then be combined in different ways at higher levels to identify cars, trucks, and airplanes.

[0038] Neural networks can be designed to have a variety of connectivity patterns. In a feedforward network, information is passed from lower layers to higher layers, where each neuron in a given layer communicates with neurons in a higher layer. As described above, hierarchical representations can be constructed in successive layers of a feedforward network. Neural networks can also have loops or feedback (also known as top-down) connections. In a loop connection, the output from a neuron in a given layer can be conveyed to another neuron in the same layer. The loop architecture can help identify patterns that span more than one input data block in the input data blocks delivered to the neural network in sequence. The connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections can be helpful when the recognition of high-level concepts can assist in discerning specific low-level features of the input.

[0039] The connections between the layers of a neural network can be fully connected or partially connected. Figure 2A An example of a fully connected neural network 202 is illustrated. In the fully connected neural network 202, neurons in a first layer may communicate their output to every neuron in a second layer, such that every neuron in the second layer will receive input from every neuron in the first layer. Figure 2B An example of a locally connected neural network 204 is illustrated. In the locally connected neural network 204, neurons in a first layer may be connected to a limited number of neurons in a second layer. More generally, the locally connected layers of the locally connected neural network 204 may be configured such that each neuron in the layer will have the same or similar connectivity pattern, but the connection strengths may have different values ​​(e.g., 210, 212, 214, and 216). The locally connected connectivity pattern may produce spatially different receptive fields in higher layers because higher layer neurons in a given region may receive inputs that have been tuned through training to properties of a limited portion of the total input to the network.

[0040] An example of a locally connected neural network is a convolutional neural network. Figure 2C An example of a convolutional neural network 206 is illustrated. The convolutional neural network 206 can be configured such that the connection strengths associated with the inputs of each neuron in the second layer are shared (e.g., 208). Convolutional neural networks may be well suited for problems where the spatial location of the inputs is meaningful.

[0041] One type of convolutional neural network is a deep convolutional network (DCN). Figure 2D A detailed example of a DCN 200 designed to recognize visual features based on an image 226 input from an image capture device 230 (such as an onboard camera) is shown. The DCN 200 of the current example can be trained to identify traffic signs and the numbers provided on traffic signs. Of course, the DCN 200 can be trained for other tasks, such as identifying lane markings or traffic lights.

[0042] DCN 200 can be trained using supervised learning. During training, DCN 200 can be presented with an image, such as image 226 of a speed limit sign, and a forward pass can then be computed to produce output 222. DCN 200 can include a feature extraction portion and a classification portion. Upon receiving image 226, convolutional layer 232 can apply a convolution kernel (not shown) to image 226 to generate a first set of feature maps 218. As an example, the convolution kernel of convolutional layer 232 can be a 5×5 kernel that generates a 28×28 feature map. In this example, because four different feature maps are generated in first set of feature maps 218, four different convolution kernels are applied to image 226 at convolutional layer 232. Convolution kernels can also be referred to as filters or convolution filters.

[0043] The first set of feature maps 218 may be subsampled by a maximum pooling layer (not shown) to generate a second set of feature maps 220. The maximum pooling layer reduces the size of the first set of feature maps 218. That is, the size of the second set of feature maps 220 (such as 14×14) is smaller than the size of the first set of feature maps 218 (such as 28×28). The reduced size provides similar information to subsequent layers while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).

[0044] exist Figure 2D In the example of , second set of feature maps 220 are convolved to generate first feature vector 224. Furthermore, first feature vector 224 is further convolved to generate second feature vector 228. Each feature of second feature vector 228 may include a number corresponding to a possible feature of image 226, such as "sign," "60," and "100." A softmax function (not shown) may convert the numbers in second feature vector 228 into probabilities. Thus, output 222 of DCN 200 may be a probability that image 226 includes one or more features.

[0045] In this example, the probability of "logo" and "60" in output 222 is higher than the probability of other numbers in output 222, such as "30," "40," "50," "70," "80," "90," and "100." Before training, output 222 generated by DCN 200 may be incorrect. Therefore, the error between output 222 and the target output can be calculated. The target output is the true value of image 226 (e.g., "logo" and "60"). The weights of DCN 200 can then be adjusted so that output 222 of DCN 200 is more closely aligned with the target output.

[0046] To adjust a weight, the learning algorithm calculates a gradient vector for the weight. The gradient indicates how much the error will increase or decrease if the weight is adjusted. At the top layer, the gradient may directly correspond to the value of the weight connecting the activated neurons in the penultimate layer to the neurons in the output layer. In lower layers, the gradient may depend on the value of the weight and the calculated error gradient of the higher layer. The weight can then be adjusted to reduce the error. This method of adjusting weights is called "backpropagation" because it involves a "backward pass" through the neural network.

[0047] In practice, the error gradient of the weights can be calculated over a small number of examples so that the calculated gradient approximates the true error gradient. This approximation method is referred to as stochastic gradient descent. Stochastic gradient descent can be repeated until the achievable error rate of the entire system stops decreasing or until the error rate reaches a target level. After learning, DCN 200 can be presented with new images, and a forward pass through DCN 200 can produce output 222, which can be considered an inference or prediction of DCN 200.

[0048] Deep Belief Network (DBN) is a probabilistic model comprising multiple layers of hidden nodes. DBN can be used to extract hierarchical representations of a training data set. DBN can be obtained by stacking layers of restricted Boltzmann machines (RBM). RBM is a type of artificial neural network that can learn probability distributions over a set of inputs. Because RBM can learn probability distributions without information about the category to which each input should be classified, RBM is often used for unsupervised learning. Using a hybrid paradigm of supervised and unsupervised learning, the bottom RBM of a DBN can be trained in an unsupervised manner and can be used as a feature extractor, while the top RBM can be trained in a supervised manner (on the joint distribution of the input and target class from the previous layer) and can be used as a classifier.

[0049] A DCN is a network within a convolutional network that is configured with additional pooling and normalization layers. DCN has achieved state-of-the-art performance on many tasks. DCN can be trained using supervised learning, where both the input and output targets are known for many examples and are used to modify the network's weights using gradient descent.

[0050] A DCN can be a feedforward network. Furthermore, as described above, connections from neurons in the first layer of a DCN to a set of neurons in the next higher layer are shared across the neurons in the first layer. The feedforward and shared connections of a DCN can be used for fast processing. For example, the computational burden of a DCN can be much smaller than that of a similarly sized neural network that includes recurrent or feedback connections.

[0051] The processing of each layer of the convolutional network can be thought of as a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on this input can be thought of as three-dimensional, with two spatial dimensions along the axes of the image and the third dimension capturing color information. The output of the convolutional connection can be thought of as forming a feature map in the subsequent layer, where each element in the feature map (e.g., 220) receives input from a certain range of neurons in the previous layer (e.g., feature map 218) and from each channel in the multiple channels. The values ​​in the feature map can be further processed with nonlinearities (such as correction, maximum value (max)(0,x)). The values ​​from neighboring neurons can be further pooled, which corresponds to downsampling and can provide additional local invariance and dimensionality reduction. Normalization corresponding to whitening can also be applied by lateral inhibition between neurons in the feature map.

[0052] The performance of deep learning architectures can increase as more labeled data points become available or as computing power increases. Modern deep neural networks are often trained with computing resources thousands of times greater than those available to typical researchers just fifteen years ago. New architectures and training paradigms can further improve deep learning performance. Rectified linear units can alleviate the training problem known as vanishing gradients. New training techniques can reduce overfitting and, therefore, enable larger models to achieve better generalization. Encapsulation techniques can extract data within a given receptive field and further improve overall performance.

[0053] Figure 3 3 is a block diagram illustrating a DCN 350. The DCN 350 may include multiple different types of layers based on connectivity and weight sharing. Figure 3 As shown, DCN 350 includes convolution blocks 354A and 354B. Each of convolution blocks 354A and 354B may be configured with a convolution layer (CONV) 356, a normalization layer (LNorm) 358, and a maximum pooling layer (MAX POOL) 360. Although only two of the convolution blocks 354A and 354B are shown, the present disclosure is not limited thereto, and any number of convolution blocks 354A and 354B may be included in DCN 350 according to design preferences.

[0054] The convolution layer 356 may include one or more convolution filters that may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filter. For example, the normalization layer 358 may provide whitening or lateral suppression. The max pooling layer 360 may provide spatial downsampling aggregation to achieve local invariance and dimensionality reduction.

[0055] For example, a parallel filter bank of a deep convolutional network can be loaded on the SOC 100 (e.g., Figure 1 ) on the CPU 102 or GPU 104 of the SOC 100 to achieve high performance and low power consumption. In an alternative embodiment, the parallel filter bank can be loaded onto the DSP 106 or ISP 116 of the SOC 100. In addition, the DCN 350 can access other processing blocks that may exist on the SOC 100, such as the sensor processor 114 and the navigation module 120 dedicated to sensors and navigation, respectively.

[0056] DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). DCN 350 may also include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of DCN 350 are weights (not shown) to be updated. The output of each layer (e.g., 356, 358, 360, 362, 364) can be used as input to a subsequent layer (e.g., 356, 358, 360, 362, 364) in DCN 350 to learn a hierarchical feature representation from input data 352 (e.g., images, audio, video, sensor data, and / or other input data) supplied to the first convolutional block in convolutional block 354A. The output of DCN 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is a probability that the input data includes a feature from a set of features.

[0057] Figure 4 is a block diagram illustrating an exemplary software architecture 400 that can modularize artificial intelligence (AI) functionality. According to aspects of the present disclosure, by using the architecture, a system on a chip (SOC) 420 (which can be similar to Figure 1 Various processing blocks (e.g., CPU 422, DSP 424, GPU 426, and / or NPU 428) of the SOC 100 support applications for tensor recomputation of artificial neural networks for the AI ​​application 402.

[0058] The AI ​​application 402 may be configured to call functions defined in the user space 404 that may, for example, provide detection and recognition of scenes indicating the current operating location of the device. For example, the AI ​​application 402 may configure the microphone and camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. The AI ​​application 402 may make a request for compiled program code associated with a library defined in the AI ​​function application programming interface (API) 406. The request may ultimately rely on the output of a deep neural network configured to provide an inferred response based on, for example, video and positioning data.

[0059] The runtime engine 408 (which may be compiled code of the runtime framework) may further be accessible to the AI ​​application 402. The AI ​​application 402 may cause the runtime engine 408 to request inference, for example, at specific time intervals or triggered by an event detected by a user interface of the AI ​​application 402. Upon causing the runtime engine 408 to provide an inference response, the runtime engine may in turn transmit a signal to the operating system in the operating system (OS) space (such as the Linux kernel 412) running on the SOC 420. The operating system may then cause continuous quantization relaxation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while the other processing blocks may be accessed through drivers (such as drivers 414, 416, or 418 for the DSP 424, GPU 426, or NPU 428, respectively). In the illustrative examples, the deep neural network may be configured to run on a combination of processing blocks such as CPU 422 , DSP 424 , and GPU 426 , or may run on NPU 428 .

[0060] Application 402 (e.g., an AI application) can be configured to call functions defined in user space 404, which can, for example, provide detection and recognition of a scene indicating the current operating location of the device. For example, application 402 can configure the microphone and camera differently depending on whether the identified scene is an office, a lecture hall, a restaurant, or an outdoor environment such as a lake. Application 402 can make a request to compiled program code associated with a library defined in a scene detection (SceneDetect) application programming interface (API) 406 to provide an estimate of the current scene. The request can ultimately rely on the output of a differential neural network configured to provide scene estimates based on, for example, video and positioning data.

[0061] The runtime engine 408 (which may be compiled code of the runtime framework) may further be accessible to the application 402. For example, the application 402 may cause the runtime engine to request scene estimation at specific time intervals or triggered by an event detected by the application's user interface. Upon causing the runtime engine to estimate the scene, the runtime engine may in turn transmit a signal to an operating system 410 (such as a Linux kernel 412) running on the SOC 420. The operating system 410 may in turn cause the calculation to be performed on the CPU 422, DSP 424, GPU 426, NPU 428, or some combination thereof. The CPU 422 may be directly accessible by the operating system, while the other processing blocks may be accessed through drivers (such as drivers 414-418 for the DSP 424, GPU 426, or NPU 428, respectively). In the illustrative example, the differential neural network may be configured to run on a combination of processing blocks (such as the CPU 422 and GPU 426), or may run on the NPU 428.

[0062] Aspects of the present disclosure relate to efficient tensor recomputation for artificial neural networks.

[0063] Given a directed acyclic graph (DAG), G = (V, E), where |V| = n and |E| = m, a node υ∈V can represent a computational operation, and a directed edge (u, v)∈E represents a data dependency, such that the output tensors of all nodes (predecessors of v) are must all exist in local memory before v is computed. Aspects of the present disclosure may determine a recomputation sequence (e.g., an ordered list) seq(G) of nodes, the recomputation sequence including each node at least once. The recomputation sequence seq(G) may be determined such that the total execution duration may be reduced and, in some aspects, minimized. The recomputation sequence seq(G) may be subject to a precedence constraint, wherein the determined sequence seq(G) satisfies the data dependencies of the DAGG. The recomputation sequence seq(G) may also be subject to a memory constraint, which limits the peak memory occupancy of the recomputation sequence seq(G) such that the peak memory occupancy is less than or equal to the local memory (e.g., tightly coupled memory) capacity M (e.g., 8MB).

[0064] Thus, aspects of the present disclosure provide an optimization model formulation that defines problem variables as hold intervals, allowing the use of only O(n) integer variables. Constraint programming (CP) can be utilized, allowing complex data dependencies and cumulative memory threshold constraints to be easily and efficiently enforced during optimization.

[0065] According to some aspects of the present disclosure, the output retention interval can model the duration or time interval for retaining the output of a node in local memory. For each node, Cv hold intervals, where each interval represents a recalculation (also called a "recalculation") of the node. The start time of the interval is and the end time of the interval The decision variables of the optimization problem can be modeled. Then, precedence constraints and memory constraints can be determined based on these decision variables. Therefore, determining which of the nodes to recompute can be solved numerically. Furthermore, a recomputation sequence seq(G) can be determined, which may include an order for executing nodes (including the recomputed nodes), based on the precedence constraints and memory constraints.

[0066] The term recalculation can be applied to the first time a node is computed and each subsequent time a node is computed. In some aspects, the number of times a node can be recalculated can be limited to C v times, so we define C for node υ v intervals. Therefore, the parameter C v can be considered as a hyperparameter.

[0067] Therefore, the hold interval for each node v∈V can be defined by the “start” and “end” times of the hold interval as: The domain is a set of integers of size O(n). v A block of memory may be allocated at the beginning of an interval and deallocated at the end of the interval.

[0068] Figure 5 is an example graph 500 illustrating the tradeoff between memory utilization and computation time according to certain aspects of the present disclosure. Figure 5 As shown in the example of , when no recomputation is performed, the computation time for computing the sequence of nodes of the computation graph may be low, but the tightly coupled memory (e.g., Figure 1 Peak memory usage of the memory 118 of the SOC 100 shown in FIG. 5 may increase (as shown by line 502). On the other hand, when heavy computations are performed, memory usage may be reduced (as shown by line 504) at the expense of a significant increase (e.g., almost doubling) in computation time.

[0069] Figure 6A is a diagram illustrating an example computation graph 600 according to various aspects of the present disclosure. Figure 6A , the example computation graph may include four nodes (labeled 1 to 4). Figure 6A Four nodes are shown in the example of , but the present disclosure is not limited thereto and may include any number of nodes.

[0070] Nodes can be coupled via edges (as indicated by arrows between nodes). Each edge and the direction of the arrows can indicate a dependency between the nodes. For example, edge 602 can indicate that the operation of node 2 depends on the output of node 1. In another example, edge 604 and edge 606 can indicate that the operation of node 4 depends on the output of node 1 and the output of node 3, respectively.

[0071] Figure 6B is an example of a method for performing various aspects of the present disclosure. Figure 6A 6. A diagram 650 of example hold intervals for example computation graph 600 is shown. A set of potential node execution events for executing nodes 1 through 4 of example computation graph 600 is shown. According to some aspects of the present disclosure, a hold interval (e.g., 652a through 652d) may be determined for executing each of the nodes. Figure 6B In the example of FIG, four holding intervals are shown; however, this is only for the convenience of illustration and not for limitation. Instead, it should be understood that any number of holding intervals can be determined based on the nodes of the computation graph.

[0072] For each hold interval (e.g., 652a through 652d), the first time slot (shown using filled event circles) may indicate computation of node v, while the remainder of the hold interval (e.g., 652a through 652d) may indicate that the output of node v is held in memory (e.g., Figure 1 18). Other event circles shown with pattern fills (e.g., event 2) may indicate that no hold interval started at that particular time (e.g., no computation occurred). However, the determination of the node execution event is a byproduct of the optimization problem and may not be known in advance.

[0073] like Figure 6B As shown in the example of , node 1 can be computed during event 1. Because the operation of node 2 depends on the output of node 1, the node 1 output can be kept in memory until event 3. At event 3, node 2 can be executed, and the node 2 output can be kept in memory until event 6.

[0074] After event 3, the node 1 output can be discarded. However, because the operation of node 4 also depends on the node 1 output, the node 1 output can be recalculated. The second interval for node 1 can start at event 7, indicating that node 1 is recalculated during event 7.

[0075] Event 1 can have a memory usage of m1. On the other hand, because the operation of node 4 depends on the output of node 3, the output of node 3 can also be kept in memory when node 1 is recalculated. Therefore, event 7 can have a memory usage of m1+m3.

[0076] The total duration of a recomputation sequence can be a weighted sum of the events in which the node is being executed, where the weights can be the actual duration of the node (e.g., in seconds or processor cycles). The peak memory usage can then be the maximum memory usage among all events. Thus, if each node outputs a unit-size tensor, then Figure 6B The peak memory usage of the solution in can be achieved at event 10, where the node 1 output and the node 3 output are kept in memory during the execution of node 4.

[0077] In addition to holding the start and end times of the intervals (e.g., 652a through 652d), the Boolean variable It can be defined to model whether the node v is active or inactive for the i-th interval. Therefore, flexibility can be provided in the number of times the node v is recalculated (for example, it may not be exactly C υ times). If node v is inactive (e.g., ), then the corresponding hold interval may not contribute to the total execution duration in the recomputation purpose and the sum in the memory constraint and precedence constraint. v and node output size m v may be unknown. Using the hold interval as a basis, the recomputation problem can be specified as follows:

[0078]

[0079] The purpose of the definition in Equation 1 is to execute the computation graph (e.g., Figure 6A The total duration of the computation graph 600). Equation 2 is a constraint that forces the end time of each interval to arrive after its start time. Equation 3 is a constraint that ensures that the hold intervals for the same node do not overlap. Equation 4 specifies the memory constraint (which can be called a memory budget), where the parameter t represents time. Equation 5 specifies the memory budget for all predecessor nodes of node v at all start times of v. Priority constraints for overlapping intervals and active intervals are enforced. Therefore, memory constraints and priority constraints can be nonlinear constraints. Equation 6 is a constraint that specifies that the start times of the intervals are all different (e.g., the computation events do not overlap). Equation 7 provides a constraint that specifies that the first hold interval for each node is active. Equation 8 provides a constraint that specifies the start time for each active interval of node v. and end time

[0080] variable The domain can be defined as follows:

[0081]

[0082] where Σ v C v Equal to the number of intervals, whose upper limit can be |D|≤nmax v C v .

[0083] The memory constraint specified in Equation 4 can limit resource usage to the local memory budget M (e.g., capacity) at time t. In some aspects, the memory constraint is expressed in terms of the variable This type of inequality can be modeled using constraint programming (CP) cumulative constraints.

[0084] refer to Figure 6B , the memory constraint (e.g., Equation 4) can limit the peak memory usage at each execution event to be less than the local memory budget M. That is, the node output size m for each hold interval at such execution event v The sum of is less than or equal to M.

[0085] As described, the precedence constraint of Equation 5 stipulates that before executing each computation task (e.g., executing a node), the outputs of all predecessor nodes of the node must be available in memory. Figure 6A The edges shown in (e.g., indicated by 602) can be modeled as resource pool (reservoir) constraints from constraint programming. For example, each predecessor node (e.g., node 1 is a predecessor node of node 2 and node 4) can be considered as a resource whose level must be maintained so that the resource does not go below zero while its successor node is being executed.

[0086] For each edge (u,v)∈E and {1,…,C v The resource level change event f(·) of} can be defined as follows:

[0087]

[0088] In addition to those functions in Formula 10, the level change function f(·) may return to zero at every other time point.

[0089] Thus, aspects of the present disclosure provide flexibility that allows for solutions that are not limited to a predetermined topological ordering. However, in some aspects, a topological ordering of the input can be enforced to reduce the size of the search space and, in turn, reduce the solution time for determining the hold interval.

[0090] For example, consider the integer variable The new domain:

[0091]

[0092] where the domain size in this example is O(n 2 ) instead of O(n). The determination of the maintenance interval can be performed in stages. The jth stage can include j events. Given a topological ordering of the nodes, the first stage can enforce the calculation of the first node in that order. In subsequent stages, the jth node in the input topological order can be forced to be calculated in the last event of stage j, while the previous events in stage j allow nodes 1,…,(j-1) to be calculated. That is, a constraint that node j can be calculated only in event j of stage can be applied. Because such a constraint can limit the start time of each interval to a specific event, the constraint in Formula 6 can be eliminated.

[0093] Therefore, the start time of the first hold interval for each node can no longer be a variable, but a fixed value. More precisely, for node v, The value of can be equal to j(j+1) / 2, where j is the index of node v in the input topological sort.

[0094] In some aspects, the hold interval can be determined in two stages. In stage 1, a variation of the optimization problem specified in equations 1 to 8 can be solved to find a memory-feasible solution. The solution to stage 1 can then be used as an initialization for stage 2, which is the optimization problem specified in equations 1 to 8. The problem in stage 1 has the purpose:

[0095]

[0096] in is the peak memory usage. For phase 1, the memory constraint in Equation 4 can be modified as follows:

[0097]

[0098] One goal of phase 1 can be to determine an intermediate solution where the peak memory usage is below the local memory target M. This goal can be achieved by considering the peak memory variable M var and the maximum value of the memory budget M as the goal. This goal can be achieved by introducing an auxiliary variable And then consider the condition that τ≥M var The linearization is performed by minimizing τ and τ ≥ M. The other constraints of the optimization problem described in Formulas 1 to 8 may remain unchanged.

[0099] Figure 77 is a flowchart illustrating a processor-implemented method 700 for tensor recomputation in an artificial neural network (ANN) according to various aspects of the present disclosure. For example, the processor-implemented method 700 may be performed by one or more processors such as a CPU (e.g., 102, 422), a GPU (e.g., 104, 426), and / or other processing units (e.g., a DSP 424 or an NPU 428). In some aspects, the processor-implemented method 700 may be implemented in a compiler.

[0100] like Figure 7 As shown, at block 702, the processor receives a graph representing an ANN. In some aspects, the graph may comprise a DAG. The graph comprises a plurality of nodes connected by edges. Each node represents an operation. As described, a node v∈V may represent a computational operation, and a directed edge (u,v)∈E may represent a data dependency such that the output tensors of all nodes (predecessors of v) are All must exist in local memory before v is calculated.

[0101] At block 704, the processor determines retention intervals for the nodes based on the priority constraints for the nodes. These retention intervals correspond to time intervals for retaining each node output in local memory. As described, the output retention interval can model the duration or time interval for retaining the output of a node in local memory. For each node, C v hold intervals, where each hold interval may represent a recalculation (also referred to as a "recalculation") of the node.

[0102] At block 706, the processor determines a node in the nodes to recalculate based on the retention interval. For example, as described, the start time of the interval and the end time of the interval The decision variables can be modeled as an optimization problem. Then, the precedence constraints and memory constraints can be determined based on these decision variables. Therefore, determining which nodes in the node to recompute can be solved numerically.

[0103] Specific implementation examples are provided in the following numbered clauses.

[0104] 1. A processor-implemented method executed by at least one processor, the method comprising:

[0105] receiving, by the at least one processor, a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation;

[0106] The at least one processor determines a hold interval for the plurality of nodes based on precedence constraints for the plurality of nodes, the hold interval corresponding to a time interval for holding each node output in a local memory; and the at least one processor determines a node to be recomputed among the plurality of nodes based on the hold interval.

[0107] 2. The processor-implemented method of clause 1 , further comprising determining, by the at least one processor, an execution order of the plurality of nodes based on the precedence constraint and the memory constraint.

[0108] 3. A processor-implemented method according to clause 1 or 2, further comprising:

[0109] The precedence constraint is determined, by the at least one processor, for each node of the plurality of nodes based on the hold interval.

[0110] 4. The processor-implemented method of any of clauses 1 to 3, further comprising determining, by the at least one processor, the memory constraint based on a physical memory capacity of the local memory and the retention interval.

[0111] 5. The processor-implemented method of any of clauses 1 to 4, wherein the hold interval is determined based on a recomputation constraint defining a number of times the node is allowed to be recomputation.

[0112] 6. The processor-implemented method of any of clauses 1 to 5, wherein the precedence constraint is determined based on the edges connecting the plurality of nodes.

[0113] 7. The processor-implemented method of any of clauses 1 to 6, wherein the local memory comprises a tightly coupled memory.

[0114] 8. A device comprising:

[0115] global memory; and

[0116] at least one processor coupled to the global memory, the at least one processor configured to:

[0117] receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation;

[0118] determining a retention interval for the plurality of nodes based on the precedence constraints for the plurality of nodes, the retention interval corresponding to a time interval for retaining each node output in a local memory; and

[0119] Nodes to be recalculated among the plurality of nodes are determined based on the holding interval.

[0120] 9. The apparatus of clause 8, wherein the at least one processor is further configured to determine an execution order of the plurality of nodes based on the precedence constraint and a memory constraint.

[0121] 10. The apparatus of clause 8 or 9, wherein the at least one processor is further configured to determine a second priority constraint for each node of the plurality of nodes based on the hold interval.

[0122] 11. The apparatus of any of clauses 8 to 10, wherein the at least one processor is further configured to determine the memory constraint based on a physical memory capacity of the local memory and the retention interval.

[0123] 12. The apparatus of any of clauses 8 to 11, wherein the at least one processor is further configured to determine the holding interval based on a recomputation constraint, the recomputation constraint defining a number of times the node is allowed to be recomputation.

[0124] 13. The apparatus of any of clauses 8 to 12, wherein the at least one processor is further configured to determine the precedence constraint based on the edges connecting the plurality of nodes.

[0125] 14. An apparatus as recited in any of clauses 8 to 13, wherein the local memory comprises a tightly coupled memory.

[0126] 15. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising:

[0127] program code for receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation;

[0128] program code for determining a hold interval for the plurality of nodes based on precedence constraints for the plurality of nodes, the hold interval corresponding to a time interval for holding each node output in local memory; and

[0129] Program code is provided for determining a node of the plurality of nodes to recompute based on the hold interval.

[0130] 16. The non-transitory computer-readable medium of clause 15, wherein the program code further comprises program code for determining an execution order of the plurality of nodes based on the precedence constraint and a memory constraint.

[0131] 17. The non-transitory computer-readable medium of clause 15 or 16, wherein the program code further comprises program code for determining a second precedence constraint for each node of the plurality of nodes based on the hold interval.

[0132] 18. The non-transitory computer-readable medium of any of clauses 15 to 17, wherein the program code further comprises program code for determining the memory constraint based on a physical memory capacity of the local memory and the retention interval.

[0133] 19. The non-transitory computer-readable medium of any one of clauses 15 to 18, wherein the program code further comprises program code for determining the hold interval based on a recalculation constraint defining a number of times the node is permitted to be recalculated.

[0134] 20. The non-transitory computer-readable medium of any one of clauses 15 to 19, wherein the program code further comprises program code for determining the precedence constraint based on the edges connecting the plurality of nodes.

[0135] 21. The non-transitory computer-readable medium of any of clauses 15 to 20, wherein the local memory comprises a tightly coupled memory.

[0136] 22. A device comprising:

[0137] means for receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation;

[0138] means for determining a retention interval for the plurality of nodes based on the precedence constraints for the plurality of nodes, the retention interval corresponding to a time interval for retaining each node output in a local memory; and

[0139] Means for determining a node of the plurality of nodes to recalculate based on the hold interval.

[0140] 23. The apparatus of clause 22, further comprising means for determining an execution order of the plurality of nodes based on the precedence constraint and a memory constraint.

[0141] 24. The apparatus of clause 22 or 23, further comprising means for determining a second precedence constraint for each node of the plurality of nodes based on the hold interval.

[0142] 25. The apparatus of any of clauses 22 to 24, further comprising means for determining the memory constraint based on a physical memory capacity of the local memory and the retention interval.

[0143] 26. The apparatus of any of clauses 22 to 25, further comprising means for determining the hold interval based on a recalculation constraint, the recalculation constraint defining a number of times the node is allowed to be recalculated.

[0144] 27. The apparatus of any of clauses 22 to 26, further comprising means for determining the precedence constraint based on the edges connecting the plurality of nodes.

[0145] 28. An apparatus as recited in any of clauses 22 to 28, wherein the local memory comprises a tightly coupled memory.

[0146] In one aspect, the receiving means, the means for determining the hold interval, and / or the means for determining the node to recalculate from among the plurality of nodes may be the GPU 104, program memory associated with the GPU 104, the fully connected layer 362, the NPU 428, and / or the routing connection processing unit 216 configured to perform the recited functions. In another configuration, the aforementioned means may be any module or any device configured to perform the functions recited by the aforementioned means.

[0147] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions. These means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally speaking, where operations are illustrated in the accompanying drawings, these operations may have corresponding paired means-plus-function components with similar numbers.

[0148] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determining" may include resolving, selecting, choosing, establishing, etc.

[0149] As used, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc.

[0150] The various illustrative logical blocks, modules, and circuits described in conjunction with this disclosure may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic components, discrete hardware components, or any combination thereof, designed to perform the functions described. While a general purpose processor may be a microprocessor, in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0151] The steps or algorithms of the methods described in conjunction with the present disclosure may be directly embodied in hardware, a software module executed by a processor, or a combination of the two. The software module may reside in any form of storage medium known in the art. Some examples of usable storage media include random access memory (RAM), read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs, and the like. The software module may include a single instruction, perhaps multiple instructions, and may be distributed over several different code segments, distributed between different programs, and distributed across multiple storage media. A storage medium may be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral with the processor.

[0152] The disclosed methods include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0153] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a device. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link various circuits together, including a processor, a machine-readable medium, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., a keypad, a display, a mouse, a joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0154] The processor may be responsible for managing the bus and general processing, including executing software stored on the machine-readable medium. The processor may be implemented using one or more general-purpose processors and / or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuits that can execute software. Software should be broadly interpreted to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or other. By way of example, the machine-readable medium may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable medium may be embodied in a computer program product. The computer program product may include packaging materials.

[0155] In a hardware implementation, the machine-readable medium may be part of a processing system separate from the processor. However, as will be readily appreciated by those skilled in the art, the machine-readable medium or any portion thereof may be external to the processing system. By way of example, the machine-readable medium may include a transmission line, a carrier modulated by data, and / or a computer product separate from the device, all of which may be accessed by the processor via a bus interface. Alternatively or in addition, the machine-readable medium or any portion thereof may be integrated into the processor, such as in the case of a cache and / or general register file. Although the various components discussed may be described as having specific locations, such as local components, they may also be configured in various ways, such as with certain components being configured as part of a distributed computing system.

[0156] The processing system can be configured as a general processing system having one or more microprocessors providing processor functionality and external memory providing at least a portion of a machine-readable medium, all of which are linked together with other support circuits via an external bus architecture. Alternatively, the processing system may include one or more neuromorphic processors for implementing the described neuron model and neural system model. As another alternative, the processing system may be implemented with an application-specific integrated circuit (ASIC) having a processor, bus interface, user interface, support circuits, and at least a portion of a machine-readable medium integrated in a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic components, discrete hardware components, or any other suitable circuits, or any combination of circuits that can perform the various functionalities described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0157] The machine-readable medium may include multiple software modules. These software modules include instructions that, when executed by a processor, cause a processing system to perform various functions. The software modules may include a sending module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, when a triggering event occurs, a software module may be loaded from a hard drive into RAM. During execution of the software module, the processor may load some of the instructions into a cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When reference is made below to the functionality of a software module, it will be understood that such functionality is implemented by the processor when executing instructions from the software module. Furthermore, it should be understood that various aspects of the present disclosure result in improvements to the functionality of a processor, computer, machine, or other system implementing such aspects.

[0158] If implemented in software, each function may be stored as one or more instructions or codes on or sent through a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other media that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is also appropriately referred to as a computer-readable medium. For example, if the software is sent from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. As used, disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVDs), floppy disks, and optical disks. (Blu- ) optical disks, where magnetic disks typically reproduce data magnetically, while optical disks reproduce data optically using lasers. Thus, in some aspects, computer-readable media may include non-transitory computer-readable media (e.g., tangible media). Moreover, for other aspects, computer-readable media may include transitory computer-readable media (e.g., signals). Combinations of the above should also be included within the scope of computer-readable media.

[0159] Thus, some aspects may include a computer program product for performing the operations presented. For example, such a computer program product may include a computer-readable medium having stored (and / or encoded) thereon instructions, the instructions being executable by one or more processors to perform the described operations. For some aspects, the computer program product may include packaging materials.

[0160] In addition, it should be understood that the modules and / or other appropriate components for performing the described methods and techniques can be downloaded and / or otherwise obtained by the user terminal and / or base station where applicable. For example, such a device can be coupled to a server to facilitate the delivery of components for performing the described methods. Alternatively, the various methods described can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or a floppy disk, etc.) so that once the storage component is coupled to or provided to the device, the user terminal and / or base station can obtain the various methods. In addition, any other suitable technology for providing the described methods and techniques to the device can be utilized.

[0161] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A processor-implemented method executed by at least one processor, the method comprising: receiving, by the at least one processor, a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation; determining, by the at least one processor, a retention interval for the plurality of nodes based on precedence constraints for the plurality of nodes, the retention interval corresponding to a time interval for retaining each node output in a local memory; as well as A node of the plurality of nodes to recompute is determined by the at least one processor based on the hold interval. 2 . The processor-implemented method of claim 1 , further comprising determining, by the at least one processor, an execution order of the plurality of nodes based on the precedence constraint and a memory constraint. 3 . The processor-implemented method of claim 2 , further comprising determining, by the at least one processor, the precedence constraint for each of the plurality of nodes based on the hold interval.

4. The processor-implemented method of claim 2, further comprising determining, by the at least one processor, the memory constraint based on a physical memory capacity of the local memory and the retention interval. 5 . The processor-implemented method of claim 1 , wherein the hold interval is determined based on a recomputation constraint that defines a number of times the node is allowed to be recomputational. The processor-implemented method of claim 1 , wherein the precedence constraint is determined based on the edges connecting the plurality of nodes.

7. The processor-implemented method of claim 1, wherein the local memory comprises a tightly coupled memory.

8. A device comprising: Global memory; and at least one processor coupled to the global memory, the at least one processor configured to: receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation; determining a retention interval for the plurality of nodes based on precedence constraints for the plurality of nodes, the retention interval corresponding to a time interval for retaining each node output in a local memory; as well as Nodes to be recalculated among the plurality of nodes are determined based on the holding interval. 9 . The apparatus of claim 8 , wherein the at least one processor is further configured to determine an execution order of the plurality of nodes based on the precedence constraint and a memory constraint. 10 . The apparatus of claim 9 , wherein the at least one processor is further configured to determine a second precedence constraint for each node of the plurality of nodes based on the hold interval.

11. The apparatus of claim 9, wherein the at least one processor is further configured to determine the memory constraint based on a physical memory capacity of the local memory and the retention interval.

12. The apparatus of claim 8, wherein the at least one processor is further configured to determine the hold interval based on a recomputation constraint defining a number of times the node is allowed to be recomputation. 13 . The apparatus of claim 8 , wherein the at least one processor is further configured to determine the precedence constraint based on the edges connecting the plurality of nodes. The apparatus of claim 8 , wherein the local memory comprises a tightly coupled memory.

15. A non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code for receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation; program code for determining a hold interval for the plurality of nodes based on a precedence constraint for the plurality of nodes, the hold interval corresponding to a time interval for holding each node output in a local memory; and Program code is provided for determining a node of the plurality of nodes to recompute based on the hold interval.

16. The non-transitory computer readable medium of claim 15, wherein the program code further comprises program code for determining an execution order of the plurality of nodes based on the precedence constraint and a memory constraint. 17 . The non-transitory computer readable medium of claim 16 , wherein the program code further comprises program code to determine a second precedence constraint for each node of the plurality of nodes based on the hold interval.

18. The non-transitory computer readable medium of claim 16, wherein the program code further comprises program code to determine the memory constraint based on a physical memory capacity of the local memory and the retention interval.

19. The non-transitory computer readable medium of claim 15, wherein the program code further comprises program code for determining the hold interval based on a recalculation constraint, the recalculation constraint defining a number of times the node is allowed to be recalculated.

20. The non-transitory computer readable medium of claim 15, wherein the program code further comprises program code for determining the precedence constraint based on the edges connecting the plurality of nodes.

21. The non-transitory computer-readable medium of claim 15, wherein the local memory comprises a tightly coupled memory.

22. A device comprising: means for receiving a graph representing an artificial neural network (ANN), the graph comprising a plurality of nodes connected by edges, and each node representing an operation; means for determining a retention interval for the plurality of nodes based on a precedence constraint for the plurality of nodes, the retention interval corresponding to a time interval for retaining each node output in a local memory; and Means for determining a node of the plurality of nodes to recalculate based on the hold interval.

23. The apparatus of claim 22, further comprising means for determining an execution order of the plurality of nodes based on the precedence constraint and a memory constraint.

24. The apparatus of claim 23, further comprising means for determining a second precedence constraint for each of the plurality of nodes based on the hold interval.

25. The apparatus of claim 23, further comprising means for determining the memory constraint based on a physical memory capacity of the local memory and the retention interval.

26. The apparatus of claim 22, further comprising means for determining the hold interval based on a recomputation constraint, the recomputation constraint defining a number of times the node is allowed to be recomputation.

27. The apparatus of claim 22, further comprising means for determining the precedence constraint based on the edges connecting the plurality of nodes.

28. The apparatus of claim 22, wherein the local memory comprises a tightly coupled memory.

Images