Semiconductor device

Abstract

A semiconductor device includes a transistor portion and a diode portion, the transistor portion including a first gate trench portion provided closest to the diode portion, and a first mesa portion provided in contact with the first gate trench portion and between the first gate trench portion and the diode portion. A first floating region is provided below the first gate trench portion, and the first mesa portion has a non-coverage region that does not overlap the first floating region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there are known semiconductor devices including transistors such as insulated gate bipolar transistors (IGBTs) (see, for example, Patent Documents 1 to 4).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent No. 6472714 Patent Document 2: Japanese Patent No. 4456013 Patent Document 3: Japanese Patent Application Laid-Open No. 2020-21941 Patent Document 4: Japanese Patent Application Laid-Open No. 2010-232627 Summary of the Invention

[0004] Technical issues In a semiconductor device, it is preferable to suppress a voltage snapback phenomenon.

[0005] Technical Solution To address the above-mentioned issues, one embodiment of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and including a drift region of a first conductivity type. Any of the semiconductor devices may include one or more transistor sections, each of which includes a collector region of a second conductivity type provided on the lower surface of the semiconductor substrate. Any of the semiconductor devices may include one or more diode sections, each of which includes a cathode region of a first conductivity type provided on the lower surface of the semiconductor substrate and arranged alternately with the transistor sections in a first direction. In any of the semiconductor devices, each of the transistor sections may include a plurality of trench sections, the plurality of trench sections being arranged side by side along the first direction and including one or more gate trench sections. In any of the semiconductor devices, each of the transistor sections may include a plurality of mesa sections, the plurality of mesa sections being regions sandwiched between the trench sections in the first direction. In any of the semiconductor devices, each of the transistor sections may include a floating region of the second conductivity type, the second conductive type being provided relative to at least one of the gate trench sections and below the lower end of the gate trench section. In any of the aforementioned semiconductor devices, the one or more gate trench portions may include a first gate trench portion disposed closest to the diode portion. In any of the aforementioned semiconductor devices, the plurality of mesa portions may include a first mesa portion that contacts the first gate trench portion and is disposed between the first gate trench portion and the diode portion. In any of the aforementioned semiconductor devices, a first floating region may be disposed below the first gate trench portion. In any of the aforementioned semiconductor devices, the first mesa portion may include a non-overlapping region that does not overlap with the first floating region.

[0006] In any of the aforementioned semiconductor devices, the plurality of trenches may include one or more dummy trenches. In any of the aforementioned semiconductor devices, the first mesa portion may be sandwiched between the first gate trench and the first dummy trench. In any of the aforementioned semiconductor devices, the first floating region disposed below the lower end of the first gate trench may not extend below the lower end of the first dummy trench.

[0007] In any of the above semiconductor devices, the first floating region may not be in contact with the first dummy trench portion when viewed from above.

[0008] In any of the above semiconductor devices, the plurality of trench portions may include a second dummy trench portion, the second dummy trench portion being arranged on a side of the first gate trench portion opposite to the first dummy trench portion. In any of the above semiconductor devices, a distance between the first floating region and the second dummy trench portion in the first direction may be smaller than a distance between the first floating region and the first dummy trench portion.

[0009] In any of the above semiconductor devices, the first floating region may be in contact with the second dummy trench portion in a plan view.

[0010] In any of the above-mentioned semiconductor devices, the first mesa portion may include an emitter region of a first conductivity type, the emitter region of the first conductivity type being arranged in contact with the upper surface of the semiconductor substrate. In any of the above-mentioned semiconductor devices, the first mesa portion may include a base region of a second conductivity type, the base region of the second conductivity type being arranged between the emitter region and the drift region. In any of the above-mentioned semiconductor devices, the first mesa portion may have a long side in the second direction. In any of the above-mentioned semiconductor devices, the first mesa portion may include the non-covered region in an intermediate region between both ends of the emitter region in the second direction.

[0011] In the middle region of any of the above-mentioned semiconductor devices, a plurality of the non-covered regions may be discretely arranged along the second direction.

[0012] In the middle region of any of the above semiconductor devices, a total length of the plurality of non-covered regions in the second direction may be smaller than a total length of regions overlapping the first floating region in the second direction.

[0013] In any of the aforementioned semiconductor devices, the first mesa portion may include a contact region of the second conductivity type, the contact region of the second conductivity type being arranged in contact with the upper surface of the semiconductor substrate and being arranged alternately with the emitter regions in the second direction. In any of the aforementioned semiconductor devices, the first floating region may be arranged below at least one of the emitter regions, with at least a portion of the contact region being the non-covered region.

[0014] In any of the above semiconductor devices, the first floating region may overlap with the entirety of at least one of the emitter regions. In any of the above semiconductor devices, the non-covered region may be provided in each of the contact regions.

[0015] Any of the above-mentioned semiconductor devices may include a well region of the second conductivity type, the well region of the second conductivity type being arranged outside the first mesa portion in the second direction and having a concentration higher than that of the base region. Any of the above-mentioned semiconductor devices may include a first extension region of the second conductivity type, the first extension region of the second conductivity type extending from the well region along the second direction to a position overlapping the emitter region.

[0016] In any of the above semiconductor devices, the well region may be further arranged outside the emitter region in the first direction. Any of the above semiconductor devices may include a second extension region of a second conductivity type, the second extension region of the second conductivity type extending from the well region along the first direction to a position overlapping the emitter region.

[0017] In any of the aforementioned semiconductor devices, the diode portion may include: a plurality of dummy trench portions arranged side by side along the first direction; and a mesa portion sandwiched between the dummy trench portions in the first direction. In any of the aforementioned semiconductor devices, the floating region may also be provided below the lower end of at least one of the dummy trench portions in the diode portion.

[0018] In any of the semiconductor devices described above, a period at which the floating regions are provided along the first direction in the diode portion may be the same as a period at which the floating regions are provided along the first direction in the transistor portion.

[0019] The transistor portion of any of the aforementioned semiconductor devices may include a boundary region between the first gate trench portion and the diode portion, the boundary region including one or more trench portions and one or more mesa portions. In any of the aforementioned semiconductor devices, the floating region may also be provided below a lower end of at least one of the trench portions in the boundary region.

[0020] In any of the semiconductor devices described above, a period of providing the floating regions along the first direction in the boundary region may be the same as a period of providing the floating regions along the first direction in the transistor portion excluding the boundary region.

[0021] In any of the above-described semiconductor devices, an area of ​​the non-covered region in the first mesa portion may be larger than an area of ​​a region of the mesa portion that contacts the gate trench portion other than the first gate trench portion and does not overlap with the floating region.

[0022] The above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 11 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0024] Figure 2 yes Figure 1 Magnified view of area D in FIG.

[0025] Figure 3 It shows Figure 2 A diagram of an example of the ee cross section in .

[0026] Figure 4 1 is a diagram showing an example of the arrangement of the floating region 202 in a plan view.

[0027] Figure 5 1 is a diagram showing another example of arrangement of the floating region 202 in a plan view.

[0028] Figure 6 It is a diagram showing another example of the ee cross section.

[0029] Figure 7 It is a diagram showing another example of the ee cross section.

[0030] Figure 8 1 is a plan view showing an example of the transition region 92 .

[0031] Figure 9 It shows Figure 8 FIG. 1 is a diagram showing an example of an ff cross section.

[0032] Figure 10 1 is an XZ cross section showing another structural example of the boundary region 90 and the diode portion 80 .

[0033] Figure 11 Graphs showing collector voltage-collector current characteristics in Examples and Reference Examples.

[0034] Figure 12 Graphs showing trade-off characteristics between conduction loss and reverse recovery dV / dt in a reference example and an embodiment.

[0035] Explanation of symbols 10···Semiconductor substrate, 11···Well region, 12···Emitter region, 14···Base region, 15···Contact region, 16···Accumulation region, 18···Drift region, 20···Buffer region, 21···Upper surface, 22···Collector region, 23···Lower surface, 24···Collector electrode, 29···Straight line portion, 30···Dummy trench portion, 30-1···First dummy Groove portion, 30-2···Second dummy groove portion, 31···Front end portion, 32···Dummy insulating film, 33···Lower end, 34···Dummy conductive portion, 38···Interlayer insulating film, 39···Straight portion, 40···Gate groove portion, 40-1···First gate groove portion, 41···Front end portion, 42···Gate insulating film, 43···Lower end, 44···Gate conductive portion Transistor portion, 45···trench, 52···emitter electrode, 54···contact portion, 60, 61, 62, 63···mesa portion, 60-1···first mesa portion, 60-2···second mesa portion, 70···transistor portion, 80···diode portion, 81···extension region, 82···cathode region, 90···boundary region, 92···transition region, 100···semiconductor device , 130···peripheral gate wiring, 131···active side gate wiring, 160···active portion, 162···end side, 164···gate pad, 190···edge terminal structure portion, 202···floating region, 202-1···first floating region, 204···first extension region, 212···non-covered region, 220···second extension region, 221···insulating film DETAILED DESCRIPTION

[0036] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the technical aspects of the invention.

[0037] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." One of the two principal surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation when a semiconductor device is mounted.

[0038] In this specification, the X-axis, Y-axis, and Z-axis are sometimes used to describe technical matters. These axes simply determine the relative positions of components and do not define specific directions. For example, the Z-axis is not limited to indicating the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is specified without specifying a positive or negative sign, it refers to a direction parallel to the +Z and -Z axes.

[0039] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0040] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side.

[0041] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0042] In this specification, the conductivity type of the impurity-doped region is described as P-type or N-type. In this specification, the term "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to produce an N-type or P-type semiconductor.

[0043] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions in a manner that includes the polarity of the charge. As an example, if the donor concentration is N D And the acceptor concentration is set to N A , then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0044] In this specification, the term "P+ type" or "N+ type" refers to a higher doping concentration than that of the P-type or N-type. In the case of "P-type" or "N-type", it means a lower doping concentration than that of the P-type or N-type. In addition, the term "P++ type" or "N++ type" refers to a higher doping concentration than that of the P+ type or N+ type. The units used in this specification are SI units unless otherwise specified. Although cm is sometimes used to represent the unit of length, calculations can be performed after conversion to meters (m).

[0045] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be set to a value in thermal equilibrium. In addition, in the N-type region, since the donor concentration is sufficiently greater than the acceptor concentration, the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the doping concentration of the N-type region is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0046] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor, or net doping in the region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in the region can be used as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in at ms / cm 3 or / cm 3 This unit is used for the concentration of donors or acceptors, or chemical concentrations, within a semiconductor substrate. The word "atoms" can be omitted.

[0047] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. In the current flow range used to measure diffusion resistance, the carrier mobility of a semiconductor substrate may be lower than that of a crystalline state. This reduction in carrier mobility is caused by carrier scattering due to disorder in the crystal structure caused by lattice defects and other factors.

[0048] The donor or acceptor concentration calculated from carrier concentrations measured by CV or SR methods can be lower than the chemical concentration of the element representing the donor or acceptor. For example, the donor concentration of phosphorus or arsenic, which act as donors, or the acceptor concentration of boron, which acts as an acceptor, in a silicon semiconductor is approximately 99% of their chemical concentrations. Meanwhile, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0049] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0050] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, the term "viewed from above" refers to the state viewed from the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two sets of edges 162 that are opposite to each other when viewed from above. Figure 1 In FIG. 1 , the X-axis and the Y-axis are parallel to any one of the end sides 162. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0051] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160. Figure 1 The active portion 160 may refer to a region that overlaps with the emitting electrode in a plan view. In addition, a region sandwiched between the active portions 160 in a plan view may also be included in the active portion 160.

[0052] The active portion 160 includes a transistor portion 70 including transistor elements such as an IGBT (Insulated Gate Bipolar Transistor). The active portion 160 also includes a diode portion 80 including diode elements such as a freewheeling diode (FWD). Figure 1 In this example, transistor portions 70 and diode portions 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0053] exist Figure 1 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". In this specification, the direction perpendicular to the arrangement direction in a plan view is sometimes referred to as the extension direction (in Figure 1 The Y-axis direction is the Y-axis direction in the figure). The transistor portion 70 and the diode portion 80 may each have a long side in the direction in which they extend. That is, the length of the transistor portion 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each trench portion described later.

[0054] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in an area other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0055] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor portion 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0056] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is positioned near edge 162. The area near edge 162 refers to the area between edge 162 and the emitter electrode when viewed from above. When semiconductor device 100 is mounted, each pad can be connected to an external circuit via wiring such as a wire.

[0057] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 to the gate trench portion. Figure 1 In FIG, the gate wiring is marked with oblique hatching.

[0058] The gate wiring of this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region, described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region when viewed from above can be considered the active portion 160.

[0059] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 can be a metal wiring containing aluminum or the like.

[0060] The active-side gate wiring 131 is provided in the active portion 160 . By providing the active-side gate wiring 131 in the active portion 160 , it is possible to reduce variations in wiring length from the gate pad 164 in each region of the semiconductor substrate 10 .

[0061] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 can be formed of a semiconductor such as polysilicon doped with impurities.

[0062] The active-side gate wiring 131 can be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 is provided so as to extend along the X-axis direction from the peripheral gate wiring 130 on one side sandwiching the active portion 160 to the peripheral gate wiring 130 on the other side, so as to cross the active portion 160 approximately at the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0063] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) which simulates the operation of a transistor portion provided in the active portion 160 .

[0064] The semiconductor device 100 of this embodiment includes an edge termination structure 190 between the active portion 160 and the edge 162 in a plan view. In this embodiment, the edge termination structure 190 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 190 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 190 can include at least one of a guard ring, a field plate, and a surface electric field reducer, disposed in an annular shape surrounding the active portion 160.

[0065] Figure 2 yes Figure 1 is an enlarged view of region D in FIG. Region D includes the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, all disposed within the upper surface of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131, both disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0066] An interlayer insulating film is provided between the emitter electrode 52, the active-side gate wiring 131, and the upper surface of the semiconductor substrate 10. Figure 2 In this embodiment, the interlayer insulating film is provided with a contact portion 54 in a manner that penetrates the interlayer insulating film. The contact portion 54 may include a contact hole provided in the interlayer insulating film and a conductive component filled in the contact hole. Figure 2 In FIG. 1 , each contact portion 54 is marked with oblique hatching.

[0067] Emitter electrode 52 is provided above gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 is connected to emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 via contact portion 54. Furthermore, emitter electrode 52 is connected to a dummy conductive portion within dummy trench 30 via a contact hole provided in the interlayer insulating film. Emitter electrode 52 can be connected to the dummy conductive portion of dummy trench 30 at the front end of dummy trench 30 in the Y-axis direction.

[0068] The active-side gate wiring 131 is connected to the gate trench 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench 40 at the front end portion 41 of the gate trench 40 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench 30.

[0069] The emitter electrode 52 is formed of a material containing metal. Figure 2 , the area where emitter electrode 52 is provided is shown. For example, at least a portion of emitter electrode 52 may be formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. Emitter electrode 52 may include a barrier metal formed from titanium, a titanium compound, or the like, beneath the aluminum region. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum may be included in the contact hole.

[0070] The well region 11 is provided so as to overlap with the active-side gate wiring 131. Even within the area not overlapping with the active-side gate wiring 131, the well region 11 is provided to extend to a predetermined width. In this example, the well region 11 is provided so as to separate from the end of the contact portion 54 in the Y-axis direction toward the active-side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is of the P- type, and the well region 11 is of the P+ type.

[0071] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0072] The gate trench portion 40 of this example may include two straight portions 39 extending in an extending direction perpendicular to the arrangement direction (portions forming a straight trench along the extending direction) and a front end portion 41 connecting the two straight portions 39 . Figure 2 The extension direction is the Y-axis direction.

[0073] At least a portion of the tip portion 41 is preferably curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39.

[0074] In transistor portion 70, dummy trench portion 30 is provided between each straight portion 39 of gate trench portion 40. One dummy trench portion 30 may be provided between each straight portion 39, or a plurality of dummy trench portions 30 may be provided. Dummy trench portion 30 may have a straight shape extending in the extension direction, or may have a straight portion 29 and a front end portion 31 similar to gate trench portion 40.

[0075] The diffusion depth of the well region 11 can be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This can alleviate electric field concentration at the bottom of each trench portion.

[0076] Mesa portions are provided between the grooves in the arrangement direction. A mesa portion refers to an area within the semiconductor substrate 10 that is sandwiched between the grooves. As an example, the upper end of the mesa portion corresponds to the upper surface of the semiconductor substrate 10. The lower end of the mesa portion is at the same depth as the lower end of the groove. In this example, the mesa portion is provided so as to extend along the grooves in the Y-axis direction on the upper surface of the semiconductor substrate 10.

[0077] In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. The transistor portion 70 in this example has a boundary region 90. Boundary region 90 is the end of the transistor portion 70 in the X-axis direction and is in contact with the diode portion 80. Boundary region 90 includes a collector region 22 provided on the lower surface 23 of the semiconductor substrate 10. Boundary region 90 may include one or more trench portions. Boundary region 90 may include a gate trench portion 40, a dummy trench portion 30, or both. Boundary region 90 includes a mesa portion 62. In this specification, when referred to simply as a mesa portion, this refers to the mesa portion 60, the mesa portion 61, and the mesa portion 62. The mesa portion 62 may have the same structure as the mesa portion 61. The boundary region 90 may be a region having the same structure as the diode portion 80 on the upper surface 21 side and the same structure as the transistor portion 70 on the lower surface 23 side. The transistor portion 70 may not have a boundary region 90. In this case, the mesa portion 60 of the transistor portion 70 and the mesa portion 61 of the diode portion 80 are arranged adjacent to each other at the boundary between the transistor portion 70 and the diode portion 80 .

[0078] A base region 14 is provided in each mesa portion. Of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, a region closest to the active-side gate wiring 131 is referred to as a base region 14-e. Figure 2 , a base region 14-e is shown as being arranged at one end of each mesa portion in the extension direction, but a base region 14-e is also arranged at the other end of each mesa portion. In each mesa portion, the region sandwiched by the base region 14-e when viewed from above can be provided with at least one of an emitter region 12 of the first conductivity type and a contact region 15 of the second conductivity type. In this example, the emitter region 12 is of the N+ type, and the contact region 15 is of the P+ type with a higher concentration than that of the base region 14. The emitter region 12 and the contact region 15 can be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0079] Mesa portion 60 of transistor portion 70 includes emitter region 12 exposed on the upper surface of semiconductor substrate 10. Emitter region 12 is provided in contact with gate trench portion 40. Mesa portion 60 in contact with gate trench portion 40 may include contact region 15 exposed on the upper surface of semiconductor substrate 10.

[0080] Emitter region 12 in mesa portion 60 is provided in contact with gate trench portion 40. Emitter region 12 may or may not be in contact with dummy trench portion 30. Emitter region 12 is also provided in a region overlapping with contact portion 54.

[0081] Contact region 15 in mesa portion 60 is provided in a region overlapping contact portion 54. Contact region 15 may or may not be in contact with gate trench portion 40. Contact region 15 may or may not be in contact with dummy trench portion 30.

[0082] exist Figure 2 In the example shown in FIG. 1 , the emitter region 12 in the mesa portion 60 extends from the groove portion on one side to the groove portion on the other side in the X-axis direction. Alternatively, the contact region 15 in the mesa portion 60 may extend from the groove portion on one side to the groove portion on the other side in the X-axis direction. Alternatively, the contact region 15 may not contact either of the two groove portions sandwiching the mesa portion 60. In this case, the base region 14 may be provided between the contact region 15 and the groove portion.

[0083] exist Figure 2 In the example, the contact regions 15 and the emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction of the groove portion (Y-axis direction). In other examples, the contact regions 15 and the emitter regions 12 of the mesa portion 60 can be arranged in a stripe shape along the extension direction of the groove portion (Y-axis direction). For example, the emitter region 12 is provided in the region in contact with the groove portion, and the contact region 15 is provided in the region sandwiched by the emitter region 12. In addition, the emitter region 12 can also be provided in the mesa portion 60 instead of the contact region 15. For example, the emitter region 12 can also be provided in the entire region sandwiched by the base region 14-e in the Y-axis direction.

[0084] Emitter region 12 is not provided in mesa portion 61 of diode portion 80. Base region 14 and contact region 15 may be provided on the upper surface of mesa portion 61. Contact region 15 may be provided in the region sandwiched between base regions 14-e on the upper surface of mesa portion 61, in contact with each base region 14-e. Base region 14 may be provided in the region sandwiched between contact regions 15 on the upper surface of mesa portion 61. Base region 14 may be arranged throughout the region sandwiched between contact regions 15. Mesa portion 62 of boundary region 90 in this example has the same structure as mesa portion 61.

[0085] A contact portion 54 is provided above each mesa portion. Contact portion 54 is located in the region sandwiched between base regions 14-e. In this example, contact portion 54 is provided above each of contact region 15, base region 14, and emitter region 12. Contact portion 54 is not provided in the region corresponding to base region 14-e and well region 11. Contact portion 54 can be located at the center of the mesa portion 60 in the arrangement direction (X-axis direction).

[0086] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. In a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. Figure 2 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0087] Cathode region 82 is positioned away from well region 11 in the Y-axis direction. This ensures a secure distance between the P-type region (well region 11), which has a high doping concentration and is formed deep, and cathode region 82, thereby improving the breakdown voltage. In this example, the Y-axis end of cathode region 82 is positioned farther from well region 11 than the Y-axis end of contact portion 54. In other examples, the Y-axis end of cathode region 82 may be positioned between well region 11 and contact portion 54.

[0088] Figure 3 It shows Figure 2 . The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0089] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. Figure 2 The contact portion 54 described in FIG.

[0090] The contact portion 54 is provided so as to penetrate the interlayer insulating film 38. The contact portion 54 may be formed of a metal different from that of the emitter electrode 52. The contact portion 54 may include tungsten. A barrier metal layer including at least one of a titanium film and a titanium nitride film may also be provided at the bottom of the contact portion 54. The contact portion 54 may be provided on the upper surface 21 of the semiconductor substrate 10 or may be provided inside the semiconductor substrate 10. Figure 3 In the example shown, contact portion 54 is a contact groove extending from upper surface 21 of semiconductor substrate 10 to the interior of each mesa portion. This increases the contact area between contact portion 54 and semiconductor substrate 10. In this cross section, the lower end of contact portion 54 of transistor portion 70 contacts emitter region 12. In this cross section, the lower end of contact portion 54 of diode portion 80 contacts base region 14.

[0091] Emitter electrode 52 is provided above interlayer insulating film 38. Emitter electrode 52 is connected to semiconductor substrate 10 via contact portion 54. Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0092] The semiconductor substrate 10 has an N-type or N-type drift region 18 . The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80 .

[0093] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0094] Emitter region 12 is exposed on upper surface 21 of semiconductor substrate 10 and is provided in contact with gate trench 40. Emitter region 12 may be in contact with the trenches on both sides of mesa portion 60. The doping concentration of emitter region 12 is higher than that of drift region 18.

[0095] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided so as to be in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0096] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. Specifically, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. Providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14 enhances the carrier injection enhancement effect (IE effect) and reduces the on-state voltage. The accumulation region 16 can be provided to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0097] A P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10 in the mesa portion 61 of the diode portion 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may also be provided below the base region 14 in the mesa portion 61.

[0098] In the mesa portion 62 of the boundary region 90, a P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 62, an accumulation region 16 may also be provided below the base region 14. The mesa portion 62 of this example has the same structure as the mesa portion 61. In each example of this specification, the center of the trench portion in the X-axis direction can be set as the end of the boundary region 90 in the X-axis direction.

[0099] In each transistor portion 70 and diode portion 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 may be an average value of the doping concentration in a region where the doping concentration distribution is substantially flat.

[0100] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (protons) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ collector region 22 and the N+ cathode region 82.

[0101] In transistor portion 70, a P+ type collector region 22 is provided below buffer region 20. The acceptor concentration in collector region 22 is higher than the acceptor concentration in base region 14. Collector region 22 may contain the same acceptor as base region 14 or a different acceptor. The acceptor in collector region 22 is, for example, boron.

[0102] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that serve as donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0103] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench is provided so as to penetrate the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reach below the base region 14. In the region where at least one of the emitter region 12, the contact region 15, and the reservoir region 16 is provided, each trench also penetrates these doped regions. The formation of the doped regions after the trench is formed is not limited to the formation of the doped regions. The formation of doped regions between the trenches after the trenches are formed is also included in the case where the trench penetrates the doped regions.

[0104] As described above, transistor portion 70 is provided with gate trench portion 40 and dummy trench portion 30. Diode portion 80 is provided with dummy trench portion 30, but no gate trench portion 40 is provided. In this example, the boundary between diode portion 80 and transistor portion 70 in the X-axis direction is the boundary between cathode region 82 and collector region 22.

[0105] In this example, the boundary region 90 is provided with the dummy trench portion 30 , but not with the gate trench portion 40 . The trench portion at the end portion of the boundary region 90 on the transistor portion 70 side may be the gate trench portion 40 .

[0106] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided within the gate trench at a position further inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0107] The gate conductive portion 44 can be arranged to be longer in depth than the base region 14. The gate trench portion 40 at this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface in the base region 14 that contacts the gate trench portion 40.

[0108] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 includes a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided within the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0109] In this example, the gate trench 40 and the dummy trench 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces that are convex downward (curved in cross section). In this specification, the depth position of the lower end 43 of the gate trench 40 is denoted as Zt.

[0110] The semiconductor device 100 of this embodiment includes a P-type floating region 202 provided below the lower end 43 of the gate trench 40. The lower end 43 of the gate trench 40 is the portion of the gate trench 40 that is closest to the lower surface 23 of the semiconductor substrate 10. Figure 3 In the example, the lower end 43 of the gate trench portion 40 is arranged at the center of the gate trench portion 40 in the X-axis direction. In addition, the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. Figure 3 In the example, the lower end 33 of the dummy groove portion 30 is arranged at the center of the dummy groove portion 30 in the X-axis direction.

[0111] At least a portion of the floating region 202 is disposed at a position overlapping with the lower end 43 when viewed from above, and is disposed below the lower end 43 in the Z-axis direction. The floating region 202 may include a portion that does not overlap with the lower end 43 when viewed from above. The floating region 202 may also include a portion disposed above the lower end 43. The floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. Figure 3 In the example shown in FIG, the floating region 202 contacts the entire curved surface portion including the lower end 43 in the gate trench portion 40. The floating region 202 can be formed by implanting a P-type dopant near the lower end of the trench structure after forming the trench structure of the gate trench portion 40 and before forming the gate conductive portion 44.

[0112] The floating region 202 is electrically floating relative to an electrode such as metal or polysilicon. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected using a P-type region or a conductive material. The doping concentration of the floating region 202 can be lower than the doping concentration of the base region 14 or higher than the doping concentration of the base region 14. In this example, the doping concentration of the floating region 202 is higher than the doping concentration of the base region 14. The doping concentration can be 1×10 15 cm -3 Above and 1×10 17 cm -3 the following.

[0113] The floating region 202 is disposed so as to be separated from the base region 14. An N-type region (in this example, at least one of the reservoir region 16 and the drift region 18) is provided between the floating region 202 and the base region 14.

[0114] Each transistor portion 70 has one or more floating regions 202. Each transistor portion 70 may have multiple floating regions 202. In each transistor portion 70, a floating region 202 may be provided in at least one gate trench portion 40, more than 50% of the gate trench portions 40, more than 80% of the gate trench portions 40, or all of the gate trench portions 40.

[0115] In at least one transistor portion 70, a floating region 202 is provided in the gate trench portion 40 closest to the diode portion 80. In a plurality of transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80. Alternatively, in all transistor portions 70, a floating region 202 may be provided in the gate trench portion 40 closest to the diode portion 80.

[0116] In this specification, the gate trench portion 40 located closest to the diode portion 80 in the first direction among the one or more gate trench portions 40 of the transistor portion 70 is referred to as the first gate trench portion 40-1. The dummy trench portion 30 located adjacent to the first gate trench portion 40-1 among the one or more dummy trench portions 30 of the transistor portion 70 is referred to as the first dummy trench portion 30-1 and the second dummy trench portion 30-2. The first dummy trench portion 30-1 is located outside the first gate trench portion 40-1. That is, the first dummy trench portion 30-1 is located between the first gate trench portion 40-1 and the diode portion 80. In this example, the first dummy trench portion 30-1 is located at the end of the boundary region 90. The second dummy trench portion 30-2 is located inside the first gate trench portion 40-1. That is, the second dummy trench portion 30 - 2 is arranged on the opposite side of the first gate trench portion 40 - 1 from the first dummy trench portion 30 - 1 .

[0117] The mesa portion 60 among the plurality of mesa portions 60 is a first mesa portion 60-1 that contacts the first gate trench 40-1 and is provided between the first gate trench 40-1 and the diode portion 80. The first mesa portion 60-1 is a mesa portion 60 sandwiched between the first gate trench 40-1 and the first dummy trench 30-1.

[0118] The mesa portion 60 that contacts the first gate trench 40-1 and is located on the opposite side of the first mesa portion 60-1 is referred to as a second mesa portion 60-2. The second mesa portion 60-2 is sandwiched between the first gate trench 40-1 and the second dummy trench 30-2.

[0119] Among the one or more floating regions 202, the floating region 202 located below the first gate trench 40-1 is referred to as a first floating region 202. Each floating region 202 may or may not extend below the lower end 33 of the trench portion (in this example, the dummy trench 30) adjacent to the corresponding gate trench 40. Each floating region 202 may or may not contact the trench portion adjacent to the gate trench 40. In this example, each floating region 202 does not extend beyond the trench portion adjacent to the gate trench 40 in the X-axis direction. Each floating region 202 does not extend below the mesa portion 60 that is not in contact with the gate trench 40.

[0120] exist Figure 31 shows the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 provided at one end portion in the X-axis direction of the transistor portion 70. When the transistor portion 70 is sandwiched between the two diode portions 80, the first gate trench portion 40-1, the first floating region 202-1, the first mesa portion 60-1, and the second mesa portion 60-2 are provided at both ends of the transistor portion 70 in the X-axis direction.

[0121] The lower end 33 of each dummy trench portion 30 may contact an N-type region (in this example, the drift region 18). In this example, no P-type region is provided below the lower end 33 on the upper surface 21 of the semiconductor substrate 10, but an N-type region (in this example, the drift region 18) is provided.

[0122] By providing the floating region 202, when the transistor portion 70 is turned on, the flow of electrons toward the lower end 43 of the first gate trench portion 40-1 can be blocked, leaving a depletion layer near the lower end 43. This reduces reverse recovery dV / dt. Reverse recovery dV / dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode portion 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, the tail portion of the voltage waveform of the IGBT provided in the opposing arm can be reduced. This improves the trade-off between conduction loss and reverse recovery dV / dt.

[0123] On the other hand, in semiconductor device 100 in which transistor section 70 and diode section 80 are arranged side by side, a portion of the electrons injected from emitter region 12 of transistor section 70 flows toward cathode region 82 of diode section 80. Consequently, the potential of the PN junction at the end of collector region 22 of transistor section 70 is less likely to rise, and voltage foldback may occur when transistor section 70 is turned on. Providing floating region 202 blocks the electron current from emitter region 12, further reducing the potential of the PN junction at the end of collector region 22 and making voltage foldback more likely to occur.

[0124] In this example, a non-overlapping region that does not overlap with the first floating region is provided in the first mesa portion 60-1, which is located near the diode portion 80. This facilitates the flow of electrons from the first mesa portion 60-1, thereby suppressing voltage foldback. In other words, the aforementioned trade-off characteristics can be improved while also suppressing voltage foldback.

[0125] Figure 4 2 is a diagram showing an example of the arrangement of the floating region 202 when viewed from above. Figure 4 In FIG, the transistor portion 70 near the boundary region 90 is shown in an enlarged manner. Figure 4 In FIG, the well region 11 is shown to be arranged outside the emitter region 12 in the Y-axis direction. Figure 1The peripheral gate wiring 130 described in FIG. 1 extends above the well region 11 along the X-axis direction.

[0126] In at least one transistor section 70, the first mesa portion 60-1 has a non-covered region 212 that does not overlap with the first floating region 202-1. The non-covered region 212 may be provided in the first mesa portion 60-1 in multiple transistor sections 70, or in all transistor sections 70. In this example, the non-covered region 212 is provided over the entire X-axis direction of the first mesa portion 60-1.

[0127] Each mesa portion 60 has a long side in the Y-axis direction. The direction of extension of the longest straight line among the end sides of the mesa portion 60 when viewed from above can be set as the long side direction of the mesa portion 60. In each mesa portion 60, the area between the two ends of the emission area 12 in the Y-axis direction is set as the intermediate area 210. In the mesa portion 60 of this example, the emission areas 12 are discretely arranged in the Y-axis direction. In this case, the outer ends of the two emission areas 12 arranged at the two ends in the Y-axis direction are set as the two ends of the intermediate area 210. In the mesa portion 60, the emission areas 12 and the contact areas 15 can be alternately arranged in the Y-axis direction.

[0128] The non-covered region 212 can be provided in the middle region 210 of the first mesa portion 60-1. In this example, a plurality of first floating regions 202-1 are discretely arranged along the Y-axis in the middle region 210 of the first mesa portion 60-1. Furthermore, a plurality of non-covered regions 212 are discretely arranged along the Y-axis in the middle region 210 of the first mesa portion 60-1. This facilitates the flow of electrons from the first mesa portion 60-1, thereby suppressing voltage foldback.

[0129] The first floating region 202-1 may overlap with the first dummy trench portion 30-1 or may be separated from the first dummy trench portion 30-1 in a plan view. When the first floating region 202-1 is separated from the first dummy trench portion 30-1, voltage foldback can be further suppressed.

[0130] In the middle region 210 of the first mesa portion 60-1, the sum of the lengths L2 of the plurality of uncovered regions 212 in the Y-axis direction can be less than the sum of the lengths L1 of the regions overlapping the first floating region 202-1 in the Y-axis direction. This facilitates improving the trade-off between conduction loss and reverse recovery dV / dt. The sum of the lengths L2 can be less than 70% of the sum of the lengths L1, or less than 50%. The sum of the lengths L2 can be greater than 10%, greater than 30%, or greater than 50% of the sum of the lengths L1.

[0131] The sum of the lengths L2 may be greater than the sum of the lengths L1. This makes it easier to suppress voltage foldback. The sum of the lengths L2 may be 1.3 times or more, 1.5 times or more, or even 2 times or more of the sum of the lengths L1. The sum of the lengths L2 may be 10 times or less, 3 times or less, or even 2 times or less of the sum of the lengths L1.

[0132] The non-covered region 212 can also be provided in the middle region 210 of the second mesa portion 60-2. The first floating region 202-1 and the non-covered region 212 of the second mesa portion 60-2 can be arranged in the same Y-axis direction as the first mesa portion 60-1. In a top view, the first floating region 202-1 of the second mesa portion 60-2 can overlap with the second dummy trench portion 30-2 or can be separated from the second dummy trench portion 30-2. As an example, the first floating region 202-1 can overlap with the second dummy trench portion 30-2 and be separated from the first dummy trench portion 30-1.

[0133] In this example, a first floating region 202-1 is disposed below at least one emitter region 12 of the first mesa portion 60-1. The first floating region 202-1 may overlap the entire corresponding emitter region 12. The first floating region 202-1 may be disposed below multiple emitter regions 12. Alternatively, the first floating region 202-1 may be disposed below all emitter regions 12 except for the emitter regions 12 disposed at both ends in the Y-axis direction. Furthermore, the first floating region 202-1 may be disposed above all emitter regions 12, including the emitter regions 12 disposed at both ends in the Y-axis direction. Providing the first floating region 202-1 so as to overlap the emitter region 12 facilitates improving the trade-off between conduction loss and reverse recovery dV / dt.

[0134] In this example, at least a portion of the contact region 15 is a non-covered region 212. Each contact region 15 may be provided with a non-covered region 212. In each contact region 15, the portion in contact with the emitter region 12 may overlap with the first floating region 202-1. Each contact region 15 may also not overlap with the first floating region 202-1.

[0135] In other examples, a first floating region 202-1 may be disposed below at least one contact region 15 of the first mesa portion 60-1. The first floating region 202-1 may be disposed below multiple contact regions 15. The first floating region 202-1 may be disposed for all contact regions 15 except for the contact regions 15 disposed at both ends in the Y-axis direction. Furthermore, the first floating region 202-1 may be disposed for all contact regions 15, including the contact regions 15 disposed at both ends in the Y-axis direction.

[0136] In this case, at least a portion of the emitter region 12 is a non-covered region 212. Each emitter region 12 may be provided with a non-covered region 212. In each emitter region 12, the portion in contact with the contact region 15 may overlap with the first floating region 202-1. Each emitter region 12 may also not overlap with the first floating region 202-1. Providing the first floating region 202-1 so that it overlaps with the contact region 15 facilitates electron flow, thereby easily suppressing voltage foldback.

[0137] In each mesa portion 60, except for the first mesa portion 60-1 and the second mesa portion 60-2, a floating region 202 can be provided. The Y-axis length of the floating region 202 of the mesa portion 60 is greater than the Y-axis length L1 of the first floating region 202-1. In this example, the length of the floating region 202 is equal to the sum of the lengths L1 and L2. The Y-axis ends of the floating region 202 in this example are located at the same position as the outer ends of the first floating region 202-1 located at the Y-axis ends. The Y-axis length of the floating region 202 can be greater than 50%, greater than 70%, or greater than 90% of the Y-axis length of the straight portion 39 of the gate trench 40.

[0138] The area of ​​the non-covered region 212 of the first mesa portion 60-1 in a plan view (referred to as a first area) can be larger than the area of ​​the region of the mesa portion 60 that contacts the gate trench portion 40 other than the first gate trench portion 40-1 and does not overlap with the floating region 202 (referred to as a second area). The first area is the value obtained by multiplying the sum of the lengths L2 by the width of the first mesa portion 60-1 in the X-axis direction. The second area is the value obtained by multiplying the sum of the lengths in the Y-axis direction of the region that does not overlap with the floating region 202 by the width of the mesa portion 60 in the X-axis direction. The second area can be zero.

[0139] like Figure 4 As shown, a first extension region 204 may be provided, extending from the well region 11 to a position overlapping with the emitter region 12. The first extension region 204 is a P-type region. The first extension region 204 is connected to the well region 11. The well region 11 is connected to the emitter electrode 52. The first extension region 204 may be provided at the same depth as the floating region 202. The first extension region 204 may have the same doping concentration as the floating region 202. The first extension region 204 is separated from the floating region 202.

[0140] In this example, the first extension region 204 overlaps with the entire emitter region 12 closest to the well region 11. The first extension region 204 may not overlap with the second emitter region 12 closest to the well region 11. By providing the first extension region 204, the region from the well region 11 to the bottom of the outermost emitter region 12 can be at the emitter potential. As a result, the electric field distribution in the region where the first extension region 204 is provided can be made uniform, thereby suppressing the reduction in withstand voltage. The first extension region 204 can be provided throughout the entire X-axis direction of the transistor portion 70. The first extension region 204 can be provided throughout the entire X-axis direction of the diode portion 80.

[0141] Figure 5 2 is a diagram showing another example of the arrangement of the floating region 202 when viewed from above. Figure 4 . In this example, the floating regions 202 other than the first floating region 202-1 are also discretely arranged along the Y-axis direction, similarly to the first floating region 202-1. In this example, the length of the floating regions 202 other than the first floating region 202-1 in the Y-axis direction may be the same as the length L1 of the first floating region 202-1. The intervals between the floating regions 202 other than the first floating region 202-1 in the Y-axis direction may be the same as the interval L2 between the first floating regions 202-1.

[0142] At least one of the floating areas 202 other than the first floating area 202-1 may be discretely arranged along the Y-axis direction. For example, the floating areas 202 adjacent to the first floating area 202-1 may be discretely arranged along the Y-axis direction. Figure 4 The example is also configured continuously along the Y axis direction. Figure 5 As shown, all floating regions 202 are discretely arranged along the Y-axis direction.

[0143] Figure 6 is a diagram showing another example of the ee cross section. The configuration of the first floating region 202-1 in this example is the same as Figure 3 Other structures can be used with Figures 3 to 5 The same applies to any of the examples described in .

[0144] In this example, the first floating region 202-1 does not extend below the lower end 33 of the first dummy trench portion 30-1 in the X-axis direction. The first floating region 202-1 does not contact the first dummy trench portion 30-1 when viewed from above. A non-covered region 212 is provided between the first floating region 202-1 and the first dummy trench portion 30-1. The first floating region 202-1 may or may not extend below the contact portion 54 of the first mesa portion 60-1. The first floating region 202-1 may or may not extend to the center of the first mesa portion 60-1 in the X-axis direction.

[0145] The first floating 202-1 can be connected to Figure 4 and Figure 5 In another example, the first floating region 202-1 may also be discretely arranged along the Y-axis direction. Figure 4 and Figure 5 Similarly, only one floating region 202 is provided continuously along the Y-axis direction. Even in this case, since the non-covered region 212 is provided between the first dummy trench portion 30-1 and the first floating region 202, voltage foldback can be suppressed.

[0146] The width of the first stage portion 60-1 in the X-axis direction is set to X1. The width of the non-covered area 212 in the X-axis direction can be more than 10% of the width X1, or more than 20%, or more than 30%. The width of the non-covered area 212 in the X-axis direction can be less than 90% of the width X1, or less than 80%, or less than 70%. Figure 6 As shown, the width of the non-covered area 212 in the X-axis direction may be less than 50% of the width X1.

[0147] The first floating region 202-1 may be in contact with the second dummy trench portion 30-2 in a plan view. In this example, the first floating region 202-1 is in contact with the second dummy trench portion 30-2 in an XZ cross section.

[0148] The width of the second mesa portion 60-2 in the X-axis direction is set to X2. Width X2 can be smaller than width X1. That is, between the first dummy trench portion 30-1 and the second dummy trench portion 30-2, the first gate trench portion 40-1 is arranged so as to be closer to the second dummy trench portion 30-2. With this configuration, when P-type dopants are implanted and diffused through the trench structure of the first gate trench portion 40-1 to form the first floating region 202-1, the first floating region 202-1 is easily separated from the first dummy trench portion 30-1 and brought into contact with the second dummy trench portion 30-2.

[0149] Figure 7 is a diagram showing another example of the ee cross section. The configuration of the first floating region 202-1 in this example is the same as Figure 6 Other structures can be used with Figure 6 The same applies to any of the examples described in .

[0150] The first floating area 202-1 of this example is also configured to be separated from the second dummy groove portion 30-2 when viewed from above. The distance between the first floating area 202-1 and the first dummy groove portion 30-1 in the X-axis direction is set to X3, and the distance between the first floating area 202-1 and the second dummy groove portion 30-2 in the X-axis direction is set to X4. The distance X4 can be smaller than the distance X3. The distance X4 can be less than 50% of the distance X3, or less than 30%. The distance X4 can also be as Figure 6 As in the example of , it is 0. This example can also suppress voltage foldback.

[0151] The floating areas 202 except the first floating area 202-1 may be connected to Figure 6 In other examples, all floating regions 202 may have the same Figure 7 The first floating region 202-1 has the same structure as the first floating region 202-1.

[0152] Figure 8 1 is a plan view showing an example of the transition region 92 . Figure 8 The structure of the transition region 92 described in the accompanying drawings can be combined with any of the examples described in this specification. Figure 8 The structure of the transition region 92 described in the specification can be combined with the structure of the floating region 202 of any example described in this specification. In other examples, Figure 8 The floating region 202 of the semiconductor device 100 described in the embodiment may have the same Figures 1 to 7 Examples of different structures. Alternatively, Figure 8 The semiconductor device 100 described in FIG. 1 may not have the floating region 202 . Figure 8 The semiconductor device 100 described in does not need to include the diode portion 80 .

[0153] In this example, the well region 11 is also arranged outside the emitter region 12 in the X-axis direction. Above the well region 11 in this example, a peripheral gate wiring 130 extending in the Y-axis direction is arranged.

[0154] The transition region 92 is arranged between the emitter region 12 (or the transistor portion 70) and the well region 11 in the X-axis direction. In the transition region 92, one or more groove portions are arranged side by side along the X-axis direction. The transition region 92 can have one or more dummy groove portions 30, one or more gate groove portions 40, or both dummy groove portions 30 and gate groove portions 40. The transition region 92 of this example has groove portions arranged in the same pattern as the transistor portion 70. The transistor portion 70 of this example is alternately arranged with one gate groove portion 40 and two dummy groove portions 30. The transition region 92 can also be alternately arranged with one gate groove portion 40 and two dummy groove portions 30.

[0155] One or more trench portions may be arranged inside the well region 11 . In this example, two dummy trench portions 30 are arranged inside the well region 11 .

[0156] The transition region 92 may include a collector region 22 at a position where the transition region 92 contacts the lower surface 23. The transition region 92 may also include a cathode region 82 at a position where the transition region 92 contacts the lower surface 23. The transition region 92 may include one or more mesa portions 63. The drift region 18 may be exposed on the upper surface 21 of the mesa portion 63. In other examples, the base region 14 may be provided on the upper surface 21 of the mesa portion 63.

[0157] Semiconductor device 100 of this embodiment includes a second extension region 220 disposed in transition region 92. Second extension region 220 is a P-type region extending from well region 11 along the X-axis direction to a position overlapping emitter region 12. Second extension region 220 is connected to well region 11. Second extension region 220 can be disposed at the same depth as floating region 202. Second extension region 220 can have the same doping concentration as floating region 202.

[0158] In this example, second extension region 204 overlaps the entire emitter region 12 of mesa portion 60 closest to well region 11 in the X-axis direction. Second extension region 204 may also overlap the entire emitter region 12 of two or more mesa portions 60 closest to well region 11. If contact region 15 is provided in mesa portion 60, second extension region 204 also overlaps with contact region 15. Second extension region 204 is not connected to floating region 202.

[0159] By providing the second extension region 220, the transition region 92 can be placed at the emitter potential. This allows the electric field distribution in the transition region 92 to be uniform, thereby suppressing the reduction in withstand voltage. The second extension region 220 can be provided in a wider range than the floating region 202 in the Y-axis direction. The second extension region 220 can be provided at the end in the Y-axis direction. Figure 4 etc. is connected to the first extension region 204 described in the foregoing.

[0160] Figure 9 It shows Figure 8FIG is an example of an ff cross section in FIG. The ff cross section is an XZ plane including the well region 11, the transition region 92, and the transistor portion 70. As described above, the peripheral gate wiring 130 is arranged above the well region 11. The peripheral gate wiring 130 and the well region 11 are insulated by an insulating film 221 such as an oxide film. Figure 9 In FIG. 5 , the upper surface structure of the emitter electrode 52 and the interlayer insulating film 38 and the like, and the lower surface structure of the collector electrode 24 and the like are omitted.

[0161] The second extension region 220 is provided below the lower ends of one or more trenches provided in the transition region 92. The second extension region 220 may contact the lower ends of the trenches and extend beyond the transition region 92 to the transistor portion 70 along the X-axis direction.

[0162] The second extension region 220 extends below the emitter region 12. The second extension region 220 may extend below the lower end of at least one gate trench portion 40 of the transistor portion 70. No floating region 202 is provided below the gate trench portion 40. By providing the second extension region 220, the electric field distribution in the transition region 92 can be made uniform, thereby suppressing a decrease in withstand voltage.

[0163] Figure 10 is an XZ cross section showing another structural example of the boundary region 90 and the diode portion 80. Figure 10 In FIG. 5 , the upper surface structure of the emitter electrode 52 and the interlayer insulating film 38 and the like, and the lower surface structure of the collector electrode 24 and the like are omitted.

[0164] exist Figures 1 to 9 In the example described in , the floating region 202 is not provided in the boundary region 90 and the diode portion 80. In this example, the floating region 202 is provided in at least one of the boundary region 90 and the diode portion 80. Figure 10 The structure described in can also be applied to Figures 1 to 9 By providing the floating region 202 in the boundary region 90, the electric field distribution in the transistor portion 70 and the boundary region 90 other than the boundary region 90 can be made uniform. By providing the floating region 202 in the diode portion 80, the electric field distribution in the transistor portion 70 and the diode portion 80 can be made uniform.

[0165] exist Figure 10 In the example, the arrangement pattern of the trench portions in the transistor portion 70 is the same as Figure 3 The examples are different. Figure 10 In the example, a gate trench portion 40 and a dummy trench portion 30 are alternately arranged along the X-axis direction. The arrangement pattern of the trench portions in the transistor portion 70 may be Figure 3 and Figure 10In the transistor portion 70 of this embodiment, a floating region 202 is provided in each gate trench portion 40 .

[0166] Figure 10 The floating region 202 of the example does not extend to a position overlapping with a trench portion (in this example, a dummy trench portion 30) arranged at a position adjacent to the corresponding gate trench portion 40. The floating region 202 may also be as follows Figures 3 to 9 As described in , it extends to a position overlapping with the trench portion arranged on at least one side of the adjacent position of the gate trench portion 40 .

[0167] exist Figure 10 In the example shown in FIG. 1 , the boundary region 90 includes a plurality of dummy trench portions 30, a plurality of mesa portions 62, and one or more floating regions 202. The floating region 202 is provided below the lower end of at least one trench portion in the boundary region 90. The period F2 of the floating regions 202 provided along the X-axis direction in the boundary region 90 can be the same as the period F1 of the floating regions 202 provided along the X-axis direction in the transistor portion 70 other than the boundary region 90. By making the period of the floating regions 202 the same, the electric field distribution can be made more uniform. The period of the floating regions 202 is the distance between the center positions of the floating regions 202 in the X-axis direction.

[0168] exist Figure 10 In the example shown in FIG, a floating region 202 is also provided below the lower end of at least one trench portion of the diode portion 80. In the diode portion 80, the period F3 of the floating regions 202 provided along the X-axis direction can be the same as the period F1 of the transistor portion 70. By making the periods of the floating regions 202 the same, the electric field distribution can be further uniformed.

[0169] The floating regions 202 in the boundary region 90 may be arranged in a plurality or continuously in the Y-axis direction. The floating regions 202 in the diode portion 80 may be arranged in a plurality or continuously in the Y-axis direction.

[0170] The periods F1, F2, and F3 of the floating region 202 may be different. Period F1 may be greater than period F2, or less than period F2. Period F1 may be greater than period F3, or less than period F3. Period F3 may be greater than period F2, or less than period F2. By adjusting periods F1 to F3, the breakdown voltage distribution of the transistor portion 70, the boundary region 90, and the diode portion 80 can be adjusted. For example, by increasing period F1, the breakdown voltage of the transistor portion 70 can be reduced, thereby relatively increasing the breakdown voltage of the diode portion 80. Conversely, by increasing period F3, the breakdown voltage of the diode portion 80 can be reduced, thereby relatively increasing the breakdown voltage of the transistor portion 70. In addition, periods F1 to F3 can be adjusted so that the breakdown voltages of the transistor portion 70, the boundary region 90, and the diode portion 80 are the same.

[0171] The X-axis direction intervals of all the trench portions of the semiconductor device 100 may be uniform. In other examples, the X-axis direction intervals of the trench portions may be non-uniform.

[0172] Figure 11 Graphs showing collector voltage-collector current characteristics in the embodiment and reference example. The reference example is an example in which the non-covered region 212 is not provided in the first terrace portion 60 - 1 . The embodiment is an example in which the non-covered region 212 is provided in the first terrace portion 60 - 1 .

[0173] In the reference example, the electron current of the first terrace portion 60-1 is not easily transferred to the collector region 22 due to the floating region 202. Therefore, in the reference example, Figure 11 As shown, voltage foldback occurs, in which collector current hardly flows until the collector voltage exceeds a predetermined voltage. In contrast, in the semiconductor device 100 of the embodiment, electron current in the first terrace portion 60-1 easily flows in the collector region 22. Therefore, voltage foldback does not occur.

[0174] Figure 12 Graphs showing trade-off characteristics between conduction loss and reverse recovery dV / dt in a reference example and an embodiment. Figure 12 This shows a trade-off relationship in which reducing the reverse recovery dV / dt leads to an increase in conduction loss.

[0175] Figure 12 The reference example in FIG. 1 is a semiconductor device that does not have the floating region 202. The semiconductor device of the embodiment is Figures 1 to 10 The semiconductor device 100 described in . The semiconductor device 100 of the embodiment improves the trade-off characteristics by including the floating region 202. For example, when the reverse recovery dV / dt is set to the same, the conduction loss of the embodiment is smaller than that of the reference example.

[0176] like Figure 12As described in , according to the semiconductor device 100, the trade-off characteristics between conduction loss and reverse recovery dV / dt can be improved. Figure 11 As described in , according to the semiconductor device 100 , voltage foldback can be suppressed.

[0177] While the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. As can be clearly seen from the description of the claims, embodiments in which such changes or improvements are made are also included in the technical scope of the present invention.

[0178] It should be noted that the order of execution of actions, sequences, steps, stages, and other processes in the apparatus, system, program, or method described in the claims, specifications, and drawings may be implemented in any order, unless otherwise indicated by phrases such as "before," "prior to," and so forth, and unless the output of a previous process is used in a subsequent process. Even if the phrases "first," "next," and so forth are used for convenience in describing the process flow in the claims, specifications, and drawings, this does not necessarily imply that the processes must be performed in that order.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; one or more transistor portions, each having a collector region of the second conductivity type provided on a lower surface of the semiconductor substrate; and One or more diode portions each having a cathode region of the first conductivity type provided on the lower surface of the semiconductor substrate and arranged alternately with the transistor portion in a first direction, Each of the transistor sections has: a plurality of trench portions arranged side by side along the first direction, including at least one gate trench portion; a plurality of mesa portions, which are regions sandwiched by the groove portions in the first direction; as well as a second conductive type floating region disposed relative to at least one of the gate trench portions and below a lower end of the gate trench portion; The one or more gate trench portions include a first gate trench portion provided closest to the diode portion, The plurality of mesa portions include a first mesa portion that is in contact with the first gate trench portion and is disposed between the first gate trench portion and the diode portion. A first floating region is provided below the first gate trench portion. The first land portion has a non-covered area that does not overlap with the first floating area.

2. The semiconductor device according to claim 1, wherein The plurality of groove portions include one or more dummy groove portions, The first mesa portion is sandwiched between the first gate trench portion and the first dummy trench portion. The first floating region disposed below the lower end of the first gate trench portion does not extend below the lower end of the first dummy trench portion.

3. The semiconductor device according to claim 2, wherein The first floating region does not contact the first dummy trench portion in a plan view.

4. The semiconductor device according to claim 3, wherein The plurality of trench portions include a second dummy trench portion, the second dummy trench portion being arranged on a side of the first gate trench portion opposite to the first dummy trench portion, In the first direction, a distance between the first floating region and the second dummy trench portion is smaller than a distance between the first floating region and the first dummy trench portion.

5. The semiconductor device according to claim 4, wherein The first floating region is in contact with the second dummy trench portion in a plan view.

6. The semiconductor device according to claim 1, wherein The first surface portion has: an emitter region of a first conductivity type disposed in contact with the upper surface of the semiconductor substrate; and a base region of the second conductivity type, which is arranged between the emitter region and the drift region, The first platform portion has a long side in the second direction, The first mesa portion has the uncovered area in a middle area between both ends of the emission area in the second direction.

7. The semiconductor device according to claim 6, wherein: In the middle area, a plurality of the non-covered regions are discretely arranged along the second direction.

8. The semiconductor device according to claim 7, wherein In the middle region, a total length of the plurality of uncovered areas in the second direction is smaller than a total length of areas overlapping the first floating area in the second direction.

9. The semiconductor device according to claim 7, wherein: The first mesa portion has a second conductive type contact region, the second conductive type contact region is provided in contact with the upper surface of the semiconductor substrate and is alternately arranged with the emitter region in the second direction. The first floating region is disposed below at least one of the emitter regions, and at least a portion of the contact region is the non-covered area.

10. The semiconductor device according to claim 9, wherein The first floating region entirely overlaps with at least one of the emitter regions, The non-covered area is provided in each of the contact areas.

11. The semiconductor device according to claim 6, wherein Also features: a well region of the second conductivity type, which is arranged outside the first mesa portion in the second direction and has a concentration higher than that of the base region; and A first extension region of the second conductivity type extends from the well region along the second direction to a position overlapping with the emitter region.

12. The semiconductor device according to claim 6, wherein Also features: a well region of the second conductivity type, which is arranged outside the emitter region in the first direction and has a concentration higher than that of the base region; and A second extension region of the second conductivity type extends from the well region along the first direction to a position overlapping with the emitter region.

13. The semiconductor device according to claim 1, wherein The diode unit has: a plurality of dummy groove portions arranged side by side along the first direction; and a mesa portion sandwiched by the dummy groove portion in the first direction, The floating region is also provided below a lower end of at least one of the dummy trench portions of the diode portion.

14. The semiconductor device according to claim 13, wherein A period at which the floating regions are provided along the first direction in the diode portion is the same as a period at which the floating regions are provided along the first direction in the transistor portion.

15. The semiconductor device according to claim 1, wherein The transistor portion includes a boundary region between the first gate trench portion and the diode portion, and the boundary region includes one or more trench portions and one or more mesa portions. The floating region is also provided below a lower end of at least one of the trench portions in the boundary region.

16. The semiconductor device according to claim 15, wherein A period in which the floating regions are provided along the first direction in the boundary region is the same as a period in which the floating regions are provided along the first direction in the transistor portion except for the boundary region.

17. The semiconductor device according to any one of claims 1 to 16, wherein: An area of ​​the non-covered region in the first mesa portion is larger than an area of ​​a region of the mesa portion that is in contact with the gate trench portion other than the first gate trench portion and does not overlap with the floating region.

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