A design method of low-pass filter digital phase-locked system and digital phase-locked method

Abstract

The present invention belongs to the field of digital phase-locked technology, and in particular relates to a design method and a digital phase-locked method for a low-pass filtering digital phase-locked system. The low-pass filtering digital phase-locked system includes a low-pass filtering module composed of k low-pass filtering units connected in series; two groups of mixed frequency signals input into the low-pass filtering module are low-pass filtered k times by the k low-pass filtering units, and then two groups of k-times low-pass filtered signals are output; when the time constant of the current low-pass filter is determined, the upper limit of the frequency range of the target voltage signal is taken as the cutoff frequency, and then the minimum value of the number of low-pass filtering units k is designed based on the cutoff frequency and the time constant. The present invention can improve the versatility of the low-pass filtering digital phase-locked system and enable the low-pass filtering digital phase-locked system to efficiently and accurately extract weak target voltage signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital phase locking, and in particular relates to a design method of a low-pass filtering digital phase locking system and a digital phase locking method. Background Art

[0002] As the core of weak signal extraction, phase-locked amplification technology directly affects the accuracy and reliability of spectral measurement.

[0003] The traditional low-pass filter schemes used in most current digital phase-locked technologies are computationally expensive and consume significant memory resources. For example, while FIR digital filters offer strictly linear phase characteristics, their convolution operations increase the FPGA logic and memory requirements by the square of their order. Similarly, the pole distribution of IIR filters leads to nonlinear phase distortion, requiring additional compensation operations. Furthermore, while adaptive filters can dynamically suppress noise, their recursive iterations place stringent demands on DSP on-chip computing resources.

[0004] To meet the computational overhead and storage resource requirements of the digital phase-locking process, traditional low-pass filter solutions, while consuming high FPGA resources, remain complex and incapable of quickly extracting weak target voltage signals. However, with the advancement of semiconductor chip technology, spectral measurement systems are increasingly moving towards miniaturization, fast response, and high sensitivity. Therefore, efficiently and accurately extracting weak target voltage signals has become a pressing challenge in the field of digital phase-locking technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a design method for a low-pass filtering digital phase-locked system, which can improve the versatility of the low-pass filtering digital phase-locked system and enable the low-pass filtering digital phase-locked system to efficiently and accurately extract weak target voltage signals.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A design method for a low-pass filtering digital phase-locked system:

[0008] The low-pass filtering digital phase-locked system includes a low-pass filtering module composed of k low-pass filtering units connected in series; two sets of mixed frequency signals input to the low-pass filtering module are low-pass filtered k times by the k low-pass filtering units, and then two sets of k low-pass filtered signals are output; each low-pass filtering unit includes two filtering circuits for performing a low-pass filtering once; each filtering circuit includes a first shifter, a second shifter, an adder and a subtractor; the adder includes two inputs, the subtractor includes two inputs, and the subtractor includes three outputs; the first shifter The input signal of the first shifter is connected to the first input of the adder, the output of the adder is connected to the first input of the subtracter, the first output of the subtracter is used to output the calculation result of the subtracter as the filtering result of the current filtering circuit, the second output of the subtracter is connected to the second input of the adder, the third output of the subtracter is connected to the input of the second shifter, and the second input of the subtracter is connected to the output of the second shifter; in the time constant of the current low-pass filter If the frequency range of the target voltage signal is determined, the upper limit of the frequency range of the target voltage signal is taken as the cutoff frequency. , and then based on the cutoff frequency and time constant Design the minimum number k of low-pass filter units.

[0009] Preferably, the low-pass filtering digital phase-locked system also includes a first DDS module, a second DDS module, a multiplier module and a feature extraction module; the first DDS module and the second DDS module are respectively used to generate two sets of different sinusoidal reference signals; after the multiplier module receives the two sets of sinusoidal reference signals and the mixed voltage digital signal output by the first DDS module and the second DDS module, it mixes the two sets of sinusoidal reference signals with the mixed voltage digital signal and outputs two sets of mixed signals to the low-pass filtering module; the low-pass filtering module outputs two sets of k-times low-pass filtered signals and sends them to the feature extraction module; the feature extraction module obtains the characteristic parameters of the voltage signal based on the two sets of k-times low-pass filtered signals.

[0010] Preferably, based on the cutoff frequency and time constant Design the minimum number of low-pass filter units k, then the minimum value of k is ;in, Indicates rounding up.

[0011] Preferably, or, when the number k of low-pass filter units connected in series in the current low-pass filter module is determined, the time constant of the current low-pass filter is The design includes the following: After determining the frequency range of the target voltage signal, take the upper limit of the frequency range as the cutoff frequency ,but .

[0012] The present invention further provides a digital phase-locking method, which is applied to a low-pass filter digital phase-locking system designed by the above-mentioned design method of a low-pass filter digital phase-locking system, and comprises the following steps:

[0013] S1, mixing the mixed voltage digital signal with two sets of different sinusoidal wave reference signals to obtain two sets of mixed signals;

[0014] S2, performing k-times low-pass filtering on the two mixed signals respectively to obtain two sets of k-times low-pass filtered signals; k is a positive integer;

[0015] S3, extracting characteristic parameters of the voltage signal in the mixed voltage digital signal: based on two groups of k-th low-pass filtered signals, obtaining the amplitude, initial phase, and frequency of the voltage signal.

[0016] Preferably, in S1, the following contents are further included: the first sinusoidal wave reference signal and mixed voltage digital signals After the mixing operation, the first mixed signal is obtained ; At the same time, the second sine wave reference signal and mixed voltage digital signals After the mixing operation, the second mixed signal is obtained ; The first sine wave reference signal With the second sine wave reference signal The amplitudes are the same and the phase difference is 90 degrees.

[0017] Preferably, in S2, when k=1, the following sub-steps are further included:

[0018] S21, respectively obtain the discrete low-pass filtering signal points of the two groups of mixed signals after the first low-pass filtering:

[0019] ;

[0020] in, Represents the i-th mixing signal The Nth low-pass filtered signal point value obtained after the first low-pass filtering, where N is a positive integer; i = 1 or 2; Represents the i-th mixing signal The value of the Nth sampling point in ; and The corresponding time points are the same; it means that the i-th mixing signal The initial sampling point value obtained by sampling at time t=0; when N=1, ;e represents a natural constant; Indicates the sampling time, which is the duration between adjacent sampling points;

[0021] S22, respectively fitting the two groups of discrete first-order low-pass filtered signal points into two groups of first-order low-pass filtered signals.

[0022] Preferably, in S21-S22, the calculation of obtaining a low-pass filtering signal point is simplified by a shifter, an adder and a subtractor in the low-pass filtering unit: , r represents the number of shifts and r is a positive integer, use replace ,use replace Then, we get the expression of the number of moving bits of the two sets of primary low-pass filtered signal points:

[0023] ;

[0024] All signal points entering the first shifter or the second shifter are right-shifted by r bits and then output; the corresponding waveforms fitted from all low-pass filtered signal points output from the first output end of the subtractor are output as the low-pass filtered signals of the current low-pass filtering unit.

[0025] Preferably, when k>1, S23 is further included after S22: S23, returns to S21, obtains the secondary low-pass filtered signals obtained after the second low-pass filtering of the two groups of primary low-pass filtered signals, and repeats S21 to S23 until two groups of k-th low-pass filtered signals are obtained; the first output end of the subtractor in the previous low-pass filtering unit is connected to the input end of the first shifter in the corresponding filter circuit in the next low-pass filtering unit; the first mixing signal and the second mixed signal It is the input of the first low-pass filter unit. After k low-pass filtering, the k-th low-pass filter unit outputs two sets of corresponding k-th low-pass filtered signals. and .

[0026] Preferably, S3 further includes the following:

[0027] Get the frequency and initial phase values ​​of two sets of k-times low-pass filtered signals and After that, the initial phase of the voltage signal is obtained and the amplitude of the voltage signal , The frequency, amplitude and initial phase of the two sets of k-th low-pass filtered signals are the same, and are also characteristic parameters of the voltage signal.

[0028] The beneficial effects of the present invention are:

[0029] (1) The design method of the low-pass filter digital phase-locked system of the present invention enables the low-pass filter digital phase-locked system to be flexibly configured simply and quickly, thereby reducing system costs and better adapting to various signal processing requirements in different application scenarios, thereby improving the versatility of the low-pass filter digital phase-locked system.

[0030] (2) The design method of the present invention enables the designed low-pass filter digital phase-locked system to ensure that noise signals above the cutoff frequency are filtered out, and even reduce the number of low-pass filter units while ensuring the filtering effect to further reduce costs.

[0031] (3) The digital phase-locked method of the present invention has an excellent filtering and noise reduction effect. While filtering out noise, it can also efficiently and highly restore the original voltage signal. Highly restoring the original voltage signal means accurately extracting the weak target voltage signal with high fidelity.

[0032] (4) The specially designed low-pass filter unit of the present invention is not only simple and compact in hardware structure, but also transforms the weighted calculation involving complex exponential terms in the filtering process into a simple recursive shift calculation that can be implemented by adders, subtractors, and shifters, thus achieving the exponential decay characteristics of the continuous-time filter, improving computational efficiency, significantly reducing FPGA communication overhead and storage resource usage, reducing the filter response time, and improving filtering efficiency. Furthermore, the structure of the low-pass filter module is made simpler and more compact.

[0033] (5) During the low-pass filtering process, regardless of which set of low-pass filtered signal points is used, the next low-pass filtered signal point is obtained by recursively fusing the previous low-pass filtered signal point with the sampling point of the current mixed signal; it is not directly obtained based solely on the sampling point of the current mixed signal. This effectively filters the noise in the mixed voltage digital signal while preventing distortion in the two sets of low-pass filtered signals after filtering.

[0034] (6) When a continuous mixed signal is processed point by point, the number of low-pass filter signal points obtained after filtering is extremely large, and the corresponding low-pass filter signal obtained after fitting is very accurate. Therefore, the digital phase-locked method of the present invention can ensure the accuracy of the low-pass filter signal fitted from the low-pass filter signal points.

[0035] (7) The low-pass filtering module of the present invention realizes multi-order low-pass filtering by connecting multiple low-pass filtering units in series. With each order of low-pass filtering, the high-frequency noise in the input signal can be gradually filtered out, and the high-frequency noise can be filtered out more effectively while retaining the low-frequency signal (such as the DC component). The extraction accuracy and anti-interference ability of the low-pass filtering module for the weak target voltage signal are improved, so that the signal finally output by the low-pass filtering module is smoother and more stable, and the final low-pass filtering effect is better, thereby improving the overall signal quality after low-pass filtering and further improving the effect of subsequent applications (such as enhancing the sensitivity and resolution of spectral detection).

[0036] (8) The low-pass filtering digital phase-locking method of the present invention can significantly reduce the FPGA communication overhead and storage resource usage, and efficiently and accurately extract the target voltage signal. Therefore, the digital phase-locking method of this embodiment can not only be used to extract the target voltage signal from a mixed voltage digital signal, but also can be used for real-time filtering to obtain the target voltage signal in a timely manner.

[0037] (9) The low-pass filtering digital phase-locked system implemented in this paper has a compact and simple structure and can extract the target signal efficiently and with high fidelity. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a flow chart of a low-pass filtering digital phase-locked method of the present invention;

[0039] Figure 2 Schematic diagram of low-pass filter unit;

[0040] Figure 3 is the original voltage signal waveform;

[0041] Figure 4 It is the waveform diagram of the mixed voltage signal;

[0042] Figure 5 This is a voltage signal waveform diagram obtained after the mixed voltage signal is processed by the digital phase-locked method of the present invention;

[0043] Figure 6 This is a schematic diagram of the overall structure of a low-pass filtering digital phase-locked system. DETAILED DESCRIPTION

[0044] In order to make the technical solution of the present invention clearer and more specific, the present invention is clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Ordinary technicians in this field, without making any creative work, make equivalent substitutions for the technical features of the technical solution of the present invention and solutions derived from conventional reasoning all fall within the scope of protection of the present invention.

[0045] After the noise and the weak voltage signal are mixed together and converted into a mixed voltage digital signal through analog-to-digital conversion, we hope to extract the weak voltage signal from the mixed voltage digital signal.

[0046] Example 1

[0047] like Figure 1 FIG. 1 is a flow chart of a low-pass filtering digital phase-locked method according to this embodiment, including the following contents:

[0048] S1, mixing the obtained mixed voltage digital signal with two sets of different sinusoidal wave reference signals to obtain two sets of mixed signals;

[0049] S2, performing k-times low-pass filtering on the two mixed signals respectively to obtain two sets of k-times low-pass filtered signals; k is a positive integer;

[0050] S3, extracting characteristic parameters of the voltage signal in the mixed voltage digital signal: based on two groups of k-th low-pass filtered signals, obtaining the amplitude, initial phase, and frequency of the voltage signal.

[0051] Obtaining the characteristic parameters of the voltage signal means determining the voltage signal.

[0052] In S1, the following are also included:

[0053] The first sine wave reference signal and mixed voltage digital signals After the mixing operation, the first mixed signal is obtained ; At the same time, the second sine wave reference signal and mixed voltage digital signals After the mixing operation, the second mixed signal is obtained ; The first sine wave reference signal With the second sine wave reference signal The amplitudes are the same and the phase difference is 90 degrees.

[0054] The first sine wave reference signal With the second sine wave reference signal Generated by two different DDS (Direct Digital Synthesis) modules.

[0055] Convert mixed voltage digital signals Expressed as an infinite multiple of the Fourier series form:

[0056] ;

[0057] in, Represents mixed voltage digital signals The amplitude is the DC component; n represents the mixed voltage digital signal The order of the harmonic components; Represents mixed voltage digital signals The modulation frequency; Represents mixed voltage digital signals The phase of ; t represents time.

[0058] The first mixed signal :

[0059] ;

[0060] The second mixed signal :

[0061] ;

[0062] in, Indicates the reference phase, which is also the first sine wave reference signal Phase of the second sine wave reference signal The phase is expressed as ; Indicates the reference amplitude, which is also the first sine wave reference signal and the second sine wave reference signal The amplitude of Indicates the reference harmonic order, which is also the first sine wave reference signal and the second sine wave reference signal The order of the harmonic components; represents the reference frequency, ; represents the reference phase difference, .

[0063] It can be seen that the first mixing signal and the second mixed signal The frequency included is The sum frequency signal and frequency are The combination of difference frequency signals.

[0064] The first mixed signal and the second mixed signal These are just expressions for mixed signals. The value of m in these two expressions can be 0, 1, ..., ∞.

[0065] In S2, the following sub-steps are also included:

[0066] S21, respectively obtain the discrete low-pass filtering signal points of the two groups of mixed signals after the first low-pass filtering: ;

[0067] ;

[0068] in, Represents the first mixing signal The Nth low-pass filtered signal point value obtained after the first low-pass filtering, where N is a positive integer; Represents the first mixing signal The value of the Nth sampling point in ; and The corresponding time points are the same; Represents the first mixing signal The N-1th low-pass filtered signal point value obtained after the first low-pass filtering; Indicates the first mixed signal The initial sampling point value obtained by sampling at time t=0 is also the first mixing signal The first sampling point value of ; when N=1, ; Represents the second mixing signal The Nth low-pass filtered signal point value obtained after the first low-pass filtering; Represents the second mixing signal The value of the Nth sampling point in ; and The corresponding time points are the same; Represents the second mixing signal The N-1th low-pass filtered signal point value obtained after the first low-pass filtering; Indicates the second mixing signal The initial sampling point value obtained by sampling at time t=0 is also the second mixing signal The first sampling point value of ; when N=1, ; represents a natural constant; Indicates the sampling time, which is the duration between adjacent sampling points. Pre-set by technicians; Indicates the time constant of the current low-pass filter, Pre-set by technicians.

[0069] The first mixed signal and the second mixed signal The duration is the same and known, when the sampling time When determining, the upper limit of the number N of sampling points or filtered signal points is also determined.

[0070] S22, respectively fitting the two groups of discrete primary low-pass filtered signal points into two groups of primary low-pass filtered signals;

[0071] S23, when k=1, execute S3; when k>1, return to S21, obtain the secondary low-pass filtered signals obtained after the second low-pass filtering of the two sets of primary low-pass filtered signals, and repeat S21~S23 until two sets of k-th low-pass filtered signals are obtained, and then execute S3.

[0072] The design of the low-pass filter unit to realize S21~S22 also includes the following:

[0073] The exponential terms in the numerical expressions of the two sets of primary low-pass filtered signal points are simplified computationally:

[0074] make , r represents the number of shift bits and r is a positive integer, so there is , After replacing the exponential term with an approximate value, we get the expression of the number of moving bits of the two sets of primary low-pass filtered signal points:

[0075] ;

[0076] ;

[0077] because and is known, so the number of shifted bits r is also known.

[0078] According to the expression of the moving bit number of the two sets of primary low-pass filter signal points, the low-pass filter unit is designed, such as Figure 2 As shown, the low-pass filter unit includes two filter circuits for obtaining two sets of primary low-pass filter signal points; each filter circuit includes a first shifter, a second shifter, an adder, and a subtractor. The adder includes two inputs, the subtractor includes two inputs, and the subtractor includes three outputs. The output of the first shifter is connected to the first input of the adder, the second output of the subtractor is connected to the second input of the adder, the output of the adder is connected to the first input of the subtractor, the second input of the subtractor is connected to the output of the second shifter, and the third output of the subtractor is connected to the input of the second shifter. The first output of the subtractor is used to output the calculation result of the subtractor as the filter result of the current filter circuit.

[0079] For the first mixed signal :

[0080] The first mixed signal After entering the first shifter, the first mixed signal is The initial sampling point value at t=0 After right shifting by r bits, we get ; Then it passes through the adder and subtractor in turn. Because there is no input at the second input of the adder and subtractor at this time, the value of the low-pass filtered signal point output by the subtractor at the sampling time t=0 is for , which is also the first mixing signal output by the subtractor The value of the first low-pass filtered signal point obtained after the first low-pass filtering.

[0081] The first low-pass filter signal point value In addition to being the first filtering result of the current filtering circuit and being outputted by the first output terminal of the subtractor, it also enters the adder and the second shifter through the other two outputs of the subtractor. At the next sampling moment, the first mixed signal is converted into The second sampling point value of After right shifting by r bits, we get ; Then enter the adder and After adding, we get + ; + Then it is sent to the subtractor, and at the same time, the subtractor is also sent to the second shifter. After right shifting by r bits, we get ;

[0082] The left subtraction operation in the subtractor is + Afterwards, + As the value of a low-pass filtered signal point at the current sampling moment , which is also the first mixing signal The value of the second low-pass filtered signal point obtained after the first low-pass filtering.

[0083] The shifter performs calculations in binary, where shifting one bit left is equivalent to multiplying by 2, and shifting one bit right is equivalent to dividing by 2.

[0084] Anyone skilled in the art can construct specific circuits of the first shifter, the second shifter, the adder, and the subtractor, which will not be described in detail here.

[0085] The first mixed signal The filtering process of the 3rd, 4th, ..., Nth first low-pass filtered signal point values ​​obtained after the first low-pass filtering is similar to the above description and will not be repeated here.

[0086] The second mixed signal The filtering process corresponding to the low-pass filtering signal point value is obtained through another set of filtering circuits, and the first mixing signal Similar, I will not repeat it here.

[0087] A low-pass filter signal point value and its corresponding time point together constitute a low-pass filter signal point. The corresponding waveform fitted by all the first low-pass filtered signal points obtained after the first low-pass filtering is used as the first mixing signal A low-pass filtered signal ; The second mixed signal The corresponding waveform fitted by all the first low-pass filtered signal points obtained after the first low-pass filtering is used as the second mixing signal A low-pass filtered signal .

[0088] The first mixed signal and the second mixed signal After inputting the low-pass filter unit, the low-pass filter unit outputs two sets of corresponding low-pass filter signals and .

[0089] Take the expression of the value of a low-pass filtered signal point as an example, because the expression of the value of a low-pass filtered signal point contains exponential terms , in obtaining and These signal point values ​​must be multiplied by the exponential term. If the existing low-pass filter (such as FIR digital filter, IIR filter or LMS adaptive filter) is used for filtering, the high computational complexity and large computational overhead of the filtering process will cause the demand for FPGA logic resources and storage resources to grow at the square of the order. Therefore, not only will the hardware performance requirements of the low-pass filter in the existing technology be high, thereby increasing the cost of the filter, but it will also greatly increase the structural complexity of the low-pass filter in the existing technology, further reducing the response time of the filter.

[0090] The specially designed low-pass filter unit of the present invention not only has a simple and compact hardware structure, but also transforms the weighted calculations involving complex exponential terms in the filtering process into simple recursive shift calculations that can be performed using adders, subtractors, and shifters. This achieves the exponential decay characteristics of the continuous-time filter, improving computational efficiency, significantly reducing communication overhead and storage resource usage, shortening the filter's response time, and improving filtering efficiency. The hardware resource consumption of the low-pass filter unit of the present invention, including communication overhead and storage usage, is only 15% to 20% of that of a comparable FIR digital filter, reducing FPGA resource consumption by approximately 75% to 80%, achieving efficient filtering.

[0091] In this embodiment, during the low-pass filtering process, regardless of the set of low-pass filtered signal points, the subsequent low-pass filtered signal point is obtained by recursively fusing the previous low-pass filtered signal point with the sampling point of the current mixed signal; it is not directly derived based solely on the sampling point of the current mixed signal. This effectively filters noise from the mixed voltage digital signal while preventing distortion in the two sets of low-pass filtered signals after filtering.

[0092] In this embodiment, a continuous mixed signal is processed point by point. Given an extremely short sampling time, the number of low-pass filtered signal points obtained after filtering is extremely large, and the corresponding low-pass filtered signal obtained after fitting is highly accurate. Therefore, the digital phase-locked method of this embodiment can ensure the accuracy of the low-pass filtered signal fitted from the low-pass filtered signal points.

[0093] Optionally, design a low-pass filter module to implement S21 to S23:

[0094] k low-pass filter units are connected in series to form a low-pass filter module, k>1 and k is a positive integer, and the first output of the subtractor in the previous low-pass filter unit is connected to the input of the first shifter in the corresponding filter circuit in the next low-pass filter unit. and the second mixed signal After inputting the first low-pass filter unit, the first low-pass filter unit outputs two sets of corresponding low-pass filter signals and ; Two sets of primary low-pass filtered signals and After inputting the second low-pass filter unit, the second low-pass filter unit outputs two sets of corresponding secondary low-pass filter signals and ;...;The kth low-pass filter unit outputs two sets of corresponding k-th low-pass filter signals and The input of the low-pass filter module is the first mixed signal and the second mixed signal , the output is two sets of corresponding k-times low-pass filtered signals and .

[0095] The filtering process of the low-pass filtering module corresponds to the description of S23.

[0096] The filtering process performed by the 2nd to kth low-pass filtering units is basically the same as described above and will not be repeated here.

[0097] The low-pass filtering module of the present invention realizes multi-order low-pass filtering by connecting multiple low-pass filtering units in series. With each order of low-pass filtering, the high-frequency noise in the input signal can be gradually filtered out, and the high-frequency noise can be more effectively filtered out while retaining the low-frequency signal (such as the DC component). The extraction accuracy and anti-interference ability of the low-pass filtering module for weak target voltage signals are improved, and the output signal of the low-pass filtering module is smoother and more stable, so that the final low-pass filtering effect is better, the overall signal quality after low-pass filtering is improved, and the effects of subsequent applications (such as enhancing the sensitivity and resolution of spectral detection) are further improved.

[0098] The following are also included in S3:

[0099] After k-times low-pass filtering, the two sets of k-times low-pass filtered signals with the sine waveform removed are obtained. and In the expression of the k-th low-pass filtered signal, when time is 0, the value of the expression corresponding to the k-th low-pass filtered signal at the initial phase can be known.

[0100] The values ​​of the expressions of the two sets of k-th low-pass filtered signals at the initial phase are recorded as and :

[0101] = ;

[0102] = ;

[0103] in, Represents the amplitude of the k-th low-pass filtered signal. The amplitudes of the two sets of k-th low-pass filtered signals are the same. It is also the amplitude of the voltage signal we hope to obtain; represents the initial phase of the k-th low-pass filtered signal, , It is also the initial phase of the voltage signal we want to obtain.

[0104] Get the initial phase .

[0105] Get the amplitude .

[0106] The frequency of the mixed voltage digital signal is known (and can be directly determined from its waveform or expression). This frequency is the frequency of the two sets of k-order low-pass filtered signals. The frequencies of the two sets of k-order low-pass filtered signals are identical, and are also the desired frequency of the voltage signal; this frequency can also be determined from the two sets of k-order low-pass filtered signals.

[0107] At this point, the extraction of characteristic parameters of the voltage signal in the mixed voltage digital signal is completed.

[0108] like Figure 3 As shown, it is the original voltage signal waveform simulated by technicians; Figure 3 After the original voltage signal is converted into the original digital voltage signal, the mixed voltage signal obtained by mixing it with the noise signal is as follows Figure 4 As shown, it can be seen that the waveform of the original voltage signal at the amplitude is significantly affected by the noise signal; Figure 5 To use the digital phase locking method of the present invention Figure 4 The voltage signal waveform obtained after processing the mixed voltage signal is shown in the figure. Figure 5 and Figure 3 The waveforms are essentially identical, especially the amplitudes, to the original voltage signals. To further verify the filtering and noise reduction effectiveness of the present invention, technicians used the present invention's digital phase-locking method to digitally phase-lock 500 sets of artificially mixed mixed voltage signals, obtaining filtered voltage signals. These filtered voltage signals were then compared with the corresponding original voltage signals, achieving an amplitude accuracy of over 99%.

[0109] The digital phase-locked method of this embodiment has a good filtering and noise reduction effect. While filtering out noise, it can efficiently and highly restore the original voltage signal. Highly restoring the original voltage signal means accurately extracting the weak target voltage signal with high fidelity.

[0110] A low-pass filtering digital phase-locked method in this embodiment uses a specially designed low-pass filtering unit to convert traditional complex floating-point operations containing exponential terms into simple recursive shift calculations that can be implemented by adders, subtractors, and shifters. The low-pass filtering unit significantly reduces FPGA communication overhead and storage resource usage while having a simple and compact structure. Furthermore, it also makes the structure of the low-pass filtering module simpler and more compact.

[0111] The present embodiment provides a low-pass filtering module for a low-pass filtering digital phase-locked method, which realizes multi-order low-pass filtering by connecting multiple low-pass filtering units in series. With each order of low-pass filtering, high-frequency noise in the input signal can be gradually filtered out, so that high-frequency noise is more effectively filtered out and low-frequency signals (such as DC components) are retained, thereby improving the extraction accuracy and anti-interference ability of the low-pass filtering module for weak target voltage signals, making the signal finally output by the low-pass filtering module smoother and more stable, making the final low-pass filtering effect better, improving the overall signal quality after low-pass filtering, and further improving the effects of subsequent applications (such as enhancing the sensitivity and resolution of spectral detection).

[0112] A low-pass filtering digital phase-locked method implemented in this embodiment can significantly reduce FPGA communication overhead and storage resource usage, and efficiently and accurately extract the target voltage signal. Therefore, the digital phase-locked method of this embodiment can not only be used to extract the target voltage signal from a mixed voltage digital signal, but also can be used for real-time filtering to obtain the target voltage signal in a timely manner.

[0113] Example 2

[0114] The present invention also provides a low-pass filtering digital phase-locked system, such as Figure 6 As shown, it includes: a first DDS module, a second DDS module, a multiplier module, a low-pass filter module, and a feature extraction module;

[0115] The first DDS module and the second DDS module are respectively used to generate two sets of different sinusoidal wave reference signals;

[0116] After receiving the two sets of sinusoidal reference signals and the mixed voltage digital signal output by the first DDS module and the second DDS module, the multiplier module performs mixing operations on the two sets of sinusoidal reference signals and the mixed voltage digital signal, and then outputs two sets of mixed signals to the low-pass filter module;

[0117] The low-pass filtering module contains k low-pass filtering units connected in series. After the k low-pass filtering units perform k low-pass filtering on the two sets of mixed signals, they output two sets of k low-pass filtered signals and send them to the feature extraction module.

[0118] The feature extraction module obtains the characteristic parameters of the voltage signal based on two sets of k-times low-pass filtered signals;

[0119] Each module or unit is programmed or configured to execute the steps of a low-pass filtering digital phase-locked method as described in Example 1.

[0120] The low-pass filtering digital phase-locked system implemented in this invention has a compact and simple structure and can extract the target signal efficiently and with high fidelity.

[0121] Example 3

[0122] This embodiment further provides a design method for a low-pass filter digital phase-locked system, which is applied to a low-pass filter digital phase-locked system as described in Example 2:

[0123] Case 1: At the current low-pass filter time constant Under the condition of being determined, the value of the number k of low-pass filter units connected in series in the low-pass filter module is designed, including the following contents:

[0124] After determining the frequency range of the target voltage signal, take the upper limit of the frequency range as the cutoff frequency ,but ,in, Indicates rounding up; that is, the minimum value of k is .

[0125] Under the condition of limited cost, the number of low-pass filter units connected in series in the low-pass filter module is k= , we can ensure that the current low-pass filter digital phase-locked system can filter out the cutoff frequency while reducing costs. Noise signal above this limit ensures the cutoff frequency The following target voltage signal can be completely retained, avoiding the loss of part of the target voltage signal during the filtering process, which would result in serious distortion of the filtered waveform.

[0126] Case 2: When the number of low-pass filter units connected in series in the current low-pass filter module is determined, the time constant of the current low-pass filter is The design includes the following:

[0127] After determining the frequency range of the target voltage signal, take the upper limit of the frequency range as the cutoff frequency ,but , that is, the time constant The minimum value of .

[0128] Under the condition of limited cost, the number k of low-pass filter units connected in series in the low-pass filter module is also determined, so that the time constant exist The above can ensure that the current low-pass filter digital phase-locked system can filter out the cutoff frequency above the noise signal and retain the cutoff frequency The following target voltage signal avoids the loss of part of the target voltage signal during the filtering process, which may cause serious distortion of the filtered waveform.

[0129] If the components in the current low-pass filter module cannot meet the time constant exist If the above is the case, the technicians need to replace the component models in the current low-pass filter module.

[0130] After the design of a low-pass filtering digital phase-locked system is completed, a low-pass filtering digital phase-locked method as described in Example 1 can be used to filter the mixed voltage digital signal.

[0131] As shown in Table 1, some time constants calculated by technicians are as follows: The corresponding cutoff frequency , technicians can also directly determine a cutoff frequency based on Table 1 without calculation. The corresponding time constant At what level (for example, 100ns level, 409.6 µs level, etc.) can we quickly determine whether the component models in the current low-pass filter module can meet the filtering requirements and realize the rapid configuration of the low-pass filter unit.

[0132] Table 1 Time constants and cutoff frequency Correspondence table

[0133] ;

[0134] The low-pass filter digital phase-locked system of the present invention can be applied in various fields, such as spectral detection. Spectra of different bands correspond to different frequency ranges. When detecting a specific band of spectrum, technicians are aware of the frequency range of the target band spectrum, and they hope to filter out spectra of other bands during the detection process, focusing the detection results only on the target band spectrum. To achieve this goal, it is necessary to design the low-pass filter digital phase-locked system so that it can filter out noise signals above the cutoff frequency, and even reduce the number of low-pass filter units while maintaining the filtering effect, thereby further reducing costs.

[0135] The design method of this embodiment enables the low-pass filtering digital phase-locked system to be flexibly configured simply and quickly, reducing system costs while better adapting to various signal processing requirements in different application scenarios, thereby improving the versatility of the low-pass filtering digital phase-locked system.

[0136] The technologies, shapes, and structures not described in detail in this embodiment are all well-known technologies. It should also be pointed out that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. The components or steps in this embodiment can be decomposed and / or recombined, and such decompositions and / or recombinations should be regarded as equivalent solutions of this application and should fall within the scope of protection of the present invention.

Claims

1. A design method for a low-pass filtering digital phase-locked system, characterized by: A low-pass filtering digital phase-locked system includes a low-pass filtering module consisting of k low-pass filtering units connected in series; two groups of mixed frequency signals input to the low-pass filtering module are subjected to k low-pass filtering by the k low-pass filtering units, and two groups of k low-pass filtered signals are output; each low-pass filtering unit includes two filtering circuits for performing a low-pass filtering; each filtering circuit includes a first shifter, a second shifter, an adder, and a subtractor; the adder includes two inputs, the subtractor includes two inputs, and the subtractor includes three outputs; the input end of the first shifter receives an input signal, the output end of the first shifter is connected to the first input end of the adder, the output end of the adder is connected to the first input end of the subtractor, the first output end of the subtractor is used to output the calculation result of the subtractor as the filtering result of the current filtering circuit, the second output end of the subtractor is connected to the second input end of the adder, the third output end of the subtractor is connected to the input end of the second shifter, and the second input end of the subtractor is connected to the output end of the second shifter; The time constant of the current low-pass filter If the frequency range of the target voltage signal is determined, the upper limit of the frequency range of the target voltage signal is taken as the cutoff frequency. , and then based on the cutoff frequency and time constant Design the minimum number k of low-pass filter units.

2. The design method of a low-pass filter digital phase-locked system according to claim 1, characterized in that: The low-pass filter digital phase-locked system also includes a first DDS module, a second DDS module, a multiplier module and a feature extraction module; the first DDS module and the second DDS module are respectively used to generate two sets of different sinusoidal reference signals; after the multiplier module receives the two sets of sinusoidal reference signals and the mixed voltage digital signal output by the first DDS module and the second DDS module, it mixes the two sets of sinusoidal reference signals with the mixed voltage digital signal and outputs two sets of mixed signals to the low-pass filter module; the low-pass filter module outputs two sets of k-times low-pass filtered signals and sends them to the feature extraction module; The feature extraction module obtains the characteristic parameters of the voltage signal based on two groups of k-th low-pass filtered signals.

3. The design method of a low-pass filter digital phase-locked system according to claim 1, characterized in that: Based on the cutoff frequency and time constant Design the minimum number of low-pass filter units k, then the minimum value of k is ;in, Indicates rounding up.

4. The design method of a low-pass filter digital phase-locked system according to claim 1, characterized in that: Alternatively, when the number k of low-pass filter units connected in series in the current low-pass filter module is determined, the time constant of the current low-pass filter is The design includes the following: After determining the frequency range of the target voltage signal, take the upper limit of the frequency range as the cutoff frequency ,but .

5. A digital phase-locked method, applied to a low-pass filter digital phase-locked system designed by the design method of a low-pass filter digital phase-locked system as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: S1, mixing the mixed voltage digital signal with two sets of different sinusoidal wave reference signals to obtain two sets of mixed signals; S2, performing k-times low-pass filtering on the two mixed signals respectively to obtain two sets of k-times low-pass filtered signals; k is a positive integer; S3, extracting characteristic parameters of the voltage signal in the mixed voltage digital signal: based on two groups of k-th low-pass filtered signals, obtaining the amplitude, initial phase, and frequency of the voltage signal.

6. A digital phase locking method according to claim 5, characterized in that: In S1, the following is also included: the first sinusoidal reference signal and mixed voltage digital signals After the mixing operation, the first mixed signal is obtained ; At the same time, the second sine wave reference signal and mixed voltage digital signals After the mixing operation, the second mixed signal is obtained ; The first sine wave reference signal With the second sine wave reference signal The amplitudes are the same and the phase difference is 90 degrees.

7. A digital phase locking method according to claim 5 or 6, characterized in that: In S2, when k=1, the following sub-steps are also included: S21, respectively obtain the discrete low-pass filtering signal points of the two groups of mixed signals after the first low-pass filtering: ; in, Represents the i-th mixing signal The Nth low-pass filtered signal point value obtained after the first low-pass filtering, where N is a positive integer; i = 1 or 2; Represents the i-th mixing signal The value of the Nth sampling point in ; and The corresponding time points are the same; Indicates the i-th mixing signal The initial sampling point value obtained by sampling at time t=0; when N=1, ; represents a natural constant; Indicates the sampling time, which is the duration between adjacent sampling points; S22, respectively fitting the two groups of discrete first-order low-pass filtered signal points into two groups of first-order low-pass filtered signals.

8. A digital phase locking method according to claim 7, characterized in that: In S21~S22, the calculation of obtaining a low-pass filter signal point is simplified by the shifter, adder and subtractor in the low-pass filter unit: , r represents the number of shifts and r is a positive integer, use replace ,use replace Then, we get the expression of the number of moving bits of the two sets of primary low-pass filtered signal points: ； All signal points entering the first shifter or the second shifter are right-shifted by r bits and then output; the corresponding waveforms fitted from all low-pass filtered signal points output from the first output end of the subtractor are output as the low-pass filtered signals of the current low-pass filtering unit.

9. A digital phase locking method according to claim 7, characterized in that: When k>1, S23 is further included after S22: S23 returns to S21, obtains the secondary low-pass filtered signals obtained after the second low-pass filtering of the two sets of primary low-pass filtered signals, and repeats S21 to S23 until two sets of k-th low-pass filtered signals are obtained; The first output end of the subtractor in the previous low-pass filter unit is connected to the input end of the first shifter in the corresponding filter circuit in the next low-pass filter unit; the first mixing signal and the second mixed signal It is the input of the first low-pass filter unit. After k low-pass filtering, the k-th low-pass filter unit outputs two sets of corresponding k-th low-pass filtered signals. and .

10. A digital phase locking method according to claim 5, characterized in that: In S3, the following is also included: obtaining the frequencies and values ​​at the initial phases of two sets of k-th low-pass filtered signals and After that, the initial phase of the voltage signal is obtained. and the amplitude of the voltage signal , The frequency, amplitude and initial phase of the two sets of k-th low-pass filtered signals are the same, and are also characteristic parameters of the voltage signal.

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