A high-voltage PCB current path optimization design method and system based on a large model

Abstract

This application relates to the field of high-voltage PCB design technology, specifically providing a high-voltage PCB current path optimization design method and system based on a large model. The method includes the following steps: S2, obtaining the current distribution using an electrical simulation model based on electrical parameters and layout information; S3, obtaining the temperature field distribution based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate; S4, obtaining the first thermomechanical stress distribution based on the temperature field distribution, the thermal expansion coefficients of the via array and the PCB substrate, and the elastic modulus of the via array and the PCB substrate; S5, analyzing whether the first thermomechanical stress distribution meets preset requirements. If yes, the new layout information is used as the final layout information; otherwise, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution, and the process returns to step S2. This method can solve the problems of local hot spots and thermomechanical stress caused by uneven current distribution in the via array of high-voltage PCBs.

Description

Technical Field

[0001] This application relates to the field of high-voltage PCB design technology, and more specifically, to a high-voltage PCB current path optimization design method and system based on a large model. Background Technology

[0002] In the field of electronic devices, high-voltage PCB design significantly reduces product size and achieves high power density by compactly stacking power circuits, control circuits, and drive circuits in a multi-layer structure. The industry commonly uses via arrays to carry large currents and employs EDA software for layout and routing design. This software calculates the minimum number of vias required based on the total current and the rated current-carrying capacity of individual vias, and tends to arrange these vias in a regular matrix form below the pads of power devices or at the corners of current paths. The design process focuses on macroscopic performance indicators such as overall voltage drop, temperature rise, and parasitic inductance to meet space constraints and efficiency requirements, driving the technology towards more efficient integration.

[0003] However, current flow follows the principle of the path of least impedance. For a current path entering from the PCB surface and flowing through the via array to the inner layers, the current is not evenly distributed among each parallel via as ideally. Furthermore, due to current congestion, most of the current concentrates in the first few vias encountered and closest to the current inlet. This means the current distribution within the via array is uneven, with edge vias carrying the majority of the current while the central vias experience very little current. This leads to highly uneven local heat generation and the formation of micro-hot spots. Because of the difference in thermal expansion coefficients between the vias and the PCB substrate, this difference causes mismatched expansion during temperature changes. This results in periodic thermomechanical stress within the via structure; each temperature cycle causes stress loading and unloading of the via structure grains. Therefore, repeated thermal cycling accelerates material fatigue, induces microcracks, and may develop into open-circuit via failures. Existing PCB design methods treat electrical performance, thermal performance, and mechanical reliability as independent optimization objectives. In other words, existing technologies lack a design method that can couple current distribution, thermal distribution, and thermomechanical stress for integrated analysis and optimization. Therefore, existing technologies cannot fundamentally prevent long-term reliability problems caused by uneven current distribution.

[0004] Currently, there is no effective technical solution to the above-mentioned problems. It should be noted that the information disclosed in this section is only for understanding the background of the present invention and therefore may include information that does not constitute prior art. Summary of the Invention

[0005] The purpose of this application is to provide a current path optimization design method and system for high-voltage PCBs based on a large model, which can solve the problems of local hot spots and thermomechanical stress caused by uneven current distribution in the via array of high-voltage PCBs.

[0006] Firstly, this application provides a high-voltage PCB current path optimization design method based on a large model, which includes the following steps:

[0007] S1. Obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array;

[0008] S2. Use the electrical simulation model to obtain the current distribution of the via array based on electrical parameters and layout information;

[0009] S3. Obtain the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate.

[0010] S4. Obtain the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate.

[0011] S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If yes, use the new layout information as the final layout information of the via array. If no, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain the new layout information, and return to step S2.

[0012] Secondly, this application also provides a high-voltage PCB current path optimization design system based on a large model, which includes:

[0013] The information acquisition module is used to acquire the electrical parameters of the current path of the high-voltage PCB and the initial layout information of the via array;

[0014] The current distribution acquisition module is used to obtain the current distribution of the via array based on electrical parameters and layout information using an electrical simulation model;

[0015] The temperature field distribution acquisition module is used to acquire the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate.

[0016] The stress distribution acquisition module is used to acquire the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate.

[0017] The layout optimization module is used to analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information, and the current distribution acquisition module is triggered to run.

[0018] As can be seen from the above, the high-voltage PCB current path optimization design method and system provided in this application solves the problems of local hot spots and thermomechanical stress caused by uneven current distribution in the via array of high-voltage PCBs by coupling electrical simulation, thermal simulation and mechanical simulation and introducing an iterative optimization mechanism. This achieves integrated optimization design of electrical performance, thermal performance and mechanical reliability, thereby effectively improving the long-term reliability of high-voltage PCBs. Attached Figure Description

[0019] Figure 1 A flowchart illustrating a high-voltage PCB current path optimization design method based on a large model, provided for embodiments of this application.

[0020] Figure 2 This is a schematic diagram of a high-voltage PCB current path optimization design system based on a large model, provided in an embodiment of this application.

[0021] Reference numerals: 1. Information acquisition module; 2. Current distribution acquisition module; 3. Temperature field distribution acquisition module; 4. Stress distribution acquisition module; 5. Layout optimization module. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Firstly, such as Figure 1As shown, this application provides a high-voltage PCB current path optimization design method based on a large model, which includes the following steps:

[0025] S1. Obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array;

[0026] S2. Use the electrical simulation model to obtain the current distribution of the via array based on electrical parameters and layout information;

[0027] S3. Obtain the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate.

[0028] S4. Obtain the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate.

[0029] S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If yes, use the new layout information as the final layout information of the via array. If no, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain the new layout information, and return to step S2.

[0030] The electrical parameters in step S1 may include current magnitude, voltage level, operating frequency, signal integrity requirements, etc. The layout information in step S1 may include the initial position coordinates of the vias, the diameter of the vias, the length of the vias, the shape of the vias, and the arrangement of the via array, etc. Step S1 can be achieved by using design input files, importing CAD data, manual input by the user, or extraction from an existing design database to obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array. This embodiment provides the necessary prerequisites for subsequent simulation and analysis by collecting this basic data, enabling the entire design process to be based on real design requirements and physical constraints.

[0031] The electrical simulation model in step S2 can employ methods such as the Finite Element Method (FEM), Finite Difference Time Domain Method (FDTD), Transmission Line Matrix Method (TLM), or SPICE-based circuit simulation models. The specific process of step S2 is as follows: the electrical parameters and layout information obtained in step S1 are input into a pre-trained three-dimensional electromagnetic field model of the via array. This model calculates the current density distribution inside each via and the entire via array by solving Swell's equations based on the input electrical parameters and layout information, thus obtaining the current distribution. Therefore, this embodiment can accurately simulate the actual current flow in the via array using the electrical simulation model based on the electrical parameters and layout information. In other words, the current distribution in this embodiment can reveal the current congestion effect and non-uniform distribution phenomenon, directly addressing the problem caused by uneven current distribution mentioned in the background art, and providing accurate input for subsequent thermal and stress analysis.

[0032] Step S3 correlates electrical and thermal performance by obtaining the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate. The resistivity of the via array in Step S3 refers to the resistivity of the via material (e.g., copper), which determines the Joule heat generated when current flows through the via array. In this embodiment, the resistivity of the via array can be obtained by querying a material resistivity database based on a pre-set via material; that is, the resistivity is a pre-set or pre-measured value. The thermal conductivity of the PCB substrate in Step S3 refers to the ability of the substrate material (e.g., FR-4) to conduct heat. This thermal conductivity affects the diffusion of heat within the substrate. In this embodiment, the thermal conductivity of the PCB substrate can be obtained by querying a PCB substrate performance database based on the PCB substrate's markings (e.g., a QR code or barcode affixed to the PCB substrate); that is, the thermal conductivity of the PCB substrate is a pre-set or pre-measured value. The specific process of step S3 can be as follows: Calculate the local heat generation rate (power dissipation) of each via and its surrounding area based on the current distribution and the resistivity of the via array; then, use a thermal simulation model (e.g., a heat conduction model based on the finite element method) to solve the heat conduction equation based on these local heat generation rates and the thermal conductivity of the PCB substrate to predict how heat diffuses and accumulates in the via array, thereby obtaining the temperature field distribution of the via array. It should be understood that this embodiment can identify potential micro-hot spots based on the temperature field distribution. This step is crucial for understanding the root causes of thermomechanical stress, as temperature changes are a direct cause of thermal stress.

[0033] Step S4 tightly integrates thermal and mechanical properties by obtaining the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate. The thermal expansion coefficient in Step S4 represents the degree to which the material expands or contracts with temperature changes, and the elastic modulus in Step S4 represents the material's ability to resist elastic deformation. The specific process of Step S4 can be as follows: Calculate the mismatched expansion or contraction caused by temperature changes using the temperature field distribution combined with the difference in thermal expansion coefficients between the via material (e.g., copper) and the PCB substrate material (e.g., FR-4); quantify the thermomechanical stress surface generated by this mismatched expansion using the elastic modulus of the via material and the PCB substrate material. For example, use structural mechanics simulation software (e.g., a stress analysis model based on the finite element method) to calculate the stress distribution at the via-substrate interface, inside the via, and the entire via array.

[0034] The preset requirements for step S5 may include maximum allowable stress value, fatigue life requirements, and reliability indicators. Step S5 is equivalent to evaluating the first thermomechanical stress distribution obtained in step S4 according to the preset requirements to determine whether it is within an acceptable range. If the stress is too high or does not meet the requirements, the layout parameters of the via array are intelligently adjusted according to the stress distribution (first thermomechanical stress distribution). Specifically, this embodiment can use optimization algorithms (such as genetic algorithms, particle swarm optimization, and machine learning-based optimization algorithms) to guide the adjustment of layout parameters to reduce stress concentration. This stress feedback-based adjustment mechanism can effectively alleviate stress concentration and optimize the structure of the via array, thereby fundamentally preventing material fatigue and failure caused by repeated thermal cycling. The adjusted new layout information is returned to step S2, forming a closed-loop optimization process to ensure that the final design achieves optimal electrical, thermal, and mechanical performance, thereby effectively solving the problem of the lack of integrated analysis and optimization in existing technologies. This application can couple electrical performance analysis, thermal performance analysis and mechanical performance analysis through the iterative loop of steps S2-S5 to form a unified optimization framework, thereby fundamentally solving the local hot spots, thermomechanical stress and long-term reliability problems caused by uneven current distribution.

[0035] The core innovation of this application lies in solving the problems of local hot spots and thermomechanical stress caused by uneven current distribution in the via array of high-voltage PCBs by coupling electrical simulation, thermal simulation and mechanical simulation and introducing an iterative optimization mechanism. This achieves integrated optimization design of electrical performance, thermal performance and mechanical reliability, thereby effectively improving the long-term reliability of high-voltage PCBs.

[0036] Specifically, this method first obtains the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array to provide basic data for subsequent simulation analysis. Next, an electrical simulation model is used to simulate and obtain the current distribution inside the via array based on the electrical parameters and layout information to identify current congestion areas. Based on this, thermal simulation is used to calculate the temperature field distribution of the via array by combining the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate to predict potential hot spots. Further, mechanical simulation is used to calculate the thermomechanical stress distribution inside the via array based on the temperature field distribution and the coefficients of thermal expansion and elastic modulus of the via array and the PCB substrate to quantify the mechanical load on the via array under operating conditions. Subsequently, the calculated thermomechanical stress distribution is evaluated to determine whether it meets the preset reliability requirements. If the stress distribution meets the requirements, the current layout information is determined as the final layout. Conversely, if the stress distribution does not meet the requirements, the layout parameters of the via array are adjusted according to the stress analysis results to alleviate stress concentration and generate new layout information. Subsequently, the new layout information is fed back to the electrical simulation step to form a closed-loop iterative optimization process and enable the design to continuously approach the optimal solution, thereby fundamentally solving the thermomechanical stress problem caused by uneven current distribution and realizing the coupled optimization of electrical, thermal and mechanical performance.

[0037] As a preferred embodiment, the solution of this application is implemented as follows: When designing a high-voltage PCB, the current requirements of the power module, the PCB stack-up structure, and the initial arrangement of vias are first input. Then, electrical simulation software (such as Ansys Maxwell or CST Studio Suite) is used to simulate the current density of the via array based on the current requirements, PCB stack-up structure, and initial via arrangement to obtain the current carrying capacity (current distribution) of each via. Thermal simulation software (such as Ansys Icepak or Flotherm) is used to calculate the temperature field of the via array region based on this current distribution, combined with the resistivity of the via material and the thermal conductivity of the PCB substrate, to obtain the temperature field distribution and identify possible hot spots. Subsequently, the temperature field data is imported into structural mechanics simulation software (such as Ansys Mechanical or Abaqus), and the thermomechanical stress distribution (first thermomechanical stress distribution) at the via-substrate interface is calculated by combining the thermal expansion coefficients and elastic moduli of the vias and substrate. If the calculated maximum stress value exceeds the material's fatigue limit or a preset safety threshold, optimization algorithms or design rules are used to adjust the relative positions of vias, via spacing, or the overall shape of the via array based on the thermomechanical stress distribution. For example, the via spacing in areas with high current density is increased, or the number of vias in those areas is increased to disperse current and stress. The adjusted layout information is then input into the electrical simulation stage, and the above simulation and evaluation process is repeated until the thermomechanical stress distribution meets all design requirements, ultimately determining the optimized layout of the high-voltage PCB via array. This method achieves integrated optimization design of electrical performance, thermal performance, and mechanical reliability, avoiding failure modes that traditional independent optimization methods cannot fundamentally prevent, thereby improving the stability and service life of high-voltage PCBs under complex operating conditions.

[0038] In some preferred embodiments, the layout parameters include the relative positions of vias, via spacing, and the overall shape of the via array. The relative positions of vias refer to the coordinate relationships between individual vias in a two-dimensional or three-dimensional space. This embodiment can use a grid coordinate system or a local coordinate system to accurately describe the center point position of each via. Alternatively, it can define vector relationships between vias to describe the coordinate relationships between individual vias in two-dimensional or three-dimensional space. Via spacing refers to the straight-line distance between the center points of any two adjacent vias. This embodiment can use uniform spacing, non-uniform spacing, or spacing based on a specific function distribution to set the via spacing. For example, the spacing can be dynamically adjusted based on current density or thermal stress gradient. The overall shape of the via array refers to the macroscopic geometric contour formed by all the vias constituting the via array. This overall shape can be a rectangle, circle, ellipse, L-shape, T-shape, or any irregular polygon. This embodiment can determine its macroscopic contour based on the available space on the PCB board or the current flow direction.

[0039] This application provides a clear and operable dimension for adjusting the via array layout based on the first thermomechanical stress distribution by explicitly defining the specific composition of the layout parameters, enabling the design method to more accurately solve thermomechanical stress problems caused by unreasonable layout. Specifically, when the via array needs to be optimized based on the first thermomechanical stress distribution, the design method can simultaneously consider adjusting the relative positions of the vias, the via spacing, and the overall shape of the via array. This embodiment can finely control the current distribution in the via array by adjusting the relative positions of the vias. For example, when local stress concentration or hot spots are found, specific vias can be strategically moved to move them away from high current density areas or to more evenly distribute the current path, thereby reducing local current density and reducing the formation of micro hot spots, thus alleviating thermomechanical stress concentration caused by uneven temperature. This embodiment can optimize the diffusion path of current in the via array and the heat conduction efficiency in the PCB substrate by adjusting the via spacing. For example, when stress analysis shows that there are excessive differences in thermal expansion or stress superposition between vias, the distance between adjacent vias can be appropriately increased or decreased to promote heat diffusion in the PCB substrate and reduce local temperature rise. This embodiment optimizes the macroscopic layout of the via array by adjusting its overall shape, allowing it to better adapt to the current paths and space constraints of high-voltage PCBs. For example, the array's geometry can be altered to optimize current inlet and outlet distribution, further balancing current distribution throughout the array. This embodiment combines microscopic via relative positions and spacing adjustments with macroscopic adjustments to the overall via array shape, enabling multi-level adjustments and comprehensive handling of complex electrical, thermal, and mechanical coupling issues. In this way, the design method moves beyond coarse adjustments based on macroscopic stress distribution to fine-tuning at the microstructural level of the via array, effectively reducing thermomechanical stress and improving the long-term reliability of high-voltage PCBs. This refined definition of layout parameters provides richer and more effective adjustment strategies during iterative optimization based on thermomechanical stress distribution, achieving a better balance between electrical performance, thermal performance, and mechanical reliability, significantly improving the accuracy and effectiveness of the optimization design.

[0040] In some preferred embodiments, the process of adjusting the layout parameters of the via array according to the first thermomechanical stress distribution includes:

[0041] A1. Obtain the first electrical performance parameters of the current via array;

[0042] A2. Generate multiple candidate via array layout schemes based on the first thermomechanical stress distribution;

[0043] A3. For each candidate via array layout scheme, obtain the second electrical performance parameter and the second thermomechanical stress distribution corresponding to the candidate via array layout scheme. Then, calculate the performance parameter change based on the first electrical performance parameter and the second electrical performance parameter, and obtain the thermomechanical stress balance based on the second thermomechanical stress distribution.

[0044] A4. Select the target via array layout scheme from all candidate via array layout schemes based on the degree of thermomechanical stress balance and the amount of performance parameter change, and adjust the layout parameters of the via array according to the target via array layout scheme.

[0045] The first electrical performance parameter refers to the quantitative index of the electrical characteristics of the current via array under a specific operating state (e.g., its resistance, inductance, or impedance). This first electrical performance parameter provides a benchmark for subsequent evaluation of the impact of different layout schemes on electrical performance. Generating multiple candidate via array layout schemes refers to systematically creating a series of new, potentially optimized via array configurations based on the current thermomechanical stress distribution using algorithms or heuristic rules. Each candidate via array layout scheme can be a set that differs in the number of vias, their relative positions, spacing, or overall geometry. This embodiment is equivalent to exploring a broader design space by generating multiple candidate via array layout schemes based on the first thermomechanical stress distribution, in order to find a better solution. The performance parameter change is a quantitative difference obtained by comparing the electrical performance parameters of the candidate via array layout schemes with those of the current via array. This performance parameter change is used to measure the degree of impact of the new layout scheme on the original electrical performance. Thermomechanical stress uniformity is an indicator that measures the uniformity of thermomechanical stress distribution within a via array. This uniformity reflects the degree to which stress is dispersed among various vias or regions. Generally, the more uniform the stress distribution, the higher the long-term reliability of the via array. This embodiment can obtain the thermomechanical stress uniformity by calculating the standard deviation of stress values ​​or the ratio of maximum stress to average stress. The step of selecting a target via array layout scheme refers to selecting the best-performing or most suitable via array layout scheme based on preset optimization objectives or comprehensive evaluation criteria after evaluating the electrical performance variations and thermomechanical stress uniformity of all candidate via array layout schemes.

[0046] Before initiating layout parameter adjustments, this scheme first acquires the initial electrical performance parameters of the current via array to provide a quantitative benchmark for evaluating the impact of new layout schemes on electrical performance. Subsequently, based on the current initial thermomechanical stress distribution, multiple different candidate via array layout schemes are intelligently generated. This generation process utilizes stress concentration information to guide the formation of new schemes; for example, stress can be dispersed by adjusting the relative position, spacing, or overall shape of the vias, thereby expanding the scope of design exploration. For each generated candidate via array layout scheme, the scheme performs comprehensive simulation and evaluation. Specifically, the scheme first acquires the second electrical performance parameters and the second thermomechanical stress distribution corresponding to the candidate via array layout scheme. Then, it calculates the change in performance parameters by comparing the second electrical performance parameters with the previously acquired first electrical performance parameters to quantify the impact of the new scheme on electrical performance. Simultaneously, based on the second thermomechanical stress distribution, the scheme obtains the degree of thermomechanical stress uniformity to measure the uniformity of its stress distribution. This scheme ensures the comprehensiveness of the optimization process by simultaneously evaluating electrical performance and thermomechanical stress, avoiding the problem of neglecting one aspect for another. Finally, after a comprehensive evaluation of all candidate schemes, the optimal target via array layout scheme is selected based on the degree of thermomechanical stress balance and the change in performance parameters. This selection process typically involves a comprehensive evaluation index that balances the improvement of electrical performance and the optimization of thermomechanical stress. In this way, it is ensured that the final selected layout scheme not only effectively reduces thermomechanical stress but also maintains or improves electrical performance, thereby achieving comprehensive optimization of the high-voltage PCB current path. After selecting the target layout scheme, the layout parameters of the via array are adjusted accordingly to complete an iterative optimization. This adjustment process is closely integrated with the analysis of the first thermomechanical stress distribution in the above scheme. When the analysis results show that the stress does not meet the requirements, this adjustment process is triggered. By systematically exploring and evaluating multiple layout schemes, an efficient optimized solution that balances electrical performance and thermomechanical stress is found. After the adjustment is completed, the new layout information is fed back to the current distribution acquisition step, forming a closed-loop optimization cycle. This iterative and multi-objective evaluation mechanism makes the optimization process no longer blind or heuristic, but systematically converges to a better solution, thereby fundamentally solving the problems of local hot spots and stress concentration caused by uneven current distribution, and significantly improving the long-term reliability of high-voltage PCB current paths.

[0047] As a preferred implementation, the first electrical performance parameters of the current via array are obtained by simulating and analyzing the geometric model of the current via array using professional electrical simulation software (such as ANSYS Q3D Extractor). For example, the total resistance and parasitic inductance of the current via array at a specific operating frequency are used as the first electrical performance parameters. Further, an intelligent optimization algorithm (such as a genetic algorithm or particle swarm optimization algorithm) is used to generate multiple candidate via array layout schemes based on the first thermomechanical stress distribution. This algorithm can automatically generate a series of via array layouts with different geometric characteristics, guided by high-stress areas or stress concentration points identified in the first thermomechanical stress distribution. For example, if the stress value of a certain via or region exceeds a threshold, the algorithm can try to increase the number of vias in that region, adjust the relative positions of the vias to disperse the current, or change the overall shape of the via array (such as changing from a regular rectangular array to a more adaptable irregular array to the current path) to more effectively disperse the thermomechanical stress. This embodiment fully explores the design space by generating multiple candidate via array layout schemes based on the first thermomechanical stress distribution. For each candidate via array layout scheme, detailed simulation analysis is performed using electrical simulation software to obtain the corresponding second electrical performance parameters. Steps S2-S4 are then used to obtain the thermomechanical stress distribution of this scheme, resulting in the second thermomechanical stress distribution. Subsequently, these second electrical performance parameters are compared with the previously obtained first electrical performance parameters to calculate the changes in performance parameters such as the rate of change of resistance and the rate of change of inductance. Simultaneously, based on the second thermomechanical stress distribution, the standard deviation of all via stress values ​​is calculated, or the ratio of the maximum stress to the average stress is calculated. This serves as a quantitative indicator of the degree of thermomechanical stress uniformity; for example, a smaller stress standard deviation indicates a more uniform stress distribution and a higher degree of thermomechanical stress uniformity. Finally, when selecting the target via array layout scheme, a pre-defined comprehensive evaluation function is used to weight and sum the degree of thermomechanical stress balance and the change in performance parameters to balance the importance of different optimization objectives. This comprehensive evaluation function can assign a high weight to the degree of thermomechanical stress balance, while setting a penalty for the deterioration of electrical performance or a reward for the improvement of electrical performance. For example, if the objective is to minimize the stress standard deviation and minimize the increase in resistance, then the comprehensive evaluation function is: Comprehensive evaluation score = w1 × (stress standard deviation) + w2 × (resistance change), where w1 and w2 are pre-defined weight coefficients. By calculating the comprehensive evaluation score of each candidate scheme, the scheme with the highest (or lowest, depending on the function definition) is selected as the target via array layout scheme. Once the target layout scheme is selected, the specific geometric parameters contained in the target layout scheme (such as the precise location, spacing, and overall shape of the vias) are applied to complete the adjustment of the via array layout parameters.This embodiment comprehensively explores the design space by obtaining the current electrical performance parameters as a benchmark before adjustment and intelligently generating multiple candidate layout schemes based on the thermomechanical stress distribution. For each candidate scheme, both the change in electrical performance and the degree of thermomechanical stress balance are evaluated, ensuring the comprehensiveness of the optimization process and avoiding the limitations that may arise from a single optimization objective. Finally, an optimized scheme that takes into account both electrical performance and thermomechanical stress distribution is selected through a comprehensive screening mechanism, thereby fundamentally solving the problems of local hot spots and stress concentration caused by uneven current distribution, achieving a comprehensive performance improvement of the current path of high-voltage PCBs, and significantly enhancing their long-term operational reliability.

[0048] In some preferred embodiments, step A4 includes:

[0049] A41. Based on the preset manufacturing process constraint parameters, conduct a manufacturing process feasibility assessment on each candidate via array layout scheme, and then remove the candidate via array layout schemes that are deemed not to have manufacturing process feasibility. The preset manufacturing process constraint parameters include minimum hole diameter, minimum hole spacing and minimum line width.

[0050] A42. For each remaining candidate via array layout scheme, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance and the change in performance parameters.

[0051] A43. Select the target via array layout scheme from the remaining candidate via array layout schemes based on comprehensive evaluation indicators.

[0052] Preset manufacturing process constraints refer to the technical specifications and limitations that must be followed during PCB manufacturing. These can be set using industry standards, factory equipment capabilities, or specific product requirements. Manufacturing process feasibility assessment is a systematic check of whether a design meets these preset manufacturing process constraints. This can be achieved using automated design rule checking (DRC) tools or manual review. Lack of manufacturing process feasibility means that the design violates at least one preset manufacturing process constraint, making it impossible to produce using conventional manufacturing processes. Minimum aperture refers to the minimum diameter of a via that can be reliably produced in PCB manufacturing. This can be determined by the capabilities of specific drilling equipment or material properties. Minimum via spacing refers to the minimum permissible distance between the centers of adjacent vias, which can be considered using drilling precision, wiring density, or thermal effects. Minimum trace width refers to the minimum width of a conductor on a PCB that can be reliably etched and maintain electrical connections, which can be limited by etching process precision or current carrying capacity. The comprehensive evaluation index refers to a unified value used to quantitatively evaluate the merits of different candidate via array layout schemes. It can be calculated using methods such as weighted summation, multi-objective optimization functions, or fuzzy comprehensive evaluation to comprehensively reflect the performance of the scheme in multiple performance dimensions.

[0053] The screening mechanism of this application ensures the actual manufacturability of the selected scheme by combining a manufacturing process feasibility assessment with a comprehensive evaluation of the degree of thermomechanical stress equilibrium and the variation of performance parameters, thereby improving the practicality and efficiency of the optimization results. Specifically, before screening the target via array layout scheme based on the degree of thermomechanical stress equilibrium and the variation of performance parameters, this embodiment first introduces a manufacturing process feasibility assessment. First, the system performs a manufacturing process feasibility assessment on all generated candidate via array layout schemes according to preset manufacturing process constraint parameters. This assessment aims to identify and remove design schemes that may theoretically have excellent performance but are practically unmanufacturable at an early stage. This embodiment effectively avoids subsequent invalid calculations and evaluations of these unmanufacturable schemes by excluding schemes that lack manufacturing process feasibility at the beginning of the screening process, thereby significantly improving the efficiency and practicality of the entire optimization process. Subsequently, for the remaining candidate via array layout schemes that have passed the manufacturing process feasibility assessment, the system calculates a comprehensive evaluation index based on the degree of thermomechanical stress equilibrium and the variation of performance parameters to scientifically compare the performance of different schemes in multiple dimensions and provide a unified and comprehensive evaluation standard for subsequent screening. Finally, based on the calculated comprehensive evaluation indicators, the system selects the optimal via array layout scheme from the remaining candidate schemes as the target via array layout scheme. This selection process ensures that the final selected scheme not only performs excellently in terms of electrical performance and thermomechanical reliability, but also fully meets the requirements of actual manufacturing processes. This combination allows the optimization design to move beyond the theoretical level and generate via array layout schemes that can be directly applied to actual production. This avoids the problems of optimization results being unimplementable or requiring extensive manual intervention, significantly improving the practicality and efficiency of high-voltage PCB current path optimization design.

[0054] In a specific embodiment, when it is necessary to select a target via array layout scheme from multiple candidate schemes, the following steps can be taken. First, during the manufacturing process feasibility assessment, a series of manufacturing process constraint parameters can be preset. For example, the minimum hole diameter can be set to 0.2 mm, the minimum hole spacing can be set to 0.4 mm, and the minimum linewidth can be set to 0.1 mm. The system can use automated design rule checking (DRC) software to scan each candidate via array layout scheme to check whether it meets these preset geometric dimensions and spacing requirements. Any scheme that does not meet these parameters (e.g., a via diameter less than 0.2 mm or a center-to-center distance between adjacent vias less than 0.4 mm) will be marked as not having manufacturing process feasibility and removed from the candidate list. Next, a comprehensive evaluation index is calculated for the remaining candidate via array layout schemes that have passed the manufacturing process feasibility assessment. For example, a weight is assigned to the degree of thermomechanical stress balance, and another weight is assigned to the variation of performance parameters. The two are then weighted and summed to obtain the final comprehensive evaluation index. The weights can be determined according to the emphasis on reliability and electrical performance in actual applications. Finally, the system can select the target via array layout scheme from the remaining candidate schemes based on a comprehensive evaluation index. For example, if a smaller comprehensive evaluation index is better (e.g., representing a combination of stress imbalance and performance degradation), the scheme with the smallest comprehensive evaluation index is selected as the target via array layout scheme. If a larger comprehensive evaluation index is better (e.g., representing superior overall performance), the scheme with the largest comprehensive evaluation index is selected. This scheme ensures the actual manufacturability of the selected scheme by introducing a manufacturing process feasibility assessment during the selection process and by selecting based on a comprehensive evaluation index. Therefore, this embodiment can avoid generating optimized schemes that are not practically applicable, thereby reducing the need for subsequent manual intervention and adjustments, and effectively improving the practicality and efficiency of the optimization design. Furthermore, this embodiment can avoid invalid calculations and evaluations of unmanufacturable schemes by excluding them at an early stage, thus improving the efficiency of the entire optimization process.

[0055] In some preferred embodiments, step A42 includes:

[0056] A421. Obtain the preset operating condition information of the PCB substrate;

[0057] A422. Determine the first weighting weight corresponding to the degree of thermomechanical stress equilibrium and the second weighting weight corresponding to the change in performance parameters based on the preset operating condition information.

[0058] A423. For each remaining candidate via array layout scheme, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance, the amount of performance parameter change, the first weighting weight, and the second weighting weight.

[0059] Preset operating condition information refers to data about the working environment and load conditions of the PCB substrate, which are pre-set or acquired in real time before actual application or operation. This data can be characterized by parameters including operating temperature range, current load magnitude, vibration frequency and amplitude, humidity, and heat dissipation conditions. The first and second weighting weights are numerical factors used to adjust the relative importance of the degree of thermomechanical stress equilibrium and the variation of performance parameters in the calculation of the comprehensive evaluation index. These factors can be determined using rule-based lookup tables, expert systems, or by generating data from historical data and operating condition information through machine learning models. The comprehensive evaluation index is a quantifiable value used to comprehensively measure the overall performance of different candidate via array layout schemes under specific operating conditions. It can be calculated using weighted summation, weighted product, or other multi-objective decision-making methods to reflect the comprehensive performance of thermomechanical reliability and electrical performance.

[0060] This application proposes an improved method for calculating comprehensive evaluation metrics. First, by acquiring preset operating condition information of the PCB substrate, crucial contextual data is provided for the subsequent evaluation process. This operating condition information forms the basis for determining the performance and reliability priorities of the via array in practical applications. Then, the system dynamically determines a first weighting weight corresponding to the degree of thermomechanical stress equilibrium and a second weighting weight corresponding to the change in performance parameters based on the preset operating condition information. This dynamic adjustment mechanism makes the evaluation no longer static and generalized, but allows for adjustments to the emphasis on thermomechanical reliability and electrical performance according to specific application scenarios. For example, under conditions with high requirements for thermomechanical reliability, the first weighting weight can be set to a higher value to ensure the via array can withstand extreme temperature cycling or vibration; while under conditions with high requirements for electrical performance, the second weighting weight can be set to a higher value to optimize current transmission efficiency and signal integrity. Finally, for each candidate via array layout scheme that has undergone manufacturing process feasibility assessment, the final comprehensive evaluation metric is calculated by combining the degree of thermomechanical stress equilibrium, the change in performance parameters, and the first and second weighting weights dynamically determined based on the current operating conditions. This weighted calculation method enables the comprehensive evaluation index to accurately reflect the actual performance of each candidate scheme under specific operating conditions. In this way, subsequent screening steps can be based on a targeted and accurate comprehensive evaluation index, thereby identifying via array layout schemes that perform well and have high reliability under specific operating conditions from among numerous candidate schemes. This not only improves the optimization effect of the layout scheme but also ensures that the final design better meets the needs of practical applications, effectively solving the problems of inaccurate evaluation and poor optimization effect caused by traditional methods failing to fully consider actual operating conditions.

[0061] In one specific embodiment, the preset operating condition information of the PCB substrate can be obtained through user interface input. For example, designers can manually select preset modes such as "high temperature and high humidity environment," "high frequency signal transmission," or "high current pulse load." The first and second weighting weights determined based on the obtained preset operating condition information can be determined using a rule-based lookup table or dynamically generated by an expert system. The lookup table is as follows: if the operating condition information indicates "high temperature cycling," the first weighting weight is set to 0.7 and the second weighting weight to 0.3 to prioritize thermomechanical stress balance; if the operating condition information indicates "high frequency signal transmission," the first weighting weight is set to 0.3 and the second weighting weight to 0.7 to prioritize changes in electrical performance parameters. For each remaining candidate via array layout scheme, the comprehensive evaluation index is calculated using a weighted summation method. The formula for calculating the comprehensive evaluation index is: Comprehensive Evaluation Index = (First Weighting Weight × Thermomechanical Stress Balance Degree) + (Second Weighting Weight × Performance Parameter Change). By acquiring preset operating condition information of the PCB substrate and dynamically determining the weighting of the thermomechanical stress balance and performance parameter changes based on this information, this embodiment enables the calculation of comprehensive evaluation indicators to better align with actual operating requirements. Therefore, this embodiment overcomes the limitations of traditional fixed-weight evaluation, ensuring that the emphasis on the thermomechanical reliability and electrical performance of the via array can be adaptively adjusted under different operating environments. Thus, this application can select target via array layout schemes suitable for specific operating conditions, thereby improving the optimization effect of the final layout scheme and enhancing the reliability and performance of the PCB substrate in practical applications.

[0062] In some preferred embodiments, the process of obtaining the degree of thermomechanical stress equilibrium based on the second thermomechanical stress distribution includes:

[0063] B1. Obtain the stress value of each through hole based on the second thermomechanical stress distribution;

[0064] B2. Calculate the stress standard deviation based on all stress values;

[0065] B3. Determine the degree of thermomechanical stress equilibrium based on the stress standard deviation and the maximum stress value.

[0066] Since the second thermomechanical stress distribution reflects the overall stress state of the via array under this layout scheme, this embodiment can refine the overall stress distribution to each individual via by obtaining the stress value of each via based on the second thermomechanical stress distribution. This allows for the analysis of the stress situation of individual vias, which is a prerequisite for accurately assessing stress uniformity. Based on this, this embodiment quantifies the dispersion of stress distribution in the via array by calculating the stress standard deviation. Specifically, the standard deviation is a statistical indicator that measures data volatility. The smaller the stress standard deviation, the closer the stress value of each via is to the average value, i.e., the more uniform the stress distribution; conversely, the larger the standard deviation, the more uneven the stress distribution. This step directly provides a key parameter for measuring the degree of uniformity, solving the problem of how to objectively assess stress uniformity. Finally, since even a small standard deviation can lead to reliability issues if all stress values ​​are very high, this embodiment effectively avoids the situation where relying solely on the standard deviation is insufficient to fully assess the degree of thermomechanical stress balance by determining the degree of thermomechanical stress balance based on the stress standard deviation and the maximum value of the stress. That is, this embodiment considers the concentration trend of stress distribution (reflected by the standard deviation) and extreme values ​​(reflected by the maximum value) when obtaining the degree of thermomechanical stress balance, thereby providing a more comprehensive and robust indicator of the degree of thermomechanical stress balance, and thus optimizing the overall design of the high-voltage PCB current path.

[0067] In some preferred embodiments, step S3 includes:

[0068] S31. Obtain the spatial location information, power dissipation characteristics and thermal boundary conditions of the power devices within the area where the via array is located;

[0069] S32. Obtain the external heat flux density distribution based on spatial location information, power dissipation characteristics, and thermal boundary conditions;

[0070] S33. Obtain the internal heat generation rate distribution based on the current distribution and the resistivity of the via array;

[0071] S34. Obtain the temperature field distribution of the via array based on the external heat flux density distribution, the internal heat generation rate distribution, and the thermal conductivity of the PCB substrate.

[0072] The spatial location information of power devices refers to their specific coordinates, dimensions, and relative position to the via array on the PCB board. This information can be obtained using CAD design files, layout databases, or 3D scanning data. Power dissipation characteristics refer to the amount of heat generated by the power devices during operation and its variation over time or under operating conditions. This information can be obtained using device datasheets, actual test data, or simulation models. Thermal boundary conditions refer to the heat exchange methods and parameters between the via array and its surrounding environment, such as ambient temperature, convective heat transfer coefficient, radiative heat transfer coefficient, or contact thermal resistance. These can be determined through environmental parameter settings, experimental measurements, or standard specifications. External heat flux density distribution refers to the distribution of heat transferred per unit area from external heat sources (such as power devices) to the via array area. This information can be obtained using thermal simulation software calculations, infrared thermal imager measurements, or theoretical formula derivation. External heat flux density distribution. The internal heat generation rate distribution refers to the heat distribution per unit volume or unit area inside the via array due to the Joule heating effect when current flows through it. In this embodiment, the internal heat generation rate distribution can be obtained by combining electrical simulation results with material resistivity calculations or measurements from a local temperature sensor array.

[0073] This application refines the steps for obtaining the temperature field distribution of a via array, aiming to comprehensively consider various heat sources affecting the temperature field of the via array, thereby obtaining a more realistic and accurate temperature field distribution. Specifically, firstly, the main external heat sources are identified and quantified by acquiring the spatial location information, power dissipation characteristics, and thermal boundary conditions of the power devices within the via array region. Since the layout of the power devices, their heat generation, and their heat exchange methods with the surrounding environment directly determine their thermal impact on the via array, this information is the basis for assessing external thermal effects. Secondly, how external heat is transferred to the via array region is quantified by calculating the external heat flux density distribution based on this power device thermal information (spatial location information, power dissipation characteristics, and thermal boundary conditions). Simultaneously, to fully consider all heat sources, this application obtains the internal heat generation rate distribution based on the current distribution and the resistivity of the via array. The internal heat generation rate distribution reflects the Joule heating effect generated when current flows through the via array itself, ensuring an accurate assessment of the via array's own heat generation. Finally, the obtained external heat flux density distribution and internal heat generation rate distribution are coupled with the thermal conductivity of the PCB substrate for comprehensive heat conduction calculations, thereby obtaining the temperature field distribution of the via array. This method, which comprehensively considers internal and external heat sources, allows the obtained temperature field distribution to more realistically reflect the actual operating temperature of the via array in the high-voltage PCB, thus effectively improving the accuracy and reliability of the first thermomechanical stress distribution. In the entire high-voltage PCB current path optimization design method, an accurate temperature field is a prerequisite for accurately assessing the thermomechanical stress of the via array, and accurate stress assessment is key to guiding layout parameter adjustments and achieving optimized design. Therefore, this example can more effectively identify potential stress concentration areas and guide layout adjustments by providing a more comprehensive temperature field model, thereby fundamentally improving the long-term reliability of high-voltage PCB design and avoiding via failure problems caused by thermomechanical stress.

[0074] In a specific embodiment, obtaining the spatial location information, power dissipation characteristics, and thermal boundary conditions of power devices within the via array area can be achieved as follows: Spatial location information is obtained by exporting the precise coordinates and dimensions of the power devices from PCB design software (e.g., Altium Designer or Cadence Allegro); power dissipation characteristics are obtained by consulting datasheets provided by the power device manufacturers; and thermal boundary conditions are set based on expert experience according to the system environment in which the PCB is located. For example, if the PCB is installed in a forced-air-cooled chassis, the convective heat transfer coefficient and ambient temperature can be set; if a heatsink is present, its thermal resistance and radiation characteristics can be considered. Then, a PCB-level thermal model is established using professional computational fluid dynamics (CFD) or finite element analysis (FEA) thermal simulation software based on the spatial location, power dissipation, and thermal boundary conditions of the power devices. The heat flux density distribution transferred from the power devices to the surrounding PCB area is obtained through simulation calculations to obtain the external heat flux density distribution. Simultaneously, current distribution simulation of the via array is first performed using electrical simulation tools (e.g., SPICE or Ansys Maxwell) to obtain the current density distribution of each via or via region. Then, Joule's law is used to calculate the heat generation rate distribution inside the via array based on the resistivity and current density distribution of the via material. Finally, when obtaining the temperature field distribution of the via array, the external heat flux density distribution and internal heat generation rate distribution obtained above are used as heat source inputs. Combined with the thermal conductivity of the PCB substrate (including in-plane and vertical thermal conductivity), thermal analysis of the via array region is performed using thermal conduction simulation software (e.g., finite element method-based thermal analysis tools). The three-dimensional temperature field distribution of the via array considering the coupling effect of internal and external heat sources is obtained by solving the heat conduction equation, thus providing accurate temperature data for subsequent stress analysis. This application, by considering not only the heat generated by current within the via array itself but also external heat sources such as power devices within the via array region when acquiring the temperature field distribution, obtains a more comprehensive and accurate temperature field distribution for the via array. This allows the temperature field model to more realistically reflect the actual operating thermal environment of the via array in high-voltage PCBs. This provides a more reliable temperature input for subsequent thermomechanical stress analysis, thereby improving the accuracy and reliability of the entire high-voltage PCB current path optimization design method and effectively preventing via failures caused by thermomechanical stress.

[0075] In some preferred embodiments, the thermal conductivity includes in-plane thermal conductivity and vertical thermal conductivity perpendicular to the direction of the PCB substrate, and step S34 includes:

[0076] S341. Divide the area where the via array is located into multiple sub-regions;

[0077] S342. For each sub-region, obtain the amount of heat generated based on the external heat flux density distribution and the internal heat generation rate distribution, and then obtain the temperature value of the sub-region based on the amount of heat generated, the in-plane thermal conductivity and the vertical thermal conductivity.

[0078] S343. Integrate all temperature values ​​to obtain the temperature field distribution of the via array.

[0079] In-plane thermal conductivity refers to the thermal conductivity of a PCB substrate in directions parallel to its surface, and can be represented by the thermal conductivity along the X and Y axes. Perpendicular thermal conductivity refers to the thermal conductivity of the PCB substrate in directions perpendicular to its surface, and can be represented by the thermal conductivity along the Z axis. Dividing the area containing the via array into multiple sub-regions means discretizing the physical space occupied by the via array into a series of smaller, interconnected computational units, which can be achieved using numerical discretization methods such as finite element mesh generation, finite difference mesh generation, or boundary element mesh generation. Heat generation refers to the total heat energy generated in a sub-region within a specific time period due to current flowing through a resistor or the action of an external heat source. In this embodiment, heat generation can be obtained by integrating or summing the volume, internal heat generation rate distribution, and external heat flux density distribution of the sub-region.

[0080] The operational logic of this scheme lies in first clarifying that thermal conductivity includes in-plane thermal conductivity and vertical thermal conductivity perpendicular to the PCB substrate. This setting reflects the difference in thermal conductivity of PCB materials in different directions. By distinguishing between these two types of thermal conductivity, the heat conduction path within the PCB can be simulated more realistically, especially in complex structures like via arrays, where heat may diffuse along the PCB layers or be conducted vertically through the vias. This consideration of anisotropic thermal conductivity allows temperature field calculations to more accurately reflect the spatial distribution and dissipation of heat, thus providing a more precise physical model for identifying local hotspots. Based on this, the area containing the via array is divided into multiple sub-regions, a crucial prerequisite for solving the local hotspot problem. Since the current distribution within the via array is uneven, i.e., the local heat generation is highly uneven, this embodiment allows subsequent temperature calculations to be performed on the specific heat load of each local area by subdividing the entire region into smaller sub-regions. This avoids the problem of treating the entire array as a homogeneous body and masking local differences, and lays the foundation for capturing microscopic temperature changes. Subsequently, for each sub-region, the amount of heat generated is obtained based on its external heat flux density distribution and internal heat generation rate distribution. Then, the temperature value of that sub-region is obtained based on the amount of heat generated, in-plane thermal conductivity, and vertical thermal conductivity. By utilizing the unique external heat flux density and internal heat generation rate of each sub-region (which directly reflect the non-uniform current distribution), the actual heat load of that sub-region can be accurately calculated. Based on this, the in-plane thermal conductivity and vertical thermal conductivity introduced earlier are combined to perform independent temperature calculations for each sub-region. This localized and refined calculation method fully considers the locality of the heat source and the anisotropy of material thermal conductivity. Therefore, this embodiment enables the temperature value of each sub-region to closely approximate the real situation, thereby accurately identifying the micro hot spots in the via array and their precise location and intensity. Finally, all temperature values ​​are integrated to obtain the temperature field distribution of the via array. By integrating the precise temperature values ​​of all sub-regions, a comprehensive and high-resolution temperature field distribution map of the via array is ultimately formed. This temperature field distribution map not only displays the overall temperature trend, but more importantly, it clearly reveals the location of local hot spots and temperature peaks, providing more accurate and reliable input data for subsequent thermomechanical stress analysis. In this way, this solution is closely integrated with the steps of obtaining external heat flux density distribution and internal heat generation rate distribution, making the entire temperature field acquisition process more accurate and detailed. This provides a more reliable foundation for subsequent thermomechanical stress analysis and layout optimization, thereby improving the long-term reliability of high-voltage PCBs.

[0081] In one specific embodiment, to obtain the temperature field distribution of the via array, the thermal conductivity of the PCB substrate in the XY plane and the thermal conductivity in the Z-axis direction are first obtained from the material supplier. Next, computer-aided design (CAD) software or specialized simulation tools are used to mesh the area containing the via array; for example, a quadrilateral or triangular finite element mesh can be used to discretize the entire area into multiple sub-regions. For each sub-region, the amount of heat generated is calculated based on its specific location in the PCB layout, combined with the external heat flux density distribution and the internal heat generation rate distribution. For example, if a sub-region is located on a high-current path, its internal heat generation rate will be higher, resulting in a higher amount of heat generated. Subsequently, using heat conduction equations (such as Fourier's law or the energy conservation equation), the steady-state temperature value of the sub-region is calculated using numerical methods (such as the finite element method or the finite difference method) based on the amount of heat generated, the in-plane thermal conductivity, and the perpendicular thermal conductivity. During the calculation process, a conduction matrix considering anisotropic thermal conductivity can be constructed, substituting the in-plane and vertical thermal conductivity coefficients respectively to accurately simulate the heat transfer in different directions. Finally, the temperature values ​​calculated from all sub-regions are integrated, for example, by mapping these discrete temperature values ​​to a continuous temperature field map, or by generating a three-dimensional temperature distribution model, thus obtaining the temperature field distribution of the entire via array. This integrated temperature field distribution can be presented in the form of a color isotherm map or a hotspot map, intuitively showing the temperature situation at various locations in the via array. This embodiment significantly improves the accuracy of temperature field modeling by introducing anisotropic thermal conductivity and region division calculation methods, enabling the system to more accurately identify and quantify micro hotspots in high-voltage PCBs. Therefore, this embodiment can overcome the problem of deviation between temperature field calculation results and actual conditions caused by the simplification of traditional methods, thereby more effectively predicting and evaluating the thermomechanical stress that the via array may face in actual operation, and thus guiding layout optimization, fundamentally improving the long-term reliability of high-voltage PCBs.

[0082] In some preferred embodiments, step S4 includes:

[0083] S41. Obtain the thermal expansion difference between the via array and the PCB substrate based on the temperature field distribution, the thermal expansion coefficient of the via array and the thermal expansion coefficient of the PCB substrate.

[0084] S42. Calculate the strain and stress of the via array based on the difference in thermal expansion, the elastic modulus of the via array and the elastic modulus of the PCB substrate, so as to obtain the first thermomechanical stress distribution of the via array.

[0085] Difference in thermal expansion refers to the inconsistency in the dimensional or volume changes of two or more different materials when subjected to the same temperature change due to their inherently different coefficients of thermal expansion. This embodiment can be achieved by determining the coefficients of thermal expansion of each material through materials science experiments and then performing theoretical calculations based on the temperature change range. Strain refers to the degree of deformation of a material under external load or internal stress. Strain is usually expressed as the deformation per unit length and can be calculated using geometric deformation analysis or continuum mechanics models. Stress refers to the internal force per unit area within a material. Stress is a measure of a material's resistance to deformation and can be calculated using mechanical equilibrium equations or constitutive relations.

[0086] This embodiment first obtains the difference in thermal expansion between the via array and the PCB substrate based on the current temperature field distribution, the thermal expansion coefficient of the via array, and the thermal expansion coefficient of the PCB substrate. This step is a crucial prerequisite for understanding and calculating thermomechanical stress. It identifies and quantifies the root cause of thermomechanical stress, namely the mismatched expansion of two different materials due to their different thermal expansion coefficients under temperature changes, providing accurate physical input for subsequent stress calculations. Next, this embodiment calculates the strain and stress of the via array based on the difference in thermal expansion and the elastic moduli of the via array and the PCB substrate, thereby obtaining the first thermomechanical stress distribution of the via array. The elastic modulus characterizes the material's ability to resist deformation. This embodiment can convert the difference in thermal expansion into actual mechanical strain and stress by considering the elastic moduli of the two materials, so that the calculated stress distribution can accurately reflect the mechanical response of the material. This step-by-step calculation method, starting from the physical root of the difference in thermal expansion, gradually derives strain and stress, making the process of obtaining the thermomechanical stress distribution clearer, more scientific, and more accurate. This refined and precise calculation method, combined with the overall optimization design method, enables subsequent layout optimization to be based on more accurate stress data. This effectively identifies potential stress concentration areas and allows for targeted adjustments to the layout, fundamentally preventing via open circuit failures caused by thermomechanical stress and significantly improving the long-term reliability of high-voltage PCBs.

[0087] In a specific embodiment, to obtain the first thermomechanical stress distribution of the via array, step S41 is performed by a thermal expansion difference calculation unit. This unit can receive temperature field distribution data output from a temperature sensor array or thermal simulation software, as well as pre-stored thermal expansion coefficient data of the via material (e.g., copper) and PCB substrate material (e.g., FR-4). This unit can also use thermal expansion formulas to calculate the expansion of the via and substrate at different temperatures based on these inputs, thereby obtaining the expansion difference between them. Subsequently, step S42 is performed by a stress-strain calculation unit. This unit can receive thermal expansion difference data and pre-stored elastic moduli of the via material and PCB substrate material. This unit can also use the stress-strain relationship in materials mechanics to calculate the strain and stress distribution of the via array under mismatched expansion. For example, a geometric model of the via and PCB substrate can be established using finite element analysis (FEA) software, the thermal expansion difference can be applied to the model as a boundary condition or load, and the elastic modulus of the material can be input. Through simulation calculation, the stress field distribution inside the via array can be obtained, thereby obtaining the first thermomechanical stress distribution.

[0088] Secondly, such as Figure 2 As shown, this application also provides a high-voltage PCB current path optimization design system based on a large model, which includes:

[0089] Information acquisition module 1 is used to acquire the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array;

[0090] Current distribution acquisition module 2 is used to acquire the current distribution of the via array based on electrical parameters and layout information using an electrical simulation model;

[0091] Temperature field distribution acquisition module 3 is used to acquire the temperature field distribution of the via array based on the current distribution, the resistivity of the via array and the thermal conductivity of the PCB substrate.

[0092] The stress distribution acquisition module 4 is used to acquire the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate.

[0093] The layout optimization module 5 is used to analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information, and the current distribution acquisition module 2 is triggered to run.

[0094] This application provides a high-voltage PCB current path optimization design system based on a large model, comprising an information acquisition module 1, a current distribution acquisition module 2, a temperature field distribution acquisition module 3, a stress distribution acquisition module 4, and a layout optimization module 5. This embodiment of the high-voltage PCB current path optimization design system based on a large model is used to execute the steps in the high-voltage PCB current path optimization design method based on a large model provided in the first aspect above. The principle of this embodiment of the high-voltage PCB current path optimization design system based on a large model is the same as the principle of the high-voltage PCB current path optimization design method based on a large model provided in the first aspect above, and will not be discussed in detail here.

[0095] As can be seen from the above, the high-voltage PCB current path optimization design method and system provided in this application solves the problems of local hot spots and thermomechanical stress caused by uneven current distribution in the via array of high-voltage PCBs by coupling electrical simulation, thermal simulation and mechanical simulation and introducing an iterative optimization mechanism. This achieves integrated optimization design of electrical performance, thermal performance and mechanical reliability, thereby effectively improving the long-term reliability of high-voltage PCBs.

[0096] In the embodiments provided in this application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of the above units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another robot, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interface; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0097] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0098] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0099] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A high-voltage PCB current path optimization design method based on a large model, characterized in that, The high-voltage PCB current path optimization design method based on a large model includes the following steps: S1. Obtain the electrical parameters of the high-voltage PCB current path and the initial layout information of the via array; S2. Using an electrical simulation model, obtain the current distribution of the via array based on the electrical parameters and the layout information; S3. Obtain the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate. S4. Obtain the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate. S5. Analyze whether the first thermomechanical stress distribution meets the preset requirements. If yes, use the new layout information as the final layout information of the via array. If no, adjust the layout parameters of the via array according to the first thermomechanical stress distribution to obtain the new layout information, and return to step S2. The process of adjusting the layout parameters of the via array according to the first thermomechanical stress distribution includes: A1. Obtain the first electrical performance parameters of the current via array; A2. Generate multiple candidate via array layout schemes based on the first thermomechanical stress distribution; A3. For each of the candidate via array layout schemes, obtain the second electrical performance parameter and the second thermomechanical stress distribution corresponding to the candidate via array layout scheme, then calculate the performance parameter change based on the first electrical performance parameter and the second electrical performance parameter, and obtain the thermomechanical stress balance based on the second thermomechanical stress distribution. A4. Select a target via array layout scheme from all the candidate via array layout schemes based on the degree of thermomechanical stress balance and the amount of performance parameter change, and adjust the layout parameters of the via array according to the target via array layout scheme.

2. The high-voltage PCB current path optimization design method based on a large model according to claim 1, characterized in that, The layout parameters include the relative positions of the vias, the via spacing, and the overall shape of the via array.

3. The high-voltage PCB current path optimization design method based on a large model according to claim 1, characterized in that, Step A4 includes: A41. Based on preset manufacturing process constraint parameters, the manufacturing process feasibility of each candidate via array layout scheme is evaluated, and then the candidate via array layout schemes that are evaluated as not having manufacturing process feasibility are removed. The preset manufacturing process constraint parameters include minimum hole diameter, minimum hole spacing and minimum line width. A42. For each of the remaining candidate via array layout schemes, calculate a comprehensive evaluation index based on the degree of thermomechanical stress balance and the change in performance parameters; A43. Select the target via array layout scheme from the remaining candidate via array layout schemes based on the comprehensive evaluation index.

4. The high-voltage PCB current path optimization design method based on a large model according to claim 3, characterized in that, Step A42 includes: A421. Obtain the preset operating condition information of the PCB substrate; A422. Determine the first weighted weight corresponding to the degree of thermomechanical stress equilibrium and the second weighted weight corresponding to the change in performance parameters based on the preset operating condition information. A423. For each of the remaining candidate via array layout schemes, a comprehensive evaluation index is calculated based on the degree of thermomechanical stress balance, the change in performance parameters, the first weighting weight, and the second weighting weight.

5. The high-voltage PCB current path optimization design method based on a large model according to claim 1, characterized in that, The process of obtaining the degree of thermomechanical stress equilibrium based on the second thermomechanical stress distribution includes: B1. Obtain the stress value of each via based on the second thermomechanical stress distribution; B2. Calculate the stress standard deviation based on all the stress values ​​stated; B3. Determine the degree of thermomechanical stress balance based on the stress standard deviation and the maximum value of the stress.

6. The high-voltage PCB current path optimization design method based on a large model according to claim 1, characterized in that, Step S3 includes: S31. Obtain the spatial location information, power dissipation characteristics and thermal boundary conditions of the power devices in the region where the via array is located; S32. Obtain the external heat flux density distribution based on the spatial location information, the power dissipation characteristics, and the thermal boundary conditions; S33. Obtain the internal heat generation rate distribution based on the current distribution and the resistivity of the via array; S34. Obtain the temperature field distribution of the via array based on the external heat flux density distribution, the internal heat generation rate distribution, and the thermal conductivity of the PCB substrate.

7. The high-voltage PCB current path optimization design method based on a large model according to claim 6, characterized in that, The thermal conductivity includes in-plane thermal conductivity and vertical thermal conductivity perpendicular to the PCB substrate direction. Step S34 includes: S341. Divide the area where the via array is located into multiple sub-regions; S342. For each sub-region, obtain the amount of heat generated based on the external heat flux density distribution and the internal heat generation rate distribution, and then obtain the temperature value of the sub-region based on the amount of heat generated, the in-plane thermal conductivity and the vertical thermal conductivity. S343. Integrate all the temperature values ​​to obtain the temperature field distribution of the via array.

8. The high-voltage PCB current path optimization design method based on a large model according to claim 1, characterized in that, Step S4 includes: S41. Obtain the thermal expansion difference between the via array and the PCB substrate based on the temperature field distribution, the thermal expansion coefficient of the via array, and the thermal expansion coefficient of the PCB substrate; S42. Calculate the strain and stress of the via array based on the thermal expansion difference, the elastic modulus of the via array, and the elastic modulus of the PCB substrate to obtain the first thermomechanical stress distribution of the via array.

9. A high-voltage PCB current path optimization design system based on a large model, characterized in that, The large-model-based high-voltage PCB current path optimization design system is used to execute the steps of the large-model-based high-voltage PCB current path optimization design method according to any one of claims 1-8, wherein the large-model-based high-voltage PCB current path optimization design system includes: The information acquisition module is used to acquire the electrical parameters of the current path of the high-voltage PCB and the initial layout information of the via array; A current distribution acquisition module is used to acquire the current distribution of the via array based on the electrical parameters and the layout information using an electrical simulation model; A temperature field distribution acquisition module is used to acquire the temperature field distribution of the via array based on the current distribution, the resistivity of the via array, and the thermal conductivity of the PCB substrate. The stress distribution acquisition module is used to acquire the first thermomechanical stress distribution of the via array based on the temperature field distribution, the thermal expansion coefficient of the via array, the thermal expansion coefficient of the PCB substrate, the elastic modulus of the via array, and the elastic modulus of the PCB substrate. The layout optimization module is used to analyze whether the first thermomechanical stress distribution meets the preset requirements. If so, the new layout information is used as the final layout information of the via array. If not, the layout parameters of the via array are adjusted according to the first thermomechanical stress distribution to obtain new layout information, and the current distribution acquisition module is triggered to run.

Images