Wafer defect detection method and related apparatus

Abstract

The application discloses a wafer defect detection method and related equipment, and relates to the technical field of data processing, and comprises the following steps: in response to a wafer defect detection instruction, a camera collects a preset first resolution image of a corresponding wafer; based on a CPU-GPU cooperative calculation strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; based on a preset wafer defect judgment rule and the binary mask, it is judged whether the wafer has defects, so as to obtain a wafer defect detection result. Through the CPU-GPU cooperative calculation strategy, the preset first resolution image is processed in parallel, the speed of image processing is improved, and the real-time performance of wafer defect detection is increased.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to wafer defect detection methods and related equipment. Background Technology

[0002] As semiconductor manufacturing processes evolve towards smaller nodes and 3D stacking technologies (such as the widespread adoption of Hybrid Bonding), wafer defect detection has become a core factor affecting product yield and cost.

[0003] In related technologies, wafer defect detection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition. Its single image data throughput is as high as 16G pixels / second. Although it can capture micron-level defects (such as scratches on Micro LED chips below 50μm), the massive amount of data leads to a significant decrease in the real-time performance of traditional processing algorithms.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is related technology. Summary of the Invention

[0005] The main purpose of this application is to provide a wafer defect detection method and related equipment, aiming to solve the technical problem of how to improve the real-time performance of wafer defect detection.

[0006] To achieve the above objectives, this application proposes a wafer defect detection method, which includes:

[0007] In response to a wafer defect detection command, the device receives a preset first resolution image of the corresponding wafer captured by the camera.

[0008] Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the binary mask corresponding to the preset first resolution image;

[0009] Based on the preset wafer defect judgment rules and the binary mask, it is determined whether there are defects in the wafer, so as to obtain the wafer defect detection result.

[0010] In one embodiment, the step of processing the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy to determine the binary mask corresponding to the preset first resolution image further includes:

[0011] Based on a preset image size, the preset first resolution image is divided into blocks to obtain multiple target sub-images;

[0012] Based on the wafer defect detection instructions and the CPU-GPU collaborative computing strategy, the local CPU is invoked to generate wafer defect detection sub-tasks corresponding to each target sub-image, and the wafer defect detection sub-tasks are allocated to multiple CUDA thread blocks corresponding to the local GPU.

[0013] Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine the binary mask corresponding to the preset first resolution image.

[0014] In one embodiment, the step of processing multiple target sub-images in parallel based on the plurality of CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block further includes:

[0015] Based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, the FAST corner points of each target sub-image are detected in parallel to obtain the target FAST corner points corresponding to each target sub-image.

[0016] Based on the target FAST corner points, determine the BRIEF descriptor corresponding to each target sub-image;

[0017] Based on the BRIEF descriptor, an initial binary mask is calculated for each target sub-image patch.

[0018] In one embodiment, the step of performing a block operation on the preset first resolution image based on a preset image size to obtain multiple target sub-images further includes:

[0019] The image at the preset first resolution is subjected to pyramid downsampling to reduce the resolution of the image at the preset first resolution, thereby obtaining an image at the preset second resolution.

[0020] The target image is obtained by using a two-dimensional Gaussian filter kernel to suppress noise in the preset second resolution image.

[0021] Based on a preset image size, the target image is divided into blocks to obtain multiple target sub-images.

[0022] In one embodiment, the BRIEF descriptor is a binary vector, and the step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner points further includes:

[0023] Obtain the initialized BRIEF descriptor string, wherein each character of the initialized BRIEF descriptor string is 0;

[0024] Based on the multiple threads contained in the CUDA thread block and the target FAST corner point, the judgment-modification atomic operation is performed in parallel on multiple characters in the initialized BRIEF descriptor string to determine the BRIEF descriptor corresponding to each target sub-image.

[0025] The step of performing parallel judgment-modification atomic operations on multiple characters in the initialized BRIEF descriptor string includes:

[0026] Determine whether each character in the initialized BRIEF descriptor string meets the modification requirements;

[0027] If the condition is met, the character that meets the modification requirement will be changed from 0 to 1.

[0028] In one embodiment, the step of determining whether a wafer has defects based on a preset wafer defect judgment rule and the binary mask to obtain a wafer defect detection result further includes:

[0029] Based on the connected component identification optimization strategy, the initial binary mask is optimized to obtain the target binary mask;

[0030] Based on the target binary mask and the preset defect judgment rule, it is determined whether each target sub-image has a defect, and multiple initial judgment results are obtained;

[0031] Based on all the initial judgment results, it is determined whether there are defects in the wafer, and the wafer defect detection results are obtained.

[0032] In one embodiment, the step of optimizing the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask further includes:

[0033] Based on the connected component identification optimization strategy and the preset small image block size, each target sub-image is divided into multiple small image blocks, wherein the connected component identification of each small image block is performed independently in the GPU shared memory;

[0034] Determine the label of each pixel in each small image patch, and merge equivalent labels based on atomic operations to obtain the initial merge result;

[0035] Based on a tree-like recursive merging strategy and a 3D thread block index, the boundary pixels of adjacent small image blocks are merged layer by layer to optimize the initial merging result and obtain the target binary mask.

[0036] Furthermore, to achieve the above objectives, this application also proposes a wafer defect detection device, which includes:

[0037] The receiving module is used to receive a preset first resolution image of the corresponding wafer acquired by the camera in response to a wafer defect detection command.

[0038] The data processing module is used to process the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy, so as to determine the binary mask corresponding to the preset first resolution image;

[0039] The judgment module is used to determine whether there are defects in the wafer based on the preset wafer defect judgment rules and the binary mask, so as to obtain the wafer defect detection result.

[0040] In one embodiment, the data processing module further includes:

[0041] The first segmentation unit is used to perform a segmentation operation on the preset first resolution image based on a preset image size to obtain multiple target sub-images;

[0042] The calling unit is used to call the local CPU to generate a wafer defect detection subtask corresponding to each target sub-image based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, and to allocate the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU.

[0043] The data processing unit is used to process multiple target sub-images in parallel based on the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, so as to determine the binary mask corresponding to the preset first resolution image.

[0044] In one embodiment, the data processing module further includes:

[0045] The detection unit is used to detect the FAST corner points of each target sub-image in parallel based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, and obtain the target FAST corner points corresponding to each target sub-image.

[0046] The first determining unit is used to determine the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner points;

[0047] The calculation unit is used to calculate the initial binary mask for each target sub-image block based on the BRIEF descriptor.

[0048] In one embodiment, the data processing module further includes:

[0049] The resolution reduction unit is used to perform pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image and obtain a preset second resolution image;

[0050] The noise suppression unit is used to suppress noise in the preset second resolution image using a two-dimensional Gaussian filter kernel to obtain the target image.

[0051] The second segmentation unit is used to perform a segmentation operation on the target image based on a preset image size to obtain multiple target sub-images.

[0052] In one embodiment, the data processing module further includes:

[0053] The acquisition unit is used to acquire the initialized BRIEF descriptor string, wherein each character of the initialized BRIEF descriptor string is 0;

[0054] The first modification unit is used to perform a judgment-modification atomic operation in parallel on multiple characters in the initialized BRIEF descriptor string based on multiple threads contained in the CUDA thread block and the target FAST corner point, so as to determine the BRIEF descriptor corresponding to each target sub-image.

[0055] The step of performing parallel judgment-modification atomic operations on multiple characters in the initialized BRIEF descriptor string includes:

[0056] The first judgment unit is used to judge whether each character in the initialized BRIEF descriptor string meets the modification requirements;

[0057] The second modification unit is used to change the character that meets the modification requirements from 0 to 1 if the conditions are met.

[0058] In one embodiment, the determination module further includes:

[0059] The optimization unit is used to optimize the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask;

[0060] The second judgment unit is used to determine whether each target sub-image has defects based on the target binary mask and the preset defect judgment rules, and to obtain multiple initial judgment results;

[0061] The second determining unit is used to determine whether there are defects in the wafer based on all the initial judgment results, and to obtain the wafer defect detection result.

[0062] In one embodiment, the determination module further includes:

[0063] A partitioning unit is used to divide each target sub-image into multiple small image blocks based on a connected component identification optimization strategy and a preset small image block size, wherein the small image blocks independently perform connected component labeling in the GPU shared memory;

[0064] The third determining unit is used to determine the label of each pixel in each small image block, and merges equivalent labels based on atomic operations to obtain the initial merging result;

[0065] The merging unit is used to merge the boundary pixels of adjacent small image blocks layer by layer based on a tree-like recursive merging strategy and 3D thread block index, so as to optimize the initial merging result and obtain the target binary mask.

[0066] In addition, to achieve the above objectives, this application also proposes a wafer defect detection device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the wafer defect detection method as described above.

[0067] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the wafer defect detection method described above.

[0068] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the wafer defect detection method described above.

[0069] One or more technical solutions proposed in this application have at least the following technical effects:

[0070] This application proposes a wafer defect detection method and related equipment, relating to the field of data processing technology. Compared to related technologies where wafer defect detection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition, achieving a single-image data throughput of up to 16G pixels / second, capable of capturing micron-level defects (such as scratches on Micro LED chips smaller than 50μm), the massive data volume significantly reduces the real-time performance of traditional processing algorithms. In this application, firstly, in response to a wafer defect detection command, the camera acquires a preset first resolution image of the corresponding wafer. Then, based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the corresponding binary mask. Finally, based on preset wafer defect judgment rules and the binary mask, the presence of defects in the wafer is determined to obtain the wafer defect detection result. This application improves image processing speed and thus enhances the real-time performance of wafer defect detection through a CPU-GPU collaborative computing strategy that processes the preset first resolution image in parallel. Attached Figure Description

[0071] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0072] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a flowchart illustrating an embodiment of the wafer defect detection method of this application.

[0074] Figure 2 This is a flowchart illustrating Embodiment 2 of the wafer defect detection method of this application;

[0075] Figure 3 This is a flowchart illustrating Embodiment 3 of the wafer defect detection method of this application;

[0076] Figure 4 This is a schematic diagram of the module structure of the wafer defect detection device according to an embodiment of this application;

[0077] Figure 5 This is a schematic diagram of the equipment structure of the hardware operating environment involved in the wafer defect detection method in this application embodiment.

[0078] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0079] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0080] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0081] The main solution in this application's embodiments is:

[0082] In this embodiment, for ease of description, the following description uses a wafer defect detection device as the execution subject.

[0083] Due to the relevant technology: wafer defect inspection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition, with a single image data throughput of up to 16G pixels / second. Although it can capture micron-level defects (such as scratches on Micro LED chips below 50μm), the massive amount of data leads to a significant decrease in the real-time performance of traditional processing algorithms.

[0084] This application provides a solution in which: first, in response to a wafer defect detection command, a camera acquires a preset first resolution image of the corresponding wafer; then, based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; finally, based on a preset wafer defect judgment rule and the binary mask, it is determined whether a defect exists on the wafer to obtain a wafer defect detection result. This application improves image processing speed by using a CPU-GPU collaborative computing strategy to process the preset first resolution image in parallel, thereby increasing the real-time performance of wafer defect detection.

[0085] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or wafer defect detection device capable of performing the above functions. The following description uses a wafer defect detection device as an example to illustrate this embodiment and the subsequent embodiments.

[0086] Based on this, embodiments of this application provide a wafer defect detection method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the wafer defect detection method of this application.

[0087] In this embodiment, the wafer defect detection method includes steps S100~S300:

[0088] Step S100: In response to the wafer defect detection command, receive a preset first resolution image of the corresponding wafer acquired by the camera;

[0089] It's important to note that a wafer defect detection command is a specific instruction used to initiate the wafer defect detection process. In semiconductor manufacturing, wafers are the fundamental material for making chips, and detecting defects on wafers (such as scratches, particle contamination, and crystal structure defects) is a crucial step in ensuring product quality. This command may be manually entered by operators or automatically issued by an automated system based on the production process.

[0090] In this embodiment, the system receives image data from a camera. The camera is part of the inspection system and can be a high-magnification TDI camera used to capture images of the wafer. The camera's function is to capture the condition of the wafer surface in image form for subsequent analysis.

[0091] It's important to note that "preset first resolution image" means the image resolution is preset, not the camera's default resolution or a randomly selected resolution. "First resolution" indicates a specific resolution level designed to meet certain detection accuracy requirements. For example, detecting larger defects may not require a high resolution, while detecting tiny crystal defects necessitates a higher resolution. This resolution is set based on the specific needs of the detection task and is a crucial parameter in the detection process.

[0092] Furthermore, when the system receives a command to initiate wafer defect detection, it receives an image of the wafer to be inspected from a camera, and the resolution of this image is a pre-set specific value (first resolution). This process is part of an automated inspection system used to ensure that wafers can be inspected according to predetermined accuracy and standards.

[0093] Step S200: Based on the CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the binary mask corresponding to the preset first resolution image;

[0094] It should be noted that the CPU (Central Processing Unit) is the main processor of a computer, which excels at handling complex logical operations and sequential tasks. It is typically used to control program flow and execute algorithms.

[0095] It should be noted that GPUs (Graphics Processing Units) were originally used for graphics rendering, but with the development of technology, GPUs have been widely used for general computing tasks due to their parallel processing capabilities, especially when dealing with large amounts of data and parallel tasks.

[0096] It's important to note that the "CPU-GPU collaborative computing strategy" is a computing architecture that leverages the strengths of both CPUs and GPUs by distributing tasks among them. The CPU handles complex logic control and serial tasks, while the GPU handles parallel computing tasks, such as pixel-level operations in image processing. This collaborative strategy can significantly improve computational efficiency, especially when dealing with large-scale data or complex tasks.

[0097] It's important to note that parallel processing refers to processing multiple tasks or data segments simultaneously. In image processing, this means operating on multiple parts of an image at the same time, rather than processing each pixel sequentially. Parallel processing can significantly reduce processing time, especially when using GPUs, as GPUs excel at processing large amounts of data concurrently.

[0098] It's important to note that in image processing, a binary mask is a special type of image where pixel values ​​have only two possibilities: 0 (black) and 1 (white). It is typically used to represent specific regions or features within an image. For example, in defect detection, a binary mask can be used to mark the location of defects, where white pixels represent defective areas and black pixels represent non-defective areas.

[0099] Specifically, the step of processing the preset first resolution image in parallel based on the CPU-GPU collaborative computing strategy to determine the binary mask corresponding to the preset first resolution image further includes steps S210~S230:

[0100] Step S210: Based on the preset image size, perform a block division operation on the preset first resolution image to obtain multiple target sub-images;

[0101] It should be noted that the preset image size refers to the pre-defined image size parameters. These parameters define how the original image is divided into multiple sub-images. For example, you can specify the width and height of each sub-image (in pixels), or specify how many rows and columns the image will be divided into.

[0102] It's important to note that block partitioning is the process of dividing a large image into multiple smaller sub-images. This operation is very common in image processing, especially when dealing with large images, as it simplifies computational complexity and improves processing efficiency. For example, in image analysis, feature extraction, or deep learning, large images are typically divided into multiple small blocks, and then each block is processed separately.

[0103] As is understandable, the result of the block operation is multiple smaller image blocks, which are called "target sub-images". Each sub-image contains a portion of the original image, but in a smaller size, making it easier for subsequent processing. For example, if a 1024×1024 pixel image is divided into 64×64 pixel sub-images, then 256 target sub-images (16×16) can be obtained.

[0104] Specifically, the step of performing a block operation on the preset first resolution image based on a preset image size to obtain multiple target sub-images further includes steps S211~S213:

[0105] Step S211: Perform pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image and obtain a preset second resolution image;

[0106] Pyramid downsampling is an image downsampling technique inspired by the concept of an image pyramid. An image pyramid is a multi-resolution representation method that generates a series of images at different resolutions by progressively reducing the image's resolution layer by layer. Pyramid downsampling typically involves smoothing filtering (filtering the original image to reduce high-frequency components and avoid aliasing during downsampling) and downsampling (taking one pixel from every certain number of pixels in the filtered image to generate a lower-resolution image. For example, taking one pixel from every other pixel reduces the image's width and height by half).

[0107] It should be noted that the purpose of downsampling is to reduce the resolution of an image to a lower level. This is usually done to meet the needs of subsequent processing, such as reducing computational load, increasing processing speed, or adapting to the resolution requirements of certain algorithms.

[0108] The preset second resolution refers to the target resolution after downsampling, which is pre-set. This resolution is usually lower than the first resolution, but the specific value depends on the application scenario and requirements.

[0109] Step S212: Use a two-dimensional Gaussian filter kernel to suppress noise in the preset second resolution image to obtain the target image;

[0110] Gaussian filtering is a commonly used image smoothing technique that uses a Gaussian function (normal distribution function) to filter images. The Gaussian filter kernel is a two-dimensional matrix whose values ​​are weights calculated based on the Gaussian function.

[0111] A Gaussian filter kernel is a two-dimensional matrix used to perform a weighted average of each pixel and its neighborhood in an image. This filtering method can effectively smooth an image while preserving its main features.

[0112] Image noise refers to unwanted, random interference signals in an image, which may originate from sensor noise, environmental interference, or other factors during image acquisition. The goal of noise suppression is to reduce these interferences, making the image clearer and smoother. Gaussian filtering is an effective noise suppression method because it smooths out random noise by weighting the pixel and its neighborhood.

[0113] Convolutional operations on an image using a Gaussian filter kernel can effectively reduce noise. The weight distribution of the Gaussian filter kernel ensures that the neighboring pixels of the center pixel contribute to the value of the center pixel, thus smoothing out local random variations.

[0114] The target image refers to the final image after noise suppression processing. This image is smoother than the original preset second-resolution image, noise is suppressed, and the main features of the image are preserved.

[0115] Understandably, a two-dimensional Gaussian filter kernel is used to suppress noise in the preset second-resolution image obtained in the previous steps. Through the convolution operation of the Gaussian filter kernel, the noise in the image is smoothed out, resulting in a clearer and smoother target image. This processing method is suitable for scenarios that require reducing image noise while preserving the main features of the image, such as in tasks like image analysis, object detection, or image enhancement.

[0116] Step S213: Based on the preset image size, perform a block operation on the target image to obtain multiple target sub-images.

[0117] Step S220: Based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, call the local CPU to generate a wafer defect detection subtask corresponding to each target sub-image, and allocate the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU.

[0118] In this step, the system generates a separate wafer defect detection subtask for each target sub-image. This means that each sub-image will be processed individually to detect any defects that may be present.

[0119] The "Wafer Defect Detection Subtask" is a detection task for each target sub-image. The goal of each subtask is to check whether there are defects in the sub-image, such as scratches, particle contamination, or crystal structure defects.

[0120] CUDA Thread Blocks: CUDA is a parallel computing platform and programming model introduced by NVIDIA for utilizing NVIDIA GPUs for computation. In CUDA, a thread block is the basic unit of parallel execution, and each thread block contains multiple threads. By distributing tasks across multiple thread blocks, the parallel computing capabilities of the GPU can be fully utilized.

[0121] In this embodiment, based on the wafer defect detection instructions and the CPU-GPU collaborative computing strategy, the system first invokes the local CPU to generate wafer defect detection subtasks for each target sub-image. Then, the system distributes these subtasks across multiple CUDA thread blocks on the local GPU to efficiently execute them using the GPU's parallel computing capabilities. This task allocation and parallel processing mechanism can significantly improve the efficiency of wafer defect detection, especially when processing a large number of sub-images.

[0122] Step S230: Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine the binary mask corresponding to the preset first resolution image.

[0123] In the preceding steps, the system has decomposed the wafer defect detection task into multiple subtasks and assigned these subtasks to different CUDA thread blocks. Each thread block is responsible for processing the defect detection task of a specific target sub-image.

[0124] It's worth noting that in GPUs, due to their powerful parallel computing capabilities, multiple CUDA thread blocks can process multiple target sub-images simultaneously. This parallel processing method can significantly improve processing speed, especially when dealing with large amounts of data.

[0125] In this embodiment, based on the wafer defect detection subtask allocated to each CUDA thread block in the preceding steps, the system utilizes the parallel computing capabilities of the GPU to process multiple target sub-images simultaneously. In this way, the system ultimately generates a binary mask corresponding to the initial image, used to mark the defect location. This parallel processing method can significantly improve the efficiency of defect detection, especially when processing high-resolution images or large amounts of image data.

[0126] Specifically, the step of processing multiple target sub-images in parallel based on the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block further includes steps S231~S233:

[0127] Step S231: Based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, the FAST corner points of each target sub-image are detected in parallel to obtain the target FAST corner points corresponding to each target sub-image.

[0128] It's important to note that in CUDA programming, shared memory is a high-speed memory located on the GPU that can be quickly accessed by all threads within the same thread block. Using shared memory can significantly improve data access speed, especially when processing image data, because spatial locality often exists between pixels in an image (adjacent pixels are frequently accessed together).

[0129] FAST (Features from Accelerated Segment Test) is a fast corner detection algorithm. It identifies corners by detecting local brightness changes in pixels within an image. The advantages of the FAST algorithm are its fast computation speed, making it suitable for real-time applications and large-scale image processing.

[0130] Understandably, since the FAST corner detection task for each target sub-image is independent, the parallel computing power of the GPU can be utilized to perform corner detection on multiple target sub-images simultaneously. Each CUDA thread block can independently process the FAST corner detection task for one target sub-image.

[0131] The target FAST corner points are the output of the FAST corner detection algorithm. For each target sub-image, the FAST algorithm detects its corner points and outputs these corner points as the detection results. These corner points can be used for subsequent image analysis, such as feature matching, target recognition, or defect detection.

[0132] In this embodiment, the system utilizes a shared memory strategy and the parallel computing capabilities of the GPU to process multiple target sub-images simultaneously through multiple CUDA thread blocks. Each thread block is responsible for detecting FAST corner points in one target sub-image. In this way, the system efficiently generates a set of FAST corner points for each target sub-image. This parallel processing method can significantly improve the speed of corner detection, especially when processing a large number of sub-images.

[0133] Step S232: Based on the target FAST corner points, determine the BRIEF descriptor corresponding to each target sub-image;

[0134] BRIEF (Binary Robust Independent Elementary Features) is a binary feature descriptor used to describe local information of feature points in an image. The main advantages of BRIEF descriptors are fast computation speed, high storage efficiency, and robustness to changes in illumination and viewpoint. It generates binary strings by comparing the brightness of pixel pairs within the neighborhood of a feature point; these strings can then be used for subsequent feature matching.

[0135] In this application, for each target sub-image, the system will calculate a BRIEF descriptor for each detected FAST corner point. The specific steps are as follows:

[0136] Step 1, Select Pixel Pairs: Within the neighborhood of each FAST corner point, select a set of predefined pixel pairs. The positions of these pixel pairs are fixed and are usually determined during algorithm design.

[0137] Step 2, compare brightness: For each pair of pixels, compare their brightness. If the brightness of one pixel is greater than the brightness of the other pixel, record a "1" in the descriptor; otherwise, record a "0".

[0138] Step 3, Generate a binary string: Through the above comparison, a binary string is generated, which is the BRIEF descriptor.

[0139] In this embodiment, based on the FAST corner points detected in each target sub-image in the preceding steps, the system calculates a BRIEF descriptor for each corner point. These descriptors are in binary form and are used to describe the local features of the corner points. In this way, the system can efficiently generate feature descriptors for each target sub-image, which can be used for subsequent tasks such as feature matching, target recognition, or defect detection.

[0140] Step S233: Calculate the initial binary mask for each target sub-image block based on the BRIEF descriptor.

[0141] In this embodiment, the system will use the BRIEF descriptor to generate an initial binary mask for each target sub-image patch. Specific steps may include:

[0142] Feature matching: Matches the BRIEF descriptor in the current target sub-image patch with known feature descriptors (e.g., standard templates or labeled defect features).

[0143] Threshold determination: Based on the matching results, determine which pixels belong to the feature region of interest (e.g., defect region). Typically, a threshold is set; only pixels with a matching degree higher than this threshold are marked as 1 (white), and the remaining pixels are marked as 0 (black).

[0144] Generate a binary mask: Based on the above judgment, generate a binary image, where white pixels represent detected feature regions and black pixels represent background or other non-feature regions.

[0145] Understandably, in this embodiment, using the BRIEF descriptor calculated in the preceding steps, the system generates an initial binary mask for each target sub-image patch. This binary mask marks potential defects or other regions of interest in the image through feature matching and thresholding. The generated initial binary mask can be used for subsequent analysis or processing, such as defect detection, feature statistics, or image segmentation tasks.

[0146] Step S300: Based on the preset wafer defect judgment rules and the binary mask, determine whether there are defects in the wafer to obtain the wafer defect detection result.

[0147] Predefined wafer defect judgment rules refer to a set of predefined rules used to determine whether a wafer has defects. These rules are usually formulated based on the wafer's manufacturing process, quality standards, and defect characteristics. For example, the rules may include: minimum or maximum defect area limits, defect shape characteristics (such as circular, linear, etc.), defect distribution density (such as the number of defects per unit area), defect grayscale or color characteristics, and contrast threshold between defects and normal areas.

[0148] In this embodiment, by combining preset judgment rules and information from a binary mask, the system needs to determine whether defects exist on the wafer. Specific steps may include:

[0149] Analyze the binary mask: Examine the distribution of white pixels in the binary mask to determine the preliminary location and shape of the defects.

[0150] Application judgment rules: Verify each possible defect area according to preset rules. For example, check whether the defect area is within the allowable range, whether the shape meets expectations, and whether the contrast is sufficient.

[0151] Based on the above analysis and verification results, it was finally determined whether the wafer had defects.

[0152] Additionally, it should be noted that the wafer defect detection result is the final output of the entire defect detection process. The result is typically a definitive judgment, such as "the wafer has a defect" or "the wafer has no defects." Furthermore, the result includes detailed information such as the specific location, quantity, and type of the defects.

[0153] In this embodiment, based on preset wafer defect judgment rules and the binary mask generated in the previous steps, the system analyzes and judges the wafer to determine whether defects exist, and finally obtains the wafer defect detection result. The preset judgment rules provide the basis for judgment, while the binary mask provides preliminary location information of the defects. The combination of the two can efficiently and accurately complete the defect detection task.

[0154] This embodiment provides a wafer defect detection method and related equipment, relating to the field of data processing technology. Compared to related technologies where wafer defect detection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition, achieving a single image data throughput of up to 16G pixels / second, capable of capturing micron-level defects (such as scratches on Micro LED chips smaller than 50μm), the massive data volume significantly reduces the real-time performance of traditional processing algorithms. In this application, firstly, in response to a wafer defect detection command, a preset first resolution image of the corresponding wafer is received from the camera. Then, based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the corresponding binary mask. Finally, based on preset wafer defect judgment rules and the binary mask, the presence of defects in the wafer is determined to obtain the wafer defect detection result. This application improves image processing speed and thus enhances the real-time performance of wafer defect detection through a CPU-GPU collaborative computing strategy that processes the preset first resolution image in parallel.

[0155] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 The BRIEF descriptor is a binary vector. The step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner points further includes steps A100~A200:

[0156] Step A100: Obtain the initialized BRIEF descriptor string, wherein each character of the initialized BRIEF descriptor string is 0;

[0157] Step A200: Based on the multiple threads contained in the CUDA thread block and the target FAST corner point, perform a judgment-modification atomic operation in parallel on multiple characters in the initialized BRIEF descriptor string to determine the BRIEF descriptor corresponding to each target sub-image.

[0158] It's important to note that in the CUDA programming model, a thread block is the basic unit of parallel execution. Each thread block contains multiple threads that can share resources within the block (such as shared memory) and work collaboratively. The number of threads in each thread block can be configured according to hardware and task requirements. These threads can execute in parallel, thereby improving computational efficiency.

[0159] In the BRIEF descriptor string, each character corresponds to a binary bit (0 or 1). These bits are modified based on the local features of the FAST corners. Leveraging CUDA's parallel computing capabilities, multiple threads can operate on multiple characters (i.e., the bits in the BRIEF descriptor string) simultaneously. This parallel processing significantly improves computational efficiency.

[0160] Specifically, the operations are performed on each bit of the BRIEF descriptor string. The specific steps are as follows:

[0161] Judgment: For each FAST corner point, select a pair of pixels (the positions of these pixels are predefined) and compare their brightness. If the brightness of one pixel is greater than that of the other pixel, the corresponding bit needs to be set to 1; otherwise, it remains 0.

[0162] Modification: Based on the judgment result, modify the corresponding bits in the BRIEF descriptor string. Since multiple threads may access and modify the same string simultaneously, atomic operations are needed to ensure data consistency and correctness. An atomic operation is an indivisible operation that prevents conflicts when multiple threads modify the same data concurrently.

[0163] It's important to note that in CUDA, atomic operations are used to ensure that modifications to shared data are thread-safe. For example, atomic operations like `atomicAdd` and `atomicExch` can be used to safely update integers or floating-point numbers. When processing binary bits, atomic operations can be used to ensure that modifications to each bit are not interfered with by other threads.

[0164] Specifically, the step of performing the judgment-modification atomic operation in parallel on multiple characters in the initialized BRIEF descriptor string includes steps A210 to A220:

[0165] Step A210: Determine whether each character in the initialized BRIEF descriptor string meets the modification requirements;

[0166] Step A220: If satisfied, change the character that meets the modification requirements from 0 to 1.

[0167] Understandably, in this embodiment, multiple threads within the CUDA thread block are used to process the FAST corner points in each target sub-image in parallel, updating each bit of the initialized BRIEF descriptor string through a decision-modify atomic operation. Ultimately, the system generates a BRIEF descriptor for each FAST corner point in each target sub-image. This parallel processing method can significantly improve the generation speed of BRIEF descriptors, especially when processing a large number of corner points and sub-images.

[0168] Based on the first and second embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to that in embodiments one and two above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 3 The step of determining whether a wafer has defects based on a preset wafer defect judgment rule and the binary mask to obtain a wafer defect detection result further includes steps B100 to B300:

[0169] Step B100: Optimize the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask;

[0170] It's important to note that in binary images, a connected component refers to a group of interconnected pixels that have the same value (usually white pixels, representing the target region). For example, in a binary mask, a connected component might represent a single defect, an object, or a feature region.

[0171] Connected component labeling is used to identify and label all connected components in a binary image. It is typically implemented using connected component labeling algorithms, such as scan-based or queue-based algorithms. Each connected component is assigned a unique identifier.

[0172] Optimization strategies refer to methods for analyzing and processing connected components, with the aim of improving the quality of the initial binary mask. Optimization strategies include:

[0173] Remove small connected components: If the area of ​​some connected components is smaller than a certain preset threshold, they may be considered noise or unimportant features and can be removed.

[0174] Merging adjacent connected components: If the distance between two connected components is less than a certain threshold, they can be merged into a larger connected component.

[0175] Shape analysis and filtering: Based on the shape characteristics of connected components (such as aspect ratio, roundness, etc.), determine whether they meet the expected characteristics. Those that do not meet the requirements can be removed or adjusted.

[0176] Contrast Enhancement: By analyzing the contrast between connected components and the background, the salience of the target region is further enhanced.

[0177] It should be noted that the target binary mask is the optimized final binary mask, which more accurately represents the target region (such as defects, objects, etc.) in the image. The target binary mask is the foundation for subsequent image analysis or processing (such as defect detection, target recognition, etc.).

[0178] In this embodiment, a connected component identification optimization strategy is used to process the initial binary mask, removing noise, merging similar regions, and adjusting its shape, thereby obtaining a more accurate target binary mask. This optimization process can significantly improve the quality of the binary mask, making it more suitable for subsequent image analysis and processing tasks.

[0179] Specifically, the step of optimizing the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask further includes steps B110~B130:

[0180] Step B110: Based on the connected component identification optimization strategy and the preset small image block size, each target sub-image is divided into multiple small image blocks, wherein the small image blocks are independently marked in the GPU shared memory;

[0181] Step B120: Determine the label of each pixel in each small image block, and merge equivalent labels based on atomic operations to obtain the initial merging result;

[0182] Step B130: Based on the tree-like recursive merging strategy and 3D thread block index, merge the boundary pixels of adjacent small image blocks layer by layer to optimize the initial merging result and obtain the target binary mask.

[0183] The preset small image patch size refers to the size at which an image is divided into multiple smaller patches (small image patches) during image processing. The small image patch size is preset and is typically determined based on the image size and processing requirements. For example, if an image is large, it can be divided into multiple smaller image patches for parallel processing on the GPU.

[0184] In this application, each target sub-image is further divided into smaller regions (small image blocks). This division aims to leverage the parallel computing power of the GPU to process each small image block independently. This significantly improves processing speed, especially when processing large images.

[0185] It's important to note that each small image patch is loaded into the GPU's shared memory and undergoes connected component labeling independently. This means that the processing of each small image patch does not interfere with each other and can be executed in parallel. The connected component labeling process typically includes:

[0186] Scan pixels in small image blocks: Examine the pixel values ​​in small image blocks one by one.

[0187] Assign a label: Assign a unique label to each connected component.

[0188] Optimize labels: Based on the connected component identifier optimization strategy, remove small connected components and merge similar connected components.

[0189] In this embodiment, each target sub-image is divided into multiple smaller image blocks according to a preset small image block size. Then, each small image block is loaded into the GPU's shared memory and connected component labeling is performed independently. This approach leverages the GPU's parallel computing capabilities to efficiently process each small image block, while simultaneously improving the efficiency and accuracy of connected component labeling. This method is particularly suitable for processing large images or scenarios requiring rapid processing.

[0190] Step B200: Based on the target binary mask and the preset defect judgment rules, determine whether each target sub-image has defects, and obtain multiple initial judgment results;

[0191] Step B300: Based on all the initial judgment results, determine whether there are defects in the wafer and obtain the wafer defect detection results.

[0192] The initial judgment result is the judgment result for each target sub-image, indicating whether the sub-image has defects. The initial judgment result may be "defect exists" or "no defect".

[0193] In this application, the initial judgment results of all target sub-images are combined to determine whether the entire wafer has defects. This step typically includes:

[0194] Count the number of defects: Count the number of sub-images marked as "defect exists".

[0195] Defect distribution assessment: Analyze the distribution of defects on the wafer, such as whether they are concentrated in a certain area.

[0196] Apply comprehensive judgment rules: Determine whether the entire wafer meets the quality standards based on preset comprehensive judgment rules (e.g., the maximum number of defects allowed, the uniformity of defect distribution, etc.).

[0197] It should be noted that the wafer defect detection result is the final output of the entire wafer defect detection process. The detection result is usually a clear judgment, such as "the wafer has defects" or "the wafer has no defects." In addition, the detection result may also include detailed information such as the specific location, quantity, and type of defects.

[0198] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the wafer defect detection method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0199] This application also provides a wafer defect detection device; please refer to [reference needed]. Figure 4 The wafer defect detection device includes:

[0200] The receiving module 10 is used to receive a preset first resolution image of the corresponding wafer acquired by the camera in response to a wafer defect detection command.

[0201] Data processing module 20 is used to process the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy, so as to determine the binary mask corresponding to the preset first resolution image;

[0202] The judgment module 30 is used to determine whether there are defects in the wafer based on the preset wafer defect judgment rules and the binary mask, so as to obtain the wafer defect detection result.

[0203] In one embodiment, the data processing module further includes:

[0204] The first segmentation unit is used to perform a segmentation operation on the preset first resolution image based on a preset image size to obtain multiple target sub-images;

[0205] The calling unit is used to call the local CPU to generate a wafer defect detection subtask corresponding to each target sub-image based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, and to allocate the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU.

[0206] The data processing unit is used to process multiple target sub-images in parallel based on the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, so as to determine the binary mask corresponding to the preset first resolution image.

[0207] In one embodiment, the data processing module further includes:

[0208] The detection unit is used to detect the FAST corner points of each target sub-image in parallel based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, and obtain the target FAST corner points corresponding to each target sub-image.

[0209] The first determining unit is used to determine the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner points;

[0210] The calculation unit is used to calculate the initial binary mask for each target sub-image block based on the BRIEF descriptor.

[0211] In one embodiment, the data processing module further includes:

[0212] The resolution reduction unit is used to perform pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image and obtain a preset second resolution image;

[0213] The noise suppression unit is used to suppress noise in the preset second resolution image using a two-dimensional Gaussian filter kernel to obtain the target image.

[0214] The second segmentation unit is used to perform a segmentation operation on the target image based on a preset image size to obtain multiple target sub-images.

[0215] In one embodiment, the data processing module further includes:

[0216] The acquisition unit is used to acquire the initialized BRIEF descriptor string, wherein each character of the initialized BRIEF descriptor string is 0;

[0217] The first modification unit is used to perform a judgment-modification atomic operation in parallel on multiple characters in the initialized BRIEF descriptor string based on multiple threads contained in the CUDA thread block and the target FAST corner point, so as to determine the BRIEF descriptor corresponding to each target sub-image.

[0218] The step of performing parallel judgment-modification atomic operations on multiple characters in the initialized BRIEF descriptor string includes:

[0219] The first judgment unit is used to judge whether each character in the initialized BRIEF descriptor string meets the modification requirements;

[0220] The second modification unit is used to change the character that meets the modification requirements from 0 to 1 if the conditions are met.

[0221] In one embodiment, the determination module further includes:

[0222] The optimization unit is used to optimize the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask;

[0223] The second judgment unit is used to determine whether each target sub-image has defects based on the target binary mask and the preset defect judgment rules, and to obtain multiple initial judgment results;

[0224] The second determining unit is used to determine whether there are defects in the wafer based on all the initial judgment results, and to obtain the wafer defect detection result.

[0225] In one embodiment, the determination module further includes:

[0226] A partitioning unit is used to divide each target sub-image into multiple small image blocks based on a connected component identification optimization strategy and a preset small image block size, wherein the small image blocks independently perform connected component labeling in the GPU shared memory;

[0227] The third determining unit is used to determine the label of each pixel in each small image block, and merges equivalent labels based on atomic operations to obtain the initial merging result;

[0228] The merging unit is used to merge the boundary pixels of adjacent small image blocks layer by layer based on a tree-like recursive merging strategy and 3D thread block index, so as to optimize the initial merging result and obtain the target binary mask.

[0229] The wafer defect detection device provided in this application, employing the wafer defect detection method in the above embodiments, can solve the technical problem of wafer defect detection. Compared with related technologies, the beneficial effects of the wafer defect detection device provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and other technical features in the wafer defect detection device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0230] This application provides a wafer defect detection device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the wafer defect detection method in the above embodiment 1.

[0231] The following is for reference. Figure 5The diagram illustrates a structural schematic of a wafer defect detection device suitable for implementing embodiments of this application. The wafer defect detection device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The wafer defect detection equipment shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this application.

[0232] like Figure 5 As shown, the wafer defect inspection device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the wafer defect inspection device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. The communication device 1009 allows the wafer defect inspection equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figures show wafer defect inspection equipment with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0233] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0234] The wafer defect detection equipment provided in this application, employing the wafer defect detection method described in the above embodiments, can solve the technical problems. Compared with related technologies, the beneficial effects of the wafer defect detection equipment provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and other technical features of this wafer defect detection equipment are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0235] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0236] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0237] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the wafer defect detection method in the above embodiments.

[0238] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0239] The aforementioned computer-readable storage medium may be included in the wafer defect detection equipment; or it may exist independently and not assembled into the wafer defect detection equipment.

[0240] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the wafer defect inspection equipment, cause the wafer defect inspection equipment to:

[0241] In response to a wafer defect detection command, the device receives a preset first resolution image of the corresponding wafer captured by the camera.

[0242] Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the binary mask corresponding to the preset first resolution image;

[0243] Based on the preset wafer defect judgment rules and the binary mask, it is determined whether there are defects in the wafer, so as to obtain the wafer defect detection result.

[0244] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0245] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0246] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0247] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described wafer defect detection method, thereby solving the technical problem of wafer defect detection. Compared with related technologies, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and will not be repeated here.

[0248] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the wafer defect detection method described above.

[0249] The computer program product provided in this application can solve the technical problem of wafer defect detection. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as those of the wafer defect detection method provided in the above embodiments, and will not be repeated here.

[0250] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for detecting wafer defects, characterized in that, The wafer defect detection method includes: In response to a wafer defect detection command, the wafer receives a preset first resolution image from a high-magnification TDI camera. Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine the binary mask corresponding to the preset first resolution image. The binary mask is determined based on the BRIEF descriptor. Based on the preset wafer defect judgment rules and the binary mask, it is determined whether there are defects in the wafer, so as to obtain the wafer defect detection result; The step of determining whether a wafer has defects based on a preset wafer defect judgment rule and the binary mask to obtain a wafer defect detection result further includes: Based on the connected component identification optimization strategy, the initial binary mask is optimized to obtain the target binary mask; Based on the target binary mask and the preset defect judgment rule, it is determined whether each target sub-image has a defect, and multiple initial judgment results are obtained; Based on all the initial judgment results, determine whether there are defects in the wafer and obtain the wafer defect detection results; The step of optimizing the initial binary mask based on the connected component identification optimization strategy to obtain the target binary mask further includes: Based on the connected component identification optimization strategy and the preset small image block size, each target sub-image is divided into multiple small image blocks, wherein the connected component identification of each small image block is performed independently in the GPU shared memory; Determine the label of each pixel in each small image patch, and merge equivalent labels based on atomic operations to obtain the initial merge result; Based on a tree-like recursive merging strategy and a 3D thread block index, the boundary pixels of adjacent small image blocks are merged layer by layer to optimize the initial merging result and obtain the target binary mask.

2. The wafer defect detection method as described in claim 1, characterized in that, The step of processing the preset first resolution image in parallel based on the CPU-GPU collaborative computing strategy to determine the binary mask corresponding to the preset first resolution image further includes: Based on a preset image size, the preset first resolution image is divided into blocks to obtain multiple target sub-images; Based on the wafer defect detection instructions and the CPU-GPU collaborative computing strategy, the local CPU is invoked to generate wafer defect detection sub-tasks corresponding to each target sub-image, and the wafer defect detection sub-tasks are allocated to multiple CUDA thread blocks corresponding to the local GPU. Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine the binary mask corresponding to the preset first resolution image.

3. The wafer defect detection method as described in claim 2, characterized in that, The step of processing multiple target sub-images in parallel based on the multiple CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block further includes: Based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, the FAST corner points of each target sub-image are detected in parallel to obtain the target FAST corner points corresponding to each target sub-image. Based on the target FAST corner points, determine the BRIEF descriptor corresponding to each target sub-image; Based on the BRIEF descriptor, an initial binary mask is calculated for each target sub-image patch.

4. The wafer defect detection method as described in claim 3, characterized in that, The step of performing a block operation on the preset first resolution image based on a preset image size to obtain multiple target sub-images further includes: The image at the preset first resolution is subjected to pyramid downsampling to reduce the resolution of the image at the preset first resolution, thereby obtaining an image at the preset second resolution. The target image is obtained by using a two-dimensional Gaussian filter kernel to suppress noise in the preset second resolution image. Based on a preset image size, the target image is divided into blocks to obtain multiple target sub-images.

5. The wafer defect detection method as described in claim 3, characterized in that, The BRIEF descriptor is a binary vector. The step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner points further includes: Obtain the initialized BRIEF descriptor string, wherein each character of the initialized BRIEF descriptor string is 0; Based on the multiple threads contained in the CUDA thread block and the target FAST corner point, the judgment-modification atomic operation is performed in parallel on multiple characters in the initialized BRIEF descriptor string to determine the BRIEF descriptor corresponding to each target sub-image. The step of performing parallel judgment-modification atomic operations on multiple characters in the initialized BRIEF descriptor string includes: Determine whether each character in the initialized BRIEF descriptor string meets the modification requirements; If the condition is met, the character that meets the modification requirement will be changed from 0 to 1.

6. A wafer defect detection device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the wafer defect detection method as described in any one of claims 1 to 5.

7. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the wafer defect detection method as described in any one of claims 1 to 5.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the wafer defect detection method as described in any one of claims 1 to 5.

Images