Compact phase shifter layout

Abstract

The present disclosure relates to a phase shifter circuit having reduced insertion loss and / or reduced area compared to other phase shifter circuits. The phase shifter circuit may include a first phase shifter circuit and a second phase shifter circuit. The first phase shifter circuit may include two overlapping coils forming three inductors. Similarly, the second phase shifter circuit may include two overlapping coils forming three inductors. The coil of the first phase shifter circuit may extend orthogonally to the coil of the second phase shifter. Thus, the first phase shifter circuit and the second phase shifter circuit may have a reduced undesired induced current during operation. Further, the coils of each of the phase shifter circuits are disposed adjacently on a plurality of circuit layers to improve the insertion loss of the phase shifter circuit, reduce the area occupied by the phase shifter circuit, or both, etc.

Description

Background Art

[0001] The present disclosure generally relates to phase shifter circuits for electronic devices.

[0002] A phase shifter circuit can adjust the phase of an input signal to a desired value. For example, an electronic device may include a phase shifter circuit. The electronic device may generate a transmit signal in the form of a beam having desired beam characteristics. The electronic device may use the phase shifter circuit to adjust the phase of the transmit signal based on the direction of the desired beam. The electronic device may then transmit the adjusted transmit signal. Similarly, the electronic device may receive a signal having desired beam characteristics. The electronic device may use the phase shifter circuit to adjust the phase of the received signal in order to receive the signal.

[0003] Limitations in the layout of the phase shifter circuit may result in reduced signal quality, reduced area occupied by the phase shifter circuit, etc. Improved phase shifter circuit layouts are desired to improve signal quality and / or reduce the area occupied by the phase shifter circuit.

[0004] This section is intended to introduce the reader to various aspects of the art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements should be read in this light, and not as admissions of prior art. Summary of the Invention

[0005] The following describes a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise summary of these specific embodiments, and that these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a number of aspects that may not be described below.

[0006] In one embodiment, a phase shifter circuit may include a first phase shifter circuit including a first coil and a second coil. The second coil may be disposed above and extend around a boundary of the first coil and may include a first twisted-loop conductor extending in a first direction. The phase shifter circuit may also include a second phase shifter circuit including a third coil and a fourth coil. The fourth coil may be disposed above and surrounded by a boundary of the third coil and may include a second twisted-loop conductor extending in a second direction different from the first direction.

[0007] In another embodiment, a phase shifter circuit may include a first coil disposed on a first circuit layer and having a first boundary. The first coil may include a first polygonal conductor comprising a first inner conductor coupled to a second inner conductor. The first coil may also include a second polygonal conductor comprising a first outer conductor coupled to a second outer conductor. The first outer conductor may be coupled to the first inner conductor, the second outer conductor may be coupled to the second inner conductor, and the first polygonal conductor may be surrounded by the second outer conductor. The phase shifter circuit may also include a second coil disposed on a second circuit layer. The second coil may be coupled to the first inner conductor and the second inner conductor and may include a first twisted-loop conductor having a second boundary that overlaps the first boundary of the first coil. Furthermore, the phase shifter circuit may include a third coil disposed on the first circuit layer. The third coil may be coupled to the second outer conductor and may not overlap with the first coil or the second coil. Furthermore, the phase shifter circuit may include a fourth coil coupled to the third coil. The fourth coil may include a second twisted-loop conductor surrounded by the third coil, and the second twisted-loop conductor may be disposed in a different direction relative to the first twisted-loop conductor.

[0008] In yet another embodiment, an electronic device includes a processing circuit, an antenna, and a phase shifter circuit coupled to the antenna and the processing circuit. The phase shifter circuit may include a first coil and a second coil coupled to the first coil. The second coil may be disposed above and extend around the first coil, and the second coil may include a first twisted loop conductor extending in a first direction. The phase shifter circuit may also include a third coil coupled to the first coil. The third coil may not overlap with the first coil and the second coil. In addition, the phase shifter circuit may include a fourth coil coupled to the third coil. The fourth coil may be disposed above and surrounded by the third coil, and the fourth coil may include a second twisted loop conductor extending in a second direction different from the first direction.

[0009] With respect to various aspects of the present disclosure, there may be various improvements to the above-mentioned features. Other features may also be incorporated into these various aspects. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments in the illustrated embodiments may be incorporated into any of the above-mentioned aspects of the present disclosure individually or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of the embodiments of the present disclosure, and does not limit the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 2 According to the embodiment of the present disclosure Figure 1 Functional diagram of the electronic equipment;

[0013] Figure 3 According to the embodiment of the present disclosure Figure 1 A schematic diagram of a transmitter of an electronic device;

[0014] Figure 4 According to the embodiment of the present disclosure Figure 1 a schematic diagram of a receiver of an electronic device;

[0015] Figure 5 According to the embodiment of the present disclosure Figures 1 to 4 A schematic diagram of a phase shifter circuit of an electronic device;

[0016] Figure 6 According to the embodiment of the present disclosure Figure 5 a first phase shifter circuit layout of the phase shifter circuit;

[0017] Figure 7 According to the embodiment of the present disclosure Figure 5 a layout of a second phase shifter circuit of the phase shifter circuit; and

[0018] Figure 8 According to an embodiment of the present disclosure, a first phase shifter circuit and a second phase shifter circuit are provided. Figure 6 and Figure 7 Layout of the phase shifter circuit. DETAILED DESCRIPTION

[0019] When introducing the elements of the various embodiments of the present disclosure, the articles "a", "an" and "the" are intended to mean that there are one or more elements in the elements. The terms "comprise", "comprising" and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the described features. In addition, specific features, structures or characteristics can be combined in any appropriate manner in one or more embodiments. The use of the terms "roughly", "close", "about", "close to" and / or "substantially" should be understood to mean including close to a target (e.g., design, value and amount), such as within the limits of any suitable or conceivable error (e.g., within 0.1% of a target, within 1% of a target, within 5% of a target, within 10% of a target, within 25% of a target, etc.). Furthermore, it should be understood that any exact value, number, measurement, etc. provided herein is contemplated to include approximations of such exact value, number, measurement, etc. (e.g., within a suitable or contemplated margin of error). Additionally, the term "set" may include one or more. That is, a set may include a single set of one member, but a set may also include sets of multiple members.

[0020] The present disclosure relates to a phase shifter circuit having reduced insertion loss and / or reduced area compared to other phase shifters. The phase shifter circuit may include, for example, a first phase shifter circuit and a second phase shifter circuit. In some embodiments, the first phase shifter circuit and the second phase shifter circuit may each include two coils forming three inductors.

[0021] The first phase shifter circuit and the second phase shifter circuit can each reduce the induced current of the phase shifter circuit during operation. The first phase shifter circuit and the second phase shifter circuit can have non-overlapping boundaries. That is, the first phase shifter circuit and the second phase shifter circuit can each guide the input signal through a plurality of polygonal conductors, which are arranged adjacent to or overlapping along multiple planes of the circuit board. The polygonal conductors of each of the first phase shifter circuit and the second phase shifter circuit can not overlap with each other or at least partially overlap. The planes of the circuit board can be arranged parallel to each other. In some cases, the induced current of one or more of the polygonal conductors destructively combines to reduce the induced current of the phase shifter circuit. Therefore, the phase shifter circuit can output a signal with improved linearity based on the reduced induced current.

[0022] Furthermore, the first phase shifter circuit and the second phase shifter circuit may each include orthogonally arranged, non-overlapping, figure-eight-shaped polygonal conductors. In some cases, the orthogonal, non-overlapping arrangement of the figure-eight-shaped polygonal conductors may increase the distance between the polygonal conductors of the first phase shifter circuit and the second phase shifter circuit. The increased distance between the polygonal conductors may reduce the induced current of the phase shifter circuits.

[0023] In some embodiments, the phase shifter circuit can have reduced insertion loss due to the reduced induced current. In some cases, the phase shifter circuit can output a signal with improved linearity due to the reduced induced current. Furthermore, in specific embodiments, due to the arrangement of the polygonal conductor in each of the inductors, the phase shifter circuit can have a reduced area compared to other phase shifters.

[0024] Figure 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor for convenience, which may be implemented as any suitable form of processing circuitry), memory 14, non-volatile storage 16, a display 18, input structures 22, an input / output (I / O) interface 24, a network interface 26, and a power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine-executable instructions), or a combination of hardware and software elements (which may be referred to as logical components). The processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to send and / or receive signals between each other. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10 .

[0025] By way of example, electronic device 10 may include any suitable computing device, including a desktop or laptop computer, a portable electronic or handheld electronic device (such as a wireless electronic device or a smart phone), a tablet computer, a wearable electronic device, and other similar devices. In additional or alternative embodiments, electronic device 10 may include an access point, such as a base station, a router (e.g., a wireless or Wi-Fi router), a hub, a switch, etc. It should be noted that Figure 1 The processor 12 and other related items in the embodiment may be embodied in whole or in part as software, hardware, or both. Figure 1The processor 12 and other related items in the electronic device 10 may be a single contained processing module, or may be fully or partially incorporated into any of the other elements within the electronic device 10. The processor 12 may be implemented using a combination of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gated logic, discrete hardware components, a dedicated hardware finite state machine, or any other suitable entity that can perform calculations or other manipulations of information. The processor 12 may include one or more application processors, one or more baseband processors, or both, and perform the various functions described herein.

[0026] exist Figure 1 In the electronic device 10, the processor 12 may be operably coupled with the memory 14 and the non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of manufacture including one or more tangible computer-readable media. The tangible computer-readable medium may include the memory 14 and / or the non-volatile storage device 16, individually or collectively, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of manufacture for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard drives, and optical disks. In addition, the program encoded on such a computer program product (e.g., an operating system) may also include instructions that can be executed by the processor 12 to enable the electronic device 10 to provide various functions.

[0027] In certain embodiments, display 18 can facilitate a user viewing images generated on electronic device 10. In some embodiments, display 18 can include a touch screen that can facilitate user interaction with a user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 can include one or more liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0028] The input structures 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., pressing a button to increase or decrease the volume level). As with the network interface 26, the I / O interface 24 may enable the electronic device 10 to interact with various other electronic devices. In some embodiments, the I / O interface 24 may include an I / O port for a hardwired connection for charging and / or content manipulation using a standard connector and protocol (such as a Lightning connector, a universal serial bus (USB), or other similar connectors and protocols). The network interface 26 may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN), such as one of the IEEE 802.11x family of protocols (e.g. ) networks; and / or wide area networks (WANs), such as any standards associated with the 3rd Generation Partnership Project (3GPP), including, for example, 3rd generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), 4th generation (4G) cellular networks, (LTE) cellular network, Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular network, 5th Generation (5G) cellular network and / or New Radio (NR) cellular network, 6th Generation (6G) or beyond 6G cellular network, satellite network, non-terrestrial network, etc. Specifically, the network interface 26 may include, for example, one or more interfaces for using cellular communication standards that define and / or implement a frequency range for wireless communication including a millimeter wave (mmWave) frequency range (e.g., 24.25-300 gigahertz (GHz)) of the 5G specification. The network interface 26 of the electronic device 10 may allow communication through the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0029] The network interfaces 26 may also include, for example, one or more interfaces for: a broadband fixed wireless access network (e.g., ), mobile broadband wireless network (mobile ), asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video terrestrial broadcasting ( ) network and its extended DVB handheld equipment ( ) network, an ultra-wideband (UWB) network, an alternating current (AC) power line, etc. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0030] As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or part of the transceiver 30 may be disposed within the processor 12. The transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas and may therefore include a transmitter and a receiver. In some embodiments, the transceiver 30 may include a phase shifter circuit. The phase shifter circuit may include, for example, a first phase shifter circuit and a second phase shifter circuit having non-overlapping boundaries. In some embodiments, the first phase shifter circuit and the second phase shifter circuit may each include two coils forming three inductors. In addition, the first phase shifter circuit and the second phase shifter circuit may each guide the input signal through a plurality of polygonal conductors of the corresponding coils, the plurality of polygonal conductors being disposed adjacently or overlappingly along a plurality of planes of the circuit board.

[0031] Figure 2 According to the embodiment of the present disclosure Figure 1 1 is a functional diagram of electronic device 10. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54, and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) can be communicatively coupled to each other directly or indirectly (e.g., through or via another component, a communication bus, a network) to send and / or receive signals between each other.

[0032] The electronic device 10 may include a transmitter 52 and / or a receiver 54, both of which enable signals to be sent and received between the electronic device 10 and an external device via, for example, a network (e.g., including a base station or access point) or a direct connection. As shown, the transmitter 52 and the receiver 54 may be combined into a transceiver 30. In some embodiments, the transmitter 52, the receiver 54, or both may include a phase shifter circuit. In some cases, the phase shifter circuit may adjust the phase of the transmitted signal so that it is transmitted by the antennas 55A-55N. For example, the phase shifter circuit may adjust the phase of the transmitted signal based on the direction of the desired transmit beam. In addition, the phase shifter circuit may adjust the phase of the signal received by the antennas 55A-55N so that it is received by the processor 12 and / or the memory 14, etc. For example, the phase shifter circuit may adjust the phase of the received signal based on the direction of the receive beam associated with the received signal.

[0033] As described above, the phase shifter circuit may include, for example, a first phase shifter circuit and a second phase shifter circuit having non-overlapping boundaries. The first phase shifter circuit and the second phase shifter circuit may each reduce the induced current of the phase shifter circuit during operation. In some embodiments, the phase shifter circuit may have reduced insertion loss and / or improved linearity. In some embodiments, the phase shifter circuit can adjust the phase of a transmitted signal and / or a received signal with improved accuracy compared to other phase shifters. Alternatively or additionally, the phase shifter circuit may have a reduced area compared to other phase shifters, as will be understood.

[0034] The electronic device 10 may also have antennas 55A-55N electrically coupled to the transceiver 30. The antennas 55A-55N may be configured in an omnidirectional or directional configuration, a single beam, a dual beam, or a multi-beam arrangement, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in the antenna group or module 55A-55N may be communicatively coupled to the corresponding transceiver 30 and each emit a radio frequency signal that may constructively and / or destructively combine to form a beam. The electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some embodiments, the transmitter 52 and the receiver 54 may transmit and receive information via other wired or wired systems or devices.

[0035] As illustrated, the various components of electronic device 10 may be coupled together via a bus system 56. Bus system 56 may include, for example, a data bus, as well as a power bus, a control signal bus, and a status signal bus in addition to the data bus. The components of electronic device 10 may be coupled together or receive or provide input to each other using some other mechanism.

[0036] Figure 3 is a schematic diagram of a transmitter 52 (e.g., transmitting circuitry) of a transceiver 30 according to an embodiment of the present disclosure. As shown, the transmitter 52 is capable of receiving outgoing data 60 in the form of a digital signal to be transmitted via one or more antennas 55. In some embodiments, the transmitter 52 may receive the outgoing data 60 from the processor 12. A digital-to-analog converter (DAC) 62 of the transmitter 52 may convert the digital signal into an analog signal, and a modulator 64 may combine the converted analog signal with a carrier signal to generate a radio wave 67 (e.g., a modulated signal).

[0037] In some embodiments, a power amplifier (PA) 66 may be coupled to the output of the modulator 64. In the depicted embodiment, a phase shifter circuit 68 may be coupled to the output of the modulator 64. In some cases, the phase shifter circuit 68 may adjust the phase of the radio wave 67. For example, the phase shifter circuit 68 may adjust the phase of the radio wave 67 based on a desired direction or characteristic of the transmit beam. That is, the phase of the radio wave 67 may correspond to the direction of the transmit beam. Thus, adjusting the phase of the radio wave 67 may adjust the direction of the transmit beam.

[0038] The power amplifier 66 receives the phase-shifted radio wave 67 (e.g., a phase-shifted and modulated signal) from the phase shifter circuit 68. The power amplifier 66 can amplify the radio wave 67 to generate an amplified signal. The power amplifier 66 can generate the amplified signal to a suitable level to drive the transmission of the signal via one or more antennas 55. It should be understood that in alternative or additional embodiments, the power amplifier 66 can be provided before the phase shifter circuit 68 and / or after the filter 69, etc.

[0039] A filter 69 (e.g., filter circuitry and / or software) of the transmitter 52 may then remove the undesirable noise from the phase-shifted, amplified radio waves 67 to generate a transmitted signal 70 to be transmitted via the one or more antennas 55. The filter 69 may include any suitable filter or filters that remove undesirable noise from the amplified signal, such as a bandpass filter, a bandstop filter, a low-pass filter, a high-pass filter, and / or a decimation filter.

[0040] The power amplifier 66 and / or the filter 69 may be referred to as part of a radio frequency front end (RFFE) (and more specifically, a transmit front end (TXFE) of the electronic device 10). Additionally, the transmitter 52 may include any suitable additional components not shown, or may exclude some of the components shown, so that the transmitter 52 can transmit the outgoing data 60 via the one or more antennas 55. For example, the transmitter 52 may include a mixer and / or a digital upconverter. As another example, if the power amplifier 66 outputs an amplified signal within or approximately within a desired frequency range (such that filtering of the amplified signal may not be necessary), the transmitter 52 may not include the filter 69. It should be understood that the transceiver 30 may include multiple branches of the transmitter 52, each of which includes similar or different components.

[0041] Figure 4is a schematic diagram of a receiver 54 (e.g., receiving circuitry) according to an embodiment of the present disclosure. As shown, the receiver 54 can receive a received signal 80 in the form of an analog signal from one or more antennas 55. A low noise amplifier (LNA) 82 can amplify the received analog signal to generate an amplified received signal 83. In some embodiments, a filter can be coupled to the input of the low noise amplifier (LNA) 82. The amplified received signal 83 can amplify the received analog signal to a suitable level for processing by the receiver 54.

[0042] In some cases, the phase shifter circuit 68 can adjust the phase of the amplified received signal 83. For example, the phase shifter circuit 68 can adjust the phase of the amplified received signal 83 based on the desired direction or characteristics of the received beam. That is, the phase of the amplified received signal 83 can correspond to the direction of the received beam. Therefore, adjusting the phase of the amplified received signal 83 can adjust the direction or characteristics of the received beam (e.g., used to receive the received signal 80). It should be understood that in alternative or additional embodiments, the phase shifter circuit 68 can be disposed before the low noise amplifier 82 and / or after the filter 84, etc.

[0043] In some embodiments, the transmitter 52 and the receiver 54 discussed above may include (e.g., share) a phase shifter circuit 68. Alternatively or additionally, the transmitter 52 may include a first phase shifter circuit 68, and the receiver 54 may include a second phase shifter circuit 68. For example, in some embodiments, the first phase shifter circuit 68 and the second phase shifter circuit 68 may include similar circuits and components.

[0044] The filter 84 (e.g., filter circuitry and / or software) may remove unwanted noise (such as cross-channel interference) from the amplified received signal 83. The filter 84 may also remove additional signals received by one or more antennas 55 at frequencies different from the desired signal. The filter 84 may include any one or more suitable filters for removing unwanted noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low-pass filter, a high-pass filter, and / or a decimation filter. The low-noise amplifier 82 and / or the filter 84 may be referred to as part of the RFFE, and more specifically, as a receiver front end (RXFE) of the electronic device 10.

[0045] The demodulator 86 can remove the RF carrier signal from the filtered signal and / or extract the demodulated signal (e.g., envelope signal) for processing. The analog-to-digital converter (ADC) 88 can receive the demodulated analog signal and convert the signal into a digital signal of the incoming data 90 for further processing by the electronic device 10. Additionally, the receiver 54 can include any suitable additional components not shown, or can exclude some of the components shown, so that the receiver 54 can receive the received signal 80 via one or more antennas 55. For example, the receiver 54 can include a mixer and / or a digital downconverter. It should be understood that the transceiver 30 can include multiple branches of the receiver 54, each of which includes similar or different components.

[0046] Figure 5 is a schematic diagram of a phase shifter circuit 68 according to an embodiment of the present disclosure. As described above, the transceiver 30 may include the phase shifter circuit 68. The phase shifter circuit 68 may include a first phase shifter circuit 120 and a second phase shifter circuit 122. The first phase shifter circuit 120 may shift (e.g., delay) the phase of an input signal by a first phase shift value (e.g., -25° or less, -47° or less, -65° or less, -90° or less, -98° or less, -90° or greater, or the like). In addition, the second phase shifter circuit 122 may shift (e.g., delay) the phase of the input signal by a second phase shift value (e.g., -25° or less, -32° or less, -39° or less, -45° or less, -52° or less, -45° or greater, or the like).

[0047] The first phase shifter circuit 120 may have a first terminal 124. The first phase shifter circuit 120 may be coupled to the second phase shifter circuit 122. Furthermore, the second phase shifter circuit 122 may have a second terminal 126. In some embodiments, the phase shifter circuit 68 may receive an input signal from the first terminal 124. In alternative or additional embodiments, the phase shifter circuit 68 may receive an input signal from the second terminal 126. The input signal may include the radio wave 67 discussed above, an amplified signal, and / or an amplified received signal 83, etc. Similarly, the first terminal 124 and the second terminal 126 may output a signal through the first terminal 124 and / or the second terminal 126. The output signal may include the conditioned radio wave 67, the amplified signal, and / or the amplified received signal 83.

[0048] The first phase shifter circuit 120 may include a first switch 130, a second switch 132, and a third switch 134. The first phase shifter circuit 120 may include a first inductor 146 (L1) and a second inductor 148 (L2) coupled to the first switch 130 and the second switch 132. The first inductor 146 may be coupled to the first terminal 124. In the depicted embodiment, the second inductor 148 may be coupled to the first switch 130 via a capacitor 158. The first inductor 146 and the second inductor 148 may have different or opposite polarities. Furthermore, when the first switch 130 is closed, the first inductor 146 and the second inductor 148 may be coupled in parallel.

[0049] The first inductor 146 and the second inductor 148 may be coupled to a third inductor 150 (L3) via the second switch 132. The third inductor 150 may be coupled to the second switch 132 and the third switch 134 at one end and to a ground connection at a second end. The third inductor 150 may be coupled to the first inductor 146 and the second inductor 148 via the second switch 132 and to a ground connection via the third switch 134. The third switch 134 may be closed (e.g., activated) and / or the second switch may be opened (e.g., deactivated) to couple the third inductor 150 to the ground connection and thereby bypass the third inductor 150.

[0050] The first switch 130 may be opened, the second switch 132 may be opened, and the third switch 134 may be closed to adjust the phase of the input signal by the first phase shift value. The first switch 130 may be closed, the second switch 132 may be closed, and the third switch 134 may be opened to bypass the first phase shifter circuit 120. Thus, the first phase shifter circuit 120 may be coupled to the second phase shifter circuit 122 via the first switch 130 and the capacitor 158.

[0051] Furthermore, the second phase shifter circuit 122 may include a fourth switch 136, a fifth switch 138, and a sixth switch 140. The second phase shifter circuit 122 may include a fourth inductor 152 (L4) and a fifth inductor 154 (L5) coupled to the fourth switch 136 and the fifth switch 138. The fifth inductor 154 may be coupled to the second terminal 126. The fourth inductor 152 and the fifth inductor 154 may have different or opposite polarities. Furthermore, when the fourth switch 136 is closed, the fourth inductor 152 and the fifth inductor 154 may be coupled in parallel.

[0052] Fourth inductor 152 and fifth inductor 154 may be coupled to sixth inductor 156 (L6) via fifth switch 138. Sixth inductor 156 may be coupled to fifth switch 138 and sixth switch 140 at one end and to a ground connection at a second end. Sixth inductor 156 may be coupled to first inductor 146 and second inductor 148 via fifth switch 138 and to a ground connection via sixth switch 140. Sixth switch 140 may be closed (e.g., activated) and / or the fifth switch may be opened (e.g., deactivated) to couple sixth inductor 156 to a ground connection and thereby bypass sixth inductor 156.

[0053] The fourth switch 136 may be opened, the fifth switch 138 may be opened, and the sixth switch 140 may be closed to adjust the phase of the input signal by the second phase shift value. The fourth switch 136 may be closed, the fifth switch 138 may be closed, and the sixth switch 140 may be opened to bypass the second phase shifter circuit 122. Thus, the phase shifter circuit 68 may adjust the phase of the input signal by the first phase shift value, the second phase shift value, or both. The processor 12 discussed above, or any other applicable component, may generate control signals to open and close switches 130, 132, 134, 136, 138, and 140.

[0054] Figure 6 1 is a layout 160 of the first phase shifter circuit 120 of the phase shifter circuit 68 according to an embodiment of the present disclosure. The first phase shifter circuit 120 may include a first coil 162 and a second coil 164. The first coil 162 may form a first inductor 146 (L1) and a second inductor 148 (L2). In addition, the second coil 164 may form a third inductor 150 (L3), as will be understood. As described above, the first phase shifter circuit 120 may shift (e.g., delay) the phase of the input signal by a first phase shift value (e.g., -25°, -47°, -65°, -90°, -98°, etc.).

[0055] The first coil 162 can be disposed on a first circuit layer 172 (e.g., a first planar surface) of the phase shifter circuit 68. The second coil 164 can be disposed on a second circuit layer 174 (e.g., a second planar surface) of the phase shifter circuit 68. The first circuit layer 172 can be disposed above or below the second circuit layer 174 and in proximity to (e.g., adjacent to) the second circuit layer. For example, the first circuit layer 172 and the second circuit layer 174 can each be disposed on different circuit layers of a printed circuit board (PCB), etc.

[0056] The first coil 162 may include a first outer conductor 180, a first inner conductor 182, a second inner conductor 184, and a second outer conductor 186. The conductors 180, 182, 184, and 186 may each form a portion of a corresponding polygonal shape, as discussed herein. The first outer conductor 180 may be coupled to the first terminal 124 of the phase shifter circuit 68. Additionally, the second outer conductor 186 may be coupled to the second phase shifter circuit 68. As described above, in some embodiments, the first phase shifter circuit 120 may receive an input signal from the first terminal 124. In alternative or additional embodiments, the first phase shifter circuit 120 may receive an input signal from the second phase shifter circuit 68.

[0057] In some embodiments, the first outer conductor 180 can be disposed at least partially symmetrically with the second outer conductor 186. The first outer conductor 180 can be disposed proximate to (e.g., adjacent to) and around the second inner conductor 184 on the first circuit layer 172. That is, the first outer conductor 180 can be disposed circularly outside (e.g., around) the second inner conductor 184 and partially surround the second inner conductor.

[0058] Similarly, the second outer conductor 186 can be disposed proximate to (e.g., adjacent to) and around the first inner conductor 182 on the first circuit layer 172. That is, the second outer conductor 186 can be concentrically disposed outside (e.g., disposed around) and partially surround the first inner conductor 182. The first inner conductor 182 and the second inner conductor 184 can be coupled to the first outer conductor 180 and the second outer conductor 186 and disposed therebetween.

[0059] Thus, first outer conductor 180 can be coupled to second outer conductor 186 via first inner conductor 182 and second inner conductor 184. In some embodiments, first outer conductor 180 can also be coupled to second outer conductor 186 via first switch 130 and capacitor 158. As described above, first switch 130 can be closed to bypass phase shifter circuit 68 by coupling first terminal 124 to second phase shifter circuit 68.

[0060] First inner conductor 182 can be coupled to first outer conductor 180 via first connector 190. Second inner conductor 184 can be coupled to second outer conductor 184 via second connector 192 that is cross-coupled above or below first connector 190. Furthermore, first inner conductor 182 can be coupled to second inner conductor 184 to form a first polygonal conductor 194. Thus, first polygonal conductor 194 can be disposed between first outer conductor 180 and second outer conductor 186 and / or twisted within the first and second outer conductors.

[0061] The first coil 162 can include a first connector 190, a second connector 192, or both. The first connector 190 can be disposed (e.g., cross-over) above or below the second connector 192 across multiple circuit layers to cross-couple the outer conductors 180 and 186 to the inner conductors 182 and 184. In particular embodiments, the first connector 190 and the second connector 192 can each be disposed on and / or between the first circuit layer 172 and / or the second circuit layer 174, etc.

[0062] In the depicted embodiment, the first polygonal conductor 194 can be surrounded (e.g., wrapped around) the first outer conductor 180 and the second outer conductor 186. A polygonal conductor, such as the first polygonal conductor 194, can have any feasible polygonal shape and / or symmetrical polygonal shape, etc. For example, the first polygonal conductor 194 (which includes the first inner conductor 182 and the second inner conductor 184) can have a circular shape, a pentagonal shape, an octagonal shape, a hexagonal shape, etc.

[0063] In some embodiments, the first outer conductor 180 and the second outer conductor 186 can be symmetrical or at least partially symmetrical. Furthermore, the first outer conductor 180 can be disposed around the second inner conductor 184, and the second outer conductor 186 can be disposed around the first inner conductor 182. In some embodiments, the first outer conductor 180 and the first inner conductor 182 can form at least a portion of a second polygonal conductor 196 (e.g., a symmetrical polygonal conductor). The first inductor 146 can include the second polygonal conductor 196 that includes the first outer conductor 180 and the first inner conductor 182.

[0064] Similarly, the second outer conductor 186 and the second inner conductor 184 can form at least a portion of a third polygonal conductor 198 (e.g., a symmetrical polygonal conductor). The second inductor 148 can include the third polygonal conductor 198, which includes the second outer conductor 186 and the second inner conductor 184. In the depicted embodiment, a first region associated with the first inductor 146 can at least partially overlap with a second region associated with the second inductor 148. The first region can be partially surrounded by the second polygonal conductor 196. Furthermore, the second region can be partially surrounded by the third polygonal conductor 198. Thus, the first inductor 146 and the second inductor 148 can be at least partially entangled.

[0065] The first inductor 146 can be coupled to the first terminal 124 and the second inductor 148. Furthermore, the second inductor 148 can be coupled to the first inductor 146 and the second phase shifter circuit 122. As described above, the first inductor 146 of the first phase shifter circuit 120 can receive an input signal from the first terminal 124 and provide an output signal to the second phase shifter circuit 68. Alternatively or additionally, the second inductor 148 of the first phase shifter circuit 120 can receive an input signal from the second phase shifter circuit 68 and provide an output signal to the first terminal 124.

[0066] The second coil 164 may include a first twisted-loop conductor 210 having a figure-8 shape. The first twisted-loop conductor 210 may include a fourth polygonal conductor 212 (e.g., a symmetrical polygonal conductor) and a fifth polygonal conductor 214 (e.g., a symmetrical polygonal conductor). The fourth polygonal conductor 212 may be cross-coupled to the fifth polygonal conductor 214 (e.g., a symmetrical polygonal conductor).

[0067] The fourth polygonal conductor 212 and the fifth polygonal conductor 214 may each have a circular shape, a pentagonal shape, an octagonal shape, and / or a hexagonal shape, etc. The third inductor 150 may include the fourth polygonal conductor 212 and the fifth polygonal conductor 214 .

[0068] The fourth polygonal conductor 212 can be cross-coupled to the fifth polygonal conductor 214 via a third connector 216 and a fourth connector 218. The second coil 164 may include the third connector 216, the fourth connector 218, or both. The third connector 216 may be disposed (e.g., cross-coupling) above or below the fourth connector 218 across multiple circuit layers to cross-couple the fourth polygonal conductor 212 to the fifth polygonal conductor 214. In a specific embodiment, the third connector 216 and the fourth connector 218 may each be disposed on the first circuit layer 172 and / or the second circuit layer 174, and / or between them, etc. Thus, the second coil 164 may form a first twisted ring conductor 210 based on the cross-coupling of the fourth polygonal conductor 212 to the fifth polygonal conductor 214.

[0069] The second coil 164 may have a first input port and a first output port on the fourth polygonal conductor 212. The first output port of the second coil 164 may be coupled to a ground connection. The first input port may be coupled to the intersection of the first inner conductor 182 and the second inner conductor 184 of the first coil 162. In a specific embodiment, the first inner conductor 182 may be separated from the second inner conductor 184 at the coupling point of the first input port.

[0070] In some embodiments, the first input port can be coupled to the intersection of first inner conductor 182 and second inner conductor 184 via second switch 132. Second switch 132 can couple first coil 162 and second coil 164, as well as decouple them. Thus, second switch 132 can be opened to bypass second coil 164. Second switch 132 can be disposed on first circuit layer 172 and / or second circuit layer 174, and / or between them, etc. In some embodiments, the first input port can also be coupled to a ground connection via third switch 134. Thus, third switch 134 can be closed to couple second coil 164 to the ground connection, thereby bypassing second coil 164.

[0071] Considering the foregoing, third inductor 150 can receive at least a portion of the input signal. As described above, third inductor 150 can receive at least a portion of the input signal when first switch 130 is open, second switch 132 is closed, and third switch 134 is open. Fourth polygonal conductor 212 and fifth polygonal conductor 214 can direct the portion of the input signal in opposite directions based on cross-coupling and a figure-eight shape.

[0072] In some cases, directing input signals in opposite directions through the adjacent polygonal conductors 212 and 214 of the second coil 164 can reduce induced currents in the first phase shifter circuit 120 during operation. For example, in certain cases, at least a portion of the induced currents of the polygonal conductors 212 and 214 can destructively combine during operation.

[0073] Furthermore, in the depicted embodiment, the second coil 164 can be disposed on the second circuit layer 174, overlying and extending at least partially around (e.g., outside) the boundary of the first coil 162 on the first circuit layer 172. For example, the first twisted ring conductor 210 can have a second boundary that overlies (e.g., substantially overlies) the first boundary of the first coil 162. In some cases, the first inductor 146 and the second inductor 148 disposed on the first circuit layer 172 can reduce the induced current of the third inductor 150 disposed on the second circuit layer 174 during operation.

[0074] Similarly, the third inductor 150 can reduce the induced current of the first inductor 146 and the second inductor 148 during operation. For example, in certain cases, at least a portion of the induced currents of the inductors 146, 148, and 150 can destructively combine during operation. It should be understood that in alternative or additional embodiments, the first coil 162 can overlie the boundary of the second coil 164 and extend at least partially around the boundary (e.g., outside the boundary).

[0075] Figure 72 is a layout 230 of the second phase shifter circuit 122 of the phase shifter circuit 68 according to an embodiment of the present disclosure. The second phase shifter circuit 122 may include a third coil 166 and a fourth coil 168. As described above, the second phase shifter circuit 122 may shift (e.g., delay) the phase of the input signal by a second phase shift value (e.g., -25°, -32°, -39°, -45°, -52°, etc.). The third coil 166 may form the fourth inductor 152 (L4) and the fifth inductor 154 (L5). In addition, the fourth coil 168 may form the sixth inductor 156 (L6).

[0076] The third coil 166 may be disposed on a first circuit layer 172 (e.g., a first planar surface) of the phase shifter circuit 68. The fourth coil 168 may be disposed on a second circuit layer 174 (e.g., a second planar surface) of the phase shifter circuit 68. As described above, the first circuit layer 172 may be disposed above or below the second circuit layer 174 and in proximity to (e.g., adjacent to) the second circuit layer.

[0077] The third coil 166 may include a third outer conductor 232 and a fourth outer conductor 234 forming a sixth polygonal conductor 236 (e.g., a symmetrical polygonal conductor). In some embodiments, the third outer conductor 232 and the fourth outer conductor 234 may each form a respective portion of the sixth polygonal conductor 236. The third outer conductor 232 may be twisted above or below the fourth outer conductor 234 to form the sixth polygonal conductor 236. The sixth polygonal conductor 236 may be formed in a circular shape, a pentagonal shape, an octagonal shape, a hexagonal shape, or the like.

[0078] In some cases, fourth coil 168 can be coupled to the intersection of third outer conductor 232 and fourth outer conductor 234. Fourth coil 168 can include a second twisted ring conductor 238 disposed between, surrounded by (e.g., encircled by), and / or coupled to third outer conductor 232 and fourth outer conductor 234, as will be understood.

[0079] In some embodiments, the third outer conductor 232 can be coupled to the second outer conductor 186 of the first coil discussed above. Additionally, the fourth outer conductor 234 can be coupled to the second terminal 126. Thus, in some cases, the second phase shifter circuit 122 can receive an input signal from the second terminal 126. Alternatively or additionally, the second phase shifter circuit 122 can receive an input signal from the first phase shifter circuit 68.

[0080] The fourth inductor 152 may include the portion of the sixth polygonal conductor 236 that includes the third outer conductor 232. The fifth inductor 154 may include the remaining portion of the sixth polygonal conductor 236 that includes the fourth outer conductor 234. In the depicted embodiment, the third region associated with the fourth inductor 152 may at least partially overlap with the fourth region associated with the fifth inductor 154. The third region may be partially surrounded by the third outer conductor 232. Furthermore, the fourth region may be partially surrounded by the fourth outer conductor 234. Thus, the fourth inductor 152 and the fifth inductor 154 may be at least partially intertwined.

[0081] In some embodiments, third outer conductor 232 can include a fifth connector 242, and fourth outer conductor 234 can include a sixth connector 244. For example, fifth connector 242 can be disposed (e.g., crossed) above or below sixth connector 244 across multiple circuit layers to twist third outer conductor 232 above or below fourth outer conductor 234. In particular embodiments, fifth connector 242 and sixth connector 244 can each be disposed on and / or between first circuit layer 172 and / or second circuit layer 174, and / or so forth.

[0082] In an alternative or additional embodiment, third outer conductor 232 can be coupled to fourth outer conductor 234 via fourth switch 136. Fourth switch 136 can couple the input / output portion of third outer conductor 232 to the input / output portion of fourth outer conductor 234, and decouple them. For example, fourth switch 136 can couple second outer conductor 186 of the first coil discussed above to second terminal 126, and decouple them. Thus, fourth switch 136 can be opened to bypass third coil 166. Fourth switch 136 can be disposed on first circuit layer 172 and / or second circuit layer 174, and / or between them, and so on.

[0083] The fourth coil 168 may include a second twisted-loop conductor 238 having a figure-eight shape. The second twisted-loop conductor 238 may include a seventh polygonal conductor 252 (e.g., a symmetrical polygonal conductor) cross-coupled to an eighth polygonal conductor 254 (e.g., a symmetrical polygonal conductor). For example, the seventh polygonal conductor 252 and the eighth polygonal conductor 254 may each have a circular shape, a pentagonal shape, an octagonal shape, and / or a hexagonal shape, etc. The sixth inductor 156 may include the seventh polygonal conductor 252 and the eighth polygonal conductor 254.

[0084] In some embodiments, the seventh polygonal conductor 252 and the eighth polygonal conductor 254 can share a portion of the respective conductors. Furthermore, the seventh polygonal conductor 252 can be cross-coupled to the eighth polygonal conductor 254 via a seventh connector 256. In some embodiments, the fourth coil 168 can include the seventh connector 256. The seventh connector 256 can be disposed (e.g., cross-connected) above or below a portion of the seventh polygonal conductor 252 and the eighth polygonal conductor 254.

[0085] The seventh connector 256 can be provided across multiple circuit layers to cross-couple the seventh polygonal conductor 252 to the eighth polygonal conductor 254. In a specific embodiment, the seventh connector 256 can be provided on the first circuit layer 172 and / or the second circuit layer 174 and / or between the first circuit layer 172 and / or the second circuit layer 174, etc. Thus, the fourth coil 168 can form the second twisted ring conductor 238 by cross-coupling the seventh polygonal conductor 252 to the eighth polygonal conductor 254.

[0086] The seventh polygonal conductor 252 may have a second input port and a second output port. The second output port may be coupled to a ground connection. The second input port may be coupled to the intersection of the third outer conductor 232 and the fourth outer conductor 234 of the third coil 166. In some embodiments, the third outer conductor 232 may be separated from the fourth outer conductor 234 at the coupling point of the second input port.

[0087] In some embodiments, the second input port can be coupled to the intersection of third outer conductor 232 and fourth outer conductor 234 via fifth switch 138. Fifth switch 138 can couple and decouple third coil 166 and fourth coil 168. Fifth switch 138 can be opened to bypass fourth coil 168. Fifth switch 138 can be disposed on first circuit layer 172 and / or second circuit layer 174, and / or between the two, etc. In some embodiments, the second input port can also be coupled to a ground connection via sixth switch 140. Thus, sixth switch 140 can be closed to couple fourth coil 168 to the ground connection, thereby bypassing fourth coil 168.

[0088] The third outer conductor 232 and the fourth outer conductor 234 can be disposed proximate to (e.g., adjacent to) and around the second twisted-ring conductor 238. The third outer conductor 232 and the fourth outer conductor 234 can be disposed in a circular manner outside of and partially around the second twisted-ring conductor 238. For example, the third coil 166 can extend around the perimeter of the second twisted-ring conductor 238. It should be understood that in alternative or additional embodiments, the second twisted-ring conductor 238 can be disposed in a circular manner outside of and partially around the third outer conductor 232 and the fourth outer conductor 234. For example, the second twisted-ring conductor 238 can extend around the perimeter of the third coil 166.

[0089] Considering the foregoing, sixth inductor 156 may receive at least a portion of the input signal. As described above, sixth inductor 156 may receive at least a portion of the input signal when fourth switch 136 is open, fifth switch 138 is closed, and sixth switch 140 is open. Seventh polygonal conductor 252 and eighth polygonal conductor 254 may be cross-coupled and have a figure-8 shape to direct the portion of the input signal in opposite directions.

[0090] In some cases, directing input signals in opposite directions through the adjacent polygonal conductors 252 and 254 of the fourth coil 168 can reduce induced currents in the second phase shifter circuit 122 during operation. For example, in some cases, at least a portion of the induced currents of the polygonal conductors 252 and 254 can destructively combine during operation.

[0091] Furthermore, in the depicted embodiment, the third coil 166 can be disposed on the first circuit layer 172, overlying and extending at least partially around (e.g., outside) the boundary of the fourth coil 168 disposed on the second circuit layer 174. In some cases, the fourth inductor 152 and the fifth inductor 154 disposed on the first circuit layer 172 can reduce the induced current of the sixth inductor 156 disposed on the second circuit layer 174 during operation.

[0092] Similarly, the sixth inductor 156 can reduce the induced current of the fourth inductor 152 and the fifth inductor 154 during operation. For example, in some cases, at least a portion of the induced currents of the inductors 152, 154, and 156 can destructively combine during operation. It should be understood that in alternative or additional embodiments, the fourth coil 168 can overlie the boundary of the third coil 166 and extend at least partially around the boundary (e.g., outside the boundary).

[0093] Figure 8 FIG2 is a layout 270 of a phase shifter circuit 68 including a first phase shifter circuit 120 and a second phase shifter circuit 122 according to an embodiment of the present disclosure. The first phase shifter circuit 120 and the second phase shifter circuit 122 can be coupled to an annular guard 272. As discussed above, the first phase shifter circuit 120 can include a first coil 162 and a second coil 164. Additionally, the second phase shifter circuit 122 can include a third coil 166 and a fourth coil 168.

[0094] The third coil 166 and the fourth coil 168 can be positioned adjacent to the first coil 162 and the second coil 164 and have no overlapping boundaries with the first coil 162 and the second coil 164. In some embodiments, the second coil 164 can be positioned and / or extend in a different direction (e.g., perpendicular to, or nearly perpendicular to) than the fourth coil 168. For example, the fourth polygonal conductor 212 and the fifth polygonal conductor 214 of the second coil 164 can extend in a first direction. In a particular embodiment, the seventh polygonal conductor 252 and the eighth polygonal conductor 254 of the fourth coil 168 can extend in a second direction that is perpendicular (e.g., nearly perpendicular) to the first direction.

[0095] In the depicted embodiment, the phase shifter circuit 68 can receive an input signal at the first terminal 124. It should be understood that, in alternative or additional cases, the phase shifter circuit 68 can receive an input signal at the second terminal 126. Furthermore, the first switch 130 is open, the second switch 132 is open, and the third switch 134 is closed. Thus, the fourth polygonal conductor 212 and the fifth polygonal conductor 214 can direct the portion of the input signal in opposite directions based on cross-coupling and having a figure-eight shape. Furthermore, the fourth switch 136 is open, the fifth switch 138 is open, and the sixth switch 140 is closed. Thus, the seventh polygonal conductor 252 and the eighth polygonal conductor 254 can cross-couple and have a figure-eight shape to direct the portion of the input signal in opposite directions.

[0096] As described above, directing the input signal in opposite directions through the adjacent polygonal conductors 212 and 214 of the second coil 164 can reduce the induced current of the first phase shifter circuit 120 during operation. Similarly, in some cases, directing the input signal in opposite directions through the adjacent polygonal conductors 252 and 254 of the fourth coil 168 can reduce the induced current of the second phase shifter circuit 122 during operation. For example, in certain cases, at least a portion of the induced currents of the inductors 146, 148, 150, 152, 154, and 156 can destructively combine during operation.

[0097] In some cases, directing the input signal in opposite directions through adjacent polygonal conductors 212 and 214 of the second coil 164 and adjacent polygonal conductors 252 and 254 of the fourth coil 168 can reduce induced current in the phase shifter circuit 68 during operation. For example, the orthogonal arrangement of the polygonal conductors 212 and 214 of the second coil 164 can increase the distance between the polygonal conductors 212, 214, 252, and 254 compared to the polygonal conductors 252 and 254 of the fourth coil 168.

[0098] Thus, in some cases, the accumulation of induced currents of the polygonal conductors 212, 214, 252, and 254 can be reduced based on the increased distance between the polygonal conductors 212, 214, 252, and 254. In certain cases, at least a portion of the induced currents of the polygonal conductors 212, 214, 252, and 254 can destructively combine to reduce the induced current of the phase shifter circuit 68 during operation. Furthermore, undesirable effects of the inductors 146, 148, 150, 152, 154, and / or 156 on each other and / or on one or more other components of the electronic device 10 (including the phase shifter circuit 68) can be reduced during operation.

[0099] Furthermore, the phase shifter circuit 68 can have reduced insertion loss due to the reduced induced current. In some cases, the phase shifter circuit 68 can output a signal with improved linearity due to the reduced induced current. Furthermore, the phase shifter circuit 68 can have a reduced area compared to other phase shifters. For example, the phase shifter circuit 68 can have a reduced area by 40%, 43%, 56%, 60%, 75%, etc. (and other percentages are possible) compared to other phase shifter circuits.

[0100] It is understood that the use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly stated to users.

[0101] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0102] The technology presented and claimed herein is cited and applied to specific examples of a physical and practical nature that significantly improve the art and is therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "a step for [performing] [the function] ...", such elements are to be construed under 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be construed under 35 U.S.C. § 112(f).

Claims

1. A phase shifter circuit, comprising: a first phase shifter circuit comprising a first coil and a second coil, the second coil being disposed above and extending around a boundary of the first coil, the second coil comprising a first twisted loop conductor extending in a first direction; and A second phase shifter circuit includes a third coil and a fourth coil, the fourth coil being disposed above and surrounded by a boundary of the third coil, the fourth coil including a second twisted ring conductor extending in a second direction different from the first direction. 2 . The phase shifter circuit of claim 1 , wherein the first twisted-loop conductor and the second twisted-loop conductor each comprise a plurality of cross-coupled polygonal conductors forming a figure-8 shape.

3. The phase shifter circuit according to claim 1 , wherein the first phase shifter circuit comprises: a first switch configured to couple a first terminal of the first phase shifter circuit to the second phase shifter circuit; and a second switch configured to bypass the second phase shifter circuit. 4 . The phase shifter circuit of claim 3 , wherein a processing circuit coupled to the phase shifter circuit is configured to close the first switch to bypass the first phase shifter circuit and to close the second switch to bypass the second phase shifter circuit. 5 . The phase shifter circuit of claim 1 , wherein the phase shifter circuit is configured to adjust the phase of a first signal before being transmitted by an antenna and to adjust the phase of a second signal after being received by the antenna. 6 . The phase shifter circuit of claim 1 , wherein the third coil and the fourth coil do not overlap with the first coil and the second coil.

7. A phase shifter circuit, comprising: The first coil is disposed on the first circuit layer and has a first boundary. The first coil includes a first polygonal conductor comprising a first inner conductor coupled to a second inner conductor, and a second polygonal conductor comprising a first outer conductor coupled to a second outer conductor, the first outer conductor coupled to the first inner conductor, and the second outer conductor coupled to the second inner conductor, the first polygonal conductor being surrounded by the second outer conductor, a second coil disposed on a second circuit layer, the second coil coupled to the first inner conductor and the second inner conductor, the second coil comprising a first twisted loop conductor having a second boundary, the second boundary overlapping the first boundary of the first coil, a third coil, the third coil being disposed on the first circuit layer, the third coil being coupled to the second outer conductor, and the third coil not overlapping with the first coil and the second coil; and A fourth coil is coupled to the third coil, the fourth coil including a second twisted-loop conductor surrounded by the third coil, and the second twisted-loop conductor is disposed in a different direction relative to the first twisted-loop conductor.

8. The phase shifter circuit of claim 7, wherein the first outer conductor is disposed around the second inner conductor, and the second outer conductor is disposed around the first inner conductor.

9. The phase shifter circuit of claim 7, wherein the first twisted-loop conductor comprises a third polygonal conductor cross-coupled to a fourth polygonal conductor.

10. The phase shifter circuit of claim 7, wherein the third coil comprises a third outer conductor and a fourth outer conductor, the fourth coil being coupled to an intersection of the third outer conductor and the fourth outer conductor. The phase shifter circuit according to claim 10 , wherein the fourth coil is provided on the second circuit layer.

12. The phase shifter circuit of claim 7, wherein the second twisted-loop conductor comprises a third polygonal conductor cross-coupled to a fourth polygonal conductor.

13. The phase shifter circuit of claim 7, wherein the first twisted-loop conductor and the second twisted-loop conductor each comprise a plurality of interconnected polygonal conductors forming a figure-8 shape.

14. The phase shifter circuit of claim 7, wherein the first twisted-loop conductor extends perpendicularly with respect to the second twisted-loop conductor.

15. The phase shifter circuit according to claim 7, comprising: a first switch configured to couple a first terminal of the phase shifter circuit to the third coil, thereby bypassing the first coil and the second coil; or a second switch configured to couple the second terminal of the phase shifter circuit to the first coil, thereby bypassing the third coil and the fourth coil.

16. An electronic device, comprising: processing circuit; antenna; and a phase shifter circuit coupled to the antenna and the processing circuit, the phase shifter circuit comprising First coil, a second coil coupled to the first coil, the second coil being disposed above and extending around the first coil, the second coil including a first twisted-loop conductor extending in a first direction, a third coil coupled to the first coil, the third coil not overlapping the first coil and the second coil, and A fourth coil is coupled to the third coil, disposed above and surrounded by the third coil, the fourth coil including a second twisted-loop conductor extending in a second direction different from the first direction.

17. The electronic device according to claim 16, comprising: a first switch configured to couple a first terminal of the phase shifter circuit to the third coil, thereby bypassing the first coil and the second coil; and a second switch configured to couple a second terminal of the phase shifter circuit to the first coil, thereby bypassing the third coil and the fourth coil. 18 . The electronic device of claim 17 , wherein the processing circuit is configured to close the first switch to bypass the first coil and the second coil, and to close the second switch to bypass the third coil and the fourth coil.

19. The electronic device of claim 16, wherein the phase shifter circuit is configured to adjust the phase of a first signal before being transmitted by the antenna and to adjust the phase of a second signal before being received by the antenna.

20. The electronic device of claim 19, wherein the processing circuit is configured to generate the first signal and receive the second signal.

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