A gate drive method for short circuit protection of a power switch

Abstract

This invention discloses a gate driving method for short-circuit protection of power switches, relating to the field of power electronics technology. The method includes: constructing an equivalent gate circuit model based on measured values ​​of parasitic inductance and input capacitance; calculating the influence factors of parasitic parameters and measured input capacitance on the driving waveform; dynamically adjusting the driving resistor according to the influence factors to generate a corrected gate driving voltage signal including a compensation pulse voltage; combining the corrected gate driving voltage signal with the real-time value of the main circuit current to obtain the circuit's operating state and calculating the equivalent short-circuit current; arranging the short-circuit current levels according to the equivalent short-circuit current to obtain different fault state levels; accurately extracting parasitic parameters and constructing an equivalent circuit model through high-frequency sweep signal injection; dynamically adjusting the driving resistor and compensation pulse voltage to optimize the gate driving waveform, thereby improving short-circuit protection accuracy and device reliability; achieving rapid short-circuit protection and significantly extending device lifespan.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a gate drive method for short-circuit protection of power switches. Background Technology

[0002] In the field of power electronics, as power semiconductor devices develop towards higher frequencies and higher integration, the reliability and safety of power switches (such as IGBTs and MOSFETs) in high-voltage, high-current applications have become a research hotspot. The gate drive circuit, as a key component controlling the switching on and off, directly affects the device's turn-on and turn-off losses, electromagnetic interference, and short-circuit withstand capability due to its dynamic response characteristics. Traditional gate drive methods often use fixed-value drive resistors to achieve basic control of the switching speed. In recent years, dynamic adjustment mechanisms have been gradually introduced, such as feedback control strategies based on detecting the collector current or gate voltage change rate, to optimize the switching process and improve system stability.

[0003] To address the issues of dynamic response lag and parameter mismatch in traditional drive circuits, both academia and industry have proposed gate drive optimization schemes based on adaptive control. For example, while traditional methods based on fixed resistor adjustment can suppress overshoot, they are difficult to adapt to parasitic parameter changes under complex operating conditions. Existing protection strategies based on state observation can detect short circuits, but they have high computational complexity, limited response speed, and require multi-level hardware redundancy design. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a gate drive method for short-circuit protection of power switches to solve the problem of uncompensated gate drive parasitic parameters.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a gate drive method for short-circuit protection of power switches, comprising: injecting a sweep frequency pulse sequence into the gate drive circuit through a high-frequency sweep frequency signal generator; acquiring the gate voltage response curve and extracting the measured values ​​of parasitic inductance and input capacitance; constructing an equivalent gate circuit model based on the measured values ​​of parasitic inductance and input capacitance; calculating the influence factors of parasitic parameters and measured values ​​of input capacitance on the drive waveform; dynamically adjusting the drive resistor according to the influence factors to generate a corrected gate drive voltage signal including a compensation pulse voltage; combining the corrected gate drive voltage signal with the real-time value of the main circuit current to obtain the circuit's operating state and calculating the equivalent short-circuit current; arranging the short-circuit current levels according to the equivalent short-circuit current to obtain different fault state levels; selecting different discharge paths based on different fault state levels, while locking the gate drive output, and restoring the drive output through a reset signal after the fault is cleared.

[0008] As a preferred embodiment of the gate drive method for short-circuit protection of power switches described in this invention, the steps of injecting a sweep frequency pulse sequence into the gate drive circuit through a high-frequency sweep frequency signal generator, acquiring the gate voltage response curve, and extracting the measured values ​​of parasitic inductance and input capacitance are as follows:

[0009] Connect the high-frequency sweep signal generator to the gate drive circuit of the device under test, and use the high-frequency sweep signal generator to inject a sweep pulse sequence into the gate drive circuit;

[0010] Based on the expected analysis of the device under test, the start frequency, end frequency and sweep speed are adjusted on the high-frequency sweep signal generator. The sweep is started using the high-frequency sweep signal generator, and the gate voltage response curve is monitored and recorded using an oscilloscope.

[0011] The measured values ​​of parasitic inductance and input capacitance are extracted from the gate voltage response curve using a frequency domain parameter extraction method.

[0012] As a preferred embodiment of the gate driving method for short-circuit protection of power switches according to the present invention, the specific steps for constructing the gate equivalent circuit model based on the measured values ​​of parasitic inductance and input capacitance are as follows:

[0013] The gate of the power device is equivalent to a capacitor. The parasitic inductance in the gate voltage response curve and the measured value of the input capacitance are combined with the internal gate resistance to construct the gate equivalent circuit model.

[0014] The gate equivalent circuit model is imported into the circuit simulation software to perform basic switching operation simulations. The simulation results are compared with the actual test data to detect whether the gate equivalent circuit model reflects the behavior of the gate drive circuit. The parameters in the gate equivalent circuit model are then adjusted.

[0015] As a preferred embodiment of the gate drive method for short-circuit protection of power switches according to the present invention, the specific steps for calculating the influence factors of parasitic parameters and measured input capacitance values ​​on the drive waveform are as follows:

[0016] Using the case where the gate equivalent circuit model simulated by the circuit simulation software has no parasitic effects as the baseline, the rise time, fall time and delay of the driving waveform in the current state are recorded to obtain the driving waveform of the baseline state.

[0017] By changing the values ​​of parasitic inductance and input capacitance one by one while keeping other conditions constant, the simulation is performed, and the corresponding changes in the driving waveform characteristics are recorded to obtain the driving waveform of the variable state.

[0018] By comparing the driving waveforms of the baseline state and the variable state, the change in the characteristics of the driving waveform caused by the change is calculated, and the influence factor of the driving waveform is obtained.

[0019] In a preferred embodiment of the gate drive method for short-circuit protection of power switches according to the present invention, the specific steps for dynamically adjusting the drive resistor according to the influencing factor to generate a corrected gate drive voltage signal including a compensation pulse voltage are as follows.

[0020] By analyzing the effects of measured values ​​of parasitic inductance and input capacitance on the rise time, fall time, and delay of the drive waveform in the frequency domain, a mathematical relationship between dynamic drive resistance and influencing factors is constructed, and the drive resistance is dynamically adjusted according to the range of parasitic parameter changes.

[0021] By using the dynamically adjusted drive resistor value and the difference between the actual drive waveform and the ideal drive waveform, the voltage amplitude and time position that need to be compensated are calculated. A high-frequency sweep frequency signal generator is used to generate a compensation pulse voltage signal, which is then superimposed on the original gate drive voltage signal to generate a corrected gate drive voltage signal.

[0022] As a preferred embodiment of the gate drive method for short-circuit protection of power switches according to the present invention, the specific steps of combining the modified gate drive voltage signal with the real-time value of the main circuit current to obtain the circuit's operating state and calculating the equivalent short-circuit current are as follows.

[0023] The real-time value of the main circuit current is obtained by using a high-precision current sensor. The collected gate drive voltage signal and the main circuit current signal are then processed synchronously to obtain synchronization signal data.

[0024] By using synchronization signal data, the actual gate drive voltage response obtained is compared with the expected ideal response to evaluate the operating state of power electronic switching devices in the circuit.

[0025] According to the changing trend of the real-time value of the main circuit current, when the current increases, as the basis for identifying a short-circuit event, using the circuit parameters and the operating state of the power electronic switching devices in the circuit, calculate the equivalent short-circuit current through electrical engineering formulas.

[0026] As a preferred solution of the gate drive method for short-circuit protection of power switches according to the present invention, wherein: according to the equivalent short-circuit current, arrange the short-circuit current levels to obtain different fault state levels, and the specific steps are as follows.

[0027] According to the current-carrying capacity, operating conditions and protection strategy requirements of the power switching devices, preset multiple short-circuit current thresholds, slight short-circuit a, medium short-circuit b, and severe short-circuit c.

[0028] Compare the calculated equivalent short-circuit current I with the short-circuit current thresholds to obtain the short-circuit current level.

[0029] When I ≤ a, the short-circuit current level is the first level.

[0030] When a < I ≤ b, the short-circuit current level is the second level.

[0031] When b < I ≤ c, the short-circuit current level is the third level.

[0032] When I > c, the short-circuit current level is the fourth level.

[0033] Obtain different fault state levels according to the short-circuit current levels respectively.

[0034] As a preferred solution of the gate drive method for short-circuit protection of power switches according to the present invention, wherein: based on different fault state levels, select different levels of discharge paths, lock the gate drive output at the same time, and restore the drive output through a reset signal after the fault is eliminated. The specific steps are as follows.

[0035] According to different fault state levels, select different levels of discharge paths. Based on the selected discharge path, generate a discharge path control signal through a programmable logic controller.

[0036] Apply the discharge path control signal to the corresponding circuit. When the first-level and second-level short circuits are detected, the corresponding circuit receives the discharge path control signal to activate the switching element and open and close the discharge path.

[0037] After detecting the third-level and fourth-level short circuits, lock the gate drive output in a hardware manner to prevent any further switching actions.

[0038] In a second aspect, the present invention provides a computer device including a memory and a processor, the memory storing a computer program, wherein: when the computer program is executed by the processor, it implements any step of the gate drive method for short-circuit protection of a power switch as described in the first aspect of the present invention.

[0039] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the gate driving method for short-circuit protection of a power switch as described in the first aspect of the present invention.

[0040] The beneficial effects of this invention are as follows: by injecting high-frequency sweep signals, parasitic parameters are accurately extracted and an equivalent circuit model is constructed. The driving resistance and compensation pulse voltage are dynamically adjusted to optimize the gate driving waveform, suppress overshoot and ringing phenomena, and improve the accuracy of short-circuit protection and the reliability of the device. Based on the parasitic parameters, the influence factors are calculated to trigger the discharge path in stages and lock the gate output. Combined with the fuse's staged fusing strategy, the fastness, selectivity and safety of short-circuit protection are achieved, significantly enhancing the short-circuit impact resistance of power switches and extending the device life. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a gate drive method for short-circuit protection of power switches.

[0043] Figure 2 This is a flowchart of a gate drive device.

[0044] Figure 3 Flowchart for generating compensation pulse voltage.

[0045] Figure 4 This is a flowchart for short-circuit protection execution. Detailed Implementation

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0048] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0049] Reference Figures 1-4 This embodiment provides a gate driving method for short-circuit protection of power switches, including the following steps:

[0050] S1. Inject a sweep frequency pulse sequence into the gate drive circuit through a high-frequency sweep frequency signal generator, collect the gate voltage response curve, and extract the measured values ​​of parasitic inductance and input capacitance.

[0051] Connect the high-frequency sweep signal generator to the gate drive circuit of the device under test, and inject the sweep pulse sequence into the gate drive circuit using the high-frequency sweep signal generator.

[0052] Specifically, with the device under test (DUT) in a safe power-off state, connect the output of the high-frequency sweep signal generator to the gate drive circuit input of the DUT via an impedance matching network (a circuit design technique used to optimize signal transmission in electronic circuits) and a BNC or SMA cable; ensure that the high-frequency sweep signal ground is correctly connected to avoid common-mode noise interference; configure the high-frequency sweep signal generator to sweep mode; set parameters such as the start frequency, end frequency, and sweep time; start the high-frequency sweep signal generator to begin injecting a sweep pulse sequence into the gate drive circuit; and monitor the response signal using an oscilloscope or other measuring equipment.

[0053] It should be noted that the specific ranges of the start frequency, end frequency, and sweep time of the high-frequency sweep signal generator are set based on the operating frequency range of the power electronic switching device under test. The start frequency should be set to a level that covers the low-frequency response characteristics of the device, typically starting from a few kHz; the end frequency needs to extend to a range sufficient to capture the high-frequency response characteristics of the device, possibly reaching the MHz level. The sweep speed (i.e., sweep time) should be chosen to clearly distinguish the detailed features in the gate voltage response curve, ensuring sufficient data points to accurately reflect response changes. The specific time depends on the experimental requirements and may range from a few seconds to several minutes. Through several experiments and monitoring and recording the gate voltage response curve with an oscilloscope, the settings can be further adjusted and optimized to meet the test requirements.

[0054] Based on the expected analysis of the device under test, the start frequency, end frequency and sweep speed are adjusted on the high-frequency sweep signal generator. The sweep is started using the high-frequency sweep signal generator, and the gate voltage response curve is monitored and recorded using an oscilloscope.

[0055] Specifically, the start and end frequencies are finely adjusted on the high-frequency sweep signal generator according to the operating frequency range of the device to cover all frequency bands of interest. The sweep speed (sweep time) is set to ensure that the detailed features in the gate voltage response can be clearly distinguished. The high-frequency sweep signal generator is connected to the gate drive circuit input terminal of the device under test through a matching network. All connections are secure and the ground wires are correctly connected to avoid interference. The high-frequency sweep signal generator is started to begin the sweep process. At the same time, the gate voltage response curve is monitored and recorded using an oscilloscope.

[0056] The measured values ​​of parasitic inductance and input capacitance are extracted from the gate voltage response curve using a frequency domain parameter extraction method.

[0057] Specifically, the collected gate voltage response curves are imported into the analysis software. Signal processing techniques are used to remove noise and unnecessary interference. The FFT (Fourier Transform) algorithm is applied to the gate voltage response curves, decomposing the original signal into a superposition of sine and cosine waves of different frequencies. Using the amplitude and phase information of the frequency components, the FFT algorithm outputs a complex array, where each element represents the intensity and phase relationship of the corresponding frequency component. The spectrum is plotted using the modulus of the complex array, displaying the energy distribution of the original signal at various frequencies, thus achieving a conversion from the time domain to the frequency domain. In the frequency domain, the influence of parasitic inductance can be identified by analyzing the phase angle changes in the low-frequency band, and the influence of the input capacitance can be identified by observing the amplitude attenuation in the high-frequency band. Characteristics related to parasitic inductance and input capacitance in the circuit are extracted separately. The phase angle in the FFT results gradually lags with increasing frequency, and the phase angle change in the low-frequency range or the impedance trend with increasing frequency is analyzed to determine the value. For the input capacitance, the measured value is extracted by evaluating the impact of the capacitance on signal attenuation in the high-frequency range or by directly measuring the position of the resonant point.

[0058] S2. Construct the gate equivalent circuit model based on the measured values ​​of parasitic inductance and input capacitance.

[0059] The gate of the power device is equivalent to a capacitor. The parasitic inductance in the gate voltage response curve and the measured value of the input capacitance are combined with the internal gate resistance to construct an equivalent gate circuit model.

[0060] Specifically, the gate of the power device is equivalent to a capacitor, reflecting the gate's charge storage requirements during switching. This is derived from the gate charge-voltage relationship curve provided in the device datasheet. The measured value of the parasitic inductance in the gate drive circuit is obtained through high-frequency sweep experiments combined with impedance analysis to reflect the high-frequency response limitations caused by packaging and layout. The actual value of the input capacitance is measured, including the coupling capacitance effect between the gate-source and drain-source. The gate resistance of the device is obtained through indirect estimation by dynamic testing and circuit simulation to simulate the limiting effect of the gate on the drive current. A complete gate equivalent circuit model is built in the circuit simulation software.

[0061] The gate equivalent circuit model is imported into the circuit simulation software to perform basic switching operation simulations. The simulation results are compared with the actual test data to detect whether the gate equivalent circuit model reflects the behavior of the gate drive circuit. The parameters in the gate equivalent circuit model are then adjusted.

[0062] Specifically, simulation parameters and excitation sources are set to simulate actual switching operating conditions, including voltage levels, current loads, and switching frequencies. Basic switching operation simulations are performed in the software environment to generate theoretical drive waveforms and response characteristic curves. The simulation results are compared with previously collected actual test data, focusing on the consistency of key indicators such as rise time, fall time, delay time, and overshoot. This ensures that the gate equivalent circuit model accurately reflects the behavior of the gate drive loop. Parameters in the gate equivalent circuit model, such as parasitic inductance and input capacitance, are adjusted to optimize the model and make it more closely resemble reality. This process is repeated iteratively, iterating through simulations and parameter adjustments, to optimize the gate equivalent circuit model by modifying parameters (such as parasitic inductance or input capacitance values).

[0063] S3. Calculate the influence factors of parasitic parameters and measured input capacitance on the driving waveform.

[0064] Using the case where the gate equivalent circuit model simulated by circuit simulation software has no parasitic effects as a baseline, the rise time, fall time and delay of the driving waveform in the current state are recorded to obtain the driving waveform of the baseline state.

[0065] Specifically, when establishing the gate equivalent circuit model in the circuit simulation software, first remove or set the parasitic inductance to zero and the input capacitance to the typical value given in the device's datasheet. Based on the gate equivalent circuit model, an ideal gate equivalent circuit model that does not consider parasitic effects is obtained. With the same drive voltage, load conditions, and simulation time range, a transient simulation is run to obtain the ideal drive waveform. Parameters such as rise time, fall time, and delay time are extracted from the simulation results, and these parameters are saved as the drive waveform characteristics of the reference state.

[0066] It should be noted that the reference state refers to the driving waveform characteristics under the ideal gate equivalent circuit model established in the circuit simulation software, without considering any parasitic effects (such as setting the parasitic inductance to zero and using the nominal value of the input capacitance).

[0067] By changing the values ​​of parasitic inductance and input capacitance one by one while keeping other conditions constant, the simulation is performed, and the corresponding changes in the driving waveform characteristics are recorded to obtain the driving waveform of the variable state.

[0068] Specifically, the baseline state is the circuit state after changing a specific parameter (such as parasitic inductance or input capacitance). After completing the baseline state simulation, keeping the drive voltage, load conditions, and other circuit parameters constant, determine the possible range of variation for parasitic inductance and input capacitance based on the actual application of the device and information provided in the datasheet, and select the increment (step size) for parameter adjustment. Initially, keep all conditions constant and adjust only one variable (e.g., start with parasitic inductance). After each adjustment, run a complete transient simulation and record the corresponding drive waveform characteristics (such as rise time, fall time, and delay time). After evaluating the entire range of parasitic inductance variation, fix the parasitic inductance at a certain value (which can be the initial value or the optimized value), and repeat the process to adjust the input capacitance individually. After each circuit parameter adjustment, run a transient simulation, record the corresponding drive waveform, and extract key indicators such as rise time, fall time, and delay time.

[0069] It should be noted that variable state refers to the change in the value of a variable over time or during program execution. Each variable has a definite value at a specific moment, and variable state refers to the state of a variable at that specific moment.

[0070] By comparing the driving waveforms of the baseline state and the variable state, the change in the characteristics of the driving waveform caused by the change is calculated, and the influence factor of the driving waveform is obtained.

[0071] Specifically, the characteristics of the driving waveform in the baseline state (such as rise time, fall time, and delay time) are compared with the corresponding characteristics in the variable state by calculating the differences in each characteristic parameter. For each driving waveform characteristic, the change is calculated using a formula, and the influence factor is also calculated using a formula. For changes in parasitic inductance or input capacitance, the above steps are repeated for each adjusted simulation result. The influence of each characteristic parameter change on the driving waveform characteristics is quantified by calculating the change in time characteristics caused by a unit parameter change, thereby obtaining the influence factor of the driving waveform.

[0072] It should be noted that the expression for calculating the change is: ;

[0073] in, It is the change in the characteristics of the driving waveform. It is a time parameter measured under variable conditions. These are the corresponding time parameters under the reference state.

[0074] The expression for calculating the impact factor is: ;

[0075] in, It is an influencing factor of the driving waveform. It is the actual change in parasitic inductance or input capacitance.

[0076] S4. Dynamically adjust the driving resistor according to the influencing factor to generate a corrected gate driving voltage signal that includes a compensation pulse voltage.

[0077] By analyzing the effects of measured values ​​of parasitic inductance and input capacitance on the rise time, fall time, and delay of the drive waveform in the frequency domain, a mathematical relationship between the dynamic drive resistance and the influencing factors is constructed, and the drive resistance is dynamically adjusted according to the range of parasitic parameter changes.

[0078] Specifically, frequency domain analysis is used to analyze the gate equivalent circuit model containing measured values ​​of parasitic inductance and input capacitance. This yields the gain (amplitude) and phase response characteristics of the circuit at different frequencies. By observing changes in phase and amplitude in the phase response characteristics, the impact on the rise time, fall time, and delay of the driving waveform is identified. By analyzing the amplitude attenuation and phase hysteresis characteristics at different frequencies in the frequency domain response, and by gradually adjusting the values ​​of parasitic inductance and input capacitance in circuit simulation software while keeping other conditions constant, the changes in rise time, fall time, and delay time of the driving waveform under different settings can be recorded. First, a baseline state is set (parasitic inductance is zero, input capacitance is the nominal value). Each parameter value is changed one by one, and simulation is run to obtain the waveform characteristic differences brought about by each change, thereby obtaining the influence relationship between parasitic inductance and input capacitance on the driving waveform characteristics. After determining the influence relationship between each parasitic parameter and the driving waveform characteristics based on the frequency domain response characteristics, according to the minimum to maximum range of parasitic inductance values ​​that may occur in actual circuits provided in the device datasheet, and the influence factor of the driving waveform, the current magnitude is controlled based on the circuit requirements to ensure stable circuit operation. Based on the operating voltage and required current of the load (such as an LED), the driving resistance is obtained using Ohm's law, and the value of the driving resistance is dynamically adjusted using mathematical relationships to compensate for performance deviations caused by parasitic effects.

[0079] It should be noted that the mathematical relationship between the dynamic drive resistance and the influence factor of the drive waveform is as follows: ;

[0080] in, For parasitic inductance, For input capacitance, For dynamic driving resistors.

[0081] By using the dynamically adjusted drive resistor value and the difference between the actual drive waveform and the ideal drive waveform, the voltage amplitude and time position that need to be compensated are calculated. A high-frequency sweep frequency signal generator is used to generate a compensation pulse voltage signal, which is then superimposed on the original gate drive voltage signal to generate a corrected gate drive voltage signal.

[0082] Specifically, based on the key electrical characteristic parameters provided in the device datasheet, such as maximum ratings, typical operating voltage and current, switching time, and input capacitance, an ideal model is simulated in circuit simulation software without considering any parasitic effects. For example, assuming the gate capacitance is ideal and ignoring all parasitic inductance and resistance, the power supply voltage and load conditions are set, and the simulation is run to generate a theoretically perfect drive waveform.

[0083] By comparing the ideal driving waveform with the actual driving waveform point by point on the same time axis, the voltage amplitude and time position that need to be compensated are obtained. A high-frequency sweep frequency signal generator is used to generate an accurate compensation pulse voltage signal based on the specific numerical results of the difference, so that the amplitude and time position accurately correspond to the value that needs to be compensated. The compensation pulse voltage signal is superimposed on the original gate driving voltage signal, and the synthesis of the two is realized through circuit design, thereby generating the corrected gate driving voltage signal.

[0084] S5. Combine the corrected gate drive voltage signal with the real-time value of the main circuit current to obtain the circuit's operating state and calculate the equivalent short-circuit current.

[0085] The real-time value of the main circuit current is obtained by using a high-precision current sensor. The collected gate drive voltage signal and the main circuit current signal are then synchronized to obtain synchronization signal data.

[0086] Specifically, a suitable current sensor is installed in the main circuit. This main circuit can be any circuit section that carries load current, such as the inverter output in a motor driver, the output terminal of a power supply, or the output line of any other power electronic converter. The current sensor is directly connected in series in the main circuit to detect the actual current flowing through the circuit in a non-invasive or invasive manner. The detected current is converted into a standard voltage signal or digital signal for the controller to process, and transmitted to the data acquisition unit for sampling and recording to obtain the current signal. The processed voltage and current signals are integrated into a synchronization dataset according to the time sequence, and the synchronization dataset is mapped to the drive state and circuit conditions at the same moment to obtain the synchronization signal data.

[0087] By using synchronization signal data, the operating state of power electronic switching devices in a circuit is evaluated by comparing the actual gate drive voltage response with the expected ideal response.

[0088] Specifically, the gate drive voltage waveform is extracted from the synchronization signal data to obtain the change in the main circuit current at the corresponding time. The extracted actual gate drive voltage response is compared point by point with a pre-set ideal response template. The ideal response template is constructed based on the typical gate drive characteristics of power electronic switching devices under normal operating conditions. The deviation values ​​between the actual response and the ideal response at each time point are obtained, including parameters such as amplitude deviation and phase deviation. Based on the magnitude and trend of the deviation values, combined with the dynamic characteristics and working principle of the power electronic switching devices, it is determined whether the power electronic switching devices are currently in a normal conduction or turn-off state, or whether there are abnormalities such as false turn-on or turn-off delay, thus obtaining the working state of the power electronic switching devices in the circuit.

[0089] Based on the real-time trend of the main circuit current, when the current increases, the equivalent short-circuit current is calculated using electrical engineering formulas, based on circuit parameters and the operating state of power electronic switching devices in the circuit, as a basis for identifying short-circuit events.

[0090] Specifically, the main circuit current data is monitored in real time using a high-precision current sensor. At the same time, the load inductance, parasitic inductance, input capacitance, and gate drive resistance are collected and measured to obtain circuit parameters. The collected main circuit current data is filtered and denoised to remove high-frequency interference. A static current change rate threshold is set based on the maximum allowable peak current characteristics of the power electronic switching devices. When the current is detected to rise sharply in a short period of time and exceed the current change rate threshold, it is identified as a potential short circuit event. Circuit parameters, including DC bus voltage, load inductance, parasitic inductance, and on-resistance of the switching devices, are immediately extracted. Based on electrical engineering principles, the equivalent short-circuit current at the moment of short circuit is calculated using formulas.

[0091] It should be noted that the electrical engineering formula is: ;

[0092] in, Indicates at a certain moment The equivalent short-circuit current, Indicates the DC bus voltage. Indicates the equivalent resistance. Represents a time variable. This represents the time constant.

[0093] S6. Arrange the short-circuit current levels according to the equivalent short-circuit current to obtain different fault state levels.

[0094] According to the current-carrying capacity, operating conditions, and protection strategy requirements of the power switch device, multiple short-circuit current thresholds are preset, including mild short-circuit a, moderate short-circuit b, and severe short-circuit c.

[0095] Specifically, collect the rated current, thermal impedance characteristics, and safe operating area (SOA) data from the device manual and adjust them according to the actual application environment; based on the simulation results, set the mild short-circuit threshold to be close to but lower than the maximum allowable peak current of the device, which will not immediately trigger the protection mechanism but serve as a warning signal; set the moderate short-circuit threshold within the range that the device can withstand but requires a rapid response to avoid damage caused by long-term overload; set the severe short-circuit threshold to a current level far beyond the safe operating range of the device. Once the severe short-circuit threshold is reached, immediately execute emergency protection measures, such as quickly turning off the switch device or cutting off the power supply, to prevent equipment damage or fire risk.

[0096] Compare the calculated equivalent short-circuit current I with the short-circuit current thresholds to obtain the short-circuit current level.

[0097] When I ≤ a, the short-circuit current level is the first level.

[0098] When a < I ≤ b, the short-circuit current level is the second level.

[0099] When b < I ≤ c, the short-circuit current level is the third level.

[0100] When I > c, the short-circuit current level is the fourth level.

[0101] Obtain different fault state levels according to the short-circuit current levels.

[0102] Specifically, when the equivalent short-circuit current is less than the mild short-circuit current threshold, the short-circuit current level is the first level, indicating normal operation or no obvious abnormality; when the equivalent short-circuit current exceeds the mild short-circuit current threshold but does not reach the moderate short-circuit current threshold, the short-circuit current level is the second level, indicating a mild short-circuit, which may be caused by transient disturbances or light overloads, and the system can issue a warning signal and enter the monitoring state; when the equivalent short-circuit current exceeds the moderate short-circuit current threshold but does not reach the severe short-circuit current threshold, the short-circuit current level is the third level, indicating a moderate short-circuit with potential risks, and preliminary protection actions (such as reducing the output power and limiting the gate drive ability) need to be initiated; when the equivalent short-circuit current exceeds the severe short-circuit current threshold, the short-circuit current level is the fourth level, indicating a severe short-circuit that may cause irreversible damage to the device, and emergency protection measures (such as quickly turning off the switch device, cutting off the main circuit power supply, and triggering the fault locking mechanism) should be immediately executed. According to the determined short-circuit current levels, different fault state levels are respectively corresponding, which are: the first level, the second level, the third level, and the fourth level.

[0103] S7. Select different discharge paths based on different fault state levels, lock the gate drive output, and restore the drive output through a reset signal after the fault is cleared.

[0104] Based on different fault state levels, different discharge paths are selected, and based on the selected discharge path, discharge path control signals are generated by the programmable logic controller.

[0105] Specifically, the current fault state level is determined based on the short-circuit current level. For level one (no fault), no discharge path needs to be triggered. For level two (warning state), a mild discharge path is activated, such as using a bypass resistor to slightly dissipate excess energy. For level three (protection action state), a moderate discharge path is selected, including activating an energy absorption circuit or adding additional heat dissipation measures. For level four (emergency shutdown state), the highest level discharge path is activated, such as quickly connecting to a high-power discharge resistor or capacitor bank to rapidly absorb a large amount of energy. Based on the selected discharge path, a corresponding control logic program is written using a PLC to monitor the fault state level in real time and generate the corresponding discharge path control signal through the programmable logic controller.

[0106] When a discharge path control signal is applied to the corresponding circuit, and a short circuit between the first and second levels is detected, the corresponding circuit receives the discharge path control signal and activates the switching element to open and close the discharge path.

[0107] Specifically, the discharge path control signal is generated by the programmable logic controller (PLC) according to the current fault state level and sent to the gate drive circuit of the switching element (such as MOSFET, IGBT or relay) in the discharge path through the digital output interface. After receiving a valid control signal, the gate drive circuit applies a drive voltage to the switching element, turns on and connects the discharge path; energy begins to be discharged in a controlled manner through the path. When the fault state is cleared or the normal state is restored, the PLC cancels the control signal, the gate drive voltage is removed, the switching element is turned off, and the discharge path is disconnected.

[0108] Upon detecting a short circuit at levels 3 and 4, the gate drive output is locked in hardware to prevent any further switching action.

[0109] Specifically, upon detecting a Level 3 (moderate short circuit) or Level 4 (severe short circuit) short circuit event, the gate drive output is immediately locked via hardware. The comparator or dedicated fault detection module in the protection circuit converts the short circuit current level signal into a hardware lockout trigger signal. The lockout trigger signal is sent to the enable pin (such as the EN pin) of the gate drive chip or an external shutdown pin (such as FLT, SD, etc.) to directly shut down the drive output stage. The lockout trigger signal can also be used to trigger latching circuits (such as RS flip-flops) or control relay operation, achieving physical isolation of the gate drive power supply or control signal path. Once locked, even if the subsequent control signal returns to normal, the lockout must be released by manual reset or power-on restart, thereby ensuring that the power switching device will not be falsely triggered to conduct before the severe fault is eliminated, achieving reliable protection for the power switch.

[0110] This embodiment also provides a computer device applicable to a gate driving method for short-circuit protection of power switches, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the gate driving method for short-circuit protection of power switches as proposed in the above embodiment.

[0111] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0112] This embodiment also provides a storage medium storing a computer program that, when executed by a processor, implements the gate driving method for short-circuit protection of a power switch as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0113] In summary, this invention improves short-circuit protection accuracy and device reliability by: accurately extracting parasitic parameters and constructing an equivalent circuit model through high-frequency sweep signal injection; dynamically adjusting the drive resistor and compensation pulse voltage to optimize the gate drive waveform, suppressing overshoot and ringing phenomena; calculating influencing factors based on parasitic parameters to trigger the discharge path in stages and lock the gate output; and combining this with a fuse-based staged fusing strategy.

[0114] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A gate driving method for short-circuit protection of power switches, characterized in that: include, A high-frequency sweep pulse sequence is injected into the gate drive circuit through a high-frequency sweep signal generator, the gate voltage response curve is collected, and the measured values ​​of parasitic inductance and input capacitance are extracted. A gate equivalent circuit model is constructed based on the measured values ​​of parasitic inductance and input capacitance, and the influence factors of parasitic parameters and measured values ​​of input capacitance on the driving waveform are calculated. The driving resistor is dynamically adjusted according to the influencing factor to generate a corrected gate driving voltage signal that includes a compensation pulse voltage. By combining the corrected gate drive voltage signal with the real-time value of the main circuit current, the operating state of the circuit is obtained, and the equivalent short-circuit current is calculated. Based on the equivalent short-circuit current, the short-circuit current levels are arranged to obtain different fault state levels; Different discharge paths are selected based on different fault state levels, while the gate drive output is locked and the drive output is restored by a reset signal after the fault is cleared.

2. The gate drive method for short-circuit protection of power switches as described in claim 1, characterized in that: The process involves injecting a sweep pulse sequence into the gate drive circuit using a high-frequency sweep signal generator, acquiring the gate voltage response curve, and extracting the measured values ​​of parasitic inductance and input capacitance. The specific steps are as follows: Connect the high-frequency sweep signal generator to the gate drive circuit of the device under test, and use the high-frequency sweep signal generator to inject a sweep pulse sequence into the gate drive circuit; Based on the expected analysis of the device under test, the start frequency, end frequency and sweep speed are adjusted on the high-frequency sweep signal generator. The sweep is started using the high-frequency sweep signal generator, and the gate voltage response curve is monitored and recorded using an oscilloscope. The measured values ​​of parasitic inductance and input capacitance are extracted from the gate voltage response curve using a frequency domain parameter extraction method.

3. The gate drive method for short-circuit protection of power switches as described in claim 2, characterized in that: The specific steps for constructing the gate equivalent circuit model based on the measured values ​​of parasitic inductance and input capacitance are as follows. The gate of the power device is equivalent to a capacitor. The parasitic inductance in the gate voltage response curve and the measured value of the input capacitance are combined with the internal gate resistance to construct the gate equivalent circuit model. The gate equivalent circuit model is imported into the circuit simulation software to simulate switching operations. The simulation results are compared with the actual test data to detect whether the gate equivalent circuit model reflects the behavior of the gate drive circuit. The parameters in the gate equivalent circuit model are then adjusted.

4. The gate drive method for short-circuit protection of power switches as described in claim 3, characterized in that: The specific steps for calculating the influence factors of parasitic parameters and measured input capacitance values ​​on the driving waveform are as follows. Using the case where the gate equivalent circuit model simulated by the circuit simulation software has no parasitic effects as the baseline, the rise time, fall time and delay of the driving waveform in the current state are recorded to obtain the driving waveform of the baseline state. By changing the values ​​of parasitic inductance and input capacitance one by one while keeping other conditions constant, the simulation is performed, and the corresponding changes in the driving waveform characteristics are recorded to obtain the driving waveform of the variable state. By comparing the driving waveforms of the baseline state and the variable state, the change in the characteristics of the driving waveform caused by the change is calculated, and the influence factor of the driving waveform is obtained.

5. The gate drive method for short-circuit protection of power switches as described in claim 4, characterized in that: The specific steps for dynamically adjusting the driving resistor based on the influencing factor to generate a corrected gate driving voltage signal including a compensation pulse voltage are as follows. By analyzing the effects of the measured values of parasitic inductance and input capacitance on the rise time, fall time, and delay phenomenon of the driving waveform in the frequency domain, constructing the mathematical relationship between the dynamic driving resistance and influencing factors, and dynamically adjusting the driving resistance according to the change range of parasitic parameters; Using the dynamically adjusted driving resistance value, combining the difference between the actual driving waveform and the ideal driving waveform, calculating the voltage amplitude and time position that need to be compensated, and using a high-frequency sweep signal generator to generate a compensated pulse voltage signal, and superimposing the compensated pulse voltage signal on the original gate driving voltage signal to generate a corrected gate driving voltage signal.

6. The gate drive method for short-circuit protection of power switches as described in claim 5, characterized in that: Combining the corrected gate driving voltage signal with the real-time value of the main circuit current to obtain the working state of the circuit and calculating the equivalent short-circuit current. The specific steps are as follows: Obtain the real-time value of the main circuit current through a high-precision current sensor, and synchronize the collected gate driving voltage signal and the main circuit current signal to obtain synchronous signal data; Using the synchronous signal data, evaluate the working state of the power electronic switch device in the circuit by comparing the obtained actual gate driving voltage response with the expected ideal response; According to the change trend of the real-time value of the main circuit current, when the current increases, as the basis for identifying a short-circuit event, use the circuit parameters and the working state of the power electronic switch device in the circuit to calculate the equivalent short-circuit current through electrical engineering formulas.

7. The gate drive method for short-circuit protection of power switches as described in claim 6, characterized in that: According to the equivalent short-circuit current, arrange the short-circuit current levels to obtain different fault state levels. The specific steps are as follows: According to the current-carrying capacity, working conditions, and protection strategy requirements of the power switch device, preset multiple short-circuit current thresholds, slightly short circuit a, moderately short circuit b, and severely short circuit c; Compare the calculated equivalent short-circuit current I with the short-circuit current threshold to obtain the short-circuit current level; When I ≤ a, the short-circuit current level is the first level; When a < I ≤ b, the short-circuit current level is the second level; When b < I ≤ c, the short-circuit current level is the third level; When I > c, the short-circuit current level is the fourth level; Obtain different fault state levels according to the short-circuit current levels respectively.

8. The gate drive method for short-circuit protection of power switches as described in claim 7, characterized in that: Based on different fault state levels, select different levels of discharge paths, lock the gate driving output at the same time, and restore the driving output through a reset signal after the fault is eliminated. The specific steps are as follows: According to different fault state levels, select different levels of discharge paths, and based on the selected discharge paths, generate a discharge path control signal through a programmable logic controller; Apply the discharge path control signal to the corresponding circuit. When the first-level and second-level short circuits are detected, the corresponding circuit receives the discharge path control signal to activate the switching element and open and close the discharge path; After detecting the third-level and fourth-level short circuits, lock the gate driving output in a hardware manner to prevent any further switching actions.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the gate driving method for short-circuit protection of a power switch according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the gate driving method for short-circuit protection of a power switch according to any one of claims 1 to 8.

Images