Transistor structure and method of fabricating the same

Abstract

The application provides a transistor structure and a manufacturing method thereof. The transistor structure comprises a substrate, a heterojunction film layer and an electrode layer. The electrode layer comprises a gate part, a source part and a drain part. The transistor structure further comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is coupled with the second dielectric layer. The first dielectric layer and the second dielectric layer are located on a side of the heterojunction film layer away from the substrate. A projection of the second dielectric layer is located between projections of adjacent gate parts and drain parts, and / or a projection of the second dielectric layer is located between projections of adjacent gate parts and source parts. At least part of a projection of the first dielectric layer is located between a projection of an adjacent gate part and a projection of the second dielectric layer. The first dielectric layer and the second dielectric layer have different lattice constants. The application decouples the off-current and the sheet resistance, and the user can independently control the off-current and the sheet resistance of the transistor structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a transistor structure and its fabrication method. Background Technology

[0002] Gallium nitride high-mobility transistors (GaNHEMTs) offer advantages over traditional transistors, including high mobility, high breakdown electric field, and low gate charge. They hold significant promise for applications in high-frequency, high-power switching devices.

[0003] Existing GaN HEMTs generally include a gate region and a drift region. The film layer layout of the gate region can adjust the turn-off current of the GaN HEMT, and the film layer layout of the drift region can adjust the sheet resistance of the drift region. However, existing transistor structures cannot achieve independent adjustment of the turn-off current and sheet resistance. Summary of the Invention

[0004] This invention provides a transistor structure and a method for fabricating the transistor structure, in order to solve the problem that in existing GaN HEMT structures, the same dielectric layer is often deposited in the gate region and the drift region, making it impossible for users to independently control the turn-off current and sheet resistance in existing GaN HEMT structures.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a transistor structure, comprising: a substrate, and a heterojunction layer and an electrode layer sequentially stacked on the substrate along a direction away from the substrate; the electrode layer comprising: a gate portion, a source portion, and a drain portion; the orthographic projection of the gate portion on the substrate is located between the orthographic projections of the adjacent source portion and the drain portion on the substrate; the transistor structure further comprises:

[0007] A first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are coupled together, and both the first dielectric layer and the second dielectric layer are located on the side of the heterojunction film layer facing away from the substrate.

[0008] The orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion on the substrate and the orthographic projections of the drain portion on the substrate, and / or, the orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion on the substrate and the orthographic projections of the source portion on the substrate.

[0009] At least a portion of the orthographic projection of the first dielectric layer on the substrate is located between the orthographic projection of the adjacent gate portion on the substrate and the orthographic projection of the second dielectric layer on the substrate.

[0010] The first dielectric layer and the second dielectric layer have different lattice constants.

[0011] Optionally,

[0012] The first dielectric layer includes a strip structure extending along the width direction of the channel, and the second dielectric layer includes a strip structure extending along the width direction of the channel.

[0013] Optionally,

[0014] The second dielectric layer includes at least two second dielectric patterns arranged along the channel width direction, and the first dielectric layer includes a first portion and at least one second portion coupled to the first portion;

[0015] The orthographic projection of the first portion on the substrate is located between the orthographic projection of the adjacent gate portion on the substrate and the orthographic projection of the second dielectric pattern on the substrate.

[0016] The orthographic projection of the second portion on the substrate and the orthographic projection of the second dielectric pattern on the substrate are alternately arranged.

[0017] Optionally,

[0018] The first dielectric layer further includes a third portion and / or a fourth portion, wherein the third portion is coupled to the second dielectric layer and the fourth portion is coupled to the second dielectric layer;

[0019] The orthographic projection of the third portion on the substrate is located between the orthographic projection of the adjacent source portion on the substrate and the orthographic projection of the second dielectric layer on the substrate.

[0020] The fourth portion lies between the orthographic projection of the adjacent drain portion onto the substrate and the orthographic projection of the second dielectric layer onto the substrate.

[0021] Optionally,

[0022] The transistor structure further includes: a gate, a source, and a drain; the gate includes at least two gate portions, the source includes at least two source portions, and the drain includes at least two drain portions; the orthographic projections of the source portions on the substrate and the orthographic projections of the drain portions on the substrate alternate, and there is an orthographic projection of the gate portion on the substrate between adjacent orthographic projections of the source portions on the substrate and the orthographic projections of the drain portions on the substrate.

[0023] Optionally,

[0024] The gate portion further includes: a gate electrode and a gate layer;

[0025] The gate layer is located between the heterojunction layer and the gate electrode;

[0026] The orthographic projection of the gate layer on the heterojunction layer at least partially overlaps with the orthographic projection of the gate electrode on the heterojunction layer;

[0027] The gate layer includes a P-type gallium nitride layer;

[0028] The heterojunction film layer includes a gallium nitride layer and an aluminum gallium nitride layer stacked together, with the gallium nitride layer located between the substrate and the aluminum gallium nitride layer.

[0029] Optionally,

[0030] The transistor structure also includes:

[0031] A protective layer is stacked on the electrode layer, covering the first dielectric layer and the second dielectric layer.

[0032] In a second aspect, embodiments of the present invention provide a method for fabricating a transistor structure, used to fabricate a transistor structure as described in any one of the first aspects, the method comprising:

[0033] Provide a substrate;

[0034] A heterojunction film layer is fabricated on the substrate.

[0035] An electrode layer is fabricated on the heterojunction film layer; the electrode layer includes: a gate portion, a source portion, and a drain portion; the orthographic projection of the gate portion on the substrate is located between the orthographic projections of the adjacent source portion on the substrate and the orthographic projections of the drain portion on the substrate.

[0036] A first dielectric layer and a second dielectric layer are fabricated, both located on the side of the heterojunction film layer facing away from the substrate. The orthographic projection of the second dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the drain portion on the substrate, and / or, the orthographic projection of the second dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the source portion on the substrate. At least a portion of the orthographic projection of the first dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the second dielectric layer on the substrate. The lattice constants of the first dielectric layer and the second dielectric layer are different.

[0037] Optionally, the manufacturing method further includes:

[0038] Fabrication of dielectric material films;

[0039] A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask region and an opening region. The mask region corresponds to the region where the first dielectric layer is located, and the opening region corresponds to the region where the second dielectric layer is located.

[0040] The dielectric material film layer at the location corresponding to the opening region is modified to form the second dielectric layer.

[0041] Optionally, the manufacturing method further includes:

[0042] Fabrication of dielectric material films;

[0043] A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask area and an opening area. The mask area corresponds to the area where the first dielectric layer is located, and the opening area corresponds to the area where the second dielectric layer is located.

[0044] Using the mask layer as a mask, the dielectric material film layer exposed in the opening area is removed to form a first dielectric layer; a second dielectric layer is then fabricated at the corresponding position in the opening area.

[0045] In this embodiment of the invention, the coupling between the first dielectric layer and the second dielectric layer is a non-detachable connection between the molecules of two heterogeneous materials (except for destructive disassembly). At the interface where the first dielectric layer and the second dielectric layer meet, the difference in lattice constants between the two dielectric layers affects the polarization intensity of the underlying heterojunction interface, ultimately changing the 2DEG concentration of the heterojunction beneath the first and second dielectric layers. This decouples the turn-off current and sheet resistance, allowing the user to independently control the turn-off current and sheet resistance of the transistor structure in this embodiment of the invention. In practical applications, the user can control the turn-off current and sheet resistance by adjusting the first dielectric layer and / or the second dielectric layer. Attached Figure Description

[0046] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0047] Figure 1 This is a top view schematic diagram of the crystal structure in the related technology;

[0048] Figure 2 for Figure 1 A schematic diagram of the cross-section along the A1A2 direction;

[0049] Figure 3 This is one of the top views of a crystal structure provided in an embodiment of the present invention;

[0050] Figure 4 for Figure 3 A schematic diagram of the cross-section along the A1A2 direction;

[0051] Figure 5 This is a second top view schematic diagram of the crystal structure provided in an embodiment of the present invention;

[0052] Figure 6 for Figure 5 A schematic diagram of the cross-section along the A1A2 direction;

[0053] Figure 7 This is a schematic flowchart illustrating the method for fabricating a transistor structure according to an embodiment of the present invention. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] The terms "first," "second," etc., used in this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, without limiting the number of objects; for example, the first object can be one or more. Furthermore, "or" in this application indicates at least one of the connected objects. For example, "A or B" covers three scenarios: Scenario 1: including A but not B; Scenario 2: including B but not A; Scenario 3: including both A and B. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0056] In the technical solutions disclosed herein, terms such as “connection,” “coupling,” or “linking” are not limited to physical or mechanical connections, but may include electrical connections.

[0057] See Figure 1 and Figure 2 As shown, in existing GaN HEMT structures, the same dielectric layer 400 is often deposited in both the gate region and the drift region. The drift region roughly encompasses the area between the gate and source, and the area between the gate and drain. The gate region includes the gate itself, but may also include the area near the gate. Because of this identical dielectric layer 400, users cannot independently control the turn-off current in the gate region and the sheet resistance in the drift region of existing GaN HEMT structures. Specifically... Figure 2 In this context, L1 represents the length of the drift region between the gate and the source (i.e., Lgs); L2 represents the length of the drift region between the gate and the drain (i.e., Lgd).

[0058] This invention provides a transistor structure, see [link to relevant documentation]. Figure 3 and Figure 4 As shown, the transistor structure includes: a substrate 100, and a heterojunction layer and an electrode layer sequentially stacked on the substrate 100 in a direction away from the substrate 100; the electrode layer includes: a gate portion 1, a source portion 2, and a drain portion 3; the orthographic projection of the gate portion 1 on the substrate 100 is located between the orthographic projections of the adjacent source portion 2 on the substrate 100 and the orthographic projections of the drain portion 3 on the substrate 100; the transistor structure further includes:

[0059] The first dielectric layer 4 and the second dielectric layer 5 are coupled together, and both the first dielectric layer 4 and the second dielectric layer 5 are located on the side of the heterojunction layer that faces away from the substrate 100.

[0060] The orthographic projection of the second dielectric layer 5 on the substrate 100 is located between the orthographic projection of the adjacent gate portion 1 on the substrate 100 and the orthographic projection of the drain portion 3 on the substrate 100, and / or the orthographic projection of the second dielectric layer 5 on the substrate 100 is located between the orthographic projection of the adjacent gate portion 1 on the substrate 100 and the orthographic projection of the source portion 2 on the substrate 100.

[0061] At least a portion of the orthographic projection of the first dielectric layer 4 onto the substrate 100 is located between the orthographic projection of the adjacent gate portion 1 onto the substrate 100 and the orthographic projection of the second dielectric layer 5 onto the substrate 100.

[0062] The first dielectric layer 4 and the second dielectric layer 5 have different lattice constants.

[0063] In some embodiments of the present invention, the first dielectric layer 4 can be made of any of the following materials: SiN, SiO2; the second dielectric layer 5 can be made of any of the following materials: GaON, AlN, AlON, SiN, SiO2. It should be noted that when the first dielectric layer 4 and the second dielectric layer 5 are made of the same material, different material growth methods can be used to prepare the first dielectric layer 4 and the second dielectric layer 5, so that the first dielectric layer 4 and the second dielectric layer 5 have different material densities, thereby ensuring that the lattice constants of the first dielectric layer 4 and the second dielectric layer 5 are different.

[0064] It should be noted that the heterojunction layer includes a first heterojunction layer 200 and a second heterojunction layer 300 sequentially stacked on the substrate 100 along a direction away from the substrate 100. In some optional embodiments, the structural formula of the first heterojunction layer 200 is Al. y Ga (1-y) N, y = 0; the general structural formula of the second heterogeneous conjunctival layer 300 composition can be Al x Ga (1-x) N, 0.1 ≤ X ≤ 0.3. In this embodiment of the invention, the coupling between the first dielectric layer 4 and the second dielectric layer 5 is a non-detachable connection between the molecules of two heterojunction materials (except for destructive disassembly). At the interface where the first dielectric layer 4 and the second dielectric layer 5 meet, the different lattice constants of the first dielectric layer 4 and the second dielectric layer 5 affect the polarization intensity of the underlying heterojunction interface, ultimately changing the 2DEG concentration of the heterojunction below the first dielectric layer 4 and the second dielectric layer 5. This decouples the turn-off current and sheet resistance, allowing the user to independently control the turn-off current and sheet resistance of the transistor structure in this embodiment of the invention. In practical applications, the user can control the turn-off current and sheet resistance by adjusting the first dielectric layer 4 and / or the second dielectric layer 5.

[0065] In some embodiments of the present invention, see optionally, see Figure 3 As shown,

[0066] The first dielectric layer 4 includes a strip structure extending along the width of the channel, and the second dielectric layer 5 includes a strip structure extending along the width of the channel.

[0067] It should be noted that the channel width direction refers to the width direction of the channel formed by the transistor structure.

[0068] In this embodiment of the invention, the first dielectric layer 4 includes a strip structure extending along the channel width direction, and the second dielectric layer 5 includes a strip structure extending along the channel width direction, which reduces manufacturing difficulty and helps to reduce manufacturing costs. For example, when manufactured using photolithography, the first dielectric layer 4 and the second dielectric layer 5 both include strip structures extending along the channel width direction, eliminating the need for users to prepare masks with complex patterns, reducing process complexity and manufacturing difficulty; furthermore, the absence of complex patterns also improves the yield rate of manufacturing the first dielectric layer 4 and the second dielectric layer 5, which helps to reduce manufacturing costs.

[0069] In some embodiments of the present invention, see optionally, see Figure 5 and Figure 6 As shown,

[0070] The second dielectric layer 5 includes at least two second dielectric patterns 51 arranged along the channel width direction, and the first dielectric layer 4 includes a first portion 41 and at least one second portion 42 coupled to the first portion 41.

[0071] The orthographic projection of the first part 41 on the substrate 100 is located between the orthographic projection of the adjacent gate portion 1 on the substrate 100 and the orthographic projection of the second dielectric pattern 51 on the substrate 100.

[0072] The orthographic projection of the second part 42 on the substrate 100 and the orthographic projection of the second dielectric pattern 51 on the substrate 100 are alternately arranged.

[0073] In this embodiment of the invention, the above structure enables the user to precisely control the turn-off current of the transistor structure according to the actual use of the transistor (e.g., the turn-off current and sheet resistance required by the transistor structure determined by the actual use), by adjusting the width W2 of the second dielectric pattern 51 in the channel width direction and the spacing W1 between adjacent second dielectric patterns 51, and to achieve precise control of the sheet resistance, thus ensuring the flexibility and ease of use of the transistor structure of this embodiment of the invention.

[0074] In some embodiments of the present invention, see optionally, see Figure 5 and Figure 6 As shown,

[0075] The first dielectric layer 4 further includes a third portion 43 and / or a fourth portion 44, wherein the third portion 43 is coupled to the second dielectric layer 5 and the fourth portion 44 is coupled to the second dielectric layer 5.

[0076] The orthographic projection of the third part 43 on the substrate 100 is located between the orthographic projection of the adjacent source part 2 on the substrate 100 and the orthographic projection of the second dielectric layer 5 on the substrate 100.

[0077] The fourth part 44 is located between the orthographic projection of the adjacent drain portion 3 on the substrate 100 and the orthographic projection of the second dielectric layer 5 on the substrate 100.

[0078] In this embodiment of the invention, the third part 43 is coupled to the second dielectric layer 5 as a non-detachable connection between two heterogeneous material molecules (except for destructive disassembly). At the interface where the third part 43 and the second dielectric layer 5 meet, stress concentration occurs due to lattice distortion or dislocations caused by the difference in lattice constants between the first dielectric layer 4 and the second dielectric layer 5. In the gallium nitride transistor structure, stress concentration further increases the concentration of two-dimensional electron gas (2-DEG) at the interface, decoupling the transistor's turn-off current and sheet resistance. The transistor structure in this embodiment of the invention can achieve high turn-off current and low sheet resistance through user control.

[0079] Optionally, the fourth part 44 is coupled to the second dielectric layer 5 as a non-detachable connection between two heterogeneous material molecules (except for destructive disassembly). At the interface where the fourth part 44 and the second dielectric layer 5 meet, stress concentration occurs at the interface between the third part 43 and the second dielectric layer 5 due to lattice distortion or dislocations caused by the difference in lattice constants between the first dielectric layer 4 and the second dielectric layer 5. In the gallium nitride transistor structure, stress concentration further increases the concentration of two-dimensional electron gas (2-DEG) at the interface, decoupling the transistor's turn-off current and sheet resistance. The transistor structure of this embodiment can achieve high turn-off current and low sheet resistance through user control.

[0080] In some embodiments of the present invention, optionally, the transistor structure further includes: a gate, a source, and a drain; the gate includes at least two gate portions 1, the source includes at least two source portions 2, and the drain includes at least two drain portions 3; the orthographic projections of the source portions 2 on the substrate 100 and the orthographic projections of the drain portions 3 on the substrate 100 alternate, and there is an orthographic projection of the gate portion 1 on the substrate 100 between adjacent orthographic projections of the source portions 2 on the substrate 100 and the orthographic projections of the drain portions 3 on the substrate 100.

[0081] In some embodiments of the present invention, the gate portion 1 may optionally include a gate electrode 11 and a gate layer 12;

[0082] Gate layer 12 is located between heterojunction layer and gate electrode 11;

[0083] The orthographic projection of the gate layer 12 on the heterojunction layer at least partially overlaps with the orthographic projection of the gate electrode 11 on the heterojunction layer;

[0084] The gate layer 12 includes a p-type gallium nitride layer; specifically, the gate layer 14 may include a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V group layers. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd). The gate layer 14 is typically used to adjust the current flow and control the charge distribution.

[0085] The heterojunction layer includes a gallium nitride layer and an aluminum gallium nitride layer stacked together, with the gallium nitride layer located between the substrate and the aluminum gallium nitride layer.

[0086] Specifically, the heterojunction layer may include: a first nitride semiconductor layer and a second nitride semiconductor layer. The first nitride semiconductor layer may comprise a group III-V layer. The first nitride semiconductor layer may comprise, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b≤1. The group III nitride may further comprise, but is not limited to, the compound AlaGa(1-a)N, where a≤1. The first nitride semiconductor layer may comprise a gallium nitride (GaN) layer. The band gap of GaN is approximately 3.4 eV. The second nitride semiconductor layer may be disposed on the first nitride semiconductor layer, and its band gap is larger than that of the first nitride semiconductor layer. The second nitride semiconductor layer may comprise a group III-V layer. The second nitride semiconductor layer may comprise, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b≤1. The group III nitride may further comprise, but is not limited to, the compound AlaGa(1-a)N, where a≦1. The bandgap of the second nitride semiconductor layer can be greater than that of the first nitride semiconductor layer. The second nitride semiconductor layer may include an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is approximately 4.0 eV. A heterojunction can be formed between the second nitride semiconductor layer and the first nitride semiconductor layer, and the polarization of the heterojunction forms a two-dimensional electron gas (2DEG) region in the first nitride semiconductor layer.

[0087] In this embodiment of the invention, the transistor structure further includes:

[0088] The protective layer 6 is stacked on the electrode layer, covering the first dielectric layer 4 and the second dielectric layer 5.

[0089] This invention provides a method for fabricating a transistor structure, used to fabricate a transistor structure as described in any one of the embodiments of this invention. See also... Figure 7 As shown, the manufacturing method includes:

[0090] Step 11: Provide a substrate;

[0091] Step 12: Fabricate a heterojunction film layer on the substrate;

[0092] Step 13: Fabricate an electrode layer on the heterojunction layer; the electrode layer includes: a gate portion, a source portion and a drain portion; the orthographic projection of the gate portion on the substrate is located between the orthographic projection of the adjacent source portion on the substrate and the orthographic projection of the drain portion on the substrate.

[0093] Step 14: Fabricate a first dielectric layer and a second dielectric layer, both of which are located on the side of the heterojunction layer facing away from the substrate; the orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion and the drain portion on the substrate, and / or, the orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion and the source portion on the substrate; at least a portion of the orthographic projection of the first dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion and the second dielectric layer on the substrate; the lattice constants of the first dielectric layer and the second dielectric layer are different.

[0094] In this embodiment of the invention, the coupling between the first dielectric layer and the second dielectric layer is a non-detachable connection between two heterogeneous materials (except for destructive disassembly). At the interface between the first and second dielectric layers, stress concentration occurs due to lattice distortion or dislocations caused by the difference in lattice constants between the two dielectric layers. In the gallium nitride transistor structure, stress concentration further increases the concentration of two-dimensional electron gas (2-DEG) at the interface, decoupling the turn-off current and sheet resistance. Referring to the fabrication method of this embodiment, the user can obtain a transistor structure that can independently control the turn-off current and sheet resistance.

[0095] In some embodiments of the present invention, the manufacturing method may optionally further include:

[0096] Step a: Fabricate the dielectric material film layer;

[0097] Step b: A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask region and an opening region. The mask region corresponds to the region where the first dielectric layer is located, and the opening region corresponds to the region where the second dielectric layer is located.

[0098] Step c: Modify the dielectric material film layer at the corresponding position of the opening area to form a second dielectric layer.

[0099] In this embodiment of the invention, the specific process of modification treatment includes any one of the following: surface oxidation, surface nitriding, ion implantation, re-deposition by physical vapor deposition after etching, and re-deposition by chemical vapor deposition after etching.

[0100] In some embodiments of the present invention, the dielectric material film layer may optionally be fabricated using physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods.

[0101] In some embodiments of the present invention, optionally, a mask layer is formed on the side of the dielectric material film layer facing away from the substrate. This may specifically include: applying photoresist to the side of the dielectric material film layer facing away from the substrate, exposing through the mask layer, immersing the wafer in a developing solution, and finally forming a mask area and an opening area on the surface of the wafer.

[0102] In this embodiment of the invention, a second dielectric layer is formed directly on the original dielectric material through modification treatment, and the original dielectric material at the corresponding position of the mask area serves as the first dielectric layer. The process is simple and can be applied in large quantities at low cost.

[0103] In some embodiments of the present invention, the manufacturing method may optionally further include:

[0104] Step d: Fabricate the dielectric material film layer;

[0105] Step e: A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask region and an opening region. The mask region corresponds to the region where the first dielectric layer is located, and the opening region corresponds to the region where the second dielectric layer is located.

[0106] Step f: Using the mask layer as a mask, remove the dielectric material film layer exposed in the opening area to form a first dielectric layer; fabricate a second dielectric layer at the corresponding position in the opening area.

[0107] In some embodiments of the present invention, the dielectric material film layer may optionally be fabricated using physical vapor deposition (PVD) or chemical vapor deposition (CVD). In practical applications, a mask layer is formed on the side of the dielectric material film layer facing away from the substrate. Removing the dielectric material film layer exposed at the opening region can be achieved using photolithography, for example: coating the dielectric material film layer with photoresist, exposing the photoresist-coated dielectric material film layer, developing and hardening the exposed dielectric material layer, and then removing the dielectric material film layer exposed at the opening region using etching. The method for fabricating a second dielectric layer at the corresponding location of the opening region includes any of the following: chemical vapor deposition or phase deposition.

[0108] The embodiments of this application have been discussed in detail above. However, it should be understood that this application provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this application.

[0109] Unless otherwise specified, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper part,” “above,” and “below” are relative to the orientation indicated in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this application are not deviated from by such arrangements.

[0110] As used in this article, the term "vertical" refers to the upward and downward directions, while the term "horizontal" refers to the direction that is transverse to the vertical direction.

[0111] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples of events or situations that occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, "generally" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0112] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0113] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0114] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials generally indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10⁴ S / m (e.g., at least 10⁵ S / m or at least 10⁶ S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0115] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0116] While this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this application and actual equipment. Other embodiments of this application may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this application. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of this application.

[0117] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A transistor structure, characterized in that, include: A substrate, and a heterojunction layer and an electrode layer sequentially stacked on the substrate in a direction away from the substrate; the electrode layer includes: a gate portion, a source portion, and a drain portion; the orthographic projection of the gate portion on the substrate is located between the orthographic projections of the adjacent source portion and the drain portion on the substrate; the transistor structure further includes: A first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are coupled together, and both the first dielectric layer and the second dielectric layer are located on the side of the heterojunction film layer facing away from the substrate. The orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion on the substrate and the orthographic projections of the drain portion on the substrate, and / or, the orthographic projection of the second dielectric layer on the substrate is located between the orthographic projections of the adjacent gate portion on the substrate and the orthographic projections of the source portion on the substrate. At least a portion of the orthographic projection of the first dielectric layer on the substrate is located between the orthographic projection of the adjacent gate portion on the substrate and the orthographic projection of the second dielectric layer on the substrate. The first dielectric layer and the second dielectric layer have different lattice constants.

2. The transistor structure according to claim 1, characterized in that: The first dielectric layer includes a strip structure extending along the width direction of the channel, and the second dielectric layer includes a strip structure extending along the width direction of the channel.

3. The transistor structure according to claim 1, characterized in that: The second dielectric layer includes at least two second dielectric patterns arranged along the channel width direction, and the first dielectric layer includes a first portion and at least one second portion coupled to the first portion; The orthographic projection of the first portion on the substrate is located between the orthographic projection of the adjacent gate portion on the substrate and the orthographic projection of the second dielectric pattern on the substrate. The orthographic projection of the second portion on the substrate and the orthographic projection of the second dielectric pattern on the substrate are alternately arranged.

4. The transistor structure according to claim 1, characterized in that: The first dielectric layer further includes a third portion and / or a fourth portion, wherein the third portion is coupled to the second dielectric layer and the fourth portion is coupled to the second dielectric layer; The orthographic projection of the third portion on the substrate is located between the orthographic projection of the adjacent source portion on the substrate and the orthographic projection of the second dielectric layer on the substrate. The fourth portion lies between the orthographic projection of the adjacent drain portion onto the substrate and the orthographic projection of the second dielectric layer onto the substrate.

5. The transistor structure according to any one of claims 1 to 4, characterized in that, The transistor structure further includes: a gate, a source, and a drain; the gate includes at least two gate portions, the source includes at least two source portions, and the drain includes at least two drain portions; the orthographic projections of the source portions on the substrate and the orthographic projections of the drain portions on the substrate alternate, and there is an orthographic projection of the gate portion on the substrate between adjacent orthographic projections of the source portions on the substrate and the orthographic projections of the drain portions on the substrate.

6. The transistor structure according to claim 1, characterized in that, The gate portion further includes: a gate electrode and a gate layer; The gate layer is located between the heterojunction layer and the gate electrode; The orthographic projection of the gate layer on the heterojunction layer at least partially overlaps with the orthographic projection of the gate electrode on the heterojunction layer; The gate layer includes a P-type gallium nitride layer; The heterojunction film layer includes a gallium nitride layer and an aluminum gallium nitride layer stacked together, with the gallium nitride layer located between the substrate and the aluminum gallium nitride layer.

7. The transistor structure according to claim 1, characterized in that, The transistor structure also includes: A protective layer is stacked on the electrode layer, covering the first dielectric layer and the second dielectric layer.

8. A method for fabricating a transistor structure, characterized in that, The method for fabricating a transistor structure as described in any one of claims 1 to 7 includes: Provide a substrate; A heterojunction film layer is fabricated on the substrate. An electrode layer is fabricated on the heterojunction film layer; the electrode layer includes: a gate portion, a source portion, and a drain portion; the orthographic projection of the gate portion on the substrate is located between the orthographic projections of the adjacent source portion on the substrate and the orthographic projections of the drain portion on the substrate. A first dielectric layer and a second dielectric layer are fabricated, both located on the side of the heterojunction film layer facing away from the substrate. The orthographic projection of the second dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the drain portion on the substrate, and / or, the orthographic projection of the second dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the source portion on the substrate. At least a portion of the orthographic projection of the first dielectric layer on the substrate lies between the orthographic projections of the adjacent gate portion and the second dielectric layer on the substrate. The lattice constants of the first dielectric layer and the second dielectric layer are different.

9. The method for fabricating a transistor structure according to claim 8, characterized in that, The manufacturing method further includes: Fabrication of dielectric material films; A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask region and an opening region. The mask region corresponds to the region where the first dielectric layer is located, and the opening region corresponds to the region where the second dielectric layer is located. The dielectric material film layer at the location corresponding to the opening region is modified to form the second dielectric layer.

10. The method for fabricating a transistor structure according to claim 8, characterized in that, The manufacturing method further includes: Fabrication of dielectric material films; A mask layer is formed on the side of the dielectric material film layer facing away from the substrate. The mask layer has a mask area and an opening area. The mask area corresponds to the area where the first dielectric layer is located, and the opening area corresponds to the area where the second dielectric layer is located. Using the mask layer as a mask, the dielectric material film layer exposed in the opening area is removed to form a first dielectric layer; a second dielectric layer is then fabricated at the corresponding position in the opening area.

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