Dynamic word line allocation in memory systems

Abstract

Aspects of the present disclosure configure a memory subsystem controller to adaptively allocate word lines (WLs). The controller accesses reliability data for a set of primary WLs of a block of a set of memory components. The controller determines that one or more WLs in the set of primary WLs of the block are associated with respective reliability data that exceeds a threshold, and in response to determining that the one or more WLs are associated with the respective reliability data that exceeds the threshold, replaces the one or more WLs in the set of primary WLs of the block with one or more dummy WLs. The controller uses the one or more dummy WLs instead of the one or more WLs in the set of primary WLs of the block to program data into the block.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application Serial No. 63 / 440,834, filed on January 24, 2023, and U.S. Provisional Application Serial No. 63 / 443,841, filed on February 7, 2023, all of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to providing adaptive media management for memory components (eg, memory dies). Background Art

[0004] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. Memory components may include, for example, non-volatile memory components and volatile memory components. Generally speaking, a host system may utilize the memory subsystem to store data on and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0006] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 is a block diagram of an example media operations manager according to some embodiments of the present disclosure.

[0008] Figure 3 is a block diagram of an example page table according to some embodiments of the present disclosure.

[0009] Figure 4 and 5 is a flow chart of an example method for performing dynamic worldline (WL) allocation according to some embodiments of the present disclosure.

[0010] Figure 6 is a block diagram illustrating a pictorial representation of a machine in the form of a computer system within which a set of instructions may be executed, causing the machine to perform any one or more of the methodologies discussed herein, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure configure system components, such as a memory subsystem controller, to perform adaptive WL allocation operations. The memory subsystem controller may identify one or more WLs for a block with a reliability metric or data exceeding a threshold (e.g., WLs with poor data retention and poor reliability). Such WLs may be defective or nearing end-of-life (EOL). Rather than discarding a block to prevent further storage to the block, the controller may replace one or more WLs with dummy WLs (e.g., WLs not associated with any block used to store data during device manufacturing). These dummy WLs are physically located at the edge of a memory device or on an interface portion of the memory device and are typically associated with a shorter lifespan than primary WLs. Because such dummy WLs are typically less reliable than primary WLs, they are not associated with the storage of data when calculating memory device capacity. However, when one or more of a block's primary WLs reaches EOL or has poor data retention, such dummy WLs can be temporarily swapped in to avoid completely discarding the block (e.g., to avoid preventing storage to the block as a whole) and thereby extend the lifespan of the block and the memory device. This ensures that the performance of the memory system remains optimal and improves the overall efficiency of operating the memory subsystem.

[0012] The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system may utilize a memory subsystem that includes one or more memory components, such as memory devices (e.g., memory dies), that store data. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data at the memory subsystem and to read data from the memory subsystem. Data (or data sets) specified by the host are hereinafter referred to as "host data," "application data," or "user data."

[0013] The memory subsystem may initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a garbage collection management operation, the memory subsystem's firmware may overwrite previously written host data from a location on the memory device to a new location. The overwritten data (e.g., as initiated by the firmware) is referred to hereinafter as "garbage collection data." "User data" may include host data and garbage collection data. "System data," hereinafter, refers to data generated and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables), data from logs, temporary data, and the like.

[0014] Many different media management operations can be performed on a memory device. For example, media management operations may include different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near miss error correction (ECC), and / or different dynamic data refreshes. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget at the same time, rather than some blocks approaching it earlier. Read disturb management counts all read operations on the memory component. If a certain threshold is reached, the surrounding area is refreshed. Near miss ECC refreshes all data read by the application that exceeds a configured error threshold. Dynamic data refresh scans all data and identifies the error status of all blocks as a background operation. If a certain error threshold for each block or ECC unit is exceeded during this scan read, a refresh operation is triggered.

[0015] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is externally managed, for example, by an external controller. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0016] There are challenges in effectively managing or performing media management operations on typical memory devices. Specifically, certain memory devices, such as NAND flash devices, contain large die-to-die reliability (RWB) and block-to-block reliability variations. As the technology used for such memory devices continues to shrink, this die-to-die reliability and block-to-block reliability variation becomes more pronounced and problematic when performing memory management. Current memory systems (e.g., SSD drives or die packaging systems) associate all memory devices in the memory system with a certain reliability specification. In some cases, each block or WL of each memory device is associated with a reliability metric, measurement, data, grade, or specification that is used to determine whether the block or WL is good or bad. The reliability metric, measurement, data, grade, or specification can be set at the time of manufacturing or during operation of the memory device, for example, by measuring data retention and / or error rates associated with specific blocks and WLs.

[0017] During operation, cells / WLs within a block may become inoperative due to defects or general degradation and wear through program-erase cycles (PECs). Additionally, due to the physical characteristics of WLs, some WLs are more likely to suffer wear-out faster than others. Additionally, high-density quad-level cell (QLC) storage systems utilize a forced single-level cell (SLC) cache system. This system uses direct-to-SLC writes and then folds the SLC blocks into QLC blocks. A proper SSD design can consider the balance of SLC blocks and QLC blocks so that from a reliability perspective, blocks allocated for SLC cache do not reach end-of-life (EOL) before the QLC area reaches end-of-life (EOL). The forced SLC cache area can be very small compared to the QLC area because QLC blocks have a 4x higher density than SLC (4 bits per cell versus 1 bit per cell) and are used for system over-provisioning optimization. Therefore, the SLC area can be exposed to extremely high PEC counts compared to QLC blocks. Conventional QLC storage systems write host data directly to the SLC cache area before folding to QLC. Due to the 4:1 block density difference and the smaller number of blocks allocated to SLC, extremely high PEC requirements are placed on the SLC area. At SLC block EOL, block retirement due to cycling is driven by the set of weakest WLs, while some WLs are still able to meet data reliability requirements. Specifically, conventional systems may eventually retire blocks, thereby preventing further storage to such blocks too early (for example, when there may still be WLs and cells that can reliably store data). This degrades the quality of the memory device and reduces the storage capacity of such devices earlier than necessary. This results in wasted system resources and increased costs, as new memory devices may need to be obtained to replace memory devices that retire prematurely.

[0018] Typical memory devices have dummy WLs at the top, bottom, and center interfaces that are not used for data storage. Aspects of the present disclosure address the above and other deficiencies by utilizing dummy WLs to replace or augment WLs that are determined to have worse reliability than the other WLs of the block. Specifically, the disclosed controller switches out damaged / defective WLs or worn WLs with new dummy WLs to maintain the full functional capability of the block and reduce the incidence of poorly grown blocks. Moreover, when a block exceeds the PEC endurance rating, the disclosed controller can use the most capable WL in the SLC block (e.g., a WL with a reliability metric or data that meets a reliability threshold and is still capable of reliably storing data without reaching a threshold error rate). This enables a smaller SLC cache area (increased system overprovisioning) to improve system block management. In this way, the disclosed controller extends the PEC capability of an SLC block by using dummy WLs for data storage as a mechanism to improve reliability.

[0019] For example, a memory controller may collect reliability data for a set of primary word lines (WLs) of a block of a memory component and determine that one or more WLs in the set of primary WLs of the block are associated with corresponding reliability data exceeding a threshold value. In response to determining that the one or more WLs are associated with corresponding reliability data exceeding the threshold value, the memory controller replaces the one or more WLs in the set of primary WLs of the block with one or more dummy WLs and programs data into the block using the one or more dummy WLs instead of the one or more WLs in the set of primary WLs of the block.

[0020] In some examples, the reliability data includes an error rate associated with the set of primary WLs of the block. In some cases, the threshold value represents a tolerable error rate. In some examples, the memory controller determines that one or more WLs are associated with corresponding reliability data exceeding the threshold value by determining that the one or more WLs have failed a verify phase of a programming cycle. In some examples, the one or more WLs correspond to defective WLs.

[0021] In some examples, the one or more dummy WLs are selected from a set of WLs that are not initially mapped to any block of the set of memory components during manufacture of the memory subsystem. In some examples, the one or more dummy WLs are physically located at a top portion, a bottom portion, an edge portion, or an interface portion of the memory subsystem.

[0022] In some examples, the memory controller alternates between programming data into a block using one or more WLs associated with corresponding reliability data exceeding a threshold and programming data into the block using one or more dummy WLs. In some examples, the memory controller determines that the number of program-erase cycles of the one or more WLs corresponds to a criterion. In response to determining that the number of program-erase cycles of the one or more WLs corresponds to the criterion, the memory controller programs the data into the block using the one or more WLs. In some cases, in response to determining that the number of program-erase cycles of the one or more WLs fails to correspond to the criterion, the memory controller programs the data into the block using the one or more dummy WLs. In some examples, the criterion includes an even number or an odd number.

[0023] In some instances, the block corresponds to a single-level cell block. In some instances, the memory controller updates a page map that identifies the WLs of the block to include one or more dummy WLs. In some instances, the page map corresponds to a single-level cell (SLC) page map. In such cases, the memory controller updates a quad-level cell (QLC) page or block map that corresponds to the SLC page map. In some instances, the memory controller combines the remaining portions of the set of primary WLs for which corresponding reliability data fails to exceed a threshold to form individual SLC blocks, and generates a QLC block that includes a plurality of SLC blocks, the plurality of SLC blocks including the individual SLC blocks.

[0024] In some examples, the memory controller determines that the plurality of SLC blocks do not completely fill the QLC block in response to determining that the individual SLC blocks include a certain number of WLs that is less than the total number of WLs in the set of primary WLs. In response to determining that the QLC block is incompletely filled, the memory controller adds additional SLC blocks to the QLC block.

[0025] In some aspects, the memory controller determines that the plurality of SLC blocks incompletely fill the QLC block in response to determining that the individual SLC blocks include a certain number of WLs that is less than the total number of WLs in the set of primary WLs. In response to determining that the QLC block is incompletely filled, the memory controller adds dummy data to the incompletely filled portion of the QLC block.

[0026] Although various embodiments are described herein as being implemented with respect to a memory subsystem (eg, a controller of a memory subsystem), some or all portions of the embodiments may be implemented with respect to a host system (eg, a software application or operating system of a host system).

[0027] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some examples of the present disclosure is illustrated. Memory subsystem 110 may include media, such as memory components 112A-112N (hereinafter also referred to as "memory devices"). Memory components 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination of such memory devices. Memory components 112A-112N may be implemented by individual dies, such that first memory component 112A may be implemented by a first memory die (or a first set of memory dies) and second memory component 112N may be implemented by a second memory die (or a second set of memory dies).

[0028] In some examples, a first memory component 112A, a block, WL, or page of the first memory component 112A, or a group of memory components including the first memory component 112A may be associated with a reliability (capability) level, data, metric, value, or measurement. The terms "reliability level," "reliability metric," "reliability data," "reliability value," and "reliability measurement" are used interchangeably throughout and may have the same meaning. The reliability data may indicate whether the block, WL, or page of the first memory component 112A can reliably store or program data. In some cases, the reliability data may represent a bit error rate (BER) for the block, WL, or page of the first memory component 112A. In some cases, the reliability data may represent a current PEC count for the block, WL, or page of the first memory component 112A. In some examples, a memory or register may be associated with all of the memory components 112A-112N, which may store a table that maps different groups, bins, WLs, boxes, and / or sets of memory components 112A-112N to corresponding reliability data.

[0029] In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual inline memory modules (NVDIMMs).

[0030] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0031] Host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or any such computing device that includes memory and processing devices. Host system 120 may include or be coupled to memory subsystem 110, such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, and the like. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Express (NVMe) interface to access memory components 112A-112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 .

[0032] Memory components 112A-112N may include any combination of different types of nonvolatile memory components and / or volatile memory components. An example of a nonvolatile memory component includes NAND-type flash memory. Each of memory components 112A-112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a block) used by host system 120. Although nonvolatile memory components such as NAND-type flash memory are described, memory components 112A-112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A-112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of nonvolatile memory cells.

[0033] The memory subsystem controller 115 may communicate with the memory components 112A through 112N to perform memory operations, such as reading data, writing data, or erasing data at the memory components 112A through 112N, as well as other such operations. The memory subsystem controller 115 may communicate with the memory components 112A through 112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near miss ECC operations, and / or different dynamic data refreshes.

[0034] In some cases, the controller 115 may initially store or program data to multiple SLC blocks of the memory components 112A through 112N. Then, at a later time, the controller 115 may collapse the multiple SLC blocks (e.g., four blocks) to which the data was programmed into a single QLC memory block. Because a QLC block is programmed fewer times than an SLC block, the QLC block may be associated with a lower PEC count than an SLC block.

[0035] The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 that is configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory that is configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or a processor 117 or controller separate from the memory subsystem 110).

[0036] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. In some examples, the commands or operations received from the host system 120 may specify configuration data for the memory components 112A-112N. The configuration data may describe reliability levels associated with different groups of memory components 112N-112N and / or different blocks within each of the memory components 112N-112N. In some cases, the reliability levels are dynamic and may be updated by the memory subsystem controller 115 during operation of the memory subsystem 110 in response to determining that a certain error rate has been reached that exceeds an error rate threshold (e.g., a reliability threshold). For example, if a good WL begins to have an error rate that exceeds the reliability threshold, the good WL may become a bad WL. In such a case, the configuration data is updated, and any block stripes that include the now-bad WL are designated as short block stripes.

[0037] The memory subsystem controller 115 may be responsible for other memory management operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system 120 into command instructions to access the memory components 112A-112N, and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM or other temporary storage location or device) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0039] The memory device may be a raw memory device (e.g., NAND), which is managed externally by an external controller (e.g., memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., a local media controller) for memory management within the same memory device package. Any of the memory components 112A to 112N may include a media controller (e.g., media controller 113A and media controller 113N) to manage the memory cells of the memory component (e.g., to perform one or more memory management operations), communicate with the memory subsystem controller 115, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0040] The memory subsystem controller 115 may include a media operations manager 122. The media operations manager 122 may be configured to access reliability data for a set of primary WLs of a block of the set of memory components. The media operations manager 122 determines that one or more WLs in the set of primary WLs of the block are associated with corresponding reliability data exceeding a threshold, and in response to determining that the one or more WLs are associated with corresponding reliability data exceeding the threshold, replaces the one or more WLs in the set of primary WLs of the block with one or more dummy WLs. The media operations manager 122 uses the one or more dummy WLs instead of the one or more WLs in the set of primary WLs of the block to program data into the block.

[0041] Depending on the embodiment, the media operations manager 122 may include logic (e.g., a transient or non-transient set of machine instructions, such as firmware) or one or more components that enable the media operations manager 122 to perform the operations described herein. The media operations manager 122 may include tangible or non-tangible units capable of performing the operations described herein. Additional details regarding the operation of the media operations manager 122 are described below.

[0042] Figure 2 is an example media operations manager 200 (which represents Figure 1 As illustrated, the media operations manager 122 includes configuration data 220, a page table module 230, and a WL replacement module 240. For some embodiments, the media operations manager 122 may be configured to communicate with the server in a component or arrangement (e.g., fewer or more components). Figure 2 The differences described in .

[0043] Configuration data 220 is accessed and / or stored with Figure 1112N. In some examples, the configuration data 220 is programmed into the media operations manager 122. For example, the media operations manager 122 can communicate with the memory components 112A through 112N to obtain the configuration data and store the configuration data 220 locally on the media operations manager 122. In some examples, the media operations manager 122 communicates with the host system 120. The host system 120 receives input from an operator or user specifying parameters, including reliability levels for different bins, groups, blocks, WLs, indications of dummy WLs, block stripes, and / or sets of the memory components 112A through 112N. The media operations manager 122 receives the configuration data from the host system 120 and stores the configuration data in the configuration data 220.

[0044] In some examples, the media operations manager 122 performs one or more test operations on different WLs, groups, or blocks of the memory components 112A-112N. The test operations are configured to determine the reliability of each block of the memory components 112A-112N. Based on the results of the test operations, the media operations manager 122 may store or update the reliability levels stored in the configuration data 220 for the different groups or blocks of the memory components 112A-112N. In some examples, the media operations manager 122 may perform the test operations periodically or regularly.

[0045] For example, the media operations manager 122 may program data into a block containing multiple primary WLs. The media operations manager 122 may read the programmed data from the block to verify proper storage of the data. Based on the verification performed, the media operations manager 122 may identify one or more WLs in the primary WLs that have a defective or reliability metric or rating below a threshold. For example, the media operations manager 122 may determine that one or more WLs in the block's primary WLs are defective and / or have poor data retention and / or have an error rate that exceeds an error rate threshold. In such cases, the media operations manager 122 transmits the identification of these affected WLs to the WL replacement module 240. The WL replacement module 240 may then communicate with the page table module 230 to replace the affected WLs with one or more dummy WLs. This ensures that storage reliability of the block containing WLs with poor reliability measurements can be optimized by using dummy WLs instead of the affected primary WLs to store data.

[0046] In some examples, the media operations manager 122 alternates between programming data into a block using one or more WLs associated with corresponding reliability data exceeding a threshold and programming data into the block using one or more dummy WLs. Specifically, the media operations manager 122 may communicate with the configuration data 220 to determine the PEC counts of WLs having a reliability level below a threshold. In response to receiving a request to program data into a block containing WLs having a reliability level below a threshold, the media operations manager 122 may determine whether the PEC counts of the WLs of the block meet criteria. For example, the media operations manager 122 may determine whether the current PEC counts of the WLs are even. In response to determining that the PEC counts of the WLs are even, the media operations manager 122 may store or program data into the block using the primary WL containing the WLs having a reliability level below the threshold. For example, the media operations manager 122 may determine whether the current PEC counts of the WLs of the block meet criteria. In response to determining that the PEC count of the WL is odd (or not even), the media operations manager 122 may use the dummy WL instead of the primary WL whose reliability level is below the threshold to store or program data to the block. This reduces the number of PECs exposed to the primary WL using the dummy WL.

[0047] In some examples, the media operations manager 122 may perform a specified number (e.g., four) of PEC cycles on the primary WL. After performing the specified number of PEC cycles on the primary WL, the media operations manager 122 may then replace the primary WL with a dummy WL. In some cases, in addition to or in lieu of the specified number of PEC cycles, the media operations manager 122 may begin using the dummy WL after a threshold period of time has elapsed since the primary WL was used, and / or after a reliability threshold is reached, and / or when a PEC cycle threshold has been reached. After performing another number (e.g., one) of PEC cycles on the dummy WL, the media operations manager 122 returns to programming data on the primary WL until the specified number (e.g., four) of PEC cycles is reached.

[0048] In some cases, the criteria may correspond to a modulo operator rather than an even or odd number. In such cases, the media operations manager 122 may calculate the modulo of the current PEC of the primary WL and may selectively and alternately cycle between programming data to the block using the primary WL and programming data to the block using the dummy WL.

[0049] In some instances, for the weakest primary WL, the primary WL can be cycled to EOL and then a dummy WL (e.g., edge WL) can be used at EOL. This allows most primary WLs (which can have greater durability than the worst-case primary WL) to continue to be utilized without adversely affecting the size of the block. In some cases, a defect is encountered during normal system operation. System error handling and recovery may discover that only one or two WLs are affected by the defect. The media operations manager 122 can continue to use this block by skipping the defective WL and using the existing dummy WL instead, thereby preventing the creation of a new block and preserving critical over-provisioning on the system.

[0050] In some cases, the media operations manager 122 may determine that the number of primary WLs that have failed (e.g., have fallen below a reliability threshold) exceeds the number of available dummy WLs. In such cases, the media operations manager 122 may change the SLC page table or page mapping to reduce the number of WLs in the SLC block. In some cases, the media operations manager 122 may determine that all dummy WLs have been used and failures still exist in the SLC block. In such cases, the media operations manager 122 may change the SLC page table or page mapping to reduce the number of WLs in the SLC block.

[0051] In some examples, in order for the dummy WL to be properly erased and programmed, the bias applied to the dummy WL is changed to match the edge main WL bias.

[0052] For example, if Figure 3 As shown, Figure 2 The page table module 230 maintains two or more page tables, such as a QLC block table 320 (or MLC or TLC table) and an SLC page table 310. The QLC block table 320 identifies which SLC blocks are identified or correspond to a particular QLC block 322. Specifically, the QLC block 322 may correspond to or store data for multiple SLC blocks in the SLC page table 310.

[0053] The page table module 230 also maintains and tracks which WLs (e.g., rows in the SLC page table 310) of a given SLC block are used to form a given SLC block. The page address of each SLC block is displayed in the contents of each cell in the SLC page table 310. Shaded cells in the SLC page table 310 represent pages located on dummy WLs. Empty cells are represented by a '-' and may be dummy WLs that cannot be cycled or used as the selected WL. Cells with a '---' symbol represent additional WLs between the WLs of the SLC block.

[0054] For example, Figure 1The media operations manager 122 may select the dummy WL 318 or the main WL 312 at one point in time to store or program data for the SLC block. At another time, the media operations manager 122 may select one or more dummy WLs 314 and 316 to use in place of the dummy WL 318 and / or the main WL 312. The page table module 230 may also maintain or store a corresponding reliability level and a reliability threshold for each WL, and test or compare the reliability level of each main WL against the reliability threshold to determine whether to use a dummy WL to replace the main WL. Specifically, the media operations manager 122 may replace a dummy WL with another dummy WL and / or replace a main WL with a dummy WL.

[0055] In some instances, the media operations manager 122 combines a portion of the set of master WLs whose corresponding reliability levels exceed a threshold to form an individual SLC block. Specifically, the media operations manager 122 may identify which master WLs and / or dummy WLs of an individual SLC block are considered reliable (e.g., have a reliability level exceeding a threshold or have an error rate below a threshold error rate). The media operations manager 122 may then select the slave SLC block based on the identified master WLs and / or dummy WLs, which may be smaller than the set of master WLs pre-associated with the SLC block during manufacturing. In some cases, the WLs used to form an SLC block are smaller than the specified number used to form other SLC blocks. In such cases, when such an SLC block is combined with other SLC blocks having a specified number of WLs, and when these combined SLC blocks are folded into a QLC block, the corresponding QLC block is incompletely populated.

[0056] In such cases, the media operations manager 122 determines that the plurality of SLC blocks do not completely fill the QLC block in response to determining that the individual SLC blocks include a certain number of WLs that is less than the total number of WLs in the set of primary WLs. In response to determining that the QLC block is incompletely filled, the media operations manager 122 identifies the WLs of the additional SLC blocks to be added to the QLC block.

[0057] In some examples, the media operations manager 122 determines that the plurality of SLC blocks incompletely fills the QLC block in response to determining that the individual SLC blocks include a number of WLs that is less than the total number of WLs in the set of primary WLs. In response to determining that the QLC block is incompletely filled, the media operations manager 122 adds dummy data to the incompletely filled portion of the QLC block.

[0058] Figure 4is a flow chart of an example method 400 for adaptively allocating WLs of a block according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The processes are executed by the media operations manager 122. Although the processes are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0059] Now refer to Figure 4 , the method (or process) 400 begins at operation 405, where the media operations manager 122 of the memory subsystem (e.g., memory subsystem 110) accesses reliability data for a set of primary WLs of a block of the set of memory components. Then, at operation 410, the media operations manager 122 of the memory subsystem determines that one or more WLs in the set of primary WLs of the block are associated with corresponding reliability data that exceeds a threshold. Thereafter, at operation 415, the media operations manager 122 replaces one or more WLs in the set of primary WLs of the block with one or more dummy WLs in response to determining that the one or more WLs are associated with corresponding reliability data that exceeds the threshold. The media operations manager 122 uses the one or more dummy WLs instead of the one or more WLs in the set of primary WLs of the block to program data into the block at operation 420.

[0060] Figure 5 is a flow chart of an example method 50 for adaptively allocating WLs of a block according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The processes are executed by the media operations manager 122. Although the processes are shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0061] Now refer to Figure 5 , the method (or process) 500 begins at operation 505, where the media operations manager 122 of the memory subsystem (e.g., memory subsystem 110) identifies a subset of the WLs of individual SLC blocks that can reliably store data. At operation 510, the media operations manager 122 combines the individual SLC blocks and multiple SLC blocks into a QLC block, and at operation 515, determines whether the QLC block is fully filled or partially filled. If the QLC block is partially filled, then at operation 520, the media operations manager 122 fills the remaining portion of the QLC block (which is not filled) with dummy data. Additionally or alternatively, at operation 525, the media operations manager 122 identifies (e.g., calculates) additional WLs for one or more SLC blocks to add to the QLC block to fully fill the QLC block.

[0062] In view of the above disclosure, various examples are described below. It should be noted that one or more features of the examples taken independently or in combination should be considered to be within the disclosure of this application.

[0063] Example 1. A system comprising: a set of memory components of a memory subsystem; and a processing device operably coupled to the set of memory components, the processing device configured to perform operations including: accessing reliability data for a set of main word lines (WLs) of a block of the set of memory components; determining that one or more WLs in the set of main WLs of the block are associated with corresponding reliability data that exceeds a threshold; in response to determining that the one or more WLs are associated with the corresponding reliability data that exceeds the threshold, replacing the one or more WLs in the set of main WLs of the block with one or more dummy WLs; and programming data into the block using the one or more dummy WLs instead of the one or more WLs in the set of main WLs of the block.

[0064] Example 2. The system of example 1, wherein the reliability data comprises an error rate associated with the set of primary WLs of the block.

[0065] Example 3. The system of example 2, wherein the threshold represents a tolerable error rate.

[0066] Example 4. The system of any of examples 1 to 3, wherein determining that the one or more WLs are associated with corresponding reliability data that exceeds the threshold comprises determining that the one or more WLs have failed a verify phase of a programming cycle.

[0067] Example 5. The system of example 4, wherein the one or more WLs correspond to defective WLs.

[0068] Example 6. The system of any of examples 1 to 5, wherein the one or more dummy WLs are selected from a set of WLs that are not initially mapped to any blocks of the set of memory components during manufacture of the memory subsystem.

[0069] Example 7. The system of example 6, wherein the one or more dummy WLs are physically located at a top portion, a bottom portion, an edge portion, or an interface portion of the memory subsystem.

[0070] Example 8. The system of any of Examples 1 to 7, the operations comprising: alternatingly cycling between programming data to the block using the one or more WLs associated with corresponding reliability data exceeding the threshold and programming data to the block using the one or more dummy WLs.

[0071] Example 9. The system of Example 8, wherein the operations include: determining that a number of program-erase cycles of the one or more WLs corresponds to a criterion; and in response to determining that the number of program-erase cycles of the one or more WLs corresponds to the criterion, programming the data to the block using the one or more WLs.

[0072] Example 10. The system of example 9, the operations comprising, in response to determining that the number of program-erase cycles of the one or more WLs fails to correspond to the criterion, programming the data to the block using the one or more dummy WLs.

[0073] Example 11. The system of any of Examples 9-10, wherein the criteria include at least one of an even WL; an odd WL; a threshold number of program cycles being executed; an elapsed usage time; a reliability threshold being reached; or a specified number of program-erase cycles being reached.

[0074] Example 12. The system of any one of Examples 1 to 11, wherein the block corresponds to a single-level unit block.

[0075] Example 13. The system of any of examples 1 to 12, the operations comprising updating a page map identifying WLs of the block to include the one or more dummy WLs.

[0076] Example 14. The system of example 13, wherein the page map corresponds to a single-level cell (SLC) page map, the operation comprising updating a quad-level cell (QLC) page or block table corresponding to the SLC page map.

[0077] Example 15. The system of Example 14, wherein the operations include: combining the remaining portions of the set of master WLs whose corresponding reliability data fails to exceed the threshold to form an individual SLC block; and generating a QLC block comprising a plurality of SLC blocks, the plurality of SLC blocks including the individual SLC block.

[0078] Example 16. The system of example 15, the operations comprising determining that the plurality of SLC blocks do not completely fill the QLC block in response to determining that the individual SLC block includes a number of WLs that is less than a total number of WLs in the set of primary WLs.

[0079] Example 17. The system of example 16, the operations comprising: in response to determining that the QLC block is incompletely filled, adding an additional SLC block to the QLC block.

[0080] Example 18. The system of any one of Example 17, the operations comprising: determining that the plurality of SLC blocks do not completely fill the QLC block in response to determining that the individual SLC block includes a certain number of WLs that is less than the total number of WLs in the set of primary WLs; and adding dummy data to the incompletely filled portion of the QLC block in response to determining that the QLC block is incompletely filled.

[0081] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0082] Figure 6 An example machine is illustrated in the form of a computer system 600 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a server or a client machine in a peer-to-peer (or distributed) network environment.

[0083] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0084] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0085] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, processing device 602 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0086] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution of the instructions by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0087] In one embodiment, instructions 626 implement the instructions corresponding to Figure 1The functionality of the media operations manager 122 is provided. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0088] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing are most effectively able to convey the substance of their work to others skilled in the art. In this document, and generally, an algorithm is conceived as a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0089] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memories and transforms it into other data represented in a similar manner as physical quantities within the computer system's memories or registers or other such information storage systems.

[0090] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), each coupled to a computer system bus; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards; or any type of medium suitable for storing electronic instructions.

[0091] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods. The structures for various such systems will be presented as set forth in the description above. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0092] The present disclosure may be provided in the form of a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0093] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: A set of memory components of a memory subsystem; as well as a processing device operatively coupled to the set of memory components, the processing device configured to perform operations comprising: accessing reliability data for a set of primary word lines (WLs) of a block of the set of memory components; determining that one or more WLs in the set of primary WLs for the block are associated with corresponding reliability data that exceeds a threshold; responsive to determining that the one or more WLs are associated with the corresponding reliability data exceeding the threshold, replacing the one or more WLs in the set of primary WLs of the block with one or more dummy WLs; as well as Data is programmed into the block using the one or more dummy WLs instead of the one or more WLs in the set of main WLs for the block. 2 . The system of claim 1 , wherein the reliability data comprises an error rate associated with the set of primary WLs of the block. The system according to claim 2 , wherein the threshold value represents a tolerable error rate.

4. The system of claim 1 , wherein determining that the one or more WLs are associated with corresponding reliability data exceeding the threshold comprises: It is determined that the one or more WLs failed a verify phase of a program cycle. The system of claim 4 , wherein the one or more WLs correspond to defective WLs.

6. The system of claim 1, wherein the one or more dummy WLs are selected from a set of WLs that are not initially mapped into any blocks of the set of memory components during manufacture of the memory subsystem. 7 . The system of claim 6 , wherein the one or more dummy WLs are physically located at a top portion, a bottom portion, an edge portion, or a center interface portion of the memory subsystem.

8. The system of claim 1, wherein the operations comprise: Alternating cycles are cycled between programming data to the block using the one or more WLs associated with respective reliability data exceeding the threshold and programming data to the block using the one or more dummy WLs.

9. The system of claim 8, wherein the operations comprise: determining that a number of program-erase cycles of the one or more WLs corresponds to a criterion; as well as In response to determining that the number of program-erase cycles of the one or more WLs corresponds to the criterion, programming the data to the block using the one or more WLs.

10. The system of claim 9, wherein the operations comprise: In response to determining that the number of program-erase cycles of the one or more WLs fails to correspond to the criterion, programming the data to the block using the one or more dummy WLs.

11. The system of claim 9, wherein the criteria include at least one of: Even WL; odd WL; a threshold number of programming cycles being executed; elapsed time of use; Reaching a reliability threshold; or Reach the specified number of program-erase cycles.

12. The system of claim 1, wherein the block corresponds to a single-level unit block.

13. The system of claim 1, wherein the operations comprise: A page map identifying the WLs of the block is updated to include the one or more dummy WLs.

14. The system of claim 13 , wherein the page map corresponds to a single-level cell (SLC) page map, the operations comprising: A quad-level cell (QLC) block table corresponding to the SLC page mapping is updated.

15. The system of claim 14, wherein the operations comprise: combining remaining portions of the set of primary WLs whose corresponding reliability data fail to exceed the threshold to form individual SLC blocks; as well as A QLC block is generated that includes a plurality of SLC blocks including the individual SLC block.

16. The system of claim 15, wherein the operations comprise: The plurality of SLC blocks is determined to not completely fill the QLC block in response to determining that the individual SLC block includes a number of WLs that is less than the total number of WLs in the set of primary WLs.

17. The system of claim 16, wherein the operations comprise: In response to determining that the QLC block is incompletely filled, one or more WLs of additional SLC blocks are identified for inclusion in the QLC block.

18. The system of claim 17, wherein the operations comprise: determining that the plurality of SLC blocks do not completely fill the QLC block in response to determining that the individual SLC block includes a number of WLs that is less than a total number of WLs in the set of primary WLs; as well as In response to determining that the QLC block is incompletely filled, dummy data is added to the incompletely filled portion of the QLC block.

19. A method comprising: accessing reliability data for a set of primary word lines (WLs) of a block of a set of memory components; determining that one or more WLs in the set of primary WLs for the block are associated with corresponding reliability data that exceeds a threshold; responsive to determining that the one or more WLs are associated with the corresponding reliability data exceeding the threshold, replacing the one or more WLs in the set of primary WLs of the block with one or more dummy WLs; as well as Data is programmed into the block using the one or more dummy WLs instead of the one or more WLs in the set of main WLs for the block.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: accessing reliability data for a set of primary word lines (WLs) of a block of a set of memory components; determining that one or more WLs in the set of primary WLs for the block are associated with corresponding reliability data that exceeds a threshold; In response to determining that the one or more WLs are associated with the corresponding reliability data that exceeds the threshold, replacing the one or more WLs in the set of primary WLs of the block with one or more dummy WLs; and Data is programmed into the block using the one or more dummy WLs instead of the one or more WLs in the set of main WLs for the block.

Images