Chip, preparation method thereof and infrared light field generation device

Abstract

The invention provides a chip and a preparation method thereof and an infrared light field generation device, the chip comprises at least one pixel, the pixel comprises a heat insulation layer and a nanometer forest absorption structure, the nanometer forest absorption structure is arranged on one side of the heat insulation layer along a first direction, the nanometer forest absorption structure comprises a nanometer forest structure and a light absorption layer, and the nanometer forest structure is arranged on the other side of the heat insulation layer along the first direction. The nanometer forest structure is connected with the heat insulation layer, the nanometer forest structure and the heat insulation layer are made of the same material, the light absorption layer covers the outer surface of the nanometer forest structure, and the nanometer forest absorption structure is constructed to absorb light energy of incident light and generate infrared light. The chip provided by the invention is good in light absorption performance, and is not liable to cause a thermal stress mismatch problem.

Description

Technical Field

[0001] The present application relates to the technical field of infrared light field generating devices, and in particular to a chip and a preparation method thereof, and an infrared light field generating device. Background Art

[0002] The chip of the infrared scene generation device can generate infrared radiation based on the principle of photothermal conversion, so that the infrared scene generation device can provide a real-time infrared image source for the infrared detection system, which can be used to test the infrared detection system's ability to detect, identify and track targets.

[0003] In related technologies, a chip includes multiple basic pixels, each of which includes a thermal insulation layer and a radiation absorption layer. The thermal insulation layer is made of a material with low thermal conductivity to improve its thermal insulation, while the radiation absorption layer is made of a material with high absorptivity to increase its absorption of incident light. When the overall temperature of the basic pixel rises, the significant difference in thermal conductivity between the thermal insulation and absorption layers can easily lead to thermal stress mismatch, resulting in separation of the radiation absorption layer from the thermal insulation layer. Summary of the Invention

[0004] Based on this, the present application provides a chip and a preparation method thereof, and an infrared light field generating device to address the deficiencies in the related art.

[0005] In a first aspect, the present application provides a chip, comprising:

[0006] At least one pixel, the pixel includes:

[0007] thermal insulation;

[0008] a nano-forest absorption structure, the nano-forest absorption structure being disposed on one side of the heat-insulating layer along the first direction, the nano-forest absorption structure being configured to absorb light energy of incident light and generate infrared light;

[0009] The nanoforest absorption structure includes a nanoforest structure and a light-absorbing layer. The nanoforest structure is connected to the heat-insulating layer. The nanoforest structure and the heat-insulating layer are made of the same material. The light-absorbing layer covers the outer surface of the nanoforest structure.

[0010] In a possible implementation, the thermal conductivity k of the heat insulation layer satisfies: k<1 W / m·K.

[0011] In one possible implementation, the nanoforest structure and the thermal insulation layer are integrally formed.

[0012] In a possible implementation, the chip further includes a support layer and a substrate, and the nanoforest absorption structure, the heat insulation layer, the support layer and the substrate are stacked and connected in sequence along a first direction.

[0013] In a possible implementation, the material of the nanoforest structure includes polyimide or photoresist.

[0014] In a possible implementation, the material of the light absorption layer includes at least one of gold, silver, chromium, aluminum, and a carbon-based material.

[0015] In one possible implementation, the nanoforest structure includes several substructures, which are arranged at intervals, and the shapes of the substructures include at least one of columnar, conical, linear and fibrous; the several substructures are all connected to the thermal insulation layer, and the light-absorbing layer covers the outer surface of the substructure.

[0016] In a possible implementation, the distance G between two adjacent substructures satisfies: 0.01 μm ≤ G ≤ 1 μm, and / or;

[0017] A height H of the substructure in the first direction satisfies: 0.5 μm ≤ H ≤ 10 μm, and / or;

[0018] The substructure is cylindrical or conical, and the diameter D of the substructure satisfies: 0.05 μm≤D≤1 μm.

[0019] In a possible implementation, the thickness T1 of the heat insulation layer in the first direction satisfies: 0.02 μm≤T1≤2 μm.

[0020] In a possible implementation, the thickness T2 of the light absorption layer satisfies: 50 nm ≤ T2 ≤ 500 nm.

[0021] In a second aspect, the present application provides a chip preparation method for preparing the chip provided in the first aspect above, the preparation method comprising:

[0022] coating a first material on a substrate to form a first film layer on one side of the substrate;

[0023] Etching the first film layer to form a heat insulation layer on a side of the first film layer facing the substrate, and forming a nano-forest structure on a side of the first film layer facing away from the substrate;

[0024] A second material is deposited on the outer surface of the nano-forest structure to form a light-absorbing layer on the outer surface of the nano-forest structure.

[0025] In a possible implementation, a first material is coated on a substrate to form a first film layer on one side of the substrate, and then the method further includes:

[0026] A photoresist is coated on the first film layer to form a photoresist layer on a side of the first film layer facing away from the substrate.

[0027] In a possible implementation, the chip further includes a support layer;

[0028] Before coating the substrate with a first material to form a first film layer on one side of the substrate, the method further includes:

[0029] depositing a third material on the substrate to form a second film layer between the substrate and the first film layer;

[0030] The second film layer is etched to form a supporting layer.

[0031] In one possible implementation, before coating the substrate with the first material to form a first film layer on one side of the substrate, the method further includes:

[0032] coating the substrate with a fourth material to form a sacrificial layer between the substrate and the first film layer;

[0033] Depositing a second material on the outer surface of the nano-forest structure to form a light-absorbing layer on the outer surface of the nano-forest structure, and then further comprising:

[0034] The sacrificial layer is removed to separate the thermal insulation layer from the substrate.

[0035] In a third aspect, the present application provides an infrared light field generating device, comprising the chip provided in the first aspect above, or comprising a chip manufactured using the chip manufacturing method provided in the second aspect above.

[0036] The present application provides a chip, a preparation method thereof, and an infrared light field generating device. The chip includes a pixel, and the pixel includes a heat insulation layer and a nanoforest absorption structure. The nanoforest absorption structure can be used to absorb incident light and generate infrared light, and the heat insulation layer is used to reduce the heat loss of the chip. Among them, the nanoforest absorption structure includes a nanoforest structure and a light absorption layer. The light absorption layer has a high extinction coefficient and can be used to absorb incident light and generate infrared light. Since the light absorption layer covers the outer surface of the nanoforest structure, the structural morphology of the nanoforest structure can increase the surface area of ​​the nanoforest absorption structure, and make the incident light repeatedly reflected and absorbed in the nanoforest absorption structure, thereby improving the absorbance of the nanoforest absorption structure. Since the thermal conductivity of the heat insulation layer is low, it is beneficial to reduce the heat loss of the pixel during operation to prevent the rapid dissipation of heat, thereby helping to improve the working efficiency of the chip. And since the nanoforest structure and the heat insulation layer are made of the same material, the thermal conductivity of the two can be guaranteed to be consistent, and thus when the overall temperature of the chip rises, it can effectively prevent problems such as thermal stress mismatch leading to separation of the nanoforest structure and the heat insulation layer. In this way, the chip provided by the present application has good light absorption performance and is not prone to thermal stress mismatch problems.

[0037] In addition to the technical problems solved by the embodiments of the present application described above, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions, other technical problems that can be solved by the chip and its preparation method and the infrared light field generating device provided by the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 A schematic diagram of the structure of the chip provided in the embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a suspended film chip provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a three-dimensional support chip provided in an embodiment of the present application;

[0042] Figure 4 This is another structural diagram of the suspended film chip provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the process flow of a suspended film chip provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of the process flow of a three-dimensional support chip provided in an embodiment of the present application;

[0045] Figure 7 Schematic diagram of the chip preparation method provided in the embodiment of the present application Figure 1 ;

[0046] Figure 8 Schematic diagram of the chip preparation method provided in the embodiment of the present application Figure 2 ;

[0047] Figure 9 Schematic diagram of the chip preparation method provided in the embodiment of the present application Figure 3 .

[0048] Description of reference numerals:

[0049] 100-pixel;

[0050] 110- thermal insulation layer;

[0051] 120-nanometer forest absorption structure; 121-nanometer forest structure;

[0052] 200-substrate;

[0053] 300-support layer; 310-hollow portion;

[0054] 400-first film layer;

[0055] 500-second film layer;

[0056] 600-photoresist layer;

[0057] 700-Sacrificial layer;

[0058] X - first direction. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0060] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to a fixed connection, an indirect connection via an intermediate medium, internal communication between two components, or an interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.

[0061] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are orientations or positional relationships based on the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0062] The terms "first," "second," and "third" (if any) in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the application described herein can, for example, be implemented in an order other than that illustrated or described herein.

[0063] In addition, the terms "comprises" and "having" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or display that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product or display.

[0064] In related art, the chip of an infrared scene generation device includes multiple basic pixels, each of which includes a thermal insulation layer and a radiation absorption layer. The thermal insulation layer is made of a material with low thermal conductivity to improve its thermal insulation rate, and the radiation absorption layer is made of a material with high absorptivity to increase its absorption rate of incident light. When the overall temperature of the basic pixel rises, due to the significant difference in thermal conductivity between the thermal insulation layer and the absorption layer, the thermal insulation layer and the absorption layer expand at different rates, causing stress at the interface between the two. This can easily lead to thermal stress mismatch, which can cause the radiation absorption layer to separate from the thermal insulation layer.

[0065] Based on this, the present application provides a chip, a preparation method thereof, and an infrared light field generating device. The absorption layer and the nanoforest structure are made of the same material with low thermal conductivity to prevent the chip from having thermal stress mismatch problems when the chip temperature rises. The nanoforest structure cooperates with the light-absorbing layer to effectively improve the absorption rate of the nanoforest absorption structure. In this way, the chip can have better light absorption and avoid the problem of thermal stress mismatch.

[0066] The specific implementation of the chip and its manufacturing method and the infrared light field generating device provided in this embodiment are described in detail below with reference to the accompanying drawings.

[0067] Reference Figure 1 As shown, the infrared light field generating device provided in the embodiment of the present application includes a chip, which is used to absorb the light energy of the incident light and radiate infrared light, so that the infrared light field generating device can provide an infrared light source for infrared detection systems such as infrared sensors and infrared detectors, thereby detecting the ability of the infrared detection system to detect, identify and track targets.

[0068] In addition, the infrared light field generating device may further include a light source, which may provide incident light for the chip. For example, the light source may be a laser, which may provide visible light laser for the chip.

[0069] Reference Figures 1 to 5 As shown, based on the above embodiment, the embodiment of the present application further provides a chip, the chip includes at least one pixel 100, the pixel 100 includes a heat insulation layer 110 and a nano forest absorption structure 120, the nano forest absorption structure 120 is arranged along the first direction (the first direction is the thickness direction of the heat insulation layer 110, refer to Figure 1 On one side of the nanoforest structure 120 (in the X direction), the nanoforest absorption structure 120 includes a nanoforest structure 121 and a light absorbing layer. The nanoforest structure 121 is connected to the thermal insulation layer 110. The nanoforest structure 121 and the thermal insulation layer 110 are made of the same material. The light absorbing layer covers the outer surface of the nanoforest structure 121. The light absorbing layer is constructed to absorb the light energy of the incident light and generate infrared light.

[0070] The thermal conductivity k of the nanoforest structure 121 satisfies: k<1 W / m·K.

[0071] It is understood that the chip provided in the embodiment of the present application can generate infrared light based on the principle of photothermal conversion, wherein the chip can include a plurality of pixel elements 100 in an array, and the specific number of pixel elements 100 is not limited here, for example Figure 4 The diagram illustrates an array of three rows and three columns of pixel elements 100. Pixel elements 100 incorporate nanoforest absorption structures 120 to absorb incident light energy, converting it into heat energy based on the photothermal conversion effect. Thermal insulation layer 110 enables the pattern design of pixel elements 100, preventing rapid heat dissipation and concentrating more energy on generating infrared light, thereby improving the efficiency of pixel elements 100. When the temperature of pixel elements 100 rises, they spontaneously radiate infrared light.

[0072] In this way, when the input of pixel 100 is a writing light scene with a spatial intensity distribution, each pixel 100 can absorb different amounts of writing light intensity, and then radiate a corresponding infrared scene with a spatial intensity distribution, thereby completing the conversion and generation from the visible light field to the infrared light field.

[0073] Specifically, nanoforest absorption structure 120 may include a nanoforest structure 121 and a light-absorbing layer. Nanoforest structure 121 is a material form composed of densely arranged nanoscale columnar, conical, or linear structures. Nanoforest structure 121 has a large surface area. When the light-absorbing layer covers the outer surface of nanoforest structure 121, it can increase the surface area of ​​the light-absorbing layer, thereby improving the light-absorbing layer's absorptivity. Furthermore, after incident light enters nanoforest absorption structure 120, the multiple columnar, conical, or linear structures formed by nanoforest structure 121 can cause the incident light to be reflected and absorbed back and forth within nanoforest absorption structure 120, making it less likely to be reflected away, thereby effectively improving the absorptivity of the light-absorbing layer. Thus, the nanoforest absorption structure 120 provided in the present embodiment has excellent light absorption performance.

[0074] It is understandable that when the light absorbing layer covers the outer surface of the nano-forest structure 121 , the nano-forest absorbing structure 120 also presents a forest morphology with multiple columnar, conical or linear structures densely arranged.

[0075] Since the nanoforest structure 121 and the thermal insulation layer 110 are made of the same material, and the thermal conductivity of the thermal insulation layer 110 and the nanoforest structure 121 are both less than 1 W / m·K, the thermal conductivity of the thermal insulation layer 110 and the nanoforest structure 121 is low and consistent. In this way, the thermal conductivity of the thermal insulation layer 110 can be ensured to be low, which is beneficial to reducing heat loss. When the overall temperature of the chip rises, since the thermal conductivity of the thermal insulation layer 110 and the nanoforest structure 121 is consistent, it can effectively prevent the separation of the nanoforest structure 121 and the thermal insulation layer 110 due to thermal stress mismatch, as well as warping and cracking of the nanoforest structure 121.

[0076] The chip provided in this embodiment includes a pixel 100, which includes a thermal insulation layer 110 and a nanoforest absorption structure 120. The nanoforest absorption structure 120 includes a nanoforest structure 121 and a light-absorbing layer. The light-absorbing layer can be used to absorb incident light and generate infrared light. Because the light-absorbing layer covers the outer surface of the nanoforest structure 121, the structural morphology of the nanoforest structure 121 can increase the surface area of ​​the nanoforest absorption structure 120 and cause the incident light to be repeatedly reflected and absorbed within the nanoforest absorption structure 120, thereby increasing the light absorption rate of the nanoforest absorption structure 120. Since the thermal insulation layer 110 has a low thermal conductivity, it is beneficial to reduce heat loss during operation of the pixel 100, thereby improving the operating efficiency of the chip. Moreover, because the nanoforest structure 121 and the thermal insulation layer 110 are made of the same material, the thermal conductivity of the two can be guaranteed to be consistent. Therefore, when the overall temperature of the chip rises, it can effectively prevent problems such as thermal stress mismatch leading to separation of the nanoforest structure 121 and the thermal insulation layer 110. As such, the chip provided in the embodiment of the present application has good light absorption performance and is less likely to have thermal stress mismatch problems.

[0077] Reference Figure 4 As shown, it should be noted that the heat insulation layer 110 can also be provided with a hollow portion 310 to reduce thermal crosstalk between the multiple pixels 100.

[0078] In some embodiments, the nanoforest structure 121 and the thermal insulation layer 110 are integrally formed. For example, a plasma etching process can be used to form the nanoforest structure 121 and the thermal insulation layer 110. In this way, the nanoforest structure 121 and the thermal insulation layer 110 can be integrally formed, thereby simplifying the chip manufacturing process and reducing chip manufacturing costs.

[0079] Reference Figure 3 and Figure 6 As shown, in a possible implementation, the chip further includes a support layer 300 and a substrate 200, and the nanoforest absorption structure 120, the heat insulation layer 110, the support layer 300 and the substrate 200 are stacked and connected in sequence along a first direction.

[0080] That is, the chip of this embodiment can be a suspended film chip or a three-dimensional support chip. When the chip is a suspended film chip, the chip can include a thermal insulation layer 110 and a nanoforest absorption structure 120. When the chip is a three-dimensional support chip, the chip can also include a substrate 200 and a support layer 300. The support layer 300 can support multiple pixels 100 on the substrate 200.

[0081] Among them, the support layer 300 can be in a columnar shape, a micro-groove shape, a micro-cavity shape, a micro-bridge shape, etc., and by controlling parameters such as the thickness and gap of the support layer 300, the heat conduction can be controlled. For example, the thicker the support layer 300 is, the more difficult it is for the heat of the pixel 100 to be conducted to the substrate 200, and the thinner the thickness of the support layer 300 is, the easier it is for the heat of the pixel 100 to be conducted to the substrate 200.

[0082] In a possible implementation, the material of the nano-forest structure 121 includes polyimide or photoresist.

[0083] It should be understood that polyimide or photoresist has a low thermal conductivity, which can improve the thermal insulation performance of the thermal insulation layer 110. Polyimide or photoresist can be processed into a nanoforest structure 121 through a plasma etching process. Moreover, after polyimide or photoresist is processed into a nanoforest structure 121, a light-absorbing material is deposited on the surface of the nanoforest structure 121 to form a light-absorbing layer, which can effectively improve the light-absorbing properties of the nanoforest absorption structure 120.

[0084] In a possible implementation, the material of the light absorbing layer includes one or more of gold, silver, chromium, aluminum, and carbon-based materials.

[0085] It should be noted that gold, silver, chromium, aluminum, and carbon-based materials have higher absorption coefficients within the visible light range, allowing the light-absorbing layer to absorb more visible light and generate infrared light. For example, within the visible light range of 400 to 500 nanometers, the extinction coefficient of gold is between 2 and 3, and within the visible light range of 500 to 600 nanometers, the extinction coefficient of gold is between 1 and 2. This effectively increases the visible light absorption rate of the nanoforest absorption structure 120.

[0086] In one possible implementation, the nanoforest structure 121 includes several substructures, each spaced apart and shaped like at least one of a column, a cone, a line, and a fiber. Each substructure is connected to the thermal insulation layer 110, and a light-absorbing layer covers the outer surface of each substructure.

[0087] It should be understood that the nanoforest structure 121 is a material form composed of densely arranged nanoscale columnar, conical, linear or fibrous structures. The nanoforest structure 121 can include multiple columnar, conical, linear and fibrous substructures. In this way, the nanoforest absorption structure 120 can present a forest-like structural form, and can make light reflect back and forth between multiple substructures, so that the light absorption layer can repeatedly absorb light.

[0088] It can be understood that when the nanoforest structure 121 is made of a material with low thermal conductivity such as polyimide, in order to make the chip's absorption rate of visible light reach more than 90%, in the specific setting, the distance G between two adjacent substructures satisfies: 0.01μm≤G≤1μm, the height H of the substructure in the first direction satisfies: 0.5μm≤H≤10μm, and when the substructure is cylindrical or conical, the diameter D of the substructure satisfies: 0.05μm≤D≤1μm.

[0089] In this way, multiple substructures can form a uniform, spaced-apart nanoforest structure 121 on one side of the thermal insulation layer 110, so as to effectively increase the surface area of ​​the nanoforest absorption structure 120 and ensure that the incident light is reflected and absorbed back and forth within the nanoforest absorption structure 120, thereby ensuring that the absorption rate of the nanoforest absorption structure 120 for visible light reaches more than 90%.

[0090] In some embodiments, the thickness T1 of the thermal insulation layer 110 in the first direction satisfies the following relationship: 0.02 μm ≤ T1 ≤ 2 μm. This allows the thermal insulation layer 110 to have a certain thickness, thereby enabling the thermal insulation layer 110 to reduce heat loss from the nanoforest absorption structure 120 without excessively increasing the volume of the pixel 100.

[0091] It is understood that the light-absorbing layer needs to evenly cover the surface of the nanoforest structure 121 to effectively absorb incident light. Furthermore, the thickness of the light-absorbing layer should not be too great to prevent the nanoforest structure 121 from being filled after the light-absorbing layer is formed on the surface of the nanoforest structure 121. This would prevent the nanoforest absorption structure 120 from ultimately presenting a forest-like morphology, which would affect the nanoforest absorption structure 120's absorption of incident light. Therefore, in one possible implementation, the thickness T2 of the light-absorbing layer satisfies the following conditions: 50nm ≤ T2 ≤ 500nm. This effectively improves the absorption rate of the nanoforest absorption structure 120 to incident light.

[0092] Based on the above embodiments, the embodiments of the present application also provide a chip preparation method for preparing the chip provided by the above embodiments, wherein the chip includes one or more pixel elements 100, the pixel element 100 includes a thermal insulation layer 110 and a nanoforest absorption structure 120, and the nanoforest absorption structure 120 includes a nanoforest structure 121 and a light absorption layer.

[0093] Reference Figures 5 to 7 Specifically, the preparation method provided in the embodiment of the present application includes:

[0094] S101 , coating a first material on a substrate 200 to form a first film layer 400 on one side of the substrate 200 .

[0095] S102 , etching the first film layer 400 to form a heat insulation layer 110 on a side of the first film layer 400 facing the substrate 200 , and forming a nanoforest structure 121 on a side of the first film layer 400 facing away from the substrate 200 .

[0096] S103 , depositing a second material on the outer surface of the nano-forest structure 121 to form a light-absorbing layer on the outer surface of the nano-forest structure 121 .

[0097] In this way, by plasma etching the first film layer 400, the thermal insulation layer 110 and the nanoforest structure 121 can be formed in one process, thereby simplifying the chip manufacturing process and reducing chip manufacturing costs. A second material is then deposited on the outer surface of the nanoforest structure 121 to form a light-absorbing layer. The light-absorbing layer and the nanoforest structure 121 together constitute the nanoforest absorption structure 120.

[0098] The first material may be a material with low thermal conductivity such as polyimide or photoresist, and the second material may be a material with high extinction coefficient such as gold, silver, chromium, aluminum and carbon-based materials.

[0099] The substrate 200 can be made of one of silicon, silicon oxide, diamond, sapphire, and silicon carbide, and this embodiment does not impose any specific restrictions on this. Before preparation, the substrate 200 can be cleaned with an RCA cleaning solution to remove impurity particles and metal ions on the substrate 200. The RCA cleaning solution can be a mixed solution of H2O2, NH4OH, and H2O.

[0100] Reference Figures 5 and 6 As shown, in a possible implementation, S101, coating a first material on a substrate 200 to form a first film layer 400 on one side of the substrate 200, and then further comprising;

[0101] S104 , coating the first film layer 400 with photoresist to form a photoresist layer 600 on a side of the first film layer 400 facing away from the substrate 200 .

[0102] When non-photosensitive polyimide is used as the first material, a photoresist layer 600 is formed on the first film layer 400 to facilitate etching of the first film layer 400 to form the nanoforest structure 121. Thus, after the first film layer 400 is formed on the substrate 200, the photoresist layer 600 is formed on the first film layer 400. Then, the photolithography and development processes are completed. The first film layer 400 is etched using the photoresist layer 600 as a mask, and the pattern of the photoresist layer 600 is transferred to the first film layer 400. The first film layer 400 is then processed into the nanoforest structure 121 and the thermal insulation layer 110. If photosensitive polyimide is used as the first material, the photolithography and development processes can be performed directly on the first film layer 400, without the need for additional preparation of the photoresist layer 600.

[0103] Reference Figure 6 and Figure 9 As shown, in a possible implementation, the chip further includes a support layer 300;

[0104] S101, coating a first material on a substrate 200 to form a first film layer 400 on one side of the substrate 200, before which the process further includes:

[0105] S105 , depositing a third material on the substrate 200 to form a second film layer 500 between the substrate 200 and the first film layer 400 .

[0106] S106 , etching the second film layer 500 to form the support layer 300 .

[0107] In this way, the photoresist layer 600 and the first film layer 400 can be used as masks to etch out the support layer 300, thereby processing a three-dimensional support chip.

[0108] Reference Figure 5 and Figure 8As shown, in a possible implementation, S101, coating a first material on a substrate 200 to form a first film layer 400 on one side of the substrate 200, before that, the process further includes:

[0109] S107 , coating the substrate 200 with a fourth material to form a sacrificial layer 700 between the substrate 200 and the first film layer 400 .

[0110] S103, depositing a second material on the outer surface of the nano-forest structure 121 to form a light-absorbing layer on the outer surface of the nano-forest structure 121, and then further comprising:

[0111] S108 , removing the sacrificial layer 700 to separate the thermal insulation layer 110 from the substrate 200 .

[0112] Thus, after the heat-insulating layer 110 and the nano-forest absorption structure 120 are manufactured, the sacrificial layer 700 can be removed to obtain a suspended film chip separated from the substrate 200. The fourth material can be silicon oxide.

[0113] For example, the sacrificial layer 700 may be immersed in a first solution, and the sacrificial layer 700 may be removed after the sacrificial layer 700 reacts with the first solution, wherein the first solution may be a hydrofluoric acid buffer solution.

[0114] Alternatively, the sacrificial layer 700 may be removed by dry etching or etching, which is not limited in the embodiment of the present application.

[0115] Reference Figure 6 and Figure 9 As shown, the preparation process of the three-dimensional support chip is described in detail below.

[0116] 1. Clean the four-inch silicon wafer substrate 200 using the RCA standard cleaning method to remove impurity particles and metal ions on the substrate 200.

[0117] Second, a silicon oxide layer is deposited on substrate 200 using chemical vapor deposition as second film layer 500. Specifically, tetraethyl orthosilicate is used as a precursor, and deposition is performed in a process chamber at a temperature of 650-850°C, with argon or nitrogen as the carrier gas and a chamber pressure of 1-100 Torr. The reaction time is controlled to obtain a 6 μm thick silicon oxide layer.

[0118] Third, the first film layer 400 was prepared on the second film layer 500 using a spin coating method. Specifically, a polyimide solution was pre-mixed with a silane coupling agent, with the silane coupling agent accounting for 5%-30%. An appropriate amount of the prepared solution was then dripped onto the center of the substrate 200. The pre-spin coating speed was 800 rpm for 10 seconds, and the main spin coating speed was 3000 rpm for 60 seconds. After spin coating, the substrate 200 was placed on a 100°C hotplate and baked for 10 minutes to complete the thermal curing, resulting in a polyimide layer approximately 5 μm thick.

[0119] Fourth, prepare a photoresist layer 600 on the first film layer 400. Specifically, a suitable amount of photoresist is dropwise applied to the center of the substrate 200. For example, an S1813 positive photoresist is used. The pre-spin coating speed is 800 rpm for 10 seconds, and the main spin coating speed is 4000 rpm for 60 seconds. After spin coating, the substrate is placed on a 115°C hotplate for 3 minutes to complete the thermal curing process. A UV exposure system is then used to perform the exposure process. An alkaline developer is then used to remove the exposed area, completing the development process.

[0120] 5. Using the photoresist layer 600 as a mask, the first film layer 400 is etched to transfer the pattern of the photoresist layer 600 to the first film layer 400. Specifically, the polyimide layer is dry-etched using an ICP (Inductively Coupled Plasma) or RIE (Reactive Ion Etching) etching process, using oxygen and / or sulfur hexafluoride as etching gases. The etching rate can be controlled by controlling the gas flow rate, chamber pressure, and RF power. The chamber pressure is 5-10 Pa, and the RF power is 200-300 W. When the pattern of the polyimide layer is completely consistent with that of the photoresist layer 600, the etching process is complete.

[0121] 6. Using the photoresist layer 600 as a mask, the second film layer 500 is etched. Specifically, the silicon oxide layer is dry-etched using ICP or RIE equipment, using carbon tetrafluoride or hexafluoroethane as the etching gas. The etching rate can be controlled by adjusting the gas flow rate, chamber pressure, temperature, and radio frequency power. The chamber pressure is 5-10 Pa, and the radio frequency power is 100-200 W. After the silicon oxide layer is etched laterally by approximately 9 μm and longitudinally by approximately 6 μm, a columnar support layer 300 with a height of approximately 6 μm and a width of approximately 2 μm is formed.

[0122] 7. Removing the photoresist layer 600. Immerse the silicon wafer substrate 200 in an acetone solution. When the photoresist and acetone react sufficiently, take out the silicon wafer substrate 200 and place it on a hot plate at 90°C for 5 minutes to dry out the moisture.

[0123] 8. A plasma etching process is used to etch the first film layer 400 into a nanoforest structure 121. Specifically, RIE equipment is used to perform plasma etching on the polyimide layer. The etching rate can be controlled by adjusting the gas flow rate, chamber pressure, and radio frequency power. The chamber pressure is 1-10 mTorr, and the radio frequency power is 150-250 W. Oxygen is first used as an etching gas with a flow rate of 20-60 sccm to etch the polyimide layer until a nanoforest structure 121 with a height of approximately 4.5 μm is formed. Argon is then used as an etching gas with a flow rate of 10-30 sccm to bombard the polyimide layer until the diameter of the nanowires reaches 100-1000 nm. In this way, the side of the first film layer 400 facing away from the substrate 200 is processed to form the nanoforest structure 121, while the side of the first film layer 400 facing away from the substrate 200 retains a relatively complete film layer structure, which is the thermal insulation layer 110.

[0124] 9. Prepare a light-absorbing layer on the nano-forest structure 121. Specifically, use PVD (Physical Vapor Deposition) equipment to sputter gold nanoparticles onto the surface of the nano-forest structure 121. The sputtering rate can be controlled by controlling the gas flow rate, chamber pressure, and radio frequency power. The chamber pressure is 5-10 Pa, the radio frequency power is 50-100 W, and the target material is 99.99% pure gold. A gold light-absorbing layer with a thickness of 50-100 nm is sputtered. Once the light-absorbing layer is prepared, the three-dimensional support chip is completed.

[0125] Reference Figure 5 and Figure 8 As shown, the preparation process of the suspended film chip is described in detail below.

[0126] 1. Clean the four-inch silicon wafer substrate 200 using the RCA standard cleaning method to remove impurity particles and metal ions on the substrate 200.

[0127] Second, a silicon oxide layer is deposited on substrate 200 using chemical vapor deposition as sacrificial layer 700. Specifically, tetraethyl orthosilicate is used as a precursor and deposition is performed in a process chamber at a temperature of 650-850°C, with argon or nitrogen as the carrier gas and a chamber pressure of 1-100 Torr. The reaction time is controlled to obtain a 400 nm thick silicon oxide layer.

[0128] Third, the first film layer 400 was prepared on the second film layer 500 using a spin coating method. Specifically, a polyimide solution was pre-mixed with a silane coupling agent, with the silane coupling agent accounting for 5%-30%. An appropriate amount of the prepared solution was then dripped onto the center of the substrate 200. The pre-spin coating speed was 800 rpm for 10 seconds, and the main spin coating speed was 3000 rpm for 60 seconds. After spin coating, the substrate 200 was placed on a 100°C hotplate and baked for 10 minutes to complete the thermal curing, resulting in a polyimide layer approximately 5 μm thick.

[0129] Fourth, a photoresist layer 600 was prepared on the first film layer 400. Specifically, an appropriate amount of photoresist was dropwise applied to the center of the substrate 200. S1813 positive photoresist was used. The pre-spin coating speed was 800 rpm for 10 seconds, and the main spin coating speed was 4000 rpm for 60 seconds. After spin coating, the substrate was placed on a 115°C hotplate for 3 minutes to complete the thermal curing process. A UV exposure system was used for the exposure process. The exposed areas were removed with an alkaline developer, and the development process was completed.

[0130] Fifth, using the photoresist layer 600 as a mask, the first film layer 400 is etched to transfer the pattern of the photoresist layer 600 to the first film layer 400. Specifically, the polyimide layer is dry-etched using an ICP or RIE device, using oxygen and / or sulfur hexafluoride as the etching gas. The etching rate can be controlled by controlling the gas flow rate, the intracavity pressure, and the radio frequency power. The intracavity pressure is 5-10 Pa, and the radio frequency power is 200-300 W. When the pattern of the polyimide layer is completely consistent with that of the photoresist layer 600, the etching process is complete.

[0131] 6. Removing the photoresist layer 600: Soak the silicon wafer substrate 200 in an acetone solution. After the photoresist and acetone react sufficiently, take out the silicon wafer substrate 200 and place it on a hot plate at 90°C for 5 minutes to dry out the moisture.

[0132] 7. A plasma etching process is used to etch the first film layer 400 into a nano-forest structure 121. Specifically, an RIE device is used to perform plasma etching on the polyimide layer. The etching rate can be controlled by adjusting the gas flow rate, the gas pressure in the chamber, and the radio frequency power. The gas pressure in the chamber is 1-10 mTorr, and the radio frequency power is 150-250W. First, oxygen is used as an etching gas with a flow rate of 20-60 sccm to etch the polyimide layer until a nano-forest structure 121 with a height of approximately 4.5 μm is formed. Then, argon is used as an etching gas with a flow rate of 10-30 sccm to bombard the polyimide layer until the diameter of the nanowire reaches 100-1000 nm. In this way, the side of the polyimide layer facing away from the substrate 200 is processed to form the nano-forest structure 121, and the side of the polyimide layer facing away from the substrate 200 retains a relatively complete film structure, which is the thermal insulation layer 110.

[0133] 8. Prepare a light-absorbing layer on the nanoforest structure 121. Specifically, gold nanoparticles are sputtered onto the surface of the nanoforest structure 121 using PVD. The sputtering rate can be controlled by controlling the gas flow rate, the intracavity pressure, and the radio frequency power. The intracavity pressure is 5-10 Pa, the radio frequency power is 50-100 W, the target material is 99.99% pure gold, and the sputtered gold light-absorbing layer has a thickness of 50-100 nm.

[0134] 9. Removing the sacrificial layer 700 from the substrate 200. Specifically, the silicon wafer substrate 200 is immersed in a hydrofluoric acid buffer solution. After the sacrificial layer 700 and the hydrofluoric acid have completely reacted, the thermal insulation layer 110 and the nanoforest absorption structure 120 are released from the substrate 200. The structure is then lifted up using a custom-made support ring and air-dried, completing the preparation of the suspended film chip.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip, characterized in that: include: At least one pixel (100), the pixel (100) comprising: thermal insulation layer (110); a nano-forest absorption structure (120), the nano-forest absorption structure (120) being arranged on one side of the heat-insulating layer (110) along a first direction, the nano-forest absorption structure (120) being configured to absorb light energy of incident light and generate infrared light; The nanoforest absorption structure (120) comprises a nanoforest structure (121) and a light absorption layer. The nanoforest structure (121) is connected to the heat insulation layer (110). The nanoforest structure (121) and the heat insulation layer (110) are made of the same material. The light absorption layer covers the outer surface of the nanoforest structure (121).

2. The chip according to claim 1, characterized in that The thermal conductivity k of the heat insulation layer (110) satisfies: k<1W / m·K.

3. The chip according to claim 1, characterized in that The nano forest structure (121) and the thermal insulation layer (110) are integrally formed.

4. The chip according to claim 1, characterized in that It also includes a substrate (200) and a support layer (300), wherein the nano forest absorption structure (120), the heat insulation layer (110), the support layer (300) and the substrate (200) are sequentially stacked and connected along the first direction.

5. The chip according to claim 1, characterized in that The material of the nano forest structure (121) includes polyimide or photoresist.

6. The chip according to claim 1, characterized in that The material of the light absorption layer includes at least one of gold, silver, chromium, aluminum and carbon-based materials.

7. The chip according to any one of claims 1 to 6, characterized in that: The nanoforest structure (121) includes a plurality of substructures, the plurality of substructures are spaced apart, and the shapes of the substructures include at least one of columnar, conical, linear, and fibrous shapes; the plurality of substructures are connected to the heat insulation layer (110), and the light absorption layer covers the outer surface of the substructure.

8. The chip according to claim 7, characterized in that The distance G between two adjacent substructures satisfies: 0.01 μm ≤ G ≤ 1 μm, and / or; The height H of the substructure in the first direction satisfies: 0.5 μm ≤ H ≤ 10 μm, and / or; The substructure is cylindrical or conical, and the diameter D of the substructure satisfies: 0.05 μm≤D≤1 μm.

9. The chip according to any one of claims 1 to 6, characterized in that: The thickness T1 of the heat insulation layer (110) in the first direction satisfies: 0.02 μm≤T1≤2 μm.

10. The chip according to any one of claims 1 to 6, characterized in that: The thickness T2 of the light absorbing layer satisfies: 50nm≤T2≤500nm.

11. A chip preparation method for preparing the chip according to any one of claims 1 to 10, characterized in that: The preparation method comprises: coating a first material on a substrate (200) to form a first film layer (400) on one side of the substrate (200); Etching the first film layer (400) to form a heat insulation layer (110) on a side of the first film layer (400) facing the substrate (200), and forming a nano forest structure (121) on a side of the first film layer (400) facing away from the substrate (200); A second material is deposited on the outer surface of the nanoforest structure (121) to form a light absorption layer on the outer surface of the nanoforest structure (121).

12. The chip preparation method according to claim 11, characterized in that: A first material is coated on a substrate (200) to form a first film layer (400) on one side of the substrate (200), and thereafter, the method further comprises: Photoresist is coated on the first film layer (400) to form a photoresist layer (600) on a side of the first film layer (400) facing away from the substrate (200).

13. The chip preparation method according to claim 11 or 12, characterized in that: The chip further comprises a supporting layer (300); Before coating a substrate (200) with a first material to form a first film layer (400) on one side of the substrate (200), the method further includes: depositing a third material on the substrate (200) to form a second film layer (500) between the substrate (200) and the first film layer (400); The second film layer (500) is etched to form the support layer (300).

14. The chip preparation method according to claim 11 or 12, characterized in that: Before coating a substrate (200) with a first material to form a first film layer (400) on one side of the substrate (200), the method further includes: coating the substrate (200) with a fourth material to form a sacrificial layer (700) between the substrate (200) and the first film layer (400); Depositing a second material on the outer surface of the nanoforest structure (121) to form a light absorbing layer on the outer surface of the nanoforest structure (121), and then further comprising: The sacrificial layer (700) is removed to separate the thermal insulation layer (110) from the substrate (200).

15. An infrared light field generating device, characterized in that: The chip comprises the chip according to any one of claims 1 to 10, or the chip manufactured by the chip manufacturing method according to any one of claims 11 to 14.

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