Data ordering method for tensor processor, tensor processor system, and medium

Abstract

The application provides a data sorting method for a tensor processor, a tensor processor system and a medium, and relates to the technical field of data processing. The method comprises the following steps: obtaining input data and the storage capacity of a single tensor processor (TPU) register, and allocating a core id for marking the initial position of each element; when the data volume of the input data is less than or equal to the storage capacity of the single TPU register, performing a single-register-level sorting operation to obtain a double-tune sequence of a single register; otherwise, performing double-tune sorting recursive division on the input data to obtain multiple sub-sequences, performing a single-register-level sorting operation on each sub-sequence respectively, and merging the sorted sub-sequences to obtain a double-tune sequence of multiple registers; wherein, the core id of the elements is transmitted when the single-register-level sorting operation on each sub-sequence is performed and the sub-sequences are merged; and the order of equal elements is adjusted according to the core id after the double-tune sequence is obtained. The application can improve the stability of the data sorting result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to a data sorting method for a tensor processor, a tensor processor system and a medium. BACKGROUND

[0002] The demand for efficient and stable parallel sorting algorithms is increasingly urgent in the current big data processing field, especially in scenarios such as deep learning that require tensor processing units (TPUs) for acceleration. TPU chips have a significant advantage in processing matrix operations due to their highly parallel architecture and instruction set design oriented towards vector calculations, but their instruction set lacks native support for single-element comparison and exchange operations in traditional sorting algorithms, which prevents classic algorithms such as quicksort and mergesort from being directly ported.

[0003] Dual tuning sorting is an efficient parallel sorting algorithm suitable for sorting networks. It can simply implement parallel computing by constructing multiple comparators, which is theoretically suitable for TPU platforms, but traditional dual tuning sorting algorithms do not guarantee the stability of sorting, i.e., the relative order of equal elements may change before and after sorting. For example, in database sorting, if two records have the same sorting key but different other attributes (such as timestamps, IDs, etc.), if the sorting algorithm cannot guarantee stability, it may cause the order of these records to change, affecting the accuracy of query results. Therefore, a solution is needed to ensure the stability of sorting. SUMMARY

[0004] The embodiments of the present application provide a data sorting method for a tensor processor, a tensor processor system and a medium to solve the problem of improving sorting stability.

[0005] In a first aspect, the embodiments of the present application provide a data sorting method for a tensor processor, comprising:

[0006] Obtaining the storage capacity of input data and a single TPU register, and allocating a core id marking the initial position for each element in the input data;

[0007] When the data volume of the input data is less than or equal to the storage capacity of a single TPU register, performing a single register level sorting operation to obtain a dual tuning sequence of a single register;

[0008] When the data amount of the input data is greater than the storage capacity of a single TPU register, the input data is recursively divided into multiple subsequences by double sorting, the single register level sorting operation is performed on each subsequence, and the sorted subsequences are merged to obtain a double sorted sequence of multiple registers; wherein, the core id of the element is transmitted when the single register level sorting operation is performed on each subsequence and the sorted subsequences are merged.

[0009] After obtaining the double sorted sequence, the order of equal elements is adjusted according to the core id.

[0010] In a possible implementation, the single register level sorting operation includes:

[0011] The data is separated into two registers according to odd bits and even bits by using a mask instruction;

[0012] The Max floating point instruction and the Min floating point instruction in the vector instruction set of the TPU are used to compare the elements at the corresponding positions in the two registers, and the larger value and the smaller value are stored in the max register and the min register, respectively;

[0013] The select instruction is used in combination with the mask operation to make the max register only retain the odd bit elements and the min register only retain the even bit elements, and the elements of the two registers are merged to form a double sorted sequence.

[0014] In a possible implementation, the merging of the sorted subsequences includes:

[0015] The elements of the two subsequences are sequentially exchanged according to the double sorting logic;

[0016] The Max floating point instruction and the Min floating point instruction in the vector instruction set of the TPU are used to compare the elements at the same positions in the two subsequences, and the larger value and the smaller value are stored in the max register and the min register, respectively;

[0017] The single register level sorting operation is performed on the elements in the max register and the min register, respectively, to obtain a double sorted sequence of the max register and a double sorted sequence of the min register.

[0018] In a possible implementation, the sequentially exchanging of the elements of the two subsequences according to the double sorting logic includes:

[0019] The elements of the two subsequences are sequentially exchanged to obtain an increasing subsequence and a decreasing subsequence.

[0020] In a possible implementation, the double sorting and recursive partitioning of the input data into multiple subsequences comprises:

[0021] The double sorting and recursive partitioning of the input data into subsequences is performed until the length of each subsequence is less than or equal to a set length; and the set length is equal to the storage capacity of a single TPU register.

[0022] In a possible implementation, before the double sorting and recursive partitioning of the input data into multiple subsequences, the method further comprises:

[0023] The input data is divided into blocks with a power-of-2 size.

[0024] When there is a block with a length less than the set length, the input data is padded to the set length.

[0025] A core id marking the initial position of each element in the padded input data is assigned.

[0026] In a possible implementation, after the order of equal elements is adjusted according to the core id, the method further comprises:

[0027] The padded values in the input data are removed according to the core id.

[0028] In a possible implementation, the order of equal elements is adjusted according to the core id, and the method comprises:

[0029] It is determined whether the core id order of equal elements is consistent with the original order.

[0030] When the determination result is inconsistent, the positions of equal elements are exchanged according to the core id.

[0031] In a second aspect, an embodiment of the present application provides a tensor processor system, comprising: a plurality of TPU registers, a vector instruction execution module, and a core id management module.

[0032] The storage capacities of the TPU registers are the same.

[0033] The core id management module is configured to assign a core id marking the initial position of each element in input data.

[0034] The vector instruction execution module is configured to execute the method in the first aspect or any possible implementation of the first aspect.

[0035] In a third aspect, the embodiments of the present application provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the method in the first aspect or any possible implementation manner of the first aspect.

[0036] In the embodiments of the present application, single register processing or recursive partitioning and merging is used according to the size of the data amount, the parallel processing capability of the TPU is fully utilized, and the sorting efficiency is improved. By recursively dividing the large data set into small blocks suitable for TPU register processing, and using the vector instructions of the TPU for parallel comparison and exchange, the double tuning sorting algorithm can be efficiently implemented on the TPU. By assigning a core id to each element and passing the core id during the sorting process, the instability problem of the traditional double tuning sorting algorithm is solved, so that the original order of equal elements can be maintained after sorting. Finally, the order of equal elements is adjusted according to the core id, further ensuring the stability of the sorting, thereby meeting the demand for stable sorting in application scenarios such as databases. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is an implementation flowchart of the data sorting method for the tensor processor provided by the embodiments of the present application;

[0038] Figure 2 is a structural schematic diagram of the tensor processor system provided by the embodiments of the present application. DETAILED DESCRIPTION

[0039] Sorting is one of the basic problems in computer science and is widely used in various data processing and analysis tasks. With the advent of the era of big data, higher requirements are placed on the efficiency, stability and parallelism of sorting algorithms. TPU is a processor designed for deep learning and other tasks, which has strong parallel computing capability, but due to its instruction set mainly facing vector operations, the direct application of traditional sorting algorithms on TPU is limited.

[0040] Double tuning sorting is an efficient parallel sorting algorithm suitable for sorting networks. It can simply implement parallel computing by constructing multiple comparators. The key to double tuning sorting is to construct a double tuning sequence, i.e. the elements in a sequence are first arranged in ascending order, and then start to decrease after a certain specific index. By recursively dividing and merging the double tuning sequence, an ordered sequence can be finally obtained. However, the traditional double tuning sorting algorithm does not guarantee the stability of the sorting, i.e. the relative order of equal elements may change before and after sorting. Some research schemes are provided for applying the double tuning sorting algorithm on TPU, which are implemented in the following ways:

[0041] 1. Vector instruction adaptation: Since the instruction set of TPU is mainly designed for vector operations, these schemes try to convert the comparison and exchange operations in dual-pivot sorting into vector instructions. However, this conversion usually only focuses on the parallelism of operations, without considering the stability of sorting. Traditional sorting algorithms (such as quicksort, mergesort, etc.) rely more on the comparison and exchange of individual elements. This mismatch of instruction sets makes traditional sorting algorithms not directly applicable on TPU.

[0042] 2. Parallel processing: Taking advantage of the multi-core parallel computing capability of TPU, these schemes distribute the stages of dual-pivot sorting (such as splitting, merging, etc.) to different cores for processing. Although this parallel processing can significantly improve the sorting speed, if there is no additional measure to ensure the stability of sorting, the relative order of equal elements may change during the sorting process.

[0043] However, these schemes have obvious limitations. Since they do not solve the problem of sorting stability, they may produce incorrect results in certain application scenarios. For example, in database sorting, if two records have the same sorting key but different other attributes (such as timestamp, ID, etc.), it is very important to maintain their relative order. If the sorting algorithm cannot guarantee stability, it may cause the order of these records to change, affecting the accuracy of query results.

[0044] The present application aims to propose a method for implementing stable sorting on TPU based on dual-pivot sorting algorithm. This method not only utilizes the parallel computing capability of TPU to speed up the sorting process, but also introduces mechanisms such as core id to ensure the stability of sorting.

[0045] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 The implementation flowchart of the data sorting method for tensor processor provided by the embodiments of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, it includes the following steps:

[0047] S101, obtaining the input data and the storage capacity of a single TPU register, and assigning a core id indicating the initial position to each element in the input data.

[0048] In the specific implementation process, there are multiple implementation ways for the storage capacity of TPU register: the current mainstream configuration is 1024 elements (determined by the 8x128-bit register structure), and some high-performance models support 2048 elements (using 16x128-bit extended architecture). This capacity elasticity design requires the sorting algorithm to have hardware adaptive capability. In this application, the TPU register with a storage capacity of 1024 is mainly described.

[0049] In the data preprocessing stage, the system acquires the input data set and detects the single TPU register capacity. A unique core id is assigned to each element to mark the original position (such as index 0 to 2047), and the core aims to solve the stability defect of traditional double-tune sorting, so that the source and state of each element can be accurately tracked during the sorting process, ensuring that when comparing and exchanging elements, not only the size of the element value is considered, but also their relative order and source information. In this way, even if two element values are equal, the original relative order can be maintained after sorting. For example: when two element values are equal (such as element A

[10] =3.5 and A

[20] =3.5), the core id can record its initial order (id:10 vs id:20), providing a trace basis for final order adjustment.

[0050] S102, when the data volume of the input data is less than or equal to the storage capacity of a single TPU register, a single-register-level sorting operation is performed to obtain a double-tune sequence of a single register.

[0051] There is no direct instruction for processing a single register sorting in the TPU register, so when the data volume of the input data is less than or equal to the storage capacity of a single TPU register, the input data is loaded into the register and a single-register-level sorting operation is directly performed.

[0052] S103, when the data volume of the input data is greater than the storage capacity of a single TPU register, the input data is recursively divided into multiple sub-sequences by double-tune sorting, and a single-register-level sorting operation is performed on each sub-sequence, and the sorted sub-sequences are merged to obtain a double-tune sequence of multiple registers; wherein the core id of the element is transmitted when performing a single-register-level sorting operation on each sub-sequence and merging the sorted sub-sequences.

[0053] When the data volume of the input data is greater than the storage capacity of a single TPU register, the single register cannot load the super-capacity data at one time. Therefore, the input data is recursively divided into multiple sub-sequences by double-tune sorting to avoid data overflow. For example, on a 1024-capacity TPU, 5000 data are divided into 5 sub-blocks (4 blocks of 1024 elements + 1 block of 904 elements), and 120 minimum values are filled to 1024 for the tail block. After recursive processing to all sub-blocks with a length ≤1024, a single-register-level sorting operation is triggered, and this hierarchical processing fully utilizes the parallel pipeline of TPU to avoid the risk of memory overflow.

[0054] During the merging and sorting of sub-sequences, the core id is always transmitted synchronously with the element to ensure that the tracking chain is not broken.

[0055] S104, after obtaining the double-tune sequence, the order of equal elements is adjusted according to the core id.

[0056] After obtaining the double-tuple sequence, if the system detects that the equal elements in the double-tuple sequence (such as the elements with a value of 3.5 appearing at positions 50 and 51), the order of the equal elements is adjusted according to the core id to ensure stability. For example: compare the core ids of the two (assuming id:20 and id:10), if id:20>id:10 (that is, the original order is id:10 first), then exchange the positions of the two elements. This operation makes the final output not only meet the global order (3.5≤3.5), but also maintain the original relative order of equal elements (id:10 always precedes id:20), solving the result distortion problem caused by disordered order in database sorting and other scenarios.

[0057] In this embodiment, single register processing or recursive division and merging is used according to the size of the data amount, which fully utilizes the parallel processing capability of TPU and improves the sorting efficiency. By recursively dividing the large data set into small blocks suitable for TPU register processing, and using the vector instruction of TPU for parallel comparison and exchange, the double-tuple sorting algorithm can be efficiently implemented on TPU. By assigning a core id to each element and passing the core id during sorting, the instability problem of the traditional double-tuple sorting algorithm is solved, so that the equal elements can maintain their original order after sorting. Finally, the order of the equal elements is adjusted according to the core id, further ensuring the stability of the sorting, thereby meeting the demand for stable sorting in database and other application scenarios.

[0058] In one possible implementation, the single register level sorting operation includes:

[0059] Separate the data into two registers according to the odd and even bits using the mask instruction;

[0060] Compare the elements at corresponding positions in the two registers using the Max floating point instruction and the Min floating point instruction in the vector instruction set of TPU, and store the large value and the small value in the max register and the min register, respectively;

[0061] Use the select instruction combined with the mask operation to make the max register only retain the odd bit elements and the min register only retain the even bit elements, and combine the elements of the two registers to form a double-tuple sequence.

[0062] Take a TPU register with a capacity of 1024 (8x128 bit structure) as an example, and describe the single register level sorting operation in detail. Assuming that the input data is 800 floating point numbers (less than the register capacity), and each element has been assigned a core id to record the original position (such as id:0 to 799). At this time, directly trigger the single register operation, and the specific process is as follows:

[0063] Step 1: Mask control for parity separation

[0064] Generate two 128-bit vector masks:

[0065] Odd mask: binary sequence [1, 0, 1, 0,..., 1, 0] (512 ones and 512 zeros alternate)

[0066] Even mask: binary sequence [0, 1, 0, 1,..., 0, 1] (512 zeros and 512 ones alternate)

[0067] Separate 800 elements by index position through the permute instruction of TPU:

[0068] Odd index elements (positions 1, 3, 5,...) are loaded into register A (actually 400 valid data + 112 padding 0); even index elements (positions 0, 2, 4,...) are loaded into register B (400 valid data + 112 padding 0);

[0069] The key significance of parity separation is to convert serial data into parallel processable vector structure, laying the foundation for subsequent batch comparison.

[0070] Step 2: Parallel comparison of vector instructions

[0071] Call TPU hardware instructions:

[0072] Max floating point (RegA, RegB) → output the larger value to the max register (e.g. A[1]=5.2>B[1]=4.7, then max[1]=5.2)

[0073] Min floating point (RegA, RegB) → output the smaller value to the min register (min[1]=4.7)

[0074] This operation completes the parallel comparison of 512 pairs of elements (i.e. 1024 / 2) at a time, compared with traditional serial comparison (512 cycles required), the speed is significantly improved.

[0075] Step 3: Data reorganization of Select instruction

[0076] Apply the correction mask to the max register and the min register:

[0077] An odd number reservation mask ([1, 0, 1, 0, …, 1, 0]) is used for the max register, and only odd bit elements (that is, 1, 3, 5, … positions of the original input sequence) are reserved; an even number reservation mask ([0, 1, 0, 1, …, 0, 1]) is used for the min register, and only even bit elements (0, 2, 4, … positions of the original input sequence) are reserved;

[0078] The data of the two registers are merged by a concat instruction to form a double monotone sequence (for example, the first half of the merged sequence is an increasing odd bit large value, and the second half is a decreasing even bit small value).

[0079] In the embodiment, the odd and even bit separation of data is implemented by using a mask instruction, parallel vector comparison is completed by combining a Max floating point instruction and a Min floating point instruction special for a TPU, a traditional operation based on scalar comparison is converted into single-cycle batch processing, and the number of calling comparison instructions is greatly reduced; and the cooperative operation of a select instruction and a mask ensures accurate recombination of the odd and even bit data, and forms a data layout strictly conforming to the double monotone sequence characteristics.

[0080] In a possible implementation manner, the merging of the sorted sub-sequences includes:

[0081] The elements of the two sub-sequences are sequentially exchanged according to a double monotone sorting logic.

[0082] The Max floating point instruction and the Min floating point instruction in the vector instruction set of the TPU are used to compare the elements at the same positions in the two sub-sequences, and the large value and the small value are stored in a max register and a min register, respectively.

[0083] Single-register-level sorting operations are respectively performed on the elements in the max register and the min register, to obtain a double monotone sequence of the max register and a double monotone sequence of the min register.

[0084] In a possible implementation manner, the sequentially exchanging of the elements of the two sub-sequences according to the double monotone sorting logic includes:

[0085] The elements of the two sub-sequences are sequentially exchanged to obtain an increasing sub-sequence and a decreasing sub-sequence.

[0086] Taking two sub-sequences (corresponding to the data of two registers) with a length of 1024 as an example, the specific operation is as follows:

[0087] ① Order adjustment: The elements of the two subsequences are swapped in order to ensure that the two subsequences meet the monotonicity sorting logic after merging. This allows the merged sequence to exhibit the characteristics of first increasing and then decreasing (or vice versa), preparing for subsequent comparison and sorting.

[0088] ② Comparison screening: The Max floating point instruction and the Min floating point instruction are used to compare the data at corresponding positions in the two subsequences. These two instructions compare the elements at the same position in the two subsequences in parallel, with the Max floating point instruction storing the larger value in the max register and the Min floating point instruction storing the smaller value in the min register. This process fully utilizes the vector computing capabilities of the TPU and efficiently completes a large number of comparison operations.

[0089] ③ In-block sorting (same as single register level sorting operation): After obtaining the max and min registers, the 1024 data in these two registers are sorted at the bottom level. The specific method is similar to when processing a single register (1024 data), that is, first use the instruction to separate the data by odd and even bits using a mask, and store them in new temporary registers, then use the Max floating point and Min floating point instructions to compare the data at corresponding positions in these temporary registers, and store the larger and smaller values in new max and min temporary registers respectively, then use the select instruction combined with the mask operation to make the max temporary register only retain the odd bit data and the min temporary register only retain the even bit data, finally merge the data in these two temporary registers to further sort the 1024 data in each register.

[0090] Repeat the above steps of subsequence monotonicity to merge the adjacent two 1024 data blocks into a monotonic sequence. With the recursion, these merged monotonic sequences are gradually merged. Each time the operation of order adjustment, comparison screening and in-block sorting is performed, and finally the construction of the entire multi-register data monotonic sequence is completed.

[0091] In the embodiment, the double-tuning structure is constructed by reversing the order of the subsequence, so that the parallel comparison of the subsequent Max floating point instruction and Min floating point instruction can directly generate the max sequence and the min sequence satisfying the recursive merging condition. The single register sorting is independently performed on the max sequence and the min sequence, so as to fully utilize the multi-core parallel capability of the TPU, avoid the serial bottleneck in the traditional merging algorithm, and ensure the sequence ordering.

[0092] In a possible implementation, the input data is recursively divided into a plurality of sub-sequences for double tuning sorting, including:

[0093] The input data is recursively divided into sub-sequences for double tuning sorting, and the length of each sub-sequence is less than or equal to a set length; wherein the set length is equal to the storage capacity of a single TPU register.

[0094] The shorter double tuning sequence obtained through recursive division still maintains the basic characteristics of the double tuning sequence, that is, the elements in the sequence are first arranged in ascending order, and then start to decrease (or vice versa) after a certain specific index. Since the division is uniformly divided according to the length, the shorter double tuning sequence has similarity in element distribution with the original sequence, only the scale is smaller. These shorter double tuning sequences will continue to be sorted through parallel comparison and exchange operations in the subsequent sorting process, gradually become ordered, and finally realize the sorting of the entire data set.

[0095] In the embodiment, the termination condition of the recursive division is set as the length of the sub-sequence being equal to the TPU register capacity, so as to ensure that each recursive node can directly call the hardware-optimized single register sorting, and avoid the additional adaptation cost caused by the irregular data block.

[0096] In a possible implementation, before the input data is recursively divided into a plurality of sub-sequences for double tuning sorting, the method further includes:

[0097] The input data is divided into blocks with a power of 2;

[0098] When there is a block with a length less than the set length, the input data is padded to the set length;

[0099] Each element in the supplemented input data is assigned a core id marking the initial position.

[0100] Optionally, the padding of the input data includes: taking the minimum value in the input data as the padding value, and padding the input data based on the padding value.

[0101] Optionally, the assignment of the core id marking the initial position to each element in the supplemented input data includes:

[0102] Assign positive values to the initial elements core id in the input data, and assign negative values to the padding values of core id.

[0103] In other possible implementations, the core id of each element in the supplemented input data is assigned a core id marking the initial position, including:

[0104] Assign values to all elements core id in the input data in order, and then add a uniform prefix or suffix to the core id of the padding values.

[0105] Taking the TPU register capacity of 1024 (8x128-bit structure) as an example, the input data set (e.g. 5000 floating-point numbers) is processed. The algorithm requires the data size to be a power of 2 (such as 1024, 2048). Since the original data 5000 does not meet this condition, the preprocessing process is started:

[0106] Step 1: 2 power block calculation

[0107] Calculate the 2 power that covers 5000: 2 12 =4096<5000, 2 13 =8192>5000

[0108] Block decision: prefer to allocate complete blocks → 8192 is too large to cause waste, so choose a combination strategy:

[0109] 4 standard blocks: 4x1024=4096 elements

[0110] 1 tail block: 5000-4096=904 elements

[0111] This block strategy balances efficiency and resources: complete blocks directly align registers, and tail blocks are processed independently to avoid space waste.

[0112] Step 2: tail block padding and core id assignment

[0113] Detect tail block 904<register capacity 1024

[0114] Padding operation: add 1024-904=120 minimum values (-3.4x10 38 , TPU single floating point minimum value)

[0115] Core id assignment design:

[0116] Assign positive integer ids (0 to 4999) to original elements

[0117] Assign negative ids (-1 to -120) to padding elements

[0118] Wherein, the negative id mechanism realizes double protection, explicitly identifies invalid data, avoids polluting the sorting result, and maintains the element position traceability chain (for example, the padding value always maps the negative id interval).

[0119] In this embodiment, the power-of-2 block strategy meets the recursive constraints of double sorting, and by padding data values and assigning negative core ids to insufficient blocks, the algorithm integrity is maintained and invalid data is explicitly identified; the negative core id mechanism provides a precise anchor point for subsequent data cleaning, ensuring that the original data is not contaminated.

[0120] In a possible implementation, after adjusting the order of equal elements according to the core id, the method further includes:

[0121] Removing the padding values in the input data according to the core id.

[0122] As an example of the foregoing embodiment, the 5000 elements of the original data are divided into 4 complete blocks (each 1024 elements) and 1 padding tail block (904 real data + 120 padding minimum values), and all padding elements are assigned negative core ids (-1 to -120). After completing the double sorting recursive operation, enter the padding value removal phase.

[0123] Scan the data stream of the final sorting result (for example, the output sequence length is 6144), detect the core id attribute of each element: positive integer id (0-4999) identifies the original data, negative integer id (-1 to -120) identifies the padding value, and then delete the element corresponding to the negative integer id, that is, remove the padding values in the input data.

[0124] In this embodiment, the padding values are quickly identified and removed based on the negative core id, eliminating the influence of preprocessing on the final result and ensuring the purity of the output data. This operation forms a closed-loop management with the core id system, verifying the robustness of the stability mechanism in data addition and deletion scenarios.

[0125] In a possible implementation, adjusting the order of equal elements according to the core id includes:

[0126] Judging whether the core id order of equal elements is consistent with the original order;

[0127] When the judgment result is inconsistent, exchanging the positions of equal elements according to the core id.

[0128] In this embodiment, by local verification and exchange of the core id order of adjacent elements, the stability deviation that may occur in the sorting process is corrected in a targeted manner. This linear adjustment strategy only acts on the subset of equal elements, avoiding the resource waste of global rearrangement, and finally achieving a strictly stable sorting.

[0129] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.

[0130] The following is the device embodiment of the application. For details not described in detail, please refer to the corresponding method embodiments described above.

[0131] Figure 2 The structure diagram of the tensor processor system provided by the embodiment of the application is shown. For ease of illustration, only the part related to the embodiment of the application is shown, and the details are as follows:

[0132] As shown in Figure 2 , the tensor processor system comprises a plurality of TPU registers, a vector instruction execution module and a core id management module.

[0133] The storage capacity of each TPU register is the same.

[0134] The core id management module is configured to assign a core id marked with an initial position to each element in the input data.

[0135] The vector instruction execution module is configured to execute the data sorting method for a tensor processor provided by any of the preceding method embodiments.

[0136] In this embodiment, single register processing or recursive division and merging is used according to the size of the data amount, which fully utilizes the parallel processing capability of the TPU and improves the sorting efficiency. By recursively dividing the large data set into small blocks suitable for TPU register processing, and using the vector instruction of the TPU for parallel comparison and exchange, the double sorting algorithm can be efficiently implemented on the TPU. By assigning a core id to each element and passing the core id during the sorting process, the instability problem of the traditional double sorting algorithm is solved, so that the original order of equal elements can be maintained after sorting. Finally, the order of equal elements is adjusted according to the core id, further ensuring the stability of the sorting, thereby meeting the demand for stable sorting in application scenarios such as databases.

[0137] For the convenience and brevity of description, only the division of the above functional modules / units is exemplified. In actual application, the above functions can be completed by different functional modules / units according to needs. The above modules / units can be realized in the form of hardware, software or a combination of hardware and software.

[0138] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method in any of the above method embodiments is implemented.

[0139] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments. If there is no special description and no logical conflict, the terms and / or descriptions of different embodiments are consistent and can be mutually referred to, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0140] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A data sorting method for a tensor processor, characterized in that: include: Obtain input data and the storage capacity of a single tensor processor (TPU) register, and assign a core ID marking an initial position to each element in the input data; When the amount of the input data is less than or equal to the storage capacity of a single TPU register, performing a single register level sorting operation to obtain a bitonic sequence of the single register; When the amount of the input data is greater than the storage capacity of a single TPU register, recursively dividing the input data into multiple subsequences by bitonic sorting, performing the single-register-level sorting operation on each subsequence, and merging the sorted subsequences to obtain a multi-register bitonic sequence; wherein, when performing the single-register-level sorting operation on each subsequence and merging the sorted subsequences, the core ID of the element is passed; After obtaining the bitune sequence, the order of equal elements is adjusted according to the core id; The step of adjusting the order of equal elements according to core IDs includes: Determine whether the core id order of equal elements is consistent with the original order; When the judgment result is inconsistent, the positions of equal elements are swapped according to the core id to maintain the original relative order of equal elements.

2. The data sorting method for a tensor processor according to claim 1, wherein: The single register level sorting operation includes: Use mask instructions to separate data into two registers by odd and even bits; Use the Max floating point instruction and Min floating point instruction in the TPU vector instruction set to compare the elements of corresponding positions in the two registers, and store the larger and smaller values ​​in the max register and min register respectively; The select instruction is combined with the mask operation to make the max register retain only the odd-numbered elements and the min register retain only the even-numbered elements, and the elements of these two registers are merged to form a bitune sequence.

3. The data sorting method for a tensor processor according to claim 1, wherein: The merging of the sorted subsequences includes: The order of the elements of the two subsequences is swapped according to the bitune sorting logic; Use the Max floating point instruction and Min floating point instruction in the TPU vector instruction set to compare the elements at the same position in the two subsequences, and store the larger and smaller values ​​in the max register and min register respectively; The single register level sorting operation is performed on the elements in the max register and the min register respectively to obtain the bitonal sequence of the max register and the bitonal sequence of the min register.

4. The data sorting method for a tensor processor according to claim 3, wherein: The step of swapping the order of the elements of the two subsequences according to the bitonal sorting logic includes: Swap the elements of the two subsequences in order to obtain an increasing subsequence and a decreasing subsequence.

5. The data sorting method for a tensor processor according to claim 1, wherein: The bitonic sorting and recursively dividing the input data into a plurality of subsequences comprises: The input data is bitonally sorted and recursively divided into subsequences whose length is less than or equal to a set length; wherein the set length is equal to the storage capacity of a single TPU register.

6. The data sorting method for a tensor processor according to claim 5, wherein: Before performing bitonic sorting on the input data and recursively dividing the input data into a plurality of subsequences, the method further includes: Dividing the input data into blocks of powers of 2; When there is a block whose data length is less than the set length, padding the input data to the set length; Assign a core id marking the initial position to each element in the supplemented input data.

7. The data sorting method for a tensor processor according to claim 6, wherein: After adjusting the order of equal elements according to core ID, the following steps are further included: Remove padding values ​​from the input data according to core id.

8. A tensor processor system, characterized in that: include: Multiple TPU registers, vector instruction execution module and core ID management module; Among them, the storage capacity of each TPU register is the same; The core id management module is used to assign a core id marking an initial position to each element in the input data; The vector instruction execution module is used to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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