Controllable test program generation method and device, storage medium and electronic equipment

Abstract

The invention provides a controllable test program generation method and device, a storage medium and electronic equipment, and relates to the field of chip testing. The electronic equipment obtains an instruction set supported by the to-be-tested processor; generating branch program fragments according to various branch instructions in the instruction set; wherein the branch program fragment comprises a plurality of branch instructions, an auxiliary code is inserted in front of and behind each branch instruction, and the auxiliary codes trigger a pre-configured instruction exception handling program to be used for returning to continue execution according to an original path after the branch instructions are executed; a test program including the branch program fragments is generated. Thus, the jump behavior of the branch instructions is constrained by inserting the auxiliary codes, so that even if a complex nested structure and jump logic are formed for a large number of branch instructions, the test program can be propelled along a set path and is not limited by the complex jump logic or an uncertain target address any more, and the test efficiency is improved. Therefore, a higher test coverage rate and more comprehensive behavior verification are realized.

Description

Technical Field

[0001] The present application relates to the field of chip testing, and more specifically, to a controllable test program generation method, device, storage medium, and electronic device. Background Art

[0002] As the core hardware of a computer system, a chip's instruction set forms a crucial bridge between software and hardware. Each instruction corresponds to a specific operating behavior within the chip. However, after chip manufacturing, chip behavior may deviate due to design flaws or production process issues. Therefore, to ensure that a chip operates as designed, it must be thoroughly tested using its instruction set.

[0003] In practice, we've discovered that branch instructions exhibit significantly different testing characteristics than sequential instructions. Specifically, sequential instructions are relatively simple and predictable, with their execution paths strictly following a fixed linear order. Each instruction is executed sequentially according to the program code's order. This characteristic allows testing tools to easily verify each sequential instruction individually, ensuring that all instructions are fully covered without omission.

[0004] In contrast, the operational characteristics of branch instructions greatly increase the complexity of their testing. The characteristic of branch instructions is that they dynamically adjust the execution flow of the program according to specific conditions or states. When multiple branch instructions are used in combination, complex nested structures and jump logic will be formed, which greatly increases the difficulty of testing. For example, branch instructions may jump to different locations within the same code segment, or they may jump across a larger address range. Furthermore, when it comes to target addresses in the form of registers, the jump range of branch instructions can even cover the entire system address space. The diversity and dynamism of branch instructions make it difficult to accurately predict the jump behavior of branch instructions. Therefore, existing testing methods find it difficult to verify branch instructions one by one, and cannot guarantee that all possible jump paths are fully covered.

[0005] Therefore, there is an urgent need to provide a solution for improving the completeness of testing to cover more branch instructions and more instruction space. Summary of the Invention

[0006] In order to overcome at least one shortcoming in the prior art, the present application provides a controllable test program generation method, device, storage medium and electronic device, which can enable the test program to advance along a predetermined path when faced with a large number of branch instructions forming a complex nested structure and jump logic, and is no longer restricted by complex jump logic or uncertain target addresses, thereby achieving higher test coverage and more comprehensive behavioral verification.

[0007] In a first aspect, the present application provides a method for generating a controllable test program, the method comprising:

[0008] Get the instruction set supported by the processor under test;

[0009] generating a branch program fragment based on multiple branch instructions in the instruction set, wherein the branch program fragment includes multiple branch instructions, and auxiliary codes are inserted before and after each branch instruction, and the auxiliary codes are used to trigger a pre-configured instruction exception handler, and the instruction exception handler is used to return to the original path and continue execution after the branch instruction is executed;

[0010] A test program including the branch program fragment is generated.

[0011] In a second aspect, the present application provides a controllable test program generation device, the device comprising:

[0012] An instruction acquisition module is used to obtain the instruction set supported by the processor under test;

[0013] a program fragment module, configured to generate a branch program fragment based on the multiple branch instructions in the instruction set, wherein the branch program fragment includes multiple branch instructions, each branch instruction having auxiliary codes inserted before and after, the auxiliary codes being configured to trigger a pre-configured instruction exception handler, the instruction exception handler being configured to return to the original path for continued execution after the branch instruction is executed;

[0014] The program construction module is used to generate a test program including the branch program fragment.

[0015] In a third aspect, the present application provides a storage medium storing a computer program, which implements the controllable test program generation method when executed by a processor.

[0016] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and the computer program implements the controllable test program generation method when executed by the processor.

[0017] Compared with the prior art, this application has the following beneficial effects:

[0018] The present application provides a controllable test program generation method, device, storage medium and electronic device. The electronic device obtains the instruction set supported by the processor to be tested; generates a branch program fragment based on the multiple branch instructions in the instruction set; wherein, the branch program fragment includes multiple branch instructions, and auxiliary codes are inserted before and after each branch instruction. The instruction exception handler triggered by the auxiliary code is used to return to the original path and continue execution after the branch instruction is executed; finally, a test program including the branch program fragment is generated. In this way, by inserting auxiliary codes to constrain the jump behavior of the branch instruction, even when faced with a large number of branch instructions forming a complex nested structure and jump logic, the test program can be advanced along the established path, no longer restricted by complex jump logic or uncertain target addresses, thereby achieving higher test coverage and more comprehensive behavior verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flow chart of a method for generating a controlled test program according to an embodiment of the present application;

[0021] Figure 2 A diagram showing the positional relationship between branch instructions and auxiliary codes provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the execution principle of the test program provided in the embodiment of the present application;

[0023] Figure 4 A schematic diagram of the virtual address mapping effect provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of a controlled test program generation device provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] To make the purpose, technical solutions, and advantages of the embodiments of the present application (hereinafter referred to as the present embodiments) clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0029] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended only to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting this application. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] In addition, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0031] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0032] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0033] Based on the above statement, as described in the background, the diversity and dynamic nature of branch instructions makes it difficult to accurately predict their jump behavior. Existing testing methods therefore struggle to verify each branch instruction individually, and cannot guarantee that all possible jump paths are fully covered. Therefore, there is an urgent need to provide a solution to improve the completeness of testing, covering more branch instructions and expanding the instruction space.

[0034] For example, assume that in an actual test scenario, the test program contains an unconditional jump instruction in register format, whose target address is dynamically determined by the register value. If this jump instruction is not constrained by any constraints, it may jump directly to a code location in the remote address space during execution, completely ignoring the subsequent branch instruction. This may cause some branch instructions to fail to be tested.

[0035] Based on the discovery of the above technical problems, the following technical solutions are proposed after creative work to solve or improve the above problems. It should be noted that the defects existing in the solutions in the above prior art are the results obtained after practice and careful study. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of this application for the above problems below should be regarded as contributions to this application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0036] In this regard, this embodiment provides a controllable test program generation method. Figure 1 As shown, the method includes:

[0037] S1, obtain the instruction set supported by the processor to be tested.

[0038] S2, generates branch program fragments according to various branch instructions in the instruction set.

[0039] Among them, the branch program fragment includes multiple branch instructions, and auxiliary codes are inserted before and after each branch instruction. The auxiliary codes are used to trigger the instruction exception handler. The instruction exception handler is used to return to the original path and continue execution after the branch instruction is executed.

[0040] S3, generating a test program including branch program fragments.

[0041] In this way, by inserting auxiliary coding to constrain the jump behavior of branch instructions, even when faced with a large number of branch instructions forming a complex nested structure and jump logic, the test program can proceed along the established path and is no longer restricted by complex jump logic or uncertain target addresses, thereby achieving higher test coverage and more comprehensive behavioral verification.

[0042] In this embodiment, the electronic device that implements the controllable test program generation method may be, but is not limited to, a mobile terminal, a tablet computer, a laptop computer, a desktop computer, and a server, etc. When it is a server, the server may be a single server or a server group. The server group may be centralized or distributed (for example, the server may be a distributed system). In some embodiments, the server may be local or remote relative to the user terminal. In some embodiments, the server may be implemented on a cloud platform; as an example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud (Community Cloud), a distributed cloud, an inter-cloud (Inter-Cloud), a multi-cloud (Multi-Cloud), etc., or any combination thereof. In some embodiments, the server may be implemented on an electronic device having one or more components.

[0043] In order to make the solution provided by this embodiment clearer, the following uses a server as an electronic device to implement the method. Figure 1 Each step of the method shown is described in detail. However, it should be understood that the operations in the flowchart may not be performed in order, and steps that have no logical contextual relationship may be reversed or performed simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more additional operations to the flowchart or remove one or more operations from the flowchart.

[0044] Continue to see Figure 1 , the method comprising:

[0045] S1, obtain the instruction set supported by the processor to be tested.

[0046] Regarding the above steps, it should be understood that the instruction sets supported by different processor architectures vary significantly. Only by clearly understanding the range of instruction sets supported by the processor under test can we construct an appropriate branch program snippet based on this, thereby effectively testing branch instructions. For example, the instruction set may be the ARM64 instruction set, the x86-64 instruction set, or the MIPS instruction set.

[0047] Based on the description of the instruction set in the above embodiment, the following Figure 1Explanation of step S2 in FIG.

[0048] S2, generates branch program fragments based on various branch instructions in the instruction set.

[0049] For the above-mentioned multiple branch instructions, taking the ARM64 instruction set as an example, the branch instructions may include conditional jump instructions, unconditional jump instructions, jump instructions in the form of immediate values, and jump instructions in the form of registers. By selecting these different types of branch instructions, it is possible to ensure that the test program fully covers the processor functions. After arranging and combining multiple branch instructions, the branch program fragment includes multiple branch instructions, and auxiliary codes are inserted before and after each branch instruction. The auxiliary codes are used to trigger a pre-configured instruction exception handler. The instruction exception handler is used to return to the original path and continue execution after the branch instruction is executed.

[0050] This embodiment provides two auxiliary codes, which are a series of special codes selected from abnormal instructions. The first is used to trigger the lock operation; the second is used to trigger the unlock operation. For example, Figure 2 As shown, the branch instruction is called the Branch instruction, and auxiliary coding is introduced and inserted before and after the Branch instruction, thereby completing the generation process of the Branch instruction.

[0051] Continue to see Figure 2 , the auxiliary code 0xad01 is the first auxiliary code, which is used to trigger the locking operation, while the auxiliary code 0xad00 is the second auxiliary code, which is used to trigger the unlocking operation. During the execution of the test program, when the auxiliary code 0xad01 located before the Branch instruction is encountered, an exception event will be triggered and the exception handling function will be entered. At this stage, the exception handling function will record the Branch instruction location as the return address, and the locking operation will be completed. Similarly, when the auxiliary code 0xad00 located after the Branch instruction is encountered, an exception event will be triggered and the exception handling function will be entered. At this time, the exception handling function will resume the execution process based on the previously recorded return address information, and the unlocking operation will be completed.

[0052] Continue to see Figure 2 As an optional implementation, a linearly executed non-branch instruction may be inserted between the Branch instruction and the first auxiliary encoding as other auxiliary instructions.

[0053] In practice, it is found that the instruction set supported by the processor under test usually contains multiple types of branch instructions, such as conditional jump instructions, unconditional jump instructions, immediate jump instructions, and register jump instructions. These instruction types are not only huge in number, but also have different behavioral characteristics and application scenarios. The way of manually selecting branch instructions is limited by people's subjective judgment ability and ability to predict complex combinations, and cannot fully cover all possible branch instructions and their operating scenarios. In this regard, Figure 1 In step S2, this embodiment provides the following optional implementation methods of this step:

[0054] S2-1, select multiple branch instructions from the instruction set.

[0055] S3-2, randomly combining multiple branch instructions to generate an initial program fragment including multiple branch instructions.

[0056] During the execution of these steps, the server uses randomization to simulate, to a certain extent, the various complex control flow scenarios that may arise in a real-world operating environment. Therefore, this random combination process not only increases the diversity of the test program but also improves the ability to detect branch logic anomalies in the processor under test.

[0057] In addition, it should be understood that the instruction set supported by the processor to be tested contains multiple types of branch instructions, such as conditional jump instructions, unconditional jump instructions, jump instructions in the form of immediate values, and jump instructions in the form of registers. When generating branch program fragments, the number of each type of branch instructions can be flexibly configured according to the test requirements. Specifically, for a certain type of branch instruction (such as a jump instruction in the form of a register), it may be necessary to insert multiple instances in the branch program fragment to verify its behavioral characteristics in different scenarios; in other cases, it may only be necessary to insert one branch instruction of this type to meet the test requirements.

[0058] S4-3, insert auxiliary codes before and after each branch instruction in the initial program fragment to obtain a branch program fragment.

[0059] It can be understood that the server inserts auxiliary code before and after each branch instruction in the initial program fragment to obtain a complete branch program fragment. The auxiliary code provides the necessary control mechanism for the test program, so that the test program executes according to the established route.

[0060] In this embodiment, the instruction exception handler includes a locking subroutine and an unlocking subroutine. Auxiliary code located before each branch instruction triggers the locking subroutine, which records the branch instruction's location. Auxiliary code located after each branch instruction triggers the unlocking subroutine, which returns to the original path based on the instruction's location and continues execution.

[0061] It should be understood that in this embodiment, the core function of the instruction exception handler is to precisely control the execution of branch instructions through the coordinated action of the locking and unlocking subroutines, and to return to the correct path for continued execution after exception handling. To achieve this goal, the instruction exception handler needs to be called through a pre-exposed system interface so that it can promptly respond to exception events triggered by the auxiliary code during the test program execution.

[0062] like Figure 3 As shown, when the test program executes a branch instruction, it first encounters auxiliary codes located before the branch instruction. These auxiliary codes are illegal instructions and their function is to trigger an instruction exception. In the exception handling function, the system determines whether the return address of the branch instruction has been recorded before, that is, whether the locking operation has been completed. If the locking operation has been completed, it returns directly from the exception and continues to execute the next instruction. If the locking operation has not been completed, the position of the first instruction after the branch unit is calculated and recorded based on the current exception return address, and then returns from the exception again to continue executing the subsequent code.

[0063] Next, when the branch instruction is executed, the test program will encounter the auxiliary code located after the branch instruction. Similarly, these auxiliary codes will also trigger exception events, thereby entering the exception handling function. At this time, the system will perform an unlocking operation, and according to the previously recorded branch instruction location information, it will resume the execution process and jump back to the return address recorded when locking to start the next round of testing. It is worth noting that regardless of whether the branch instruction is a conditional jump or an unconditional jump, it will eventually execute the auxiliary code 0xad00 (or similar auxiliary code). Although the auxiliary code may not belong to the current branch unit, but to other branch units or branch targets, the exception event it triggers can still enable the correct execution of the unlocking operation.

[0064] Based on the above explanation of the branch program fragment, we will continue to Figure 1 Explanation of step S3 in the following example:

[0065] S3, generating a test program including branch program fragments.

[0066] In practice, it was found that when a test program contains branch instructions, the target address of these branch instructions is usually determined by their type. For example, in the ARM64 instruction set, some conditional jump instructions have a jump range of 2M, while unconditional jump and immediate jump instructions have a range of up to ±128M. Register-based jump instructions may cover a larger address space range, even reaching the entire system address space. However, in the actual operating environment, the memory space available for test programs is often limited and needs to be coordinated with the operating system's memory management mechanism.

[0067] Therefore, conventional approaches either test only some branch instructions, resulting in an inability to fully test all branch instructions. Alternatively, they directly constrain the jump range of branch instructions. Without this constraint, if the target address of a branch instruction in the test program exceeds the memory range allocated to the test program, execution may result in a jump to memory areas occupied by the operating system or other applications, leading to abnormalities such as illegal access or system crashes.

[0068] In view of this, the test program also includes a linear program segment and an initialization segment. Based on the linear program segment and the initialization segment, this embodiment also provides Figure 1 The following optional implementations of step S3 are shown:

[0069] The server may generate a test program including a branch program segment, a linear program segment, and an initialization segment, wherein the initialization segment is used to initialize the running environment of the test program, and the linear program segment is used to provide a jump space for the branch program segment.

[0070] In this way, the server stitches together the three program fragments mentioned above to obtain a complete test program. In addition, it should be understood that the end of the linear program fragment also contains auxiliary code that triggers the unlock subroutine, so that even after jumping to the linear program fragment, it can still return to the original path and continue execution.

[0071] The above initialization fragment includes virtual address mapping parameters for mapping the linear program fragment into a virtual address space that satisfies the jump range of the branch program fragment, thereby solving the problem that the jump range of the branch program fragment does not match the actual available physical address space.

[0072] It should be understood that a virtual address refers to a logical address space representation corresponding to a physical address, which is converted into an actual physical address by a memory management unit (MMU), thereby allowing the program to operate within a larger logical address space without being restricted by the size of physical memory. Specifically, the virtual address mapping parameters contained in the initialization fragment are used to define the mapping relationship between the linear program fragment and the virtual address space. These parameters generally include but are not limited to information such as the base address, segment size, and segment offset. Based on these parameters, the linear program fragment can be mapped according to a specific segment division method.

[0073] For example, a linear program segment is called a branch target. If the goal is to support jumps within a 128MB range, the 128MB virtual address space can be divided into multiple 2MB segments, and each segment of the virtual address space is mapped to the physical address space where the branch target is located. This effectively expands the actual jump range of the branch program segment.

[0074] like Figure 4 As shown, to map a linear program fragment into a virtual address space that meets the branch program fragment's jump requirements, the test program must first be loaded and the branch target's physical address space extracted. For jumps within the ±128MB range, ±128MB of virtual address space is mapped before and after the test program, with each segment of virtual address space corresponding to the branch target's physical address space. This effectively covers all target address ranges that branch instructions may involve, ensuring that the test program's jump operations always occur within the predefined virtual address space without exceeding the range or interfering with other memory areas.

[0075] For branch instructions in register form, since their jump range may cover the entire system address space, a more flexible mapping strategy is required. Specifically, before a branch instruction in register form is executed, the auxiliary code preceding the branch instruction will trigger a locking subroutine. While recording the instruction position of the branch instruction, the locking subroutine will also determine the type of branch instruction following the auxiliary code. If it is a branch instruction in register form, a virtual address is generated in a pseudo-random manner and recorded in the corresponding register. This virtual address falls within a specified virtual address range, so that it corresponds to the physical address space of the branch target.

[0076] In this way, even if the target address of the branch instruction is located anywhere within the full address space, the test program can map it to a safe virtual address space through the virtual address mapping mechanism, thereby avoiding interference with the memory area of ​​the operating system or other applications.

[0077] In this way, by introducing virtual addresses, this embodiment can improve test efficiency while enhancing support for complex nested branches and extending test coverage to all possible jump scenarios, thereby providing a more reliable solution for the verification of branch instructions.

[0078] In addition, for the above-mentioned linear program fragment, in this embodiment, the server may further select a plurality of non-branch instructions from the instruction set; and generate the linear program fragment according to the plurality of non-branch instructions.

[0079] This means the server selects a variety of non-branch instructions from the instruction set supported by the processor under test. These non-branch instructions are those that don't involve program control flow transfers, such as arithmetic and logical operations, and data load / store instructions. The range and number of these instructions can be flexibly adjusted based on actual testing requirements, but they must be able to work in conjunction with the branch program snippets to form a complete test program.

[0080] The server then generates a linear program fragment based on the selected non-branch instructions to provide jump space for the branch program fragment. Specifically, the branch program fragment may need to jump to a specific target address during execution, and these target addresses are often within the range defined by the linear program fragment.

[0081] Based on the same inventive concept as the controlled test program generation method provided in this embodiment, this embodiment also provides a controlled test program generation device, which includes at least one software function module that can be stored in a memory or fixed in an electronic device in the form of software. The processor in the electronic device is used to execute the executable module stored in the memory. For example, the software function module and computer program included in the device. Please refer to Figure 5 Functionally, the device can include:

[0082] An instruction acquisition module 11 is used to acquire the instruction set supported by the processor to be tested;

[0083] A program fragment module 12 is configured to generate a branch program fragment based on multiple branch instructions in the instruction set, wherein the branch program fragment includes multiple branch instructions, each of which is preceded and followed by auxiliary codes, the auxiliary codes being used to trigger a pre-configured instruction exception handler, which is used to return to the original path and continue execution after the branch instruction is executed;

[0084] The program construction module 13 is used to generate a test program including branch program fragments.

[0085] In this embodiment, the instruction acquisition module 11 is used to implement Figure 1 In step S1, the program fragment module 12 is used to implement Figure 1 In step S2, the program construction module 13 is used to implement Figure 1 Therefore, for a detailed description of each of the above modules, please refer to the specific implementation of the corresponding step.

[0086] It should be understood that, since the method for generating a controlled test program provided in this embodiment has the same inventive concept, the device can also implement other steps or sub-steps of the method through the above modules.

[0087] Optionally, the program fragment module 12 is further specifically configured to:

[0088] Select multiple branch instructions from the instruction set;

[0089] Randomly combining multiple branch instructions to generate an initial program fragment including multiple branch instructions;

[0090] Auxiliary codes are inserted before and after each branch instruction in the initial program fragment to obtain a branch program fragment.

[0091] Optionally, the test program further includes a linear program segment and an initialization segment, and the program construction module 13 is further configured to:

[0092] A test program including a branch program segment, a linear program segment, and an initialization segment is generated, wherein the initialization segment is used to initialize the running environment of the test program, and the linear program segment is used to provide a jump space for the branch program segment.

[0093] Optionally, the program fragment module 12 is further configured to:

[0094] Select a variety of non-branch instructions from the instruction set;

[0095] Generate linear program fragments based on various non-branching instructions.

[0096] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0097] It should also be understood that if the above embodiments are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application.

[0098] Therefore, this embodiment further provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, the controlled test program generation method provided in this embodiment is implemented. The storage medium can be a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, among other media that can store program code.

[0099] This embodiment provides an electronic device for implementing a controlled test program generation method. Figure 6 As shown, the electronic device includes a processor 22 and a memory 21. In addition, the memory 21 stores a computer program, and the processor realizes the generation of the controlled test program provided in this embodiment by reading and executing the computer program corresponding to the above embodiment in the memory 21.

[0100] Continue to see Figure 6 The electronic device further includes a communication unit 23. The memory 21, the processor 22 and the communication unit 23 are electrically connected to each other directly or indirectly via a system bus 24 to achieve data transmission or interaction.

[0101] The memory 21 may be an information recording device based on any electronic, magnetic, optical or other physical principles, for recording execution instructions, data, etc. In some embodiments, the memory 21 may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0102] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a magnetic disk drive, a solid-state drive, any type of storage disk (such as a CD, DVD, etc.), or a similar storage medium, or a combination thereof.

[0103] The communication unit 23 is used to send and receive data through a network. In some embodiments, the network may include a wired network, a wireless network, a fiber optic network, a telecommunications network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth network, a ZigBee network, or a near field communication (NFC) network, or any combination thereof. In some embodiments, the network may include one or more network access points. For example, the network may include a wired or wireless network access point, such as a base station and / or a network switching node, through which one or more components of the service request processing system can connect to the network to exchange data and / or information.

[0104] The processor 22 may be an integrated circuit chip having signal processing capabilities, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), an application-specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0105] I understand. Figure 6 The structure shown is for illustration only. Figure 6 More or fewer components than shown, or with Figure 6 Different configurations shown. Figure 6 The components shown may be implemented in hardware, software, or a combination thereof.

[0106] It should be understood that the devices and methods disclosed in the above embodiments may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented using a dedicated hardware-based system that performs a specified function or action, or may be implemented using a combination of dedicated hardware and computer instructions.

[0107] The above descriptions are merely examples of various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A controllable test program generation method, characterized in that: The method comprises: Get the instruction set supported by the processor under test; generating a branch program fragment based on multiple branch instructions in the instruction set, wherein the branch program fragment includes multiple branch instructions, and auxiliary codes are inserted before and after each branch instruction, and the auxiliary codes are used to trigger a pre-configured instruction exception handler, and the instruction exception handler is used to return to the original path and continue execution after the branch instruction is executed; A test program including the branch program fragment is generated.

2. The controllable test program generation method according to claim 1, characterized in that: Generate a branch program fragment according to the instruction set, including: Selecting the plurality of branch instructions from the instruction set; Randomly combining the multiple branch instructions to generate an initial program fragment including the multiple branch instructions; Auxiliary codes are inserted before and after each branch instruction in the initial program fragment to obtain the branch program fragment.

3. The controllable test program generation method according to claim 2, characterized in that: The multiple branch instructions include jump instructions in the form of immediate values, unconditional jump instructions, conditional jump instructions, and jump instructions in the form of registers.

4. The method for generating a controllable test program according to any one of claims 1 to 3, wherein: The instruction exception handling program includes a locking subroutine and an unlocking subroutine; The auxiliary code located before each branch instruction is used to trigger the locking subroutine, and the locking subroutine is used to record the instruction position of the branch instruction; The auxiliary code located after each branch instruction is used to trigger the unlocking subroutine, and the unlocking subroutine is used to return to the original path and continue execution according to the instruction position.

5. The controllable test program generation method according to claim 1, characterized in that: The test program further includes a linear program segment and an initialization segment, and generating a test program including the branch program segment and the instruction exception handling program includes: A test program including the branch program fragment, the linear program fragment, and the initialization fragment is generated, wherein the initialization fragment is used to initialize the running environment of the test program, and the linear program fragment is used to provide a jump space for the branch program fragment.

6. The controllable test program generation method according to claim 5, characterized in that: The method further comprises: selecting a plurality of non-branch instructions from the instruction set; A linear program fragment is generated according to the plurality of non-branch instructions.

7. The controllable test program generation method according to claim 5, characterized in that: The initialization fragment includes virtual address mapping parameters for mapping the linear program fragment into a virtual address space that satisfies the jump range of the branch program fragment.

8. A controllable test program generating device, characterized in that: The device comprises: An instruction acquisition module is used to obtain the instruction set supported by the processor under test; a program fragment module, configured to generate a branch program fragment based on the multiple branch instructions in the instruction set, wherein the branch program fragment includes multiple branch instructions, each branch instruction having auxiliary codes inserted before and after, the auxiliary codes being configured to trigger a pre-configured instruction exception handler, the instruction exception handler being configured to return to the original path for continued execution after the branch instruction is executed; The program construction module is used to generate a test program including the branch program fragment.

9. A storage medium, characterized in that: The storage medium stores a computer program, and the computer program, when executed by a processor, implements the controllable test program generation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the controllable test program generation method according to any one of claims 1 to 7.

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