An FFT operation method based on a SIMD computing platform

Abstract

The application discloses an FFT operation method based on a SIMD computing platform, and the method comprises the following steps: acquiring a vector set R composed of real number vectors with a length of N, storing the real number vectors in a floating point number with a length of size, and allocating 2L-2 blocks of continuous storage spaces with a length of N* size in the memory; wherein N is an integer power of 2, and L is the logarithm of N with 2 as the base; sequentially sending the real number vectors in R into the allocated continuous storage spaces with a length of N* size to form a queue, and performing a flow water FFT operation based on an ARMv8 SIMD architecture; there are a real number queue with a length of L and a virtual number queue with a length of L-2 in the memory, which respectively store the real part vectors and the virtual part vectors of complex numbers; the real number vectors after L times of operation and the virtual number vectors after L-2 times of operation will be dequeued; new real number vectors are enqueued, and the step 2 is repeated. The application can improve the complex number calculation rate and save the required storage overhead.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to an FFT operation method based on a SIMD computing platform. Background Art

[0002] The Fast Fourier Transform (FFT) algorithm is listed as one of the "Top Ten Algorithms of the 20th Century" and plays an important role in many large-scale scientific computing fields, such as solving differential equations and molecular dynamics. As part of the HPC Challenge benchmark program, it can also be used to evaluate the architecture and overall performance of supercomputers.

[0003] The FFT is an efficient implementation of the Discrete Fourier Transform (DFT). Directly computing an N-point DFT requires approximately O(N²) complex arithmetic operations, where each operation consists of a multiplication and an addition. The introduction of efficient algorithms can significantly reduce computational complexity. The key to this reduction lies in the fact that only N of the N² elements in the DFT matrix (of size N×N) are unique, and that a long DFT can be computed using multiple shorter DFTs. These algorithms that reduce complexity are collectively referred to as FFTs.

[0004] In FFT algorithms, algorithms that take complex input and output complex numbers are called C2C (complex to complex) algorithms. Similarly, algorithms that take real input and output complex numbers are called R2C (real to complex) algorithms. R2C algorithms are widely used in scientific research and engineering. Currently, the most mature and widely used FFT algorithm is the Cooley-Tukey algorithm. When calculating the R2C FFT using a complex FFT algorithm, the original method is to treat a real input vector of length N as a complex vector with an imaginary part of zero for the C2C FFT calculation. This original method converts the original length N vector into a length 2N vector, which not only increases memory usage and the number of memory access requests, but also significantly wastes computing resources due to the ineffective calculation of the imaginary part.

[0005] Therefore, when using complex FFT algorithms for R2C FFT calculations, improving the speed of complex calculations and reducing the required storage overhead is a pressing issue. Furthermore, the ARMv8 architecture is a widely used reduced instruction set architecture in modern processors. It features support for high-performance SIMD computing, a rich vector instruction set, and the ability to parallelize large numbers of floating-point and integer operations. When using complex FFT algorithms for R2C FFT calculations, combining them with the ARMv8 architecture can further improve computational efficiency and resource utilization. Summary of the Invention

[0006] To address these issues, the present invention aims to provide an FFT computation method based on a SIMD computing platform. This method, when performing R2C FFT operations using a complex FFT algorithm on a SIMD (Single Instruction Multiple Data) computing platform, improves the complex number computation rate and reduces the required storage overhead. Furthermore, to further optimize computational efficiency, the present invention fully utilizes the hardware design features of the ARMv8 SIMD architecture, leveraging its vector registers, pipeline execution mechanism, and instruction set optimization to achieve efficient FFT operations.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] In one aspect, a FFT operation method based on a SIMD computing platform is provided, comprising the following steps:

[0009] Step 1. Obtain a vector set R consisting of real vectors of length N. The real vectors are stored as floating-point numbers of length size, and allocate 2L-2 blocks of continuous storage space of length N × size in memory. Based on the register characteristics of the ARMv8 SIMD architecture, align the vector data to 128 bits to facilitate efficient instruction reading and storage. Where N is an integer power of 2, and L is the logarithm of N with base 2 as the base.

[0010] Step 2: The real vectors in R are sequentially sent into the continuous storage space of length N×size allocated in step 1 to form a queue, and pipeline FFT operation is performed; there is a real queue of length L and an imaginary queue of length L-2 in the memory, which respectively store the real part vector and imaginary part vector of the complex number; the real vector that completes L operations and the imaginary vector that completes L-2 operations will be dequeued; for vector loading and operation, SIMD instructions such as ld1 and fadd can be used for batch processing to increase the speed;

[0011] Step 3: Add the new real vector to the queue and repeat step 2.

[0012] Optionally, pipeline FFT operations are performed on real vectors fed from R into continuous memory, including:

[0013] Step 2.1. Send the real vector R[j] to the end of the queue formed in step 1, and perform "bit-reversal" on the sequence numbers of each element in R[j], that is, reverse the binary value of the sequence number bit by bit, and reorder the elements according to the permuted sequence number;

[0014] Step 2.2. Perform pipeline FFT iterations on the real vectors R[j-L+1], R[j-L+2], ..., R[j] and the corresponding imaginary vectors I[j-L+1], I[j-L+2], ..., I[j-2] in memory in descending order of sequence number, and use the SIMD instruction set of the ARMv8 architecture to improve parallel processing efficiency. The SIMD instruction set includes: ld1, st1, and fmul.

[0015] Optionally, pipeline FFT iterations are performed on the real vectors and the corresponding imaginary vectors in the memory in descending order of sequence number, including:

[0016] Step 2.2.1. For any real vector R[p], let s be the number of iterations it has gone through; if s ≥ 2, group the elements in R[p] and its corresponding imaginary vector I[p] into groups of n according to their sequence numbers, where n = 2 s+1 For each group, use the vector registers v0 to v31 of the ARMv8 SIMD hardware to calculate its discrete Fourier transform DFT in blocks;

[0017] Step 2.2.2, if s=1 or s=0, group the elements in R[p] into groups of n according to their sequence numbers, where n=2 s+1 ; For each group, calculate its discrete Fourier transform DFT.

[0018] Optionally, if s ≥ 2, for each group, calculate its discrete Fourier transform DFT, including:

[0019] Step 2.2.1.1. For each group of n elements in R[p], label them as a[0], a[1], ..., a[n-1]; similarly, label each group of n elements in I[p] as b[0], b[1], ..., b[n-1];

[0020] Step 2.2.1.2. For each value of k from 0 to n / 2-1, assign the variable ω the value of (exp(2πi / n)) k ,The variable ω is called the rotation factor in the FFT algorithm.,The real and imaginary parts of ω are stored as floating-point numbers c and d, respectively.,The ARMv8 SIMD instructions are used to batch load the data and align the calculations;

[0021] In the ARMv8 architecture, the real and imaginary parts are stored in vector registers respectively, and multiple groups of complex operations are performed simultaneously in a vectorized manner;

[0022] Step 2.2.1.3, let a[k+n / 2] be a, let b[k+n / 2] be b; calculate the complex number t=(a+bi)×(c+di), which can be converted into a×c-b×d+[(a+b)×(c+d)-a×c-b×d]i; store the result of a×c-b×d into a floating-point number tr, and store the result of (a+b)×(c+d)-a×c-b×d into a floating-point number ti; the converted calculation formula only needs to perform three multiplication operations a×c, b×d, (a+b)×(c+d), compared with the four multiplication operations a×c, a×d, b×c, b×d of the original calculation formula, one multiplication operation can be saved;

[0023] Step 2.2.1.4, calculate a[k]-tr and store it in a[k+n / 2]; calculate b[k]-ti and store it in b[k+n / 2]; calculate a[k]+tr and store it in a[k]; calculate b[k]+ti and store it in b[k];

[0024] Step 2.2.1.5, after the DFT calculation of R[p] and I[p] is completed, if s=L, R[p] and I[p] are the head of the respective queue; let R[p] and I[p] out of the queue, and write the values into the corresponding position in the memory for storing the calculation results, in this process, the ARMv8 pipeline optimization storage operation is used.

[0025] Optionally, if s=1 or s=0, for each group, calculate the discrete Fourier transform DFT, including:

[0026] Step 2.2.2.1, for each group of n elements in R[p], mark them as a[0], a[1], …, a[n-1];

[0027] Step 2.2.2.2, for each value of k=0 to n / 2-1, assign the variable ω the value (exp(2πi / n)) k , the real part and the imaginary part of ω are stored as floating-point numbers c and d, respectively;

[0028] Step 2.2.2.3, if s=1, let a[k+n / 2] be a, calculate the complex number t=a(c+di), store the result of a×c into a floating-point number tr, and store the result of a×d into a floating-point number ti; create I[p] on the memory space initialized in step 2.2.1.5, make it join the imaginary number queue from the tail, and execute step 2.2.1.4;

[0029] Step 2.2.2.4, if s=0, d is 0 at this time; calculate tr=a[k+n / 2]×c; calculate a[k]-tr and store it in a[k+n / 2]; calculate a[k]+tr and store it in a[k].

[0030] On the other hand, an electronic device is provided, comprising a processor and a memory, wherein the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the above-mentioned FFT operation method based on the SIMD computing platform.

[0031] On the other hand, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement the above-mentioned FFT operation method based on the SIMD computing platform.

[0032] The beneficial effects brought about by the technical solution provided by the present invention include at least:

[0033] In an embodiment of the present invention, a computational method is provided for improving the computational speed and reducing storage overhead when performing R2C FFT operations using a complex FFT algorithm. First, the real vector is reversed and then placed into a queue in memory. By storing the real and imaginary parts of the complex number in two vectors (i.e., a real vector and an imaginary vector), respectively, the common waste of storage space and computing power when performing R2C operations using a complex FFT algorithm can be avoided. At the same time, the calculations in the complex FFT algorithm involve a large number of repeated addition and multiplication operations between the real and imaginary parts, and the rotation factors. Since the present invention uses a method of storing the real and imaginary parts in two vectors, respectively, addressing is more convenient when reading and writing numbers continuously, making it more user-friendly to single instruction multiple data (SIMD) computing platforms.

[0034] Furthermore, the present invention fully combines the hardware design characteristics of the ARMv8 SIMD architecture, and by utilizing its vector registers, pipeline execution mechanism, and instruction set optimization, further improves computational efficiency and resource utilization while optimizing the FFT algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a flow chart of an FFT operation method based on a SIMD computing platform provided by an embodiment of the present invention;

[0037] Figure 2 is a schematic diagram of a data structure including two queues provided in an embodiment of the present invention;

[0038] Figure 3a and Figure 3bThis is a schematic diagram of a process for FFT iterative calculation (butterfly operation) provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Embodiments of the present invention provide an FFT calculation method based on a SIMD computing platform. This method reduces the required storage overhead when performing R2C FFT calculations using a complex FFT algorithm on the SIMD computing platform and improves the rate of complex calculations in butterfly operations. The method is suitable for platforms that support vector architectures.

[0041] like Figure 1 As shown, the method includes the following steps:

[0042] Step 1. Obtain a vector set R consisting of real vectors of length N. Real vectors are stored as floating-point numbers of length size (such as single-precision floating-point numbers). Allocate 2L-2 blocks of contiguous storage space of length N × size in memory and load the real vectors of R into ARMv8 SIMD vector registers in blocks. Based on the register characteristics of the ARMv8 SIMD architecture, align the vector data to 128 bits to facilitate efficient instruction reading and storage. Where N is an integer power of 2, and L is the logarithm of N to the base 2, L = log2N.

[0043] Step 2: The real vectors in R are sequentially queued into the contiguous storage space of length N × size allocated in Step 1, and pipelined FFT operations are performed. A real queue of length L and an imaginary queue of length L-2 are stored in memory, respectively, to store the real and imaginary vectors of complex numbers. Real vectors that have completed L operations and imaginary vectors that have completed L-2 operations are dequeued. SIMD instructions such as ld1 and fadd can be used for batch processing of vector loads and operations to increase speed.

[0044] Memory stores L real vectors and L-2 imaginary vectors, forming a real queue of length L and an imaginary queue of length L-2, respectively. The L-2 imaginary vectors in the imaginary queue are the imaginary parts of the real vectors generated by the FFT iteration. Only real vectors that have undergone the second iteration have corresponding imaginary vectors.

[0045] The operations of each round of calculation are as follows:

[0046] Step 2.1: Send the real vector R[j] to the end of the queue formed in step 1, and perform "bit-reversal" on the sequence numbers of each element in R[j]. That is, the binary value of the sequence number is reversed bit by bit, and the elements are reordered according to the permuted sequence number. On the ARMv8 platform, Neon's shift instructions can be used to efficiently perform binary bit-reversal.

[0047] Step 2.2. Perform pipeline FFT iterations on the real vectors R[j-L+1], R[j-L+2], ..., R[j] and the corresponding imaginary vectors I[j-L+1], I[j-L+2], ..., I[j-2] in memory in descending order of sequence number, and use the SIMD instruction set of the ARMv8 architecture (such as ld1, st1, fmul, etc.) to improve parallel processing efficiency.

[0048] The operation of performing one FFT iteration on each real vector R[p] is as follows (let s be the number of iterations R[p] has gone through):

[0049] Step 2.2.1. If s≥2, group the elements in R[p] and its corresponding imaginary vector I[p] into groups of n according to their sequence numbers, where n=2 s+1 For each group, the discrete Fourier transform (DFT) is calculated in blocks using vector registers v0 to v31 of the ARMv8 SIMD hardware. The calculation method is as follows:

[0050] Step 2.2.1.1. For each group of n elements in R[p], label them as a[0], a[1], ..., a[n-1]; similarly, label each group of n elements in I[p] as b[0], b[1], ..., b[n-1];

[0051] Step 2.2.1.2. For each value of k from 0 to n / 2-1, assign the variable ω the value of (exp(2πi / n)) k ,The variable ω is called the rotation factor in the FFT algorithm. The real and imaginary parts of ω are stored as floating-point numbers c and d, respectively. ARMv8 SIMD instructions are used to batch load the data and align the calculations.

[0052] In the ARMv8 architecture, the real and imaginary parts are stored in vector registers respectively, and multiple groups of complex operations are performed simultaneously in a vectorized manner.

[0053] Step 2.2.1.3. Let a[k+n / 2] be a and b[k+n / 2] be b. Calculate the complex number t=(a+bi)×(c+di), which can be converted to a×cb×d+[(a+b)×(c+d)-a×cb×d]i. Store the result of a×cb×d into the floating-point number tr, and store the result of (a+b)×(c+d)-a×cb×d into the floating-point number ti. The converted formula only requires three multiplication operations: a×c, b×d, and (a+b)×(c+d). Compared to the original formula's four multiplication operations: a×c, a×d, b×c, and b×d, this eliminates one multiplication operation, resulting in better performance.

[0054] Step 2.2.1.4. Calculate a[k]-tr and store it in a[k+n / 2]; calculate b[k]-ti and store it in b[k+n / 2]; calculate a[k]+tr and store it in a[k]; calculate b[k]+ti and store it in b[k];

[0055] Step 2.2.1.5. After the DFT calculations for R[p] and I[p] are completed, if s = L for R[p], then both R[p] and I[p] are at the head of their respective queues. Dequeue R[p] and I[p] and write their values ​​to the corresponding locations in memory used to store the calculation results. During this process, the ARMv8 pipeline is used to optimize storage operations.

[0056] Step 2.2.2, if s=1 or s=0, group the elements in R[p] into groups of n according to their sequence numbers, where n=2 s+1 ; For each group, calculate its discrete Fourier transform DFT; the calculation method is as follows:

[0057] Step 2.2.2.1. For each group of n elements in R[p], label them as a[0], a[1], ..., a[n-1];

[0058] Step 2.2.2.2. For each value of k from 0 to n / 2-1, assign the variable ω the value of (exp(2πi / n)) k , the real and imaginary parts of ω are stored as floating point numbers c and d respectively;

[0059] Step 2.2.2.3. If s = 1, denote a[k + n / 2] as a, calculate the complex number t = a(c + di), store the result of a × c into the floating-point number tr, and store the result of a × d into the floating-point number ti; create I[p] in the memory space initialized in step 2.2.1.5, add it to the imaginary number queue from the end, and execute step 2.2.1.4;

[0060] Step 2.2.2.4. If s = 0, then d is 0; calculate tr = a[k+n / 2]×c; calculate a[k]-tr and store it in a[k+n / 2]; calculate a[k]+tr and store it in a[k], and use NEON's st1 instruction to quickly write the vector to memory to avoid the inefficiency of a single scalar write operation.

[0061] Step 3: Add the new real vector to the queue and repeat step 2.

[0062] Specifically, update j+=1 and go to step 2.1.

[0063] In summary, this invention improves the storage of FFT data to be processed, thus avoiding the waste of storage space and computing power in R2C-type FFT calculations. Furthermore, the improved data structure is highly amenable to data parallelization and, when combined with appropriate computational methods, can significantly increase computational speed in SIMD architectures, particularly vector architecture platforms.

[0064] In addition, the ARMv8 architecture provides several advantages for the FFT algorithm: 1. SIMD vectorized calculation. ARMv8 provides a series of vectorized instructions that allow one instruction to operate on multiple sets of data, greatly improving computing efficiency. 2. The ARMv8 architecture supports multi-stage pipeline design and can simultaneously process multiple multiplication and addition operations in the FFT algorithm. 3. Memory access optimization. The ARMv8 processor allows efficient aligned memory access, significantly reducing memory access latency in FFT operations. 4. Register utilization. ARMv8 provides a total of 32 vector registers that can store multiple sets of data at a time, reducing the number of data loading and storage times in the FFT algorithm.

[0065] The present invention fully combines the hardware design characteristics of the ARMv8 SIMD architecture. By utilizing its vector registers, pipeline execution mechanism and instruction set optimization, it further improves the computing efficiency and resource utilization while optimizing the FFT algorithm.

[0066] like Figure 2 Figure 1 shows a data structure for storing FFT data to be processed, provided by an embodiment of the present invention. This data structure includes two queues: a queue on the left, of length L, storing real data vectors; and a queue on the right, of length L-2, storing imaginary data vectors. Each element in the queue is a vector of N floating-point numbers of size size.

[0067] like Figure 3a and Figure 3b FIG2 is a schematic diagram of a method for iterative FFT calculation (butterfly operation) according to an embodiment of the present invention. Obviously, in actual use, this process will be performed in a data-parallel manner (i.e., iterating multiple pairs of data simultaneously) and pipelined.

[0068] In one embodiment of the present invention, a computational method is provided for improving the computational speed and reducing storage overhead when performing R2C FFT operations using a complex FFT algorithm. First, a real vector is reversed and then queued in memory. By storing the real and imaginary parts of the complex number in two separate vectors (i.e., a real vector and an imaginary vector), the waste of storage space and computing power commonly associated with R2C operations using a complex FFT algorithm can be avoided.

[0069] At the same time, the calculations in the complex FFT algorithm involve a large number of repeated addition and multiplication operations between the real part values, imaginary part values ​​and rotation factors. Since the present invention adopts the method of storing the real part and imaginary part in two vectors respectively, addressing is more convenient when continuously reading and writing numbers, and it is more friendly to the single instruction multiple data (SIMD) computing platform, especially the ARMv8 architecture platform.

[0070] The ARMv8 architecture's instruction set, through SIMD technology, provides powerful support for vectorized operations. In this paper, since the real and imaginary parts are stored as independent vectors, this storage structure better matches the ARMv8 Neon vector registers. This operating mode fully utilizes Neon's registers and pipeline design, further improving computational efficiency.

[0071] An embodiment of the present invention also provides an electronic device, which may have relatively large differences due to different configurations or performance, and may include one or more processors (central processing units, CPU) and one or more memories, wherein the memories store at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the steps of the above-mentioned FFT operation method based on the SIMD computing platform.

[0072] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including instructions. The instructions are executable by a processor in a terminal to perform the aforementioned FFT calculation method based on a SIMD computing platform. For example, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device.

[0073] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0074] References in the specification to "one embodiment," "an embodiment," "exemplary embodiments," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement that feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0075] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] The present invention encompasses any alternatives, modifications, equivalents, and solutions that fall within the spirit and scope of the present invention. To provide a thorough understanding of the present invention, specific details are described in detail below in connection with the preferred embodiments of the present invention, but those skilled in the art will be able to fully understand the present invention without these detailed descriptions. Furthermore, to avoid unnecessary confusion regarding the essence of the present invention, well-known methods, processes, procedures, components, and circuits have not been described in detail.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An FFT calculation method based on a SIMD computing platform, characterized in that: The following steps are involved: Step 1. Obtain a vector set R consisting of real vectors of length N. Real vectors are stored as floating-point numbers of length size, and allocate 2L-2 blocks of continuous storage space of length N×size in memory; where N is an integer power of 2 and L is the logarithm of N with base 2. Step 2: The real vectors in R are sequentially sent into the continuous storage space of length N × size allocated in step 1 to form a queue, and pipeline FFT operations are performed based on the ARMv8 SIMD architecture. The memory contains a real queue of length L and an imaginary queue of length L-2, which store the real and imaginary vectors of complex numbers, respectively. The real vectors that have completed L operations and the imaginary vectors that have completed L-2 operations will be dequeued. Step 3: Add the new real vector to the column and repeat step 2; The pipeline FFT operation is performed on the real vector sent from R into the continuous storage space, including: Step 2.

1. Send the real vector R[j] to the end of the queue formed in step 1, and perform "bit-reversal" on the sequence numbers of each element in R[j], that is, reverse the binary value of the sequence number bit by bit, and reorder the elements according to the permuted sequence number; Step 2.2, perform pipeline FFT iterations on the real vectors R[j-L+1], R[j-L+2], ..., R[j] and the corresponding imaginary vectors I[j-L+1], I[j-L+2], ..., I[j-2] in memory in descending order of sequence number, and use the SIMD instruction set of the ARMv8 architecture to improve parallel processing efficiency. The SIMD instruction set includes: ld1, st1, and fmul; Among them, the real vector and the corresponding imaginary vector in the memory are subjected to pipeline FFT iteration from high to low in sequence, including: Step 2.2.

1. For any real vector R[p], let s be the number of iterations it has gone through; if s ≥ 2, group the elements in R[p] and its corresponding imaginary vector I[p] into groups of n according to their sequence numbers, where n = 2 s+1 ; For each group, calculate its discrete Fourier transform DFT; Step 2.2.2, if s=1 or s=0, group the elements in R[p] into groups of n according to their sequence numbers, where n=2 s+1 ; For each group, calculate its discrete Fourier transform DFT.

2. The FFT calculation method based on the SIMD computing platform according to claim 1, characterized in that: If s ≥ 2, for each group, calculate its discrete Fourier transform DFT, including: Step 2.2.1.

1. For each group of n elements in R[p], label them as a[0], a[1], ..., a[n-1]; similarly, label each group of n elements in I[p] as b[0], b[1], ..., b[n-1]; Step 2.2.1.

2. For each value of k from 0 to n / 2-1, assign the variable ω the value of (exp(2πi / n)) k ,The variable ω is called the rotation factor in the FFT algorithm.,The real and imaginary parts of ω are stored as floating-point numbers c and d, respectively.,The ARMv8 SIMD instructions are used to batch load the data and align the calculations; Step 2.2.1.

3. Let a[k+n / 2] be a and b[k+n / 2] be b. Calculate the complex number t = (a+bi) × (c+di), and convert the equation to a × cb × d + [(a+b) × (c+d) - a × cb × d]i. Store the result of a × cb × d into the floating-point number tr, and store the result of (a+b) × (c+d) - a × cb × d into the floating-point number ti. The converted equation requires only three multiplication operations: a × c, b × d, and (a+b) × (c+d). Step 2.2.1.

4. Calculate a[k]-tr and store it in a[k+n / 2]; calculate b[k]-ti and store it in b[k+n / 2]; calculate a[k]+tr and store it in a[k]; calculate b[k]+ti and store it in b[k]; Step 2.2.1.

5. After the DFT calculations for R[p] and I[p] are completed, if s = L for R[p], then both R[p] and I[p] are at the head of their respective queues. Dequeue R[p] and I[p] and write their values ​​to the corresponding locations in memory used to store the calculation results. During this process, the ARMv8 pipeline is used to optimize storage operations.

3. The FFT operation method based on the SIMD computing platform according to claim 2, characterized in that: If s=1 or s=0, for each group, calculate its discrete Fourier transform DFT, including: Step 2.2.2.

1. For each group of n elements in R[p], label them as a[0], a[1], ..., a[n-1]; Step 2.2.2.

2. For each value of k from 0 to n / 2-1, assign the variable ω the value of (exp(2πi / n)) k , the real and imaginary parts of ω are stored as floating point numbers c and d respectively; Step 2.2.2.

3. If s = 1, denote a[k + n / 2] as a, calculate the complex number t = a(c + di), store the result of a × c into the floating-point number tr, and store the result of a × d into the floating-point number ti; create I[p] in the memory space initialized in step 2.2.1.5, add it to the imaginary number queue from the end, and execute step 2.2.1.4; Step 2.2.2.

4. If s=0, then d is 0; calculate tr=a[k+n / 2]×c; calculate a[k]-tr and store it in a[k+n / 2]; calculate a[k]+tr and store it in a[k].

4. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the FFT operation method based on the SIMD computing platform according to any one of claims 1 to 3.

5. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the FFT operation method based on the SIMD computing platform according to any one of claims 1 to 3.

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