Reference circuit recommendation method and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of PCB design or chip design, in particular to a reference circuit recommendation method and electronic equipment, which can actively recommend a reference circuit, do not need a user to manually search a related circuit, improve the drawing operation efficiency and reduce the time consumption of manually browsing a historical schematic diagram. The method comprises the following steps: recommending at least one reference circuit candidate item matched with a key device according to the key device inserted in a canvas; in response to a user instruction, a reference circuit is determined from the at least one reference circuit candidate.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB design or chip design, and in particular to a reference circuit recommendation method and electronic equipment. Background Art

[0002] Integrated circuit hardware manufacturers can effectively leverage the experience gained from historical schematics when developing new projects, using classic circuit modules as reference circuits. This can improve operational efficiency, shorten product development cycles, and reduce product costs. Currently, hardware engineers typically need to manually search for reference circuits within schematics, which is time-consuming and requires further improvement in search efficiency. Summary of the Invention

[0003] The embodiments of the present application provide a reference circuit recommendation method and electronic device, which can proactively recommend reference circuit candidates that match key components to users without requiring users to manually search, thereby improving search efficiency and saving time.

[0004] In a first aspect, an embodiment of the present application provides a reference circuit recommendation method, which recommends at least one reference circuit candidate that matches the key component inserted in the canvas; and determines a reference circuit from the at least one reference circuit candidate in response to a user instruction.

[0005] Based on the key components currently inserted by the user in the canvas, reference circuit candidates that match the key components are actively recommended to the user, eliminating the need for the user to manually search through multiple schematics, saving search time and improving drawing efficiency.

[0006] In one embodiment, before recommending at least one reference circuit candidate that matches the key component, at least one reference circuit candidate may be determined.

[0007] The process of determining at least one reference circuit candidate, i.e., automatically extracting multiple reference circuits from a schematic diagram, achieves automatic extraction and identification of reference circuits, eliminating the need for manual user search. For example, a schematic parsing module and a local circuit extraction module can be used to extract local circuits as reference circuits. Alternatively, a reference circuit calculation module (optional) can be used to extract features and perform cluster analysis on multiple local circuits to obtain reference circuit candidates in multiple categories (also referred to as application scenarios).

[0008] In one possible implementation manner, determining at least one reference circuit candidate may be determining a reference circuit candidate in at least one application scenario, where one application scenario includes at least one reference circuit candidate; recommending at least one reference circuit candidate that matches a key component may be recommending a reference circuit candidate for at least one application scenario corresponding to the key component; and determining a reference circuit from at least one reference circuit candidate may be determining a reference circuit from the reference circuit candidates for at least one application scenario.

[0009] Recommending different categories of reference circuit candidates according to different application scenarios can help users quickly select the required category when there are a large number of reference circuit candidates, and then further filter out reference circuits that meet the needs from the corresponding category.

[0010] In one possible implementation, determining at least one reference circuit candidate can include determining a local circuit containing key components based on a schematic file; constructing a graph structure corresponding to the local circuit; determining an embedding vector corresponding to the graph structure based on a graph neural network model GNN; and determining a reference circuit candidate for at least one application scenario based on multiple embedding vectors.

[0011] The schematic parsing module and the local circuit extraction module are used to identify the local circuit containing key components based on the schematic file. The graph neural network model (GNN) is used to determine the embedding vector corresponding to the graph structure. Based on multiple embedding vectors, the reference circuit calculation module is used to identify candidate reference circuits for at least one application scenario.

[0012] Based on the schematic file, a local circuit containing key components is determined. The method can be to first obtain a bipartite graph based on the schematic file; the bipartite graph includes a first node and a second node, the first node is used to represent the component, the second node is used to represent the network, and the first connection edge between the first node and the second node is used to represent the pin; determine the key component; determine the device category corresponding to each first node in the bipartite graph, and the network category corresponding to each second node; use the key component as the source node and the specified first node or second node as the target node, and search for the signal transmission path from the source node to the target node according to the penetration rules of each component category and / or each network category; extract the peripheral circuit of the key component based on the signal transmission path to obtain the local circuit containing the key component.

[0013] The first node is the device node, and the second node is the network node. Key components are identified, meaning whether the pin count of the device currently dragged or inserted into the drawing window canvas meets a preset threshold. If so, it is identified as a key component. A depth-first search is performed with the key component as the source node and the specified (i.e., user-defined or default rules supported) device node or network node as the target node. Penetration rules are used to determine whether the device or network of the next node in the current search path can be penetrated when performing a depth-first search.

[0014] By combining depth-first search and penetration rules, local circuits are automatically extracted based on bipartite graphs, which is one of the key operations for achieving active reference circuit recommendation.

[0015] In one possible implementation, searching for the signal transmission path from the source node to the target node may be performed by using a depth-first search algorithm to search for the signal transmission path from the source node to the target node.

[0016] In one possible implementation, the graph structure includes multiple third nodes, where the third nodes are used to represent devices or networks; and the second connecting edges between different third nodes are directed edges.

[0017] To construct a graph structure corresponding to a local circuit, devices or networks in the local circuit can be represented by third nodes. Directed second connecting edges are constructed between different third nodes based on signal direction to obtain a graph structure. To prevent confusion, nodes in the graph structure are defined as third nodes. Third nodes can represent either device nodes or network nodes. The graph structure can contain only one type of node, and the edges between nodes must be directed.

[0018] In one possible implementation, based on the graph neural network model GNN, determining the embedding vector corresponding to the graph structure can be to determine the original features corresponding to each third node in the graph structure; inputting the node features into the trained GNN, and outputting the embedding vector corresponding to the graph structure.

[0019] In one possible implementation, the GNN includes an encoder and a decoder; based on the graph neural network model GNN, before determining the embedding vector corresponding to the graph structure, the encoder and decoder can also be trained based on a self-supervised method of mask node reconstruction to obtain the trained GNN.

[0020] In one possible implementation, a self-supervised method based on mask node reconstruction is used to train an encoder and a decoder, which may be to determine at least one third node in the graph structure as a target node to be masked; encode the original features of each node in the graph structure by the encoder to obtain an encoded first graph feature; perform a masking operation on the feature of the target node in the first graph feature to obtain a masked second graph feature; perform a decoding operation on the second graph feature to obtain a decoded third graph feature; calculate the value of a loss function based on the original graph feature and the third graph feature; wherein the original graph feature includes the original features corresponding to each third node in the graph structure; and optimize the trainable parameters in the encoder and the decoder based on the value of the loss function.

[0021] The above training method is a self-supervised learning method based on mask node reconstruction. The GNN model after training can effectively extract the whole-image features of the local circuit. Through the whole-image features (the embedding vector corresponding to a local circuit), classification can be performed to obtain multiple categories of reference circuit candidates.

[0022] In one possible implementation, based on multiple embedding vectors, determining reference circuit candidates for at least one application scenario can be performed by performing cluster analysis on the multiple embedding vectors, and using local circuits corresponding to the embedding vectors clustered into the same category as reference circuit candidates under the same application scenario to obtain reference circuit candidates for at least one application scenario.

[0023] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, wherein the processor is configured to execute a computer program or instruction in a memory to implement any of the methods described above.

[0024] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed by a processor, the method as described in any one of the above items is implemented.

[0025] In a fourth aspect, an embodiment of the present application also provides a chip system, comprising: a communication interface for inputting and / or outputting data; a processor for executing a computer executable program so that a device equipped with the chip system executes any of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a flow chart for manually searching for a reference circuit in a solution in the related art;

[0027] Figure 2 A schematic diagram of a flow chart of manually searching for a reference circuit based on CBB in another solution in the related art;

[0028] Figure 3 This is an example diagram of an interface for actively recommending reference circuit candidates in the reference circuit recommendation method provided in an embodiment of the present application;

[0029] Figure 4 An example diagram of the system architecture of the reference circuit recommendation method provided in an embodiment of the present application;

[0030] Figure 5 A schematic diagram of a process flow for automatically recommending candidate reference circuits in a reference circuit recommendation method according to an embodiment of the present application;

[0031] Figure 6 An example diagram of a system architecture in a specific embodiment of the reference circuit recommendation method provided in an embodiment of the present application;

[0032] Figure 7 This is an example diagram of a bipartite graph in the reference circuit recommendation method provided in an embodiment of the present application;

[0033] Figure 8 A schematic diagram of a flow chart for extracting a local circuit based on a bipartite graph in a reference circuit recommendation method provided in an embodiment of the present application;

[0034] Figure 9 This is an example diagram of a graph structure corresponding to a local circuit constructed in the reference circuit recommendation method provided in an embodiment of the present application;

[0035] Figure 10 A schematic diagram of a flow chart of training a GNN model using a self-supervised learning method based on mask node reconstruction in a reference circuit recommendation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to better understand the technical solutions of this specification, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] It should be clear that the embodiments described are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this specification.

[0038] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a," "an," "the," and "the" used in the examples of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0039] When developing new projects for hardware products such as integrated circuits, historical experience can be reused by searching for schematics of related projects or creating common building blocks (CBBs).

[0040] In one solution of related technology, hardware engineers can follow the following Figure 1 The order shown is to reuse the historical schematic diagram experience. First, the hardware engineer needs to manually search for related schematic diagrams to find schematic diagrams with similar functions to the current design schematic diagram; then, open each page of the schematic diagram one by one, locate the related page, that is, locate the schematic page where the related device is located, and judge whether the circuit module in each page meets the current requirements. If the current circuit module does not meet the requirements, continue to open the remaining schematic diagrams. If the current circuit module meets the requirements, the circuit is a reference circuit, and the reference circuit is found. The reference circuit is copied to the schematic diagram currently being drawn. After that, the hardware engineer needs to manually modify the reference circuit according to the actual situation.

[0041] This solution requires hardware engineers and other staff to manually open the schematic diagram for review, which is time-consuming. Secondly, this solution does not archive circuit modules separately, and circuit modules need to be searched one by one in the schematic diagram, which has a long update cycle for circuit modules. Furthermore, each search requires manual review, and manual judgment is required on the correctness of the circuit, which makes maintenance difficult.

[0042] In another solution in the related art, Figure 2 As shown, hardware engineers use the Common Circuit Block (CBB) to query the device code and search the historical CBB library for the CBB containing the device code. If the CBB exists, they open each relevant CBB one by one to determine whether it meets the current requirements. They then update the CBB and copy it to the current schematic project for use. If it doesn't exist, they query the schematic of the device's parent board. Alternatively, if the CBB containing the device code does not meet the current requirements, they can also query the schematic of the device's parent board, manually modify a similar circuit, and copy the modified circuit as a reference to the currently drawn schematic.

[0043] In this other solution, the CBB module needs to be manually delineated and then stored in the warehouse, which takes a long time to produce. In addition, after entering the database, the CBB may not meet the usage scenarios of others when it is called by others, and the CBB module needs to be manually modified. Therefore, the update cycle of the CBB module is long and maintenance is more difficult.

[0044] In view of this, in order to solve one or more problems including time-consuming and low search efficiency of manual search of historical circuit modules, difficulty in manual maintenance, long update cycle of historical circuit modules, and unclear functional division, an embodiment of the present application proposes a reference circuit recommendation method. The method recommends at least one reference circuit candidate that matches the key components inserted in the canvas, and then, in response to user instructions (such as a selection operation), determines a reference circuit from at least one reference circuit candidate.

[0045] The method proposed in the embodiment of the present application can be applied to the PCB design field or the chip design field. For example, one of the application scenarios of this method can be to actively recommend circuits to users when drawing in the PCB design field. Alternatively, circuit diagrams are also used in the chip design field, and this method can be applied to the application scenario of chip design in the chip design field.

[0046] Specifically, the method can be applied to various applications that support drawing circuit diagrams. For example, the product corresponding to the method can be a plug-in or an upgrade program. The plug-in can be applied to the application to implement the reference circuit recommendation method proposed in the embodiment of the present application; or, the reference circuit recommendation method proposed in the embodiment of the present application can be implemented by upgrading the application.

[0047] Actively recommend at least one reference circuit candidate that matches the key component to the user, where the match can be that the reference circuit contains a component with the same code as the key component, or that the reference circuit contains a component that has a mapping relationship with the code of the key component.

[0048] For example, in some embodiments, the key component code can be used as an index to search the reference circuit database for reference circuits containing components with the same device code and recommend them to the user as candidate reference circuits. Alternatively, in other embodiments, it is not ruled out that in some practical applications, the device codes contained in the reference circuit required by the user may not be consistent with the codes of the key components currently dragged into the canvas by the user. In this case, a mapping table can be established to record the mapping relationship between the codes of the key components and the codes of the target components. During the search, the mapping table can be used to search for target components that have a mapping relationship with the code of the key component currently inserted into the canvas by the user, and multiple local circuits containing the target components can be selected from the reference circuit database and recommended to the user as at least one candidate reference circuit.

[0049] Furthermore, in some embodiments, recommending at least one reference circuit candidate that matches the key component may involve displaying multiple reference circuit candidates on the application interface. For example, at least one reference circuit candidate that matches the key component may be displayed in an appropriate location such as the side, bottom, or lower right corner of the drawing window. Alternatively, a shortcut button for inserting a reference circuit may be added to the toolbar, and a user clicking the shortcut button automatically displays one or more recommended reference circuit candidates. Of course, in other embodiments, a shortcut button for inserting a reference circuit may also be provided in the menu bar.

[0050] In some embodiments, the at least one reference circuit candidate recommended to match the key component may be a candidate recommended for different application scenarios. For example, if the reference circuit database contains multiple reference circuits that match the current key component, the multiple matching reference circuits can be classified into multiple categories. Since reference circuits under a category are often used in the same application scenario, a category can be used as an application scenario. In other words, to determine the reference circuit candidate for at least one application scenario, the user can first select an application scenario from the recommended reference circuit candidates under at least one application scenario. Then, under the application scenario category, multiple specific reference circuit candidates are displayed to the user. Based on the user's selection, one candidate is determined as the reference circuit to be added.

[0051] For example, Figure 3 In the example interface shown, the user has inserted a key component T01 into the current canvas. Based on the device code of the key component T01, the reference circuit database is searched for reference circuits containing the same device code or related device codes (i.e., there is a mapping relationship), and the reference circuits are displayed to the user as candidates in the interface. For example, Figure 3 The figure shows three reference circuit candidates, namely R01, R02, and R03. Users can select the candidate that best meets their requirements as the reference circuit. This eliminates the need for users to flip through multiple schematics or open CBBs one by one, improving search efficiency or recommendation efficiency and reducing time consumption.

[0052] In some embodiments, the reference circuit candidates R01, R02, and R03 may be reference circuit candidates for three different application scenarios, indicating that three categories of reference circuit candidates are recommended, wherein one application scenario may include multiple specific reference circuits. When the user selects one of the application scenarios (also referred to as a recommendation category), specific reference circuit candidates will continue to be displayed to the user, and the user can select a specific circuit from them as a reference circuit.

[0053] In other embodiments, the reference circuit candidates R01, R02, and R03 represent specific reference circuits without dividing them into different application scenarios or different recommendation categories. A circuit selected by the user from R01, R02, and R03 is the reference circuit.

[0054] It should be noted that Figure 3 The circuits shown are for illustrative purposes only and are not intended to limit the key components and reference circuit candidates actually presented.

[0055] like Figure 4 As shown, the reference circuit recommendation method proposed in the embodiment of the present application can be based on the following Figure 4 The system architecture shown is implemented.

[0056] First, a reference circuit database needs to be constructed. The process of constructing a reference circuit database is the process of determining at least one reference circuit candidate (e.g., a reference circuit candidate for at least one application scenario). Specifically, multiple reference circuits can be automatically extracted from the schematic database to form the reference circuit database. Alternatively, the reference circuit database can be a database composed of multiple reference circuits automatically extracted from the schematics in the schematic database.

[0057] In the schematic operation process, the user drags a device into the drawing page, and the device is identified as a key device. Next, based on the device code of the key device, the reference circuit candidate is actively pushed to the user or actively pushed to the user in response to the user's instruction. For example, the user instruction can be a button that the user clicks to quickly insert or recommend a reference circuit. The system automatically obtains the circuit module (reference circuit) that matches the key device from the reference circuit database, and displays it as a candidate in the drawing window or other displayable location. The user can complete the design by selecting the circuit module (reference circuit) of the corresponding category or selecting a specific reference circuit candidate and inserting it into the drawing page. Among them, the reference circuit is in a modifiable format, which means that the user is supported to modify the reference circuit.

[0058] After the schematic is drawn, it can be archived into the schematic database to provide new reference circuit materials, that is, the schematic database and the reference circuit database can be continuously updated, supporting the addition of the latest classic circuit modules as reference circuit candidates.

[0059] Key components are those with a pin count greater than or equal to a predetermined threshold. The threshold can be a constant. For example, if the threshold is 5, then if the pin count of the component currently dragged into the canvas is greater than or equal to 5, the component will be selected as the key component. Based on the key component's code, matching reference circuit candidates will be searched in the reference circuit database and proactively recommended to the user. The threshold can also be set to other values, such as 4 or 6, or can be user-defined, with the user-set value being used as the threshold.

[0060] Specifically, the following method can be used to automatically extract reference circuits from schematic diagrams: based on the schematic diagram, local circuits are extracted, and a graph structure corresponding to the local circuit is constructed. Based on the graph neural network model GNN, the embedding vector corresponding to the graph structure is determined. After obtaining multiple embedding vectors, reference circuit candidates for at least one application scenario are determined based on the multiple embedding vectors.

[0061] For example, Figure 5 As shown, based on the schematic diagram, the local circuit containing key components is first extracted. Then, using the components and networks in the local circuit as nodes, directed edges are established based on the signal transmission direction to construct the graph structure of the local circuit. The node features (raw features) of each node in the graph structure are determined, and the raw features of each node are input into the trained GNN model to extract the entire graph features of the local circuit and output an embedding vector. Generally speaking, one embedding vector can be obtained for a local circuit. After obtaining multiple embedding vectors based on multiple local circuits, the multiple embedding vectors are clustered and analyzed. Based on the clustering results, multiple categories of reference circuit candidates are obtained. Each category corresponds to an application scenario, and each application scenario contains at least one reference circuit candidate.

[0062] To facilitate understanding, a brief explanation of the technical terms that may be involved is given first:

[0063] Schematic diagram: In hardware PCB engineering design, a circuit diagram is formed by drawing the relationship between devices and network connections.

[0064] Drawing page: Schematics can be stored in the form of drawing pages. Each schematic page will draw a certain circuit module, and the entire schematic is composed of all the drawing pages connected.

[0065] Device code: Hardware devices are recorded by a unified code. Through the device code, the relevant information of the device can be found in the device library.

[0066] Network: The physical connection between pins, which can also be called a transmission line. For example, microstrip line, stripline, coaxial cable, jumper wire, etc. are all networks.

[0067] Network coding: The network is recorded by a unified code. Through network coding, relevant information of the network can be found in the corresponding library.

[0068] Critical device: A device whose pin count exceeds a predetermined threshold.

[0069] Small components: resistors, inductors, capacitors, as well as diodes, transistors and other small devices.

[0070] Bipartite graph: It has two different types of nodes, and there is no connection between nodes of the same type.

[0071] Penetration rules: These rules determine whether a device needs to be penetrated. Device signals and power, when transmitted over a network, must continue penetrating through certain small devices until they reach the next layer of circuit connection. However, some devices do not need to be penetrated, so penetration rules are set to indicate whether penetration is allowed.

[0072] A specific embodiment is listed below.

[0073] like Figure 6 As shown, the method proposed in the embodiment of the present application can be based on Figure 6 The system architecture shown in the figure is executed. Through the three modules of schematic parsing, local circuit extraction, and reference circuit calculation (optional), reference circuits are automatically extracted from the schematic database. This enables automatic extraction of classic schematic circuits, automatic classification of circuit modules, and automatic search for similar circuit modules, solving the problems of complex manual search and difficult manual maintenance.

[0074] The schematic parsing module is used to create a bipartite graph based on the schematic file.

[0075] Schematic files are organized into pages. Each page records only the location and connection relationships of the device and network elements on the current page. This is a proprietary file format. Multiple devices may be connected to the same network, and the same device may be connected to multiple networks. By analyzing the connections between devices in the schematic, the schematic file can be abstracted into the connections between devices and networks. Devices are considered as nodes, and networks as nodes. This allows us to construct a bipartite graph of the device-network node connections.

[0076] For example, Figure 7 As shown in the figure, rectangles represent device nodes, circles represent network nodes, and the edges between device and network nodes represent pins. That is, the pins connecting the device to the network are represented by the edges between the device and network nodes. A bipartite graph can be an undirected graph.

[0077] It should be noted that when building a bipartite graph, you can construct the corresponding bipartite graph for each page. After obtaining the bipartite graph for each page, you can stitch the bipartite graphs corresponding to different pages in the same schematic into a complete global bipartite graph. In the following steps, unless otherwise specified, the bipartite graph used refers to the global bipartite graph.

[0078] Local circuit extraction module: It is used to obtain the signal transmission path around the key device based on the bipartite graph through depth-first search and penetration rule, and extract the local circuit with the key device as the source node.

[0079] For example, Figure 8 As shown, first identify the device category corresponding to each device node and the network category corresponding to each network node in the bipartite graph. After determining the key components, a depth-first search algorithm is used to search for paths around the key components. When performing a depth-first search, the penetration rule can be combined. For example, when a node is searched, the network category or device category of the node is obtained, and the penetration rule is used to determine whether the node needs to be penetrated. If so, the search continues through the node to the next node on the path until the target node is reached. If the penetration rule determines that the currently searched node does not need to be penetrated, the search on the path is stopped and other paths are searched.

[0080] It should be noted that in the embodiment of the present application, a search method combining a depth-first search algorithm and a penetration rule is adopted. Among them, the search depth of the depth-first search algorithm can adopt a default preset depth or support user-defined settings. The key component is the source node, and the target node can adopt a default node or support user-defined settings. For example, the default preset depth is 10, that is, the search can be stopped when the 10th layer is searched. Alternatively, the user specifies the search depth and the search is performed according to the user-specified search depth.

[0081] Because the power and signal network transmission rules for similar devices are generally similar, network nodes and / or device nodes in the device-network bipartite graph constructed in the schematic parsing module can be categorized by identifying them using network names (network codes) and / or device codes. For example, networks can be automatically categorized into power, signal, ground, and other network categories.

[0082] For example, as a feasible classification method, in network coding, "GND" generally represents a ground network, which can be classified as a ground network category; "*V*" generally represents a power network, where "*" represents a number, for example, "5V3" and "3V3" can both be classified as power network categories; other networks except ground networks and power networks are classified as signal network categories.

[0083] Similarly, the device code generally contains device type information. Based on the device code (device name), devices can be divided into multiple categories. For example, they can be divided into clocks, power supplies, small devices, ICs (Integrated Circuits), etc.

[0084] After determining the device and network categories, devices or networks of the same category can be processed using the same penetration rules.

[0085] Automatically identify multi-pin devices as key components in the schematic diagram, using the key component node as the source node and a specified device node or network node as the target node. Using a depth-first search algorithm, starting from the key component node (source node), the system searches for the signal transmission paths surrounding the key component based on the penetration rules for each type of device and each type of network it passes through. Based on the signal transmission paths, the system extracts the peripheral circuits of the key component and obtains the circuit module where the key component resides as the local circuit.

[0086] The local circuit may be in a bipartite graph format, and a corresponding local circuit in a schematic diagram format may be determined based on the bipartite graph of the local circuit as a reference circuit. Of course, in some embodiments, the local circuit may be a portion of a schematic diagram determined by searching for a path based on the bipartite graph, and the local circuit may not be in a bipartite graph format but in a schematic diagram format. It should be noted that the reference circuit candidates recommended to the user are local circuits in a schematic diagram format.

[0087] Therefore, in some embodiments, the reference circuit calculation module may not be provided, but only the schematic diagram parsing module and the local circuit extraction module may be included, and the local circuit extracted from the local circuit may be directly recommended to the user as a reference circuit.

[0088] In this embodiment, after obtaining the local circuit, the reference circuit is further extracted through the reference circuit calculation module, and cluster analysis is performed based on the extracted whole-image features to classify multiple reference circuits into different categories for recommendation.

[0089] The reference circuit calculation module is used to extract the whole-graph features of the local circuit. Specifically, the whole-graph features can be represented by an embedded vector.

[0090] Specifically, after obtaining the local circuit where the key components are located, the local circuit (circuit module) is represented in the form of a graph structure, that is, a graph structure corresponding to the local circuit is constructed. Figure 9 As shown in the figure, in the graph structure, device nodes and network nodes are represented by the same node. Unlike the bipartite graph, there is only one type of node in the graph structure, and the edges between nodes are directed edges. The direction of the edge is determined by the signal transmission direction or the network transmission direction.

[0091] After the graph structure is constructed, the original features (also called initial features) of each node in the graph structure are determined.

[0092] Exemplarily, in this embodiment, the original features of each node used to represent a device in the graph structure can be determined based on one or more of the device's type, description, number of pins, and resistance, capacitance, and inductance values, where the type is the device category, and different device categories can be numbered to convert the category into a specific number. Resistance, capacitance, and inductance values ​​are specific resistance values, capacitance values, or inductance values ​​of devices such as resistors, capacitors, and inductors. It should be noted that the description is text, and a natural language processing (NLP) model can be used to obtain features corresponding to the text. For example, the text used to describe the device is input into the NLP model, and the vector extracted by the NLP model output is spliced ​​with the type number, number of pins, and resistance, capacitance, and inductance values ​​to obtain the original features corresponding to a complete device node.

[0093] Similarly, based on one or more of the network's signal voltage classification, voltage value, and network transmission direction, the original features used to represent the nodes in the graph structure can be constructed. Signal voltage classifications can use different numbers to represent different categories, and different network transmission directions can use different numerical values. Thus, by combining one or more of these features, the original features of the network nodes can be obtained.

[0094] It should be noted that the original features of device nodes and network nodes may be heterogeneous. These heterogeneous features need to be converted into homogeneous features. This means converting original features of different dimensions into features of the same dimension, maintaining the dimensionality of the original features of the network and device nodes. For example, the original features of a homogeneous network or device are an M*1-dimensional feature vector, where M is the dimension of the elements in the original features.

[0095] After determining the original features of each node in the graph structure, the self-supervised method of mask node reconstruction is used to combine the topological connection relationship of the local circuit and the original features of each node. Through the GNN model, the features of the entire graph are extracted. For example, if the local circuit contains N nodes, then the extracted features of the entire graph can be an M*N dimensional embedding vector.

[0096] Specifically, the reference circuit calculation module can be implemented based on a graph neural network model (Graph Neural Networks, GNN). For example, in this embodiment, the GNN can be a GraphMAE (Self-Supervised Masked Graph Autoencoders). The GraphMAE proposed in the embodiment of the present application includes an encoder and a decoder, and both the encoder and the decoder can be implemented based on a GIN (Graph Isomorphism Network) model.

[0097] Before putting GraphMAE into use, it needs to be trained. The training process is as follows: Figure 10 shown.

[0098] The graph structure corresponding to the local circuit contains 9 nodes. After determining the original features of each node, the nodes to be masked are randomly marked, for example, Figure 10 As shown in , nodes indicated by dashed lines are nodes to be masked. For example, a node coded as R91012, a node coded as VCC_12V_PICO, and a node coded as J7001 are marked as nodes to be masked.

[0099] Afterwards, the original features of the 9 nodes in the graph structure and the information used to represent the topological connection relationship between the nodes in the graph structure are input into the encoder, and the encoder performs encoding operations to obtain the encoded graph features (first graph features). Among them, the information used to represent the topological connection relationship between the nodes in the graph structure can be an adjacency matrix. For example, Figure 10 As shown in the figure, the dimension of the original feature of each node is 5. After encoding the original features of 9 nodes, a 9*4-dimensional first graph feature is obtained.

[0100] It should be noted that, in this embodiment, the encoding process for obtaining the first graph feature may only mark the nodes to be masked, and the mask operation may not be performed on the nodes to be masked. Therefore, the encoding input is the original features of 9 nodes, rather than the original features of 6 nodes. That is to say, in this embodiment, the mask operation can be performed after encoding and before decoding.

[0101] It should be noted that, in other embodiments, it is not ruled out that the mask operation is set in other stages. For example, the input features of the encoder can be masked, and then the masked features are encoded and then decoded. That is, the masked object is not limited to the first image feature after encoding.

[0102] After obtaining the first graph feature through encoding, a masking operation is performed based on the first graph feature. Specifically, the features corresponding to the nodes to be masked in the first graph feature are masked. For example, the encoded features corresponding to nodes R91012, VCC_12V_PICO, and node J7001 are masked. That is, the mask code is used to cover the features of the above three nodes in the first graph feature. In other words, the original data in rows 3, 6, and 8 of the first graph feature is deleted and replaced with the mask code, resulting in the masked second graph feature. Exemplarily, the mask code can be a string of random numbers.

[0103] Next, the decoder is used to decode the second graph feature. As can be seen from the figure, the second graph feature has a 9*4 dimension. After the decoding operation, the third graph feature is obtained, which has the same dimension as the original graph feature and a 9*5 dimension.

[0104] Next, the loss function is used to calculate the loss function values ​​corresponding to the original graph features and the third graph features. Based on the loss function values, the trainable parameters in the encoder and decoder are optimized. This is repeated over multiple rounds until the loss function converges, completing the training. For example, the loss function can be a cross-entropy loss function or another loss function.

[0105] It should be noted that as the database is continuously updated, GraphMAE can continue to be trained after it is put into use to continue to improve its performance during use.

[0106] After training, GraphMAE is used to extract the whole graph features of local circuits, such as Figure 10 As shown in Figure 2, the third graph feature is the whole graph feature extracted by GraphMAE, which can also be called an embedding vector.

[0107] It should be noted that the local circuit extraction module is limited to a module for realizing the local circuit extraction function; the reference circuit calculation module is limited to a module that can realize the whole-image feature extraction of the local circuit. Modules that can realize the above functions can be used as local circuit extraction modules and reference circuit calculation modules. Moreover, the above-mentioned schematic analysis module, local circuit extraction module and reference circuit calculation module can be combined as desired, for example, three modules are integrated into the same module, or two of the modules are integrated into the same module. As long as the above functions can be realized, there can be many specific module settings, which are not listed one by one in this manual.

[0108] The rules for extracting local circuits support user-configured rules, and can be replaced by other search algorithms besides the depth-first search algorithm, but are not limited to the depth-first search algorithm.

[0109] In addition, the GNN model can be GraphMAE, and it can also be replaced by training other models to achieve similar effects. That is, this embodiment only uses GraphMAE as an example for illustrative purposes. In actual applications, other models can be used to replace GraphMAE, for example, self-supervised visual representation models (Bidirectional Encoder Image Transformers, BEiT), Graph Transformer, or Graphformer can be used instead.

[0110] Thus, during the usage phase, the trained GraphMAE can be used to extract embedding vectors corresponding to local circuits. After obtaining multiple embedding vectors corresponding to multiple local circuits, cluster analysis can be performed to divide the multiple embedding vectors into different clusters or classes. Specifically, a distance-based clustering algorithm can be used to cluster based on the distance or similarity between different embedding vectors. For example, a clustering algorithm such as K-Means, K-Medoids, or CLARANS can be used.

[0111] After performing cluster analysis, reference circuit candidates for one or more application scenarios can be recommended to the user based on the clustering results. One application scenario can correspond to a candidate set, including at least one reference circuit.

[0112] Thus, in this embodiment, the schematic parsing module, the local circuit extraction module, and the reference circuit calculation module are automatically called in sequence in the background to obtain the circuit modules containing the key components in the schematic project and archive them in the reference circuit database. When the user is drawing, the circuit database can be searched for circuits containing components with the same or corresponding (with a mapping relationship) codes based on the codes of the key components currently inserted by the user. These circuits are recommended to the user as reference circuit candidates. The recommendation method is generally displayed in the drawing window or in an appropriate area of ​​the interface where the drawing window is located.

[0113] From the above, it can be seen that the establishment of CBB in the related art requires manual summary of historical projects, which is inefficient. The solution proposed in the embodiment of the present application pre-builds a reference circuit database, which can realize that when the user draws the schematic diagram, he clicks on the relevant device and automatically recommends the relevant reference circuits from the reference circuit database; it realizes the functions of automatic extraction of classic circuits in the schematic diagram, automatic classification of circuit modules, and automatic search of similar circuit modules, solving the problems of complex manual search and difficult manual maintenance.

[0114] Among them, by constructing a circuit diagram topology structure database (i.e., a reference circuit database) and based on the sub-graph feature (i.e., the whole-graph feature of the local circuit) extraction algorithm, the automatic extraction of the reference circuit of the key component is realized. The circuit module where the component is located can be identified from the complex circuit, eliminating the possibility of omissions and errors in the manual extraction of circuit paths.

[0115] In addition, in some embodiments, the schematic diagram parsing module, the local circuit extraction module, and the reference circuit calculation module are used to extract the subcircuit modules (ie, local circuits) in the schematic diagram and calculate the characteristics of the local circuits.

[0116] Among them, the extraction of local circuits can automatically extract the peripheral circuits of the device based on the penetration rules of each type of device or network, without the need for manual search.

[0117] Optionally, the node features and topological connection relationships contained in the local circuit extracted from the schematic diagram are converted into feature vectors (i.e., embedding vectors), which contain multi-dimensional information and can more accurately achieve similarity matching between different reference circuits, solving the problem of relying on manual identification of different circuits.

[0118] An embodiment of the present application further provides an electronic device, comprising: a processor, wherein the processor is configured to execute a computer program or instruction in a memory to implement the method described in any of the above embodiments.

[0119] Exemplarily, the processor may include one or more processing units, for example, a neural-network processing unit (NPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a digital signal processor (DSP), a baseband processor, etc. The different processing units may be independent devices or integrated into one or more processors. The controller may generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0120] The memory can be used to store computer executable program code, which includes instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function, etc. The data storage area can store data (such as input data, output data) created during the use of the electronic device. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in a memory provided in the processor.

[0121] It should be understood that the structure illustrated in the embodiment of the present invention is merely an example and does not limit the electronic device. The electronic device in the embodiment of the present application may include more or fewer components than shown, or combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0122] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed by a processor, the method described in any of the above embodiments is implemented.

[0123] An embodiment of the present application further provides a computer program product, which includes a program. When the program is executed by an electronic device, the electronic device implements the method described in any of the above embodiments.

[0124] An embodiment of the present application also provides a chip system, including: a communication interface for inputting and / or outputting data; and a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any of the above embodiments.

[0125] The above-mentioned computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device.

[0126] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0127] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0128] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0129] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0130] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

Claims

1. A reference circuit recommendation method, characterized in that: The method comprises: Recommend at least one reference circuit candidate matching the key component according to the key component inserted in the canvas; In response to a user instruction, a reference circuit is determined from the at least one reference circuit candidate.

2. The method according to claim 1, wherein Before recommending at least one reference circuit candidate matching the key component, the method further includes: At least one reference circuit candidate is identified.

3. The method according to claim 2, wherein Identify at least one reference circuit candidate, including: Determining a reference circuit candidate in at least one application scenario, where one application scenario includes at least one reference circuit candidate; Recommend at least one reference circuit candidate that matches the key component, including: Recommending reference circuit candidates for at least one application scenario corresponding to the key components; Determining a reference circuit from the at least one reference circuit candidate includes: A reference circuit is determined from the reference circuit candidates of the at least one application scenario.

4. The method according to any one of claims 1 to 3, wherein Identify at least one reference circuit candidate, including: Based on the schematic file, determine the local circuit containing key components; Constructing a graph structure corresponding to the local circuit; Determine an embedding vector corresponding to the graph structure based on a graph neural network model GNN; Based on the multiple embedding vectors, a reference circuit candidate for at least one application scenario is determined.

5. The method according to claim 4, wherein Based on the schematic file, identify the local circuit containing key components, including: Obtaining a bipartite graph based on a schematic file; the bipartite graph includes a first node and a second node, the first node is used to represent a device, the second node is used to represent a network, and a first connecting edge between the first node and the second node is used to represent a pin; Identify key components; Determine a device category corresponding to each first node in the bipartite graph, and a network category corresponding to each second node; Taking the key device as a source node and the designated first node or second node as a target node, searching for a signal transmission path from the source node to the target node according to penetration rules for each device category and / or each network category; According to the signal transmission path, the peripheral circuit of the key component is extracted to obtain the local circuit including the key component.

6. The method according to claim 5, wherein Searching for a signal transmission path from the source node to the target node includes: A depth-first search algorithm is used to search for a signal transmission path from the source node to the target node.

7. The method according to any one of claims 4 to 6, wherein: The graph structure includes multiple third nodes, and the third nodes are used to represent devices or networks; the second connection edges between different third nodes are directed edges.

8. The method according to any one of claims 4 to 7, wherein Based on the graph neural network model GNN, determining the embedding vector corresponding to the graph structure includes: Determining original features corresponding to each third node in the graph structure; The node features are input into the trained GNN, and the embedding vector corresponding to the graph structure is output.

9. The method according to any one of claims 4 to 8, wherein The GNN includes an encoder and a decoder; Before determining the embedding vector corresponding to the graph structure based on the graph neural network model GNN, the method further includes: Based on the self-supervised method of mask node reconstruction, the encoder and decoder are trained to obtain the trained GNN.

10. The method according to claim 9, wherein The encoder and decoder are trained using a self-supervised method based on mask node reconstruction, comprising: determining at least one third node in the graph structure as a target node to be masked; Encoding the original features of each node in the graph structure by an encoder to obtain encoded first graph features; In the first graph feature, a mask operation is performed on the feature of the target node to obtain a masked second graph feature; performing a decoding operation on the second image feature to obtain a decoded third image feature; Calculating a value of a loss function based on the original graph features and the third graph features; wherein the original graph features include original features corresponding to each third node in the graph structure; Based on the value of the loss function, trainable parameters in the encoder and the decoder are optimized.

11. The method according to any one of claims 4 to 10, wherein: Determine, based on the multiple embedding vectors, a reference circuit candidate for at least one application scenario, including: A cluster analysis is performed on the multiple embedding vectors, and local circuits corresponding to the embedding vectors clustered into the same category are used as reference circuit candidates in the same application scenario, so as to obtain reference circuit candidates for at least one application scenario.

12. An electronic device, characterized in that: The electronic device comprises: A processor, configured to execute a computer program or instruction in a memory to implement the method according to any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored program, wherein the program implements the method according to any one of claims 1 to 11 when executed by a processor.

14. A chip system, characterized in that: include: a communication interface for inputting and / or outputting data; A processor, configured to execute a computer executable program so that a device equipped with the chip system executes the method according to any one of claims 1 to 11.

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