Signal debugging method, electronic device and medium based on dynamic configuration

Abstract

The present application relates to the technical field of signal processing, and particularly relates to a signal debugging method based on dynamic configuration, an electronic device and a medium, which comprises the following steps: S1, dividing a preset cache line into K block information {B1, B2,..., B k ,...,B K}; S2, obtaining a to-be-debugged input signal information list {A1, A2,..., A n ,...,A N}; S3, determining B1 k corresponding to B2 k containing A2 n as a target block identifier, generating a target block identifier list {C1, C2,..., C r ,...,C R}, and storing the target block identifier list in a preset first memory; and S4, grabbing a target debugging input signal from the input signal based on the target block identifier list and the to-be-debugged input signal information list. The present application realizes flexible configuration of signal debugging, and improves the performance of a hardware simulation system.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a signal debugging method based on dynamic configuration, electronic equipment and medium. Background Art

[0002] Current hardware simulation systems, such as those based on field programmable gate array (FPGA) platforms, typically support fully visible signal debugging and partial signal debugging. When a hardware simulation system supports fully visible signal debugging, the sampling performance of the hardware simulation system is affected by the number of signals, and high speed and fully visible signals cannot be achieved simultaneously. Due to the huge amount of data collected, the bandwidth of the hardware simulation system for processing data has a bottleneck, and it can usually only support fully visible signals at a speed of tens of K cycle / s. When a hardware simulation system supports partial signal debugging, although a higher debugging speed can be obtained, when a user needs to change the debugging input signal, it is often necessary to recompile, and flexible configurability cannot be achieved. Therefore, how to achieve flexible and configurable signal debugging and improve the performance of the hardware simulation system has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a signal debugging method, electronic equipment and medium based on dynamic configuration, which realizes flexible configuration of signal debugging and improves the performance of hardware simulation system.

[0004] According to a first aspect of the present invention, a signal debugging method based on dynamic configuration is provided, comprising:

[0005] Step S1: Divide the preset cache line into K block information {B1, B2, .., B k ,...,B K}, B k is the kth block information of the preset cache line, the value range of k is 1 to K, K is the total number of blocks contained in the preset cache line, B k ={B1 k ,B2 k}, B1 k is the kth block identifier, B2 k B1 k A range of bits corresponding to a predetermined cache line, where the predetermined cache line is equal to the sum of the bit widths of M input signals, where M is the total number of input signals;

[0006] Step S2: Get the list of input signal information to be debugged {A1, A2, ..., A n ,...,A N}, A nThe nth input signal to be debugged, the value range of n is 1 to N, N is the total number of input signals to be debugged, N≤M, A n ={A1 n ,A2 n}, A1 n A2 is the nth input signal to be debugged. n The range of bits corresponding to the nth input signal to be debugged in a preset cache line, the data of the input signal to be debugged sampled in each sampling period is stored in one cache line;

[0007] Step S3: All the files containing A2 n Median B2 k Corresponding B1 k Determine the target block identifier and generate a target block identifier list {C1, C2, ..., C r ,...,C R}, and stored in the preset first memory, C r is the rth target block identifier in the target block identifier list, where r ranges from 1 to R, and R≤K;

[0008] Step S4: Based on {C1, C2, ..., C r ,...,C R} and {A1,A2,...,A n ,...,A N}Grab the target debug input signal from the input signal.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. Through the above technical solution, the present invention provides a signal debugging method, electronic device, and medium based on dynamic configuration, which can achieve considerable technological advancement and practicality, and has wide industrial application value, and has at least the following beneficial effects:

[0012] The present invention divides a preset cache line into multiple blocks, sets a corresponding block identifier for each block, obtains an information list of input signals to be debugged based on the corresponding relationship between the input signals to be debugged and the blocks, and configures a target block identifier list in a preset first memory according to debugging requirements, thereby achieving flexible configuration of the signals to be debugged, capturing the target debugging input signal from the input signal, and improving the performance of the hardware simulation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 This is a flow chart of a signal debugging method based on dynamic configuration provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a signal debugging method based on dynamic configuration, such as Figure 1 Shown, including:

[0017] Step S1: Divide the preset cache line into K block information {B1, B2, .., B k ,...,B K}, B k is the kth block information of the preset cache line, the value range of k is 1 to K, K is the total number of blocks contained in the preset cache line, B k ={B1 k ,B2 k}, B1 k is the kth block identifier, B2 k B1 k The corresponding bit range in the preset cache line is equal to the sum of the bit widths of M input signals, where M is the total number of input signals.

[0018] The K blocks may be of equal or unequal sizes, preferably, the K blocks are of equal sizes. The bit widths of different input signals may be equal or unequal.

[0019] Step S2: Get the list of input signal information to be debugged {A1, A2, ..., A n ,...,A N}, A n The nth input signal to be debugged, the value range of n is 1 to N, N is the total number of input signals to be debugged, N≤M, A n ={A1 n ,A2 n}, A1 n A2 is the nth input signal to be debugged. n The bit range corresponding to the nth input signal to be debugged in the preset cache line is stored in a cache line. The data of the input signal to be debugged sampled in each sampling period is stored in a cache line.

[0020] It should be noted that the input signal information to be debugged in the list of input signal information to be debugged may include all partial input signals, performing full signal visibility debugging, or it may include only partial input signals, implementing partial signal debugging, and can be flexibly configured based on needs. The list of input signal information to be debugged can be specified by the user based on application requirements.

[0021] Step S3: All the files containing A2 n Median B2 k Corresponding B1 k Determine the target block identifier and generate a target block identifier list {C1, C2, ..., C r ,...,C R}, and stored in the preset first memory, C r The rth target block identifier in the target block identifier list, where r ranges from 1 to R, and R≤K.

[0022] It should be noted that the larger the block size of the cache line, the smaller the preset first memory is set, the greater the area savings, but the lower the compression rate. Therefore, it can be seen that the block size needs to be set by taking into account factors such as area and compression rate. Preferably, each block is 16 bits long, and the block size is set to 16 bits to better balance area and compression rate. It is understandable that the block size is set to 16 bits, which is only a preferred embodiment and can also be set to values ​​such as 8 bits or 32 bits. The bits of an input signal to be debugged may be distributed in the same block or in multiple blocks. The same block may correspond to one input signal to be debugged, multiple input signals to be debugged, or no input signal to be debugged. Steps S1-S3 can be specifically implemented by host computer software. That is, the host computer software pre-divides the cache line into K blocks and determines a target block identifier list based on the correspondence between the input signal to be debugged and the bits of the blocks. The target block identifier list can be flexibly configured according to application requirements.

[0023] Step S4: Based on {C1, C2, ..., C r ,...,C R} and {A1,A2,...,A n ,...,A N}Grab the target debug input signal from the input signal.

[0024] As an embodiment, the preset first memory is a random access memory (RAM). The first memory can be interconnected with the signal sampling module. During the sampling process, the signal sampling module uses {C1, C2, ..., C r ,...,C R}Capture target debugging input signal.

[0025] As an embodiment, step S4 includes:

[0026] Step S41: Acquire input signal.

[0027] It should be noted that the input signal may specifically be an input signal of a hardware simulation platform.

[0028] Step S42: Based on {C1, C2, ..., C r ,...,C R} Grab each C from the input signal r Corresponding data D r .

[0029] Step S43: All D r The data is stored in a preset cache line in a preset second memory.

[0030] It can be understood that when N=M, all D r Can fill the preset cache line, when N <M时,前采样周期采集的所有D r The preset cache line is not fully occupied. One preset cache line in the preset second memory is equal to the sum of the bit widths of the M input signals, and data in the same sampling period is cached in one preset cache line in the preset second memory. The preset second memory can specifically be a RAM.

[0031] Step S44: Each D collected in the current sampling period r The D corresponding to the data collected in the previous cycle r Compare the D collected in the current sampling period with the same comparison result. r Discard the D with different comparison results.r The current sampling period identifier is packaged, compressed, and uploaded to a preset third memory.

[0032] It should be noted that change detection compression is implemented through step S44 to save bandwidth. All Dr collected in the current sampling period can be processed in two ways. One way is temporarily stored in the preset second memory through step S43, and the other way is compared with the data of the previous sampling period cached previously. The comparison results are connected with the original data and sent to the downstream compression and packaging module for processing. The compression and packaging module processes the data according to the comparison results. If the Dr of the current sampling period r and the corresponding D in the previous clock cycle r If different, D in the current sampling period r and C r Pack and keep; otherwise, D r It reduces repeated transmission of the same data, improves the sampling efficiency of the hardware simulation system and improves the performance of the hardware simulation system while ensuring the accuracy of the sampled data.

[0033] Step S45: Based on {A1, A2, ..., A n ,...,A N} and the preset third memory generate a target debugging input signal.

[0034] It should be noted that after sampling starts, according to the pre-stored {C1, C2, ..., C r ,...,C R} capture data, it can filter out unnecessary signals and output only the signals that the user wants to observe. This greatly improves the sampling performance. In addition, this {C1, C2, ..., C r ,...,C R It can be dynamically configured and adjusted at any time, ensuring flexibility in signal debugging. As an example, the preset third memory is a double data rate synchronous dynamic random access memory (Double Data Rate, DDR).

[0035] As an embodiment, step S45 includes:

[0036] Step S451: Recover all C samples sampled in each sampling period based on the data recorded in the third memory. r Corresponding data.

[0037] Step S452: Based on all A1 n and A2 n The corresponding relationship is that all C r Get each A1 in the corresponding data nCorresponding data.

[0038] Step S453: Based on each A1 n The data corresponding to each sampling period generates a corresponding signal waveform.

[0039] It is understandable that, based on the fact that the data recorded in the third memory may contain sampled data of non-to-be-debugged input signals, it is only necessary to obtain the signal waveform corresponding to each to-be-debugged input signal through steps S451 to S453. n The data corresponding to each sampling period further generates the corresponding signal waveform based on each A1 n The corresponding signal waveform is A1 n Debug.

[0040] As an embodiment, step S451 includes:

[0041] Step S4511: Determine whether there is C corresponding to the i-th sampling period in the third memory. r If the corresponding data exists, execute step S4522; otherwise, execute step S4523, i=1,2,...

[0042] Step S4522: directly read the C corresponding to the i-th sampling period r For the corresponding data, execute step S4524.

[0043] Step S4523: Get the nearest C r The sampling period of the corresponding data corresponds to C r For the corresponding data, execute step S4524.

[0044] Step S4524: Generate all C corresponding to the i-th sampling period r Corresponding data.

[0045] It should be noted that if there is a C corresponding to the i-th sampling period in the third memory, r The corresponding data is directly used as the C corresponding to the i-th sampling period. r If the corresponding data does not exist, it means that the C corresponding to the i-th sampling period has been uploaded in the historical sampling period. r The corresponding data are the same data, so it is necessary to obtain the corresponding data in the historical sampling period.

[0046] As an embodiment, after step S4, the method further includes:

[0047] Step S5: When the input signal to be debugged needs to be adjusted, return to step S2.

[0048] It should be noted that when the user needs to adjust the input signal to be debugged, the user directly returns to step S2 to reconstruct the input signal information list to be debugged {A1, A2, ..., A n ,...,A N}, without the need for recompilation, enabling flexible adjustment of the input signal to be debugged according to demand. Compared to existing debugging scenarios where all signals are visible, the embodiments of the present invention can significantly increase the sampling frequency and improve the performance of the hardware emulation system. The hardware emulation system can specifically be an FPGA-based hardware emulation system.

[0049] The embodiment of the present invention divides a preset cache line into multiple blocks, sets a corresponding block identifier for each block, obtains an information list of input signals to be debugged based on the corresponding relationship between the input signals to be debugged and the blocks, and configures a target block identifier list in a preset first memory according to debugging requirements, thereby achieving flexible configuration of the signals to be debugged, capturing the target debugging input signal from the input signal, and improving the performance of the hardware simulation system.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0052] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0053] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0054] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A signal debugging method based on dynamic configuration, characterized in that: include: Step S1: Divide the preset cache line into K block information {B1, B2, .., B k ,...,B K }, B k is the kth block information of the preset cache line, the value range of k is 1 to K, K is the total number of blocks contained in the preset cache line, B k ={B1 k ,B2 k }, B1 k is the kth block identifier, B2 k B1 k A range of bits corresponding to a predetermined cache line, where the predetermined cache line is equal to the sum of the bit widths of M input signals, where M is the total number of input signals; Step S2: Get the list of input signal information to be debugged {A1, A2, ..., A n ,...,A N }, A n The nth input signal to be debugged, the value range of n is 1 to N, N is the total number of input signals to be debugged, N≤M, A n ={A1 n ,A2 n }, A1 n A2 is the nth input signal to be debugged. n The range of bits corresponding to the nth input signal to be debugged in a preset cache line, the data of the input signal to be debugged sampled in each sampling period is stored in one cache line; Step S3: All the files containing A2 n Median B2 k Corresponding B1 k Determine the target block identifier and generate a target block identifier list {C1, C2, ..., C r ,...,C R }, and stored in the preset first memory, C r is the rth target block identifier in the target block identifier list, where r ranges from 1 to R, and R≤K; Step S4: Based on {C1, C2, ..., C r ,...,C R } and {A1,A2,...,A n ,...,A N }Grab the target debug input signal from the input signal.

2. The method according to claim 1, characterized in that Each block is 16 bits long.

3. The method according to claim 1, characterized in that The preset first memory is RAM.

4. The method according to claim 1, wherein The step S4 comprises: Step S41: obtaining an input signal; Step S42: Based on {C1, C2, ..., C r ,...,C R } Grab each C from the input signal r Corresponding data D r ; Step S43: All D r storing the data in a preset cache line of a preset second memory; Step S44: Each D collected in the current sampling period r The D corresponding to the data collected in the previous cycle r Compare the D collected in the current sampling period with the same comparison result. r Discard the D with different comparison results. r The current sampling period identifier is packaged, compressed and uploaded to a preset third memory; Step S45: Based on {A1, A2, ..., A n ,...,A N } and the preset third memory generate a target debugging input signal.

5. The method according to claim 4, characterized in that The preset second memory is RAM, and the preset third memory is DDR.

6. The method according to claim 5, characterized in that The step S45 includes: Step S451: Recover all C samples sampled in each sampling period based on the data recorded in the third memory. r Corresponding data; Step S452: Based on all A1 n and A2 n The corresponding relationship is that all C r Get each A1 in the corresponding data n Corresponding data; Step S453: Based on each A1 n The data corresponding to each sampling period generates a corresponding signal waveform.

7. The method according to claim 6, characterized in that The step S451 includes: Step S4511: Determine whether there is C corresponding to the i-th sampling period in the third memory. r If the corresponding data exists, execute step S4522; otherwise, execute step S4523, i=1, 2, ...; Step S4522: directly read the C corresponding to the i-th sampling period r For the corresponding data, execute step S4524; Step S4523: Get the nearest C r The sampling period of the corresponding data corresponds to C r For the corresponding data, execute step S4524; Step S4524: Generate all C corresponding to the i-th sampling period r Corresponding data.

8. The method according to claim 1, characterized in that After step S4, the method further includes: Step S5: When the input signal to be debugged needs to be adjusted, return to step S2.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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