Method for reducing fpga resources in odd multiple clock rate conversion

Abstract

The application discloses a method for realizing odd multiple clock rate conversion and reducing FPGA resources, relates to the technical field of FPGA resource optimization, and realizes FPGA resource optimization in the design of a FIR filter through odd multiple clock rate conversion and hardware multiplexing technology.The method reduces the number of multipliers and saves DSP resources compared with a traditional FIR filter implementation method through 1.5 times clock rate promotion and time sharing multiplexing, is especially suitable for low-cost FPGA applications with limited resources, realizes lossless data conversion through cross-clock domain design controlled by a signal effective flag Valid signal, guarantees data integrity, and realizes the optimization target of replacing area with speed through dynamic scheduling of a three-period counter to complete all tap calculation of two sampling data within three clock periods.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of FPGA (Field Programmable Gate Array) resource optimization, and particularly relates to a method for reducing FPGA resources by realizing odd multiple clock rate conversion. BACKGROUND

[0002] FPGA has become a key hardware platform for real-time signal processing due to its parallel computing capability and reconfigurable characteristics. Among them, DSP (Digital System Processing) is the core resource for realizing efficient multiply-accumulate operation, and is commonly used in FIR (Finite Impulse Response) filter, frequency domain transformation and matrix operation.

[0003] Considering the cost, power consumption and other problems, as few FPGAs as possible are used in the system to realize high complexity algorithms, which increases the demand for the number of DSPs inside the FPGA, resulting in the following challenges: 1) resource competition: multiple algorithm modules, such as multi-channel FIR, may simultaneously compete for DSP resources; 2) clock rate limitation: the speed of DSP can reach 500MHz~1GHz, but in the case of large engineering quantity, in order to meet the timing convergence, the design of high-end FPGA chip generally does not exceed 400MHz; power consumption constraint: high-density DSP use will cause power consumption to surge and timing to be difficult to converge, thereby affecting system stability and development cycle.

[0004] For an N-order FIR filter, in the traditional implementation mode, each tap coefficient needs to correspond to a multiplier, the data rate is synchronized with the system clock, and the hardware cannot be reused. When the data rate is lower than the maximum capability of the DSP, the hardware utilization is low.

[0005] In order to reduce the occupation of DSP resources, the existing resource optimization methods include: coefficient symmetry optimization, which can reduce 50% of the multipliers, but is only suitable for symmetric coefficient scenarios; using LUT (Look-Up Table) to replace the multiplier, but only suitable for low-order filters, and the LUT resource explodes when the order is high. SUMMARY

[0006] In order to solve the above problems in the prior art, the application provides a method for reducing FPGA resources by realizing odd multiple clock rate conversion. The technical problems to be solved by the application are realized through the following technical scheme:

[0007] The application provides a method for reducing FPGA resources by realizing odd multiple clock rate conversion, which is suitable for FIR filters, and the method comprises:

[0008] Convert the sampling data from the original clock domain to a processing clock domain with 1.5 times the rate;

[0009] In the processing clock domain, the sampling data is tapped using a shift register and a Valid signal to form a 15-TAP delay line;

[0010] A three-cycle counter is used for timing scheduling, the tap coefficients of the FIR filter are dynamically updated based on the timing scheduling, and the taps of the 15-TAP delay line are multiplied with the tap coefficients through time-multiplexed multipliers, wherein the multiplication operation of two sampling data is completed within three clock cycles in the processing clock domain;

[0011] The output results of the multipliers are accumulated to complete convolution operation to obtain filtered data;

[0012] The filtered data is converted from the processing clock domain to the original clock domain and output.

[0013] Compared with the prior art, the beneficial effects of the present application are:

[0014] The odd multiple clock rate conversion method of the present application realizes the optimization of FPGA resources in the design of FIR filters through odd multiple clock rate conversion and hardware multiplexing technology. The present application realizes the reduction of the number of multipliers and the saving of DSP resources through 1.5 times clock rate improvement and time-multiplexing, compared with the traditional FIR filter implementation method, which is especially suitable for low-cost FPGA applications with limited resources. Through the cross-clock domain design controlled by the Valid signal, lossless data conversion is realized to ensure data integrity. Through the dynamic scheduling of the three-cycle counter, the tap calculation of two sampling data is completed within three clock cycles to realize the optimization goal of speed for area.

[0015] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a schematic diagram of an odd multiple clock rate conversion method for reducing FPGA resources provided by an embodiment of the present application;

[0017] Figure 2 is a block diagram of a FIR filter structure provided by an embodiment of the present application;

[0018] Figure 3 is a flowchart of a method for implementing a 15th-order FIR filter according to the present application.

[0019] Figure 4 This is a block diagram of a multiplier multiplexing implementation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] To further illustrate the technical means and effectiveness of the present invention in achieving the intended purpose, the following describes in detail a method for reducing FPGA resources by converting an odd-number clock rate according to the present invention, in conjunction with the accompanying drawings and specific implementation methods.

[0021] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0022] The embodiment of the present invention provides a method for reducing FPGA resources by converting an odd-number clock rate, which is applicable to an FIR filter.

[0023] First, the structure of the FIR filter is explained. The output of the FIR filter Can be represented as input data With unit sampling response The linear convolution of is calculated as follows:

[0024] ;

[0025] in, is the output of the FIR filter, is the unit impulse response, is the sampling time, is the unit impulse response length.

[0026] The system function is expressed as:

[0027] ;

[0028] in, is a system function, is one unit delay.

[0029] The FIR filter is composed of a set of "tapped delay line" adders and multipliers. Each multiplier corresponds to the multiplication operation of a FIR tap coefficient. Then, the FIR filter structure Figure 2 As shown, according to the principle of FIR filter structure, when the FIR filter coefficients are not symmetrical, the required multipliers are the same as the order of the FIR filter.

[0030] The odd multiple clock rate conversion method for reducing FPGA resources provided by the present application realizes FPGA resource optimization in the FIR filter design through the odd multiple clock rate conversion and hardware multiplexing technology, and compared with the traditional FIR filter, the number of multipliers is reduced and the DSP resources are saved.

[0031] Please refer to Figure 1 , Figure 1 is a schematic diagram of an odd multiple clock rate conversion method for reducing FPGA resources provided by an embodiment of the present application, as Figure 1 shown, the odd multiple clock rate conversion method for reducing FPGA resources of the present embodiment comprises the following steps:

[0032] Step 1: converting the sampling data from the original clock domain to the processing clock domain with 1.5 times the rate.

[0033] Step 2: in the processing clock domain, using a shift register and a Valid signal to perform a tapping operation on the sampling data to form a 15-TAP delay line.

[0034] Step 3: using a three-period counter to perform timing scheduling, dynamically updating the tap coefficients of the FIR filter based on the timing scheduling, and performing multiplication operation on the taps of the 15-TAP delay line and the tap coefficients through the time-multiplexed multipliers, wherein the multiplication operation of two sampling data is completed within three clock periods in the processing clock domain.

[0035] Step 4: accumulating the output results of the multipliers to complete the convolution operation to obtain the filtered data.

[0036] Step 5: converting the filtered data from the processing clock domain to the original clock domain and outputting.

[0037] The method of the present embodiment is described in detail taking the 15-order FIR filter sampling data original clock domain of 240MHz as an example.

[0038] In the present embodiment, the cross-clock domain operation can be realized through the FIFO buffer to convert the sampling data from the original clock domain to the processing clock domain with 1.5 times the rate. Specifically, the 240MHz original clock domain is converted to the 360MHz processing clock domain through the FIFO buffer.

[0039] In the present embodiment, the Valid signal is a 2 / 3 duty cycle pulse signal, and the 15-TAP delay line mainly completes the shift operation on the input sampling data. The FPGA internally uses a bit shift register to perform a tapping operation on the sampling data according to the 360MHz clock and the 2 / 3 duty cycle Vaild signal, and each sampling data is tapped for 15 times.

[0040] According to the FIR filter structure, for a 15th order FIR filter, each sample data needs to be multiplied by 15 tap coefficients and then accumulated to obtain the corresponding filtered data. In this embodiment, the multiplication operation of two sample data is completed within three clock periods of the processing clock domain. In three clock periods, 10 tap coefficients of one sample data or 5 tap coefficients of two sample data are processed in each clock period, 15 tap coefficients of two sample data are processed in three clocks, and a total of 30 multiplications are performed. Therefore, the 15th order FIR filter needs 10 multipliers.

[0041] In the 360 MHz clock domain, because the input rate of data (240 MHz) is lower than the processing clock, it is necessary to dynamically control the data flow and the calculation logic through timing scheduling to ensure the correct execution of the multiplier multiplexing. In this embodiment, the data shift coordination, tap coefficient updating, multiplier multiplexing, and accumulation operation are performed through a three-period counter (0-2 counter).

[0042] In this embodiment, the three-period counter includes three states of state-0, state-1, and state-2, which correspond to three clock periods of the processing clock domain, respectively.

[0043] Specifically, the control logic of the data shift coordination performed through the three-period counter is as follows:

[0044] In the state-0 state, the Valid signal is high, and the sample data at time n enters the shift register.

[0045] In the state-1 state, the Valid signal is high, and the sample data at time n+1 enters the shift register.

[0046] In the state-2 state, the Valid signal is low, and no sample data enters the shift register.

[0047] Through the three-period counter and the Valid signal, it can be ensured that the data only enters the shift delay line in the valid period (state-0 and state-1), avoiding the interference of invalid data on the calculation. In addition, in the state-2 state, the Valid signal is low, and the delay line is kept to enable the multiplier to complete the calculation of the current data.

[0048] Because the data updates the sample data twice within 3 clock periods, the multiplier needs to dynamically select the tap coefficient for the current calculation. The tap coefficient updating and the multiplier multiplexing are controlled through the three-period counter to implement the multiplication operation. The specific control logic is as follows:

[0049] In the state-0 state, the 0th tap coefficient to the 9th tap coefficient of the FIR filter is selected, and the 0th tap to the 9th tap of the 15-TAP delay line of the sampling data at the n moment is multiplied by the 0th tap coefficient to the 9th tap coefficient through the multiplier;

[0050] In the state-1 state, the 10th tap coefficient to the 14th tap coefficient and the 0th tap coefficient to the 4th tap coefficient of the FIR filter are selected, the 10th tap to the 14th tap of the 15-TAP delay line of the sampling data at the n moment is multiplied by the 10th tap coefficient to the 14th tap coefficient through the multiplier, and the 0th tap to the 4th tap of the 15-TAP delay line of the sampling data at the n+1 moment is multiplied by the 0th tap coefficient to the 4th tap coefficient through the multiplier;

[0051] In the state-2 state, the 5th tap coefficient to the 14th tap coefficient of the FIR filter is selected, and the 5th tap to the 14th tap of the 15-TAP delay line of the sampling data at the n+1 moment is multiplied by the 5th tap coefficient to the 14th tap coefficient through the multiplier.

[0052] Please refer to Figure 4 , Figure 4 is a kind of multiplexer implementation block diagram provided in the embodiment of the application, wherein Tap0-14 represents 15 taps of 15-TAP delay line, Mult-0~Mult-9 represents 10 multipliers. As shown in Figure 4 , sampling data is valid in state-0 and state-1, and 10 multipliers perform 15 tap calculation of two sampling data in three clock cycles, a total of 30 multiplications are completed, and the dynamic update tap coefficient is completed through three period counter control logic.

[0053] The accumulation operation is the core computing link of the FIR filter, responsible for accumulating the output results of the multiplier as required, and finally generating the filtering data. In the embodiment, the accumulation operation specifically includes:

[0054] The output results of all multipliers in the state-0 state and the output results of the 0th multiplier to the 4th multiplier in the state-1 state are accumulated to obtain the filtering data of the sampling data at the n moment.

[0055] The output results of the 5th multiplier to the 9th multiplier in the state-1 state and the output results of all multipliers in the state-2 state are accumulated to obtain the filtering data of the sampling data at the n+1 moment.

[0056] In the embodiment, the processing stage of the sampling data is completed under the processing clock domain, and thus the filtered data needs to be converted to the original clock domain when output. Specifically, the cross-clock domain operation can be realized by a FIFO buffer to convert the filtered data from the processing clock domain to the original clock domain and output, i.e., from 360MHz to 240MHz output. Figure 3

[0057] The method of the present application realizes lossless data conversion through the cross-clock domain design controlled by the signal Valid signal, guarantees data integrity, dynamically schedules through a three-cycle counter, completes all tap calculation of two sampling data within three clock cycles, and realizes the optimization target of area for speed.

[0058] It should be noted that the method of the present application for reducing FPGA resources through odd multiple clock rate conversion can also be extended to other odd multiple rate conversion scenarios (such as 5:4, 7:5), and can be adapted to FIR filter designs of different orders through adjustment of the counter period and the multiplier distribution strategy.

[0059] It should be noted that in this document, the terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variant are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the article or device including the element. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The directions or positional relationships indicated by "up", "down", "left", "right" and the like are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0060] ​In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In the specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific feature or characteristic described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.

[0061] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A method for reducing FPGA resources in odd multiple clock rate conversion, comprising: The method is suitable for a FIR filter, and comprises the following steps: ​ Converting sample data from an original clock domain to a processing clock domain with a rate of 1.5 times; In the processing clock domain, performing a tap operation on the sample data by using a shift register and a Valid signal to form a 15-TAP delay line; Performing timing scheduling by using a three-period counter, dynamically updating tap coefficients of the FIR filter based on the timing scheduling, and performing a multiplication operation on taps of the 15-TAP delay line and the tap coefficients by using time-division multiplexing multipliers, wherein the multiplication operation on two sample data is completed within three clock periods of the processing clock domain; the three-period counter comprises three states of state-0, state-1 and state-2, which correspond to the three clock periods of the processing clock domain, respectively; In the state-0, the 0th tap coefficient to the 9th tap coefficient of the FIR filter are selected, and the 0th tap coefficient to the 9th tap coefficient are multiplied with the 0th tap to the 9th tap of the 15-TAP delay line of the sample data at the n time by using the multipliers; In the state-1, the 10th tap coefficient to the 14th tap coefficient and the 0th tap coefficient to the 4th tap coefficient of the FIR filter are selected, the 10th tap coefficient to the 14th tap coefficient are multiplied with the 10th tap to the 14th tap of the 15-TAP delay line of the sample data at the n time by using the multipliers, and the 0th tap coefficient to the 4th tap coefficient are multiplied with the 0th tap to the 4th tap of the 15-TAP delay line of the sample data at the n+1 time by using the multipliers; In the state-2, the 5th tap coefficient to the 14th tap coefficient of the FIR filter are selected, and the 5th tap coefficient to the 14th tap coefficient are multiplied with the 5th tap to the 14th tap of the 15-TAP delay line of the sample data at the n+1 time by using the multipliers; Accumulating output results of the multipliers to complete convolution operation and obtain filtered data; comprising: Accumulating output results of all the multipliers in the state-0 and output results of the 0th multiplier to the 4th multiplier in the state-1 to obtain the filtered data of the sample data at the n time; Accumulating output results of the 5th multiplier to the 9th multiplier in the state-1 and output results of all the multipliers in the state-2 to obtain the filtered data of the sample data at the n+1 time; Converting the filtered data from the processing clock domain to the original clock domain and outputting the filtered data. Converting sample data from an original clock domain to a processing clock domain with a rate of 1.5 times, comprising:

2. The method for reducing FPGA resources for odd multiple clock rate conversion according to claim 1, wherein, Converting the sample data from the original clock domain to the processing clock domain with the rate of 1.5 times by using FIFO buffering to realize cross-clock domain operation. ​ 3. The method for reducing FPGA resources for odd multiple clock rate conversion implementation according to claim 1, wherein, The number of the multipliers is 10.

4. The method for reducing FPGA resources for odd multiple clock rate conversion according to claim 1, wherein, The Valid signal is a 2 / 3 duty cycle pulse signal, wherein, In the state-0 state, the Valid signal is high, and the sampling data at the n moment enters the shift register; In the state-1 state, the Valid signal is high, and the sampling data at the n+1 moment enters the shift register; In the state-2 state, the Valid signal is low, and no sampling data enters the shift register.

5. The method for reducing FPGA resources for odd multiple clock rate conversion implementation according to claim 1, wherein, Converting the filtered data from the processing clock domain to the original clock domain and outputting, comprising: Crossing clock domain operation is realized through a FIFO buffer, and the filtered data is converted from the processing clock domain to the original clock domain and outputted.

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