Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of preventing a short circuit between signal lines. According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; a pixel disposed in the display area; a first driving voltage line connected to the pixels in the display area and extending to the non-display area; an initialization voltage line connected to the pixel in the display area, extending to the non-display area, and overlapping the first driving voltage line in the non-display area; and a dummy line disposed in the non-display area and overlapping the first driving voltage line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from and all benefits arising from Korean Patent Application No. 10-2024-0030571 filed on March 4, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of preventing a short circuit between signal lines. Background Art

[0004] An organic light emitting display device includes a display element, for example, an organic light emitting diode, whose brightness is changed by electric current. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device capable of preventing a short circuit between signal lines.

[0006] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; pixels arranged in the display area; a first driving voltage line connected to the pixels in the display area and extending to the non-display area; an initialization voltage line connected to the pixels in the display area, extending to the non-display area, and overlapping with the first driving voltage line in the non-display area; and a dummy line arranged in the non-display area and overlapping with the first driving voltage line.

[0007] In an embodiment, the dummy line has a floating state.

[0008] In an embodiment, the dummy line is disposed on the same layer as the initialization voltage line.

[0009] In an embodiment, the first driving voltage line includes: a first lower voltage line disposed on a substrate and extending in a first direction; and a first upper voltage line, which is connected to the first lower voltage line on the first lower voltage line and extends in a second direction intersecting the first direction.

[0010] In an embodiment, the dummy line overlaps the first upper voltage line.

[0011] In an embodiment, the dummy line is connected to the first upper voltage line.

[0012] In an embodiment, the dummy line is disposed on the same layer as the first lower voltage line.

[0013] In an embodiment, the display device further includes an insulating layer between the first lower voltage line and the first upper voltage line, wherein the dummy line is disposed between the substrate and the insulating layer.

[0014] In an embodiment, the dummy line is disposed adjacent to the initialization voltage line.

[0015] In an embodiment, one end portion of the dummy line is disposed at one end portion of the substrate.

[0016] In an embodiment, one end portion of the imaginary line includes a carbonized region.

[0017] In an embodiment, the dummy line has a width greater than that of the initialization voltage line.

[0018] In an embodiment, the dummy line is provided as a plurality of dummy lines.

[0019] In an embodiment, the plurality of dummy lines each overlaps the first driving voltage line, and the plurality of dummy lines are not connected to each other.

[0020] In an embodiment, the display device further includes a second driving voltage line overlapping the dummy line and the initialization voltage line in the non-display area.

[0021] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; pixels arranged in the display area; a first driving voltage line arranged in the display area and the non-display area; an initialization voltage line arranged in the display area and the non-display area and overlapping with the first driving voltage line in the non-display area; and a dummy line overlapping with the first driving voltage line in the non-display area.

[0022] In an embodiment, the dummy line has a floating state.

[0023] In an embodiment, the dummy line is disposed on the same layer as the initialization voltage line.

[0024] In an embodiment, the first driving voltage line includes: a first lower voltage line disposed on a substrate and extending in a first direction; and a first upper voltage line, which is connected to the first lower voltage line on the first lower voltage line and extends in a second direction intersecting the first direction.

[0025] In an embodiment, the dummy line overlaps the first upper voltage line.

[0026] In an embodiment, the dummy line is connected to the first upper voltage line.

[0027] In an embodiment, the dummy line is disposed on the same layer as the first lower voltage line.

[0028] In an embodiment, the display device further includes an insulating layer between the first lower voltage line and the first upper voltage line, wherein the dummy line is disposed between the substrate and the insulating layer.

[0029] In an embodiment, the dummy line is disposed adjacent to the initialization voltage line.

[0030] In an embodiment, one end portion of the dummy line is disposed at one end portion of the substrate.

[0031] In an embodiment, one end portion of the imaginary line includes a carbonized region.

[0032] In an embodiment, the dummy line has a width greater than that of the initialization voltage line.

[0033] According to the display device according to the present disclosure, short circuits between signal lines can be prevented.

[0034] However, aspects of the present disclosure are not limited to the aspects set forth herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0036] Figure 1 is a cross-sectional view illustrating a schematic stack structure of a display device according to an embodiment.

[0037] Figure 2 is a plan view illustrating arrangement of lines of a display device according to an embodiment.

[0038] Figure 3 is a pixel circuit diagram of a display device according to an embodiment.

[0039] Figure 4 is a plan view of a display device according to an embodiment.

[0040] Figure 5 yes Figure 4 An enlarged plan view of region Q1.

[0041] Figure 6 yes Figure 4 An enlarged plan view of region Q1.

[0042] Figure 7 It shows Figure 5 A plan view of a modified example of .

[0043] Figure 8 It shows Figure 6 A plan view of a modified example of .

[0044] Figure 9 yes Figure 4 An enlarged plan view of region Q3.

[0045] Figure 10 It is along Figure 5 and Figure 6 1 is a cross-sectional view of a display device according to an embodiment taken along line X1 - X1 ′.

[0046] Figure 11 yes Figure 10 An enlarged cross-sectional view of region Q4.

[0047] Figure 12 It shows Figure 11 sectional view of a modified example of the structure shown in .

[0048] Figure 13 It is along Figure 9 1 is a cross-sectional view of a display device according to an embodiment taken along line X2 - X2 ′.

[0049] Figure 14 is a plan view of dummy lines and peripheral components in a base substrate including a display panel according to an embodiment.

[0050] Figure 15 Among them Figure 14 A plan view of a display device with the base substrate and the dummy panel removed.

[0051] Figure 16 is used to describe the Figure 14 Diagram of the charge distribution caused by the imaginary lines.

[0052] Figure 17 is used to describe the Figure 15 Diagram of the charge distribution caused by the imaginary lines.

[0053] Figure 18 is a plan view of dummy lines and peripheral components in a base substrate including a display panel according to an embodiment.

[0054] Figure 19 Among them Figure 18 A plan view of a display device with the base substrate and the dummy panel removed.

[0055] Figure 20 is a diagram showing the result of a simulation to which the configuration of the display device according to the embodiment is applied.

[0056] Figure 21 and Figure 22 is a plan view of a display device according to an embodiment. DETAILED DESCRIPTION

[0057] The advantages and features of the present disclosure and the methods for achieving the same may be more readily understood by reference to the following detailed description of exemplary embodiments and the accompanying drawings. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art, and the present disclosure will be limited only by the appended claims.

[0058] It will be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer can be directly on the other element or layer, or intervening elements or layers may be present. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings to describe the embodiments are merely examples, and the present disclosure is not limited to the details shown.

[0059] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0060] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other, and may be technically operated and driven in various ways. The embodiments may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0061] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0062] Figure 1 is a cross-sectional view illustrating a schematic stack structure of the display device 1 according to the embodiment.

[0063] refer to Figure 1 The display device 1 can be applied to various electronic devices, namely, small and medium-sized electronic devices such as tablet PCs, smart phones, car navigation units, cameras, central information displays (CIDs) provided in vehicles, watch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles, as well as medium and large-sized electronic devices such as televisions, exterior billboards, monitors, personal computers, and laptop computers. These are presented as examples only, but the display device 1 can also be applied to other electronic devices without departing from the present disclosure.

[0064] The display device 1 may include a display area DA that displays an image and a non-display area NDA that does not display an image. In some embodiments, the non-display area NDA may be located around the display area DA and may surround the display area DA. The image displayed in the display area DA can be viewed by a user in the third direction Z in the direction of the arrow in the drawing.

[0065] The schematic stacking structure of the display device 1 is described. In some embodiments, the display device 1 may include Figure 1 The display panel 100 may include a display substrate 10, a color conversion substrate 30 facing the display substrate 10, a sealing member 50 coupling the display substrate 10 and the color conversion substrate 30, and a filler 70 filled between the display substrate 10 and the color conversion substrate 30.

[0066] The display substrate 10 may include elements and circuits for displaying images, for example, pixel circuit elements such as switching elements, self-luminous elements, and a pixel defining layer that defines an emission area and a non-emission area in the display area DA, which will be described later. In an exemplary embodiment, the self-luminous element may include at least one of an organic light-emitting diode, a quantum dot light-emitting diode, an inorganic material-based micro light-emitting diode (e.g., a micro-LED), and an inorganic material-based light-emitting diode with a nanometer size (e.g., a nano-LED). Hereinafter, in order to simplify the description, the case where the self-luminous element is an organic light-emitting element will be described as an example.

[0067] Color conversion substrate 30 may be positioned on display substrate 10 to face display substrate 10. In some embodiments, color conversion substrate 30 may include a color conversion pattern for converting the color of incident light. In some embodiments, color conversion substrate 30 may include at least one of a color filter and a wavelength conversion pattern as the color conversion pattern. In some embodiments, color conversion substrate 30 may include both a color filter and a wavelength conversion pattern.

[0068] The sealing member 50 may be positioned between the display substrate 10 and the color conversion substrate 30 in the non-display area NDA. The sealing member 50 may be provided in the non-display area NDA along the edges of the display substrate 10 and the color conversion substrate 30 to surround the display area DA in a plan view. The display substrate 10 and the color conversion substrate 30 may be coupled to each other via the sealing member 50.

[0069] In some embodiments, the sealing member 50 may be made of an organic material. For example, the sealing member 50 may be made of epoxy resin, but is not limited thereto. In some other embodiments, the sealing member 50 may be applied in the form of glass frit including glass or the like.

[0070] Filler 70 may be positioned in a space between display substrate 10 and color conversion substrate 30 that is surrounded by sealing member 50. Filler 70 may fill the space between display substrate 10 and color conversion substrate 30.

[0071] In some embodiments, the filler 70 may be made of a material capable of transmitting light. In some embodiments, the filler 70 may be made of an organic material. For example, the filler 70 may be made of a silicon-based organic material, an epoxy-based organic material, or a mixture of a silicon-based organic material and an epoxy-based organic material.

[0072] In some embodiments, the filler 70 can be made of a material having an extinction coefficient that is substantially zero. There is a correlation between the refractive index and the extinction coefficient, and as the refractive index decreases, the extinction coefficient also decreases. In addition, when the refractive index is 1.7 or less, the extinction coefficient can converge to substantially zero. In some embodiments, the filler 70 can be made of a material having a refractive index of 1.7 or less, thereby preventing or minimizing the light provided by the self-luminous element from being absorbed while passing through the filler 70. In some embodiments, the filler 70 can be made of an organic material having a refractive index of 1.4 to 1.6.

[0073] although Figure 1 The display device 1 is shown to include a display substrate 10, a color conversion substrate 30, a sealing member 50, and a filler 70. However, in some embodiments, the display device 1 may not include the sealing member 50 and the filler 70, and the color conversion substrate 30 may include the second substrate 310 (for example, see FIG. Figure 10 、 Figure 13 ) can be set on the display substrate 10.

[0074] Figure 2 is a plan view showing the arrangement of lines of the display device 1 according to the embodiment.

[0075] refer to Figure 2 The display device 1 may include a plurality of lines. The lines of the display device 1 may include a plurality of scan lines SL, a plurality of data lines DL, a plurality of initialization voltage lines VIL, a plurality of first driving voltage lines VDL, and a plurality of second driving voltage lines VSL. Although not shown in the drawings, other conductive lines may also be provided in the display device 1.

[0076] The data line DL, the initialization voltage line VIL, the first driving voltage line VDL, and the second driving voltage line VSL may extend to the non-display area NDA to be connected to the pad electrodes PD provided in the pad area PDA of the non-display area NDA. The pad electrodes PD may include a data pad electrode PD_D connected to the data line DL, an initialization voltage pad electrode PD_VI connected to the initialization voltage line VIL, a first voltage pad electrode PD_VDL connected to the first driving voltage line VDL, and a second voltage pad electrode PD_VSL connected to the second driving voltage line VSL.

[0077] As used herein, the term "connected" may mean not only that one component is connected to another component through physical contact, but also that one component is connected to another component through another component. This can also be understood as one part and another part of an integral element being connected to form an integral element via another component. Furthermore, if one component is connected to another component, in addition to being directly connected by physical contact, this can also be interpreted to include the meaning of being electrically connected via another component.

[0078] The drawings illustrate that each of the pad electrodes PD is provided in the pad area PDA provided on the upper side of the display area DA, but are not limited thereto. Some of the plurality of pad electrodes PD may be provided on the lower side or in any one area on the left and right sides of the display area DA.

[0079] The display device 1 may include a plurality of pixels arranged in a display area DA (see, for example, Figure 3 The above lines may pass through each pixel PX or its vicinity to apply a driving signal to each pixel PX. For example, a scan line SL, a data line DL, an initialization voltage line VIL, a first driving voltage line VDL, and a second driving voltage line VSL may be connected to each pixel PX in the display area DA.

[0080] A plurality of adjacent pixels PX may constitute a unit pixel. In this case, three adjacent pixels PX may provide light of different colors. For example, three adjacent pixels PX may provide red light, green light, and blue light, respectively.

[0081] Figure 3 is a pixel circuit diagram of the display device 1 according to the embodiment.

[0082] refer to Figure 3 The pixel PX of the display device 1 according to the embodiment may include a light emitting diode EL and a pixel circuit PC connected to the light emitting diode EL. According to some embodiments, the pixel circuit PC may include three transistors T1, T2, and T3 and one storage capacitor Cst.

[0083] The light emitting diode EL emits light by the current supplied by the first transistor T1. The light emitting diode EL includes a first electrode, a second electrode, and at least one light emitting element disposed therebetween. The light emitting element can emit light of a specific wavelength band by an electrical signal transmitted from the first electrode and the second electrode.

[0084] One end of the light emitting diode EL can be connected to the source electrode of the first transistor T1, and the other end thereof can be connected to a second driving voltage line VSL, and a low potential voltage (hereinafter referred to as the second driving voltage) lower than the high potential driving voltage (hereinafter referred to as the first driving voltage) of the first driving voltage line VDL is supplied to the second driving voltage line VSL.

[0085] The first transistor T1 regulates current flowing from a first drive voltage line VDL to the light-emitting diode EL based on a voltage difference between a gate electrode and a source electrode. A first drive voltage is applied to the first drive voltage line VDL. For example, the first transistor T1 may be a drive transistor for driving the light-emitting diode EL. The gate electrode of the first transistor T1 may be connected to the source electrode of the second transistor T2. The source electrode of the first transistor T1 may be connected to the first electrode of the light-emitting diode EL. The drain electrode of the first transistor T1 may be connected to the first drive voltage line VDL. The first drive voltage is applied to the first drive voltage line VDL.

[0086] The second transistor T2 is turned on by a scan signal of the scan line SL to connect the data line DL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the scan line SL, the source electrode of the second transistor T2 may be connected to the gate electrode of the first transistor T1, and the drain electrode of the second transistor T2 may be connected to the data line DL.

[0087] The third transistor T3 is turned on by a scan signal of the scan line SL to connect the initialization voltage line VIL to one end of the light emitting diode EL. A gate electrode of the third transistor T3 may be connected to the scan line SL, a drain electrode of the third transistor T3 may be connected to the initialization voltage line VIL, and a source electrode of the third transistor T3 may be connected to one end of the light emitting diode EL or the source electrode of the first transistor T1.

[0088] In an embodiment, the source electrode and the drain electrode of each of the transistors T1, T2, and T3 are not limited to those described above, and vice versa. Each of the transistors T1, T2, and T3 may be formed of a thin film transistor. Figure 3In the embodiment, each of the transistors T1, T2, and T3 is described as being formed of an N-type metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto. For example, each of the transistors T1, T2, and T3 may be formed of a P-type MOSFET. In an embodiment, some of the transistors T1, T2, and T3 may be formed of an N-type MOSFET, and the others may be formed of a P-type MOSFET.

[0089] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst stores a difference voltage between the gate voltage and the source voltage of the first transistor T1.

[0090] although Figure 3 The embodiment shows that the gate electrodes of the second transistor T2 and the third transistor T3 are connected to the same scan line SL, and therefore, the second transistor T2 and the third transistor T3 are simultaneously turned on by the scan signal applied from the same scan line SL, but the present disclosure is not limited thereto, and the gate electrode of the second transistor T2 may be connected to any one of the scan lines SL, and the gate electrode of the third transistor T3 may be connected to another scan line SL different from the any one of the scan lines SL.

[0091] The number of transistors and capacitors in the pixel circuit PC may vary. Depending on the embodiment, the pixel circuit PC of the pixel PX may have various other modified structures, such as a 2T1C structure including two transistors and one storage capacitor, a 7T1C structure including seven transistors and one storage capacitor, and a 6T1C structure including six transistors and one storage capacitor.

[0092] Figure 4 is a plan view of the display device 1 according to the embodiment. Figure 5 yes Figure 4 An enlarged plan view of region Q1, and more specifically, included in Figure 4 Schematic plan view of a display substrate 10 in a display device 1 of FIG. Figure 6 yes Figure 4 An enlarged plan view of region Q1, and more specifically, included in Figure 4 Schematic plan view of the color conversion substrate 30 in the display device 1. Figure 7 It shows Figure 5 A plan view of a modified example of . Figure 8 It shows Figure 6 A plan view of a modified example of . Figure 9 yes Figure 4 An enlarged plan view of region Q3.

[0093] Apart from Figure 1 In addition, further reference Figures 4 to 9In some embodiments, as Figure 4 As shown in , the display device 1 may have a rectangular shape in a plan view. The display device 1 may include a first side L1 and a third side L3 extending in a first direction (X direction) and a second side L2 and a fourth side L4 extending in a second direction (Y direction) intersecting the first direction (X direction). The angles at which the sides of the display device 1 meet may be right angles, but are not limited to this. In some embodiments, the lengths of the first side L1 and the third side L3 and the lengths of the second side L2 and the fourth side L4 may be different from each other. For example, the first side L1 and the third side L3 may be relatively longer than the second side L2 and the fourth side L4. The planar shape of the display device 1 is not limited to the illustrated shape, but may have a circular shape or other shapes.

[0094] In some embodiments, the display device 1 may further include a flexible circuit board (FPC) and a driver chip (IC).

[0095] like Figure 5 As shown in FIG, in the display area DA, a plurality of emission areas LA1, LA2, and LA3 and a non-emission area NLA may be defined on the display substrate 10.

[0096] In some embodiments, a first emission area LA1, a second emission area LA2, and a third emission area LA3 may be defined in the display area DA of the display substrate 10. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may be areas in which light generated by the light emitting elements of the display substrate 10 is emitted to the outside of the display substrate 10, and the non-emission area NLA may be an area in which light is not emitted to the outside of the display substrate 10. In some embodiments, in the display area DA, the non-emission area NLA may surround each of the first emission area LA1, the second emission area LA2, and the third emission area LA3.

[0097] In some embodiments, the light emitted to the outside in the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be light of a third color. In some embodiments, the third color light may be blue light and may have a peak wavelength in the range of about 440 nm to about 480 nm. Here, the peak wavelength refers to a wavelength at which the intensity of the light is the greatest.

[0098] In some embodiments, the first emission area LA1, the second emission area LA2, and the third emission area LA3 may form one group, and a plurality of groups may be defined in the display area DA.

[0099] like Figure 5As shown in , the first emission area LA1 and the third emission area LA3 may be adjacent to each other along the first direction (X direction), and the second emission area LA2 may be located on one side of the first emission area LA1 and the third emission area LA3 along the second direction (Y direction). However, the present disclosure is not limited thereto, and the arrangement of the first emission area LA1, the second emission area LA2, and the third emission area LA3 may be variously changed. For example, as Figure 5 As shown in the figure, the first emission area LA1, the second emission area LA2, and the third emission area LA3 can be positioned sequentially along the first direction (X direction). In some embodiments, in the display area DA, the first emission area LA1, the second emission area LA2, and the third emission area LA3 can form a group and be repeatedly arranged along the first direction (X direction) and the second direction (Y direction).

[0100] Hereinafter, the following will be described. Figure 5 The case where the first emission area LA1, the second emission area LA2, and the third emission area LA3 are provided as shown in FIG is taken as an example.

[0101] like Figure 6 As shown in FIG, in the display area DA, a plurality of light-transmitting areas TA1, TA2, and TA3 and a light-blocking area BA may be defined on the color conversion substrate 30. The light-transmitting areas TA1, TA2, and TA3 may be areas through which light emitted from the display substrate 10 passes through the color conversion substrate 30 and is provided to the outside of the display device 1. The light-blocking area BA may be an area through which light emitted from the display substrate 10 is not transmitted.

[0102] In some embodiments, a first light-transmitting area TA1 , a second light-transmitting area TA2 , and a third light-transmitting area TA3 may be defined on the color conversion substrate 30 .

[0103] The first light-transmitting area TA1 may correspond to or overlap the first emission area LA1. Similarly, the second light-transmitting area TA2 may correspond to or overlap the second emission area LA2, and the third light-transmitting area TA3 may correspond to or overlap the third emission area LA3.

[0104] When Figure 5 When the first emission area LA1 and the third emission area LA3 shown in FIG may be adjacent to each other along the first direction (X direction) and the second emission area LA2 is located at one side of the first emission area LA1 and the third emission area LA3 along the second direction (Y direction), the first light-transmitting area TA1 and the third light-transmitting area TA3 may be adjacent to each other along the first direction (X direction) and the second light-transmitting area TA2 may be located at one side of the first light-transmitting area TA1 and the third light-transmitting area TA3 along the second direction (Y direction), as shown in FIG Figure 4 As shown in .

[0105] In some embodiments, when Figure 7 When the first emission area LA1, the second emission area LA2 and the third emission area LA3 are positioned sequentially along the first direction (X direction), the first light-transmitting area TA1, the second light-transmitting area TA2 and the third light-transmitting area TA3 can also be positioned sequentially along the first direction (X direction), as shown in FIG. Figure 8 As shown in .

[0106] In some embodiments, each of the first light-transmitting area TA1, the second light-transmitting area TA2, and the third light-transmitting area TA3 may have a quadrilateral shape in a plan view. For example, the quadrilateral shape may be a rectangular shape or a square shape. However, the present disclosure is not limited thereto, and each of the first light-transmitting area TA1, the second light-transmitting area TA2, and the third light-transmitting area TA3 may have a circular shape, an elliptical shape, or other polygonal shape in a plan view.

[0107] In some embodiments, light of a third color provided from the display substrate 10 can pass through the first light-transmitting area TA1, the second light-transmitting area TA2, and the third light-transmitting area TA3 and be provided to the outside of the display device 1. When the light emitted from the first light-transmitting area TA1 to the outside of the display device 1 is referred to as first emitted light, the light emitted from the second light-transmitting area TA2 to the outside of the display device 1 is referred to as second emitted light, and the light emitted from the third light-transmitting area TA3 to the outside of the display device 1 is referred to as third emitted light, the first emitted light can be light of a first color, the second emitted light can be light of a second color different from the first color, and the third emitted light can be light of a third color different from the first and second colors. In some embodiments, the third color light can be blue light having a wavelength range of 380 nm to 500 nm and a peak wavelength within the range of 440 nm to 480 nm, and the first color light can be red light having a wavelength range of 600 nm to 780 nm and a peak wavelength within the range of 610 nm to 650 nm. In addition, the light of the second color may be green light having a wavelength range of 500 nm to 600 nm and having a peak wavelength within the range of 510 nm to 550 nm.

[0108] The light-blocking area BA may be positioned around the first light-transmitting area TA1, the second light-transmitting area TA2, and the third light-transmitting area TA3 of the color conversion substrate 30 in the display area DA. In some embodiments, the light-blocking area BA may surround the first light-transmitting area TA1, the second light-transmitting area TA2, and the third light-transmitting area TA3. In addition, the light-blocking area BA may also be positioned in the non-display area NDA of the display device 1.

[0109] like Figure 6As shown in FIG, in the display area DA, a plurality of light-transmitting areas TA1, TA2, and TA3 and a light-blocking area BA may be defined on the color conversion substrate 30. The light-transmitting areas TA1, TA2, and TA3 may be areas through which light emitted from the display substrate 10 passes through the color conversion substrate 30 and is provided to the outside of the display device 1. The light-blocking area BA may be an area through which light emitted from the display substrate 10 is not transmitted.

[0110] refer to Figure 4 and Figure 9 , the dam member DM and the sealing member 50 may be disposed in the non-display area NDA of the display device 1 .

[0111] In a process of forming the encapsulation layer disposed in the display area DA, the dam member DM may block overflow of the organic material (or monomer), thereby preventing the organic material of the encapsulation layer from extending toward the edge of the display device 1 .

[0112] In some embodiments, the dam member DM may be disposed to completely surround the display area DA in a plan view.

[0113] As described above, the sealing member 50 may couple the display substrate 10 and the color conversion substrate 30 to each other.

[0114] The sealing member 50 may be positioned further outward than the dam member DM in the non-display area NDA, and may be disposed to completely surround the dam member DM and the display area DA in a plan view.

[0115] The non-display area NDA of the display device 1 may include a pad area PDA, and the plurality of pad electrodes PD may be positioned in the pad area PDA.

[0116] The display substrate 10 (see Figure 1 ) may include the above-mentioned dam member DM and pad electrode PD.

[0117] The flexible circuit board FPC may be connected to the pad electrode PD. The flexible circuit board FPC may be connected to the display substrate 10 (see FIG. Figure 1 ) and is electrically connected to a circuit board that provides signals and power for driving the display device 1.

[0118] The driver chip IC may be electrically connected to the circuit board to receive data and signals. In some embodiments, the driver chip IC may be a data driver chip and may receive data control signals and image data from the circuit board and generate and output data voltages corresponding to the image data.

[0119] In some embodiments, the driver chip IC may be mounted on a flexible circuit board (FPC). For example, the driver chip IC may be mounted on the flexible circuit board (FPC) in the form of a chip on film (COF).

[0120] The data voltage provided from the driving chip IC, the power provided from the circuit board, etc. can be transmitted to the display substrate 10 (see FIG. 1 ) via the flexible circuit board FPC and the pad electrode PD. Figure 1 ) pixel circuit, etc.

[0121] Hereinafter, the structure of the display device 1 will be described in more detail.

[0122] Figure 10 It is along Figure 5 and Figure 6 1 is a cross-sectional view of the display device 1 according to the embodiment taken along line X1 - X1 ′. Figure 11 yes Figure 10 An enlarged cross-sectional view of region Q4. Figure 12 It shows Figure 11 sectional view of a modified example of the structure shown in . Figure 13 It is along Figure 9 1 is a cross-sectional view of the display device 1 according to the embodiment taken along line X2 - X2 ′.

[0123] Apart from Figures 1 to 9 In addition, further reference Figures 10 to 13 The display device 1 may include the display substrate 10 and the color conversion substrate 30 as described above, and may further include a filler 70 positioned between the display substrate 10 and the color conversion substrate 30 .

[0124] Hereinafter, the display substrate 10 will be described.

[0125] The first substrate 110 of the display substrate 10 can be made of a light-transmitting material. In some embodiments, the first substrate 110 can be a glass substrate or a plastic substrate. When the first substrate 110 is a plastic substrate, the first substrate 110 can be flexible. The first substrate 110 can have a display area DA and a non-display area NDA similar to those of the display device 1.

[0126] In some embodiments, in the display area DA, a plurality of emission areas LA1 , LA2 , and LA3 and a non-emission area NLA may be defined at the first substrate 110 as described above.

[0127] In some embodiments, the first side L1, the second side L2, the third side L3, and the fourth side L4 of the display device 1 may be the same as the four sides of the first substrate 110. That is, the first side L1, the second side L2, the third side L3, and the fourth side L4 of the display device 1 may be referred to as the first side L1, the second side L2, the third side L3, and the fourth side L4 of the first substrate 110, respectively.

[0128] The first conductive layer may be positioned on the first substrate 110. The first conductive layer may include a lower light blocking layer BML, a first lower voltage line VDLa, an initialization voltage line VIL, and a dummy line DML. In other words, the first lower voltage line VDLa, the initialization voltage line VIL, and the dummy line DML may be disposed on the same layer. The lower light blocking layer BML may overlap with the active layer ACT, which will be described later, in the thickness direction (Z direction). In addition, although not shown, since a portion of the lower light blocking layer BML may overlap with the second conductive layer, which will be described later, a storage capacitor Cst may be formed in the region where the lower light blocking layer BML overlaps with the second conductive layer.

[0129] The lower light blocking layer BML may block external light or light from the light emitting diode EL from being incident on the active layer ACT, thereby preventing leakage current from being generated due to light in a thin film transistor to be described later, or reducing the leakage current.

[0130] In some embodiments, the lower light blocking layer BML may be made of a material that blocks light and has conductivity. For example, the lower light blocking layer BML may include a single material of a metal such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), or neodymium (Nd), or an alloy thereof. In some embodiments, the lower light blocking layer BML may have a single-layer or multi-layer structure. For example, when the lower light blocking layer BML has a multi-layer structure, the lower light blocking layer BML may have a stacked structure of titanium (Ti) / copper (Cu) / indium tin oxide (ITO) or a stacked structure of titanium (Ti) / copper (Cu) / aluminum oxide (Al2O3), but is not limited thereto. In some embodiments, the first lower voltage line VDLa, the initialization voltage line VIL, and the dummy line DML may be made of the same material as the lower light blocking layer BML described above.

[0131] According to some embodiments, the dummy line DML may prevent the overlap area OVA (see FIG. 1 ) of the first upper voltage line VDLb and the initialization voltage line VIL from being overlapped. Figure 14 ) accumulates a large amount of charge (to be described later), thereby preventing a short circuit between the first upper voltage line VDLb and the initialization voltage line VIL.

[0132] In some embodiments, the width W1 of the dummy line DML can be greater than the width W2 of the initialization voltage line VIL. Therefore, the overlapping area between the dummy line DML and the first upper voltage line VDLb (described later) can be greater than the overlapping area OVA between the initialization voltage line VIL and the first upper voltage line VDLb. In this case, the charge of the first upper voltage line VDLb (described later) can be dispersed to the dummy line DML better than to the initialization voltage line VIL. If charge accumulates in the overlapping area between the dummy line DML and the first upper voltage line VDLb and the insulating layer (e.g., the buffer layer 111 and the gate insulating layer 115) between the dummy line DML and the first upper voltage line VDLb is damaged, the first upper voltage line VDLb and the dummy line DML may be connected to each other. In other words, the first upper voltage line VDLb and the dummy line DML may short-circuit. Since the dummy line DML is a floating line to which no signal is applied, no circuit problems will occur even if the first upper voltage line VDLb and the dummy line DML short-circuit. In addition, when the first upper voltage line VDLb and the dummy line DML are short-circuited, the area of ​​the first upper voltage line VDLb increases, thereby increasing the above-mentioned charge distribution effect.

[0133] The buffer layer 111 may be positioned on the first conductive layer. The buffer layer 111 may be positioned on the first substrate 110 and may be provided in the display area DA and the non-display area NDA. The buffer layer 111 may block foreign matter or moisture from penetrating through the first substrate 110. For example, the buffer layer 111 may include a material such as SiO2, SiN x or SiON, and can be formed as a single layer or a multilayer.

[0134] The active layer ACT may be positioned on the buffer layer 111. The active layer ACT may be disposed in the display area DA and the non-display area NDA. The active layer ACT may be disposed to correspond to each of the first emission area LA1, the second emission area LA2, and the third emission area LA3 in the display area DA, and may constitute the above-mentioned lines SL, DL, VIL, VDL, and VSL. The active layer ACT may constitute thin film transistors T1, T2, and T3 (see FIG. Figure 3 ). The following description focuses on the case where the active layer ACT is used as the active layer of the thin film transistors T1, T2, and T3. The active layer ACT may include a source electrode SE, a drain electrode DE, and a channel region CH, which will be described later. The channel region CH may be formed in a region of the active layer ACT that overlaps with a gate electrode GE, which will be described later. The source electrode SE and the drain electrode DE may be formed on both sides of the channel region CH.

[0135] In some embodiments, the active layer ACT may include an oxide semiconductor. For example, the active layer ACT may be formed of a Zn oxide-based material (e.g., Zn oxide, In-Zn oxide, or Ga-In-Zn oxide), and may also be an In-Ga-Zn-O (IGZO) semiconductor containing a metal such as indium (In) or gallium (Ga). However, the present disclosure is not limited thereto, and the active layer ACT may include amorphous silicon, polycrystalline silicon, or the like.

[0136] The gate insulating layer 115 may be positioned on the active layer ACT. In some embodiments, the gate insulating layer 115 may be positioned in the display area DA and the non-display area NDA. In some embodiments, the gate insulating layer 115 may include a silicon nitride, such as SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O, HfO2, ZrO2 and other inorganic materials.

[0137] The second conductive layer (or gate conductive layer) may be positioned on the gate insulating layer 115, and the second conductive layer may include a gate electrode GE, a first upper voltage line VDLb, a first connection electrode CE1, and a second connection electrode CE2. The gate electrode GE, the first connection electrode CE1, and the second connection electrode CE2 may be positioned in the display area DA to overlap with the active layer ACT. Figure 13 As shown in , the first upper voltage line VDLb may overlap the dummy line DML and the initialization voltage line VIL.

[0138] The gate electrode GE may overlap the channel region CH of the active layer ACT. The channel region CH may be spaced apart from the gate electrode GE with a gate insulating layer 115 therebetween.

[0139] The second connection electrode CE2 may be connected to the source electrode SE and the lower light-blocking layer BML. For example, one side of the second connection electrode CE2 may be connected to the source electrode SE of the active layer ACT through a contact hole penetrating the gate insulating layer 115, and the other side of the second connection electrode CE2 may be connected to the lower light-blocking layer BML through a contact hole penetrating the gate insulating layer 115 and the buffer layer 111.

[0140] The first connection electrode CE1 may be connected to the drain electrode DE and the first lower voltage line VDLa. For example, one side of the first connection electrode CE1 may be connected to the drain electrode DE of the active layer ACT through a contact hole penetrating the gate insulating layer 115, and the other side of the first connection electrode CE1 may be connected to the first lower voltage line VDLa through a contact hole penetrating the gate insulating layer 115 and the buffer layer 111.

[0141] The first upper voltage line VDLb can be connected to the aforementioned first lower voltage line VDLa. For example, the first upper voltage line VDLb can be connected to the first lower voltage line VDLa through a contact hole that penetrates the gate insulating layer 115 and the buffer layer 111. The first upper voltage line VDLb can constitute the aforementioned first driving voltage line VDL together with the first lower voltage line VDLa. In other words, the first driving voltage line VDL may include a first lower voltage line VDLa and a first upper voltage line VDLb. The first lower voltage line VDLa may intersect with the first upper voltage line VDLb in the display area DA. For example, a plurality of first lower voltage lines VDLa may extend in the first direction, and a plurality of first upper voltage lines VDLb may extend in the second direction. Therefore, the first driving voltage line VDL including a plurality of first lower voltage lines VDLa and a plurality of first upper voltage lines VDLb may have a grid form in the display area DA. According to some embodiments, the first upper voltage line VDLb may be as shown in FIG. Figure 13 In the example shown in , φ overlaps with the dummy line DML and the initialization voltage line VIL.

[0142] In view of the adhesion with the adjacent layers, the surface flatness of the stacked layers, the processability, etc., the second conductive layer (for example, the gate electrode GE, the first upper voltage line VDLb, the first connection electrode CE1 and the second connection electrode CE2) may include one or more materials of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may be formed as a single layer or a multilayer. In some embodiments, the second conductive layer may include any one of transparent conductive oxides (TCO) other than the above materials. For example, the second conductive layer may include tungsten oxide (W x O y ), titanium oxide (TiO2), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), magnesium oxide (MgO), etc.

[0143] For example, the second conductive layer may have a structure in which titanium (Ti), copper (Cu), and indium tin oxide (ITO) are stacked from the bottom, but is not limited thereto.

[0144] The second conductive layer may further include a capacitor electrode overlapping the lower light blocking layer BML, and thus the aforementioned storage capacitor Cst may be formed in an overlapping region of the capacitor electrode and the lower light blocking layer BML.

[0145] The passivation layer 117 may be positioned on the second conductive layer. In some embodiments, the passivation layer 117 may be positioned in the display area DA and the non-display area NDA. In some embodiments, the passivation layer 117 may include a material such as SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O, HfO2, ZrO2 and other inorganic materials.

[0146] The via layer 130 may be positioned on the passivation layer 117. The via layer 130 may cover the thin film transistors T1, T2, and T3 in the display area DA. In some embodiments, the via layer 130 may be a planarization layer. In some embodiments, the via layer 130 may be made of an organic material. For example, the via layer 130 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In some embodiments, the via layer 130 may include a photosensitive organic material.

[0147] In the display area DA, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be positioned on the via layer 130. Each of the anode electrodes AE1, AE2, AE3 may be connected to the source electrode SE of each transistor via a contact hole penetrating the via layer 130 and the passivation layer 117. For example, the first anode electrode AE1 may be connected to the source electrode SE of the first transistor T1 via a contact hole penetrating the via layer 130 and the passivation layer 117.

[0148] The first anode electrode AE1 may overlap the first emission area LA1 and may partially extend to the non-emission area NLA. The second anode electrode AE2 may overlap the second emission area LA2 and may partially extend to the non-emission area NLA. The third anode electrode AE3 may overlap the third emission area LA3 and may partially extend to the non-emission area NLA.

[0149] In some embodiments, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be reflective electrodes. In this case, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be a metal layer containing a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, or Cr. In an embodiment, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may further include a metal oxide layer stacked on the metal layer. In an exemplary embodiment, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have a multilayer structure, for example, a double-layer structure of ITO / Ag, Ag / ITO, ITO / Mg, or ITO / MgF, or a triple-layer structure of ITO / Ag / ITO.

[0150] The connection electrode CNE may be electrically connected to the second driving voltage line VSL in the non-display area NDA and may be in direct contact with the second driving voltage line VSL. In some embodiments, although not shown, the connection electrode CNE may be disposed in the display area DA and may be electrically connected to the second driving voltage line VSL in the display area DA.

[0151] The pad electrode PD may be disposed in the non-display area NDA and may be electrically connected to the first upper voltage line VDLb of the aforementioned second conductive layer.

[0152] The pixel-defining layer 150 may be positioned on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The pixel-defining layer 150 may include an opening exposing the first anode electrode AE1, an opening exposing the second anode electrode AE2, and an opening exposing the third anode electrode AE3, and may define a first emission area LA1, a second emission area LA2, a third emission area LA3, and a non-emission area NLA. That is, the area of ​​the first anode electrode AE1 that is not covered by the pixel-defining layer 150 and is exposed may be the first emission area LA1. Similarly, the area of ​​the second anode electrode AE2 that is not covered by the pixel-defining layer 150 and is exposed may be the second emission area LA2, and the area of ​​the third anode electrode AE3 that is not covered by the pixel-defining layer 150 and is exposed may be the third emission area LA3. In addition, the area where the pixel-defining layer 150 is located may be the non-emission area NLA.

[0153] In some embodiments, the pixel defining layer 150 may include an organic insulating material selected from the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0154] In some embodiments, the pixel defining layer 150 may overlap with a light blocking pattern 250 to be described later. In addition, in some embodiments, the pixel defining layer 150 may also overlap with a bank pattern 370 to be described later.

[0155] like Figure 10 and Figure 13 As shown in FIG, the light emitting layer OL may be positioned on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3.

[0156] In some embodiments, the light-emitting layer OL may have a continuous film shape formed over the plurality of emission areas LA1, LA2, and LA3 and the non-emission area NLA. Although the drawings illustrate that the light-emitting layer OL is positioned only in the display area DA, the present disclosure is not limited thereto. In some other embodiments, a portion of the light-emitting layer OL may also be positioned in the non-display area NDA. A more detailed description of the light-emitting layer OL will be provided later.

[0157] The cathode electrode CE may be located on the light-emitting layer OL. A portion of the cathode electrode CE may also be located in the non-display area NDA. The cathode electrode CE may be electrically connected to the connection electrode CNE in the non-display area NDA and may be in contact with the connection electrode CNE. A driving voltage (e.g., a second driving voltage) supplied to the second driving voltage line VSL may be transmitted to the cathode electrode CE via the connection electrode CNE.

[0158] In some embodiments, the cathode electrode CE may have a semi-transmissive or transmissive property. When the cathode electrode CE has a semi-transmissive property, the cathode electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, or a compound or mixture thereof, such as a mixture of Ag and Mg. In addition, when the cathode electrode CE has a thickness of tens to hundreds of angstroms, the cathode electrode CE may have a semi-transmissive property.

[0159] When the cathode electrode CE has a transmissive property, the cathode electrode CE may include a transparent conductive oxide (TCO). For example, the cathode electrode CE may include tungsten oxide (W x O y ), titanium oxide (TiO2), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), magnesium oxide (MgO), etc.

[0160] In some embodiments, the cathode electrode CE may completely cover the light emitting layer OL. Figure 13 As shown in , an end portion of the cathode electrode CE may be positioned relatively more outward than an end portion of the light emitting layer OL, and the end portion of the light emitting layer OL may be completely covered by the cathode electrode CE.

[0161] The first anode electrode AE1, the light-emitting layer OL, and the cathode electrode CE may constitute a first light-emitting element ED1. The second anode electrode AE2, the light-emitting layer OL, and the cathode electrode CE may constitute a second light-emitting element ED2. The third anode electrode AE3, the light-emitting layer OL, and the cathode electrode CE may constitute a third light-emitting element ED3. Each of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may emit emission light LE.

[0162] like Figure 11 As shown in FIG, the emission light LE finally emitted from the light emitting layer OL may be mixed light in which the first component LE1 and the second component LE2 are mixed. Each of the first component LE1 and the second component LE2 in the emission light LE may have a peak wavelength within a range of 440 nm or greater and less than 480 nm. That is, the emission light LE may be blue light.

[0163] like Figure 11 As shown in , in some embodiments, the light-emitting layer OL may have a structure in which a plurality of light-emitting layers overlap, for example, a tandem structure. For example, the light-emitting layer OL may include a first stack ST1 including a first light-emitting layer EML1, a second stack ST2 positioned on the first stack ST1 and including a second light-emitting layer EML2, a third stack ST3 positioned on the second stack ST2 and including a third light-emitting layer EML3, a first charge generation layer CGL1 positioned between the first stack ST1 and the second stack ST2, and a second charge generation layer CGL2 positioned between the second stack ST2 and the third stack ST3. The first stack ST1, the second stack ST2, and the third stack ST3 may be arranged to overlap each other.

[0164] The first light emitting layer EML1 , the second light emitting layer EML2 , and the third light emitting layer EML3 may be disposed to overlap with each other.

[0165] In some embodiments, all of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit light of a third color, such as blue light. For example, each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be a blue light-emitting layer and may include an organic material.

[0166] In some embodiments, at least one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit first blue light having a first peak wavelength, and at least another of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit second blue light having a second peak wavelength different from the first peak wavelength. For example, any one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit first blue light having a first peak wavelength, and the other two of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit second blue light having a second peak wavelength. That is, the emission light LE ultimately emitted from the light-emitting layer OL may be mixed light in which the first component LE1 and the second component LE2 are mixed, and the first component LE1 may be the first blue light having the first peak wavelength, and the second component LE2 may be the second blue light having the second peak wavelength.

[0167] In some embodiments, one of the first peak wavelength and the second peak wavelength may be within a range of 440 nm or greater and less than 460 nm, and the other may be within a range of 460 nm or greater and less than 480 nm. However, the range of the first peak wavelength and the range of the second peak wavelength are not limited thereto. For example, both the range of the first peak wavelength and the range of the second peak wavelength may include 460 nm. In some embodiments, one of the first blue light and the second blue light may be dark blue, and the other may be sky blue.

[0168] According to some embodiments, the light LE emitted from the light-emitting layer OL may be blue light and may include both long-wavelength and short-wavelength components. Consequently, the light-emitting layer OL may emit blue light having an emission peak within a wide wavelength range as the emitted light LE. This has the advantage of improving color visibility at side viewing angles compared to conventional light-emitting elements that emit blue light with a sharp emission peak.

[0169] In some embodiments, each of the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may include a host and a dopant. The material of the host is not particularly limited as long as it is commonly used. For example, tris(8-hydroxyquinoline)aluminum (Alq3), 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP), poly(n-vinylcarbazole) (PVK), 9,10-di(naphthalene-2-yl)anthracene (ADN), 4,4',4"-tris(carbazol-9-yl)-triphenylamine (TCTA), 1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene (TPBi), 3-tert-butyl-9,10-di(naphthalene-2-yl)anthracene (TBADN), distyrylarylene (DSA), 4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl (CDBP) or 2-methyl-9,10-bis(naphthalene-2-yl)anthracene (MADN) can be used.

[0170] Each of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 that emits blue light may include, for example, a fluorescent material including any one selected from the group consisting of spiro-DPVBi, spiro-6P, distyryl-benzene (DSB), distyryl-arylene (DSA), a polyfluorene (PFO)-based polymer, and a poly(p-phenylene vinylene) (PPV)-based polymer. As another example, a phosphorescent material including an organometallic complex such as (4,6-F2ppy)2Irpic may be included.

[0171] As described above, at least one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 emits blue light in a wavelength range different from the wavelength range of at least another of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3. To emit blue light in different wavelength ranges, the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include the same material, and the resonance distance may be adjusted. In an embodiment, to emit blue light in different wavelength ranges, at least one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 and at least another of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may include different materials from each other.

[0172] However, the present disclosure is not limited thereto, and the first to third light emitting layers EML1 , EML2 , and EML3 may emit blue light having a peak wavelength within the range of 440 nm to 480 nm and may be made of the same material.

[0173] In an embodiment, at least any one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit first blue light having a first peak wavelength, another one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit second blue light having a second peak wavelength different from the first peak wavelength, and the remaining one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may emit third blue light having a third peak wavelength different from the first peak wavelength and the second peak wavelength. In some other embodiments, any one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be within a range of 440 nm or greater and less than 460 nm. Another one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be within a range of 460 nm or greater and less than 470 nm, and the remaining one of the first peak wavelength, the second peak wavelength, and the third peak wavelength may be within a range of 470 nm or greater and less than 480 nm.

[0174] According to some other embodiments, the emission light LE emitted from the light emitting layer OL is blue light and includes a long wavelength component, an intermediate wavelength component, and a short wavelength component. Therefore, the light emitting layer OL can emit blue light having an emission peak in a wide wavelength range as the emission light LE, thereby improving color visibility at a side viewing angle.

[0175] According to the above embodiment, compared with a conventional light emitting element that does not adopt a tandem structure (ie, a structure in which a plurality of light emitting layers are stacked), there are advantages in that light efficiency is increased and the life of the display device 1 is increased.

[0176] In some other embodiments, at least one of the first, second, and third light-emitting layers EML1, EML2, and EML3 may emit light of a third color, such as blue light, and at least another of the first, second, and third light-emitting layers EML1, EML2, and EML3 may emit light of a second color, such as green light. In some other embodiments, the peak wavelength of blue light emitted by at least one of the first, second, and third light-emitting layers EML1, EML2, and EML3 may be within a range of 440 nm or greater and 480 nm or less, or 460 nm or greater and 480 nm or less. The green light emitted from at least one of the first, second, and third light-emitting layers EML1, EML2, and EML3 may have a peak wavelength within a range of 510 nm to 550 nm.

[0177] For example, any one of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be a green light-emitting layer that emits green light, and the remaining two of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 may be blue light-emitting layers that emit blue light. When the remaining two of the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3 are blue light-emitting layers, the peak wavelength ranges of the blue light emitted by the two blue light-emitting layers may be the same, or may be different from each other.

[0178] According to some other embodiments, the emission light LE emitted from the light-emitting layer OL may be a mixed light in which a first component LE1, which is blue light, and a second component LE2, which is green light, are mixed. For example, when the first component LE1 is deep blue light and the second component LE2 is green light, the emission light LE may be sky blue light. Similar to the above-described embodiment, the emission light LE, which is a mixture of blue light and green light, emitted from the light-emitting layer OL includes a long-wavelength component and a short-wavelength component. Therefore, ultimately, the light-emitting layer OL can emit blue light having an emission peak in a wider wavelength range as the emission light LE, thereby improving color visibility at a side viewing angle. In addition, since the second component LE2 of the emission light LE is green light, it can supplement the green light component of the light provided from the display device 1 to the outside, thereby improving the color reproducibility of the display device 1.

[0179] In some embodiments, the green light emitting layer among the first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may include a host and a dopant. The material of the host included in the green light emitting layer is not particularly limited as long as it is commonly used. For example, tris(8-hydroxyquinoline)aluminum (Alq3), 4,4'-bis(N-carbazolyl)-1,1'-biphenyl (CBP), poly(n-vinylcarbazole) (PVK), 9,10-di(naphthalene-2-yl)anthracene (ADN), 4,4',4"-tris(carbazol-9-yl)-triphenylamine (TCTA), 1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene (TPBi), 3-tert-butyl-9,10-di(naphthalene-2-yl)anthracene (TBADN), distyrylarylene (DSA), 4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl (CDBP) or 2-methyl-9,10-bis(naphthalene-2-yl)anthracene (MADN) can be used.

[0180] The dopants included in the green light-emitting layer may include fluorescent materials or phosphorescent materials, the fluorescent materials including, for example, tris(8-hydroxyquinoline)aluminum (Alq3), phosphorescent materials such as fac tris(2-phenylpyridine)iridium (Ir(ppy)3), bis(2-phenylpyridine)(acetylacetonate)iridium(III) (Ir(ppy)2(acac)) and tris(2-phenyl-4-methyl-pyridine)iridium (Ir(mpyp)3).

[0181] The first charge generation layer CGL1 may be positioned between the first and second stacks ST1 and ST2. The first charge generation layer CGL1 may be used to inject charge into each light-emitting layer. The first charge generation layer CGL1 may be used to control the charge balance between the first and second stacks ST1 and ST2. The first charge generation layer CGL1 may include an n-type charge generation layer CGL11 and a p-type charge generation layer CGL12. The p-type charge generation layer CGL12 may be disposed on the n-type charge generation layer CGL11 and between the n-type charge generation layer CGL11 and the second stack ST2.

[0182] The first charge generation layer CGL1 may have a structure in which an n-type charge generation layer CGL11 and a p-type charge generation layer CGL12 are in contact with each other. The n-type charge generation layer CGL11 is positioned closer to the anode electrodes AE1, AE2, and AE3 between the anode electrodes AE1, AE2, and AE3 and the cathode electrode CE. The p-type charge generation layer CGL12 is positioned closer to the cathode electrode CE between the anode electrodes AE1, AE2, and AE3. The n-type charge generation layer CGL11 provides electrons to the first light-emitting layer EML1 adjacent to the anode electrodes AE1, AE2, and AE3, and the p-type charge generation layer CGL12 provides holes to the second light-emitting layer EML2 included in the second stack ST2. The first charge generation layer CGL1 is positioned between the first stack ST1 and the second stack ST2 to provide charges to each light-emitting layer, thereby improving luminous efficiency and reducing driving voltage.

[0183] The first stack ST1 may be positioned on the first, second, and third anode electrodes AE1, AE2, and AE3, and may further include a first hole transport layer HTL1, a first electron blocking layer BIL1, and a first electron transport layer ETL1.

[0184] The first hole transport layer HTL1 may be provided on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first hole transport layer HTL1 is used to promote the transport of holes and may include a hole transport material. The hole transport material may include carbazole-based derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene-based derivatives, triphenylamine-based derivatives such as N,N'-bis(3-methylphenyl)-N,N'-diphenyl)-[1,1-biphenyl]-4,4'-diamine (TPD) and 4,4',4"-tri(N-carbazolyl)triphenylamine (TCTA), N,N'-di(1-naphthyl)-N,N'-diphenylbenzidine (NPB), 4,4'-cyclohexylenebis[N,N-bis(4-methylphenyl)aniline] (TAPC), etc., but the present disclosure is not limited thereto.

[0185] The first electron blocking layer BIL1 may be positioned on the first hole transport layer HTL1 and between the first hole transport layer HTL1 and the first light emitting layer EML1. The first electron blocking layer BIL1 may include a hole transport material and a metal or metal compound to prevent electrons generated in the first light emitting layer EML1 from moving into the first hole transport layer HTL1. In some embodiments, the first hole transport layer HTL1 and the first electron blocking layer BIL1 may be formed as a single layer in which the respective materials are mixed.

[0186] The first electron transport layer ETL1 may be positioned on the first light emitting layer EML1 and between the first charge generation layer CGL1 and the first light emitting layer EML1. In some embodiments, the first electron transport layer ETL1 may include an electron transport material such as tris(8-hydroxyquinoline)aluminum (Alq3), 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)phenyl (TPBi), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole. (TAZ), 4-(naphthalene-1-yl)-3,5-diphenyl-4H-1,2,4-triazole (NTAZ), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD), bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), bis(benzoquinoline-10-hydroxy)beryllium (BeBq2), 9,10-di(naphthalene-2-yl)anthracene (ADN) and mixtures thereof. However, the present disclosure is not limited to the types of electron transport materials. The second stack ST2 can be positioned on the first charge generation layer CGL1 and further include a second hole transport layer HTL2, a second electron blocking layer BIL2 and a second electron transport layer ETL2.

[0187] The second hole transport layer HTL2 may be positioned on the first charge generation layer CGL1. The second hole transport layer HTL2 may be made of the same material as the first hole transport layer HTL1, or may include one or more materials selected from the examples of the materials included in the first hole transport layer HTL1. The second hole transport layer HTL2 may be formed as a single layer or multiple layers.

[0188] The second electron blocking layer BIL2 may be positioned on the second hole transport layer HTL2 and between the second hole transport layer HTL2 and the second light emitting layer EML2. The second electron blocking layer BIL2 may be formed of the same material and the same structure as the first electron blocking layer BIL1, or may include one or more materials selected from the examples of the materials included in the first electron blocking layer BIL1.

[0189] The second electron transport layer ETL2 may be positioned on the second light emitting layer EML2 and between the second charge generation layer CGL2 and the second light emitting layer EML2. The second electron transport layer ETL2 may be formed of the same material and the same structure as the first electron transport layer ETL1, or may include one or more materials selected from the examples of the materials included in the first electron transport layer ETL1. The second electron transport layer ETL2 may be formed as a single layer or multiple layers.

[0190] The second charge generation layer CGL2 may be positioned on the second stack ST2 and between the second stack ST2 and the third stack ST3 .

[0191] The second charge generation layer CGL2 may have the same structure as the first charge generation layer CGL1. For example, the second charge generation layer CGL2 may include an n-type charge generation layer CGL21 disposed closer to the second stack ST2 and a p-type charge generation layer CGL22 disposed closer to the cathode electrode CE. The p-type charge generation layer CGL22 may be disposed on the n-type charge generation layer CGL21.

[0192] The second charge generation layer CGL2 may have a structure in which an n-type charge generation layer CGL21 and a p-type charge generation layer CGL22 contact each other. The first charge generation layer CGL1 and the second charge generation layer CGL2 may be made of different materials or may be made of the same material.

[0193] The third stack ST3 may be positioned on the second charge generation layer CGL2 and may further include a third hole transport layer HTL3 and a third electron transport layer ETL3 .

[0194] The third hole transport layer HTL3 may be positioned on the second charge generation layer CGL2. The third hole transport layer HTL3 may be made of the same material as the first hole transport layer HTL1, or may include one or more materials selected from the examples of the materials included in the first hole transport layer HTL1. The third hole transport layer HTL3 may be formed as a single layer or multiple layers. When the third hole transport layer HTL3 is formed as multiple layers, each layer may include a different material.

[0195] The third electron transport layer ETL3 may be positioned on the third light-emitting layer EML3 and between the cathode electrode CE and the third light-emitting layer EML3. The third electron transport layer ETL3 may be formed of the same material and the same structure as the first electron transport layer ETL1, or may include one or more materials selected from the examples of the materials included in the first electron transport layer ETL1. The third electron transport layer ETL3 may be formed as a single layer or multiple layers. When the third electron transport layer ETL3 is formed as multiple layers, each layer may include a different material.

[0196] Although not shown in the drawings, the hole injection layer may also be positioned at least one of the following: between the first stack ST1 and the first anode electrode AE1, between the second anode electrode AE2 and the third anode electrode AE3, between the second stack ST2 and the first charge generation layer CGL1, and between the third stack ST3 and the second charge generation layer CGL2. The hole injection layer can be used to more smoothly inject holes into the first light-emitting layer EML1, the second light-emitting layer EML2, and the third light-emitting layer EML3. In some embodiments, the hole injection layer may be made of one or more materials selected from the group consisting of copper phthalocyanine (CuPc), poly(3,4)-ethylenedioxythiophene (PEDOT), polyaniline (PANI), and N,N-dinaphthyl-N,N'-diphenylbenzidine (NPD), but the present disclosure is not limited thereto. In some embodiments, the hole injection layer may be positioned between the first stack ST1 and the first anode electrode AE1, between the second anode electrode AE2 and the third anode electrode AE3, between the second stack ST2 and the first charge generation layer CGL1, and between the third stack ST3 and the second charge generation layer CGL2.

[0197] Although not shown in the drawings, the electron injection layer may also be positioned at least one of the following: between the third electron transport layer ETL3 and the cathode electrode CE, between the second charge generation layer CGL2 and the second stack ST2, and between the first charge generation layer CGL1 and the first stack ST1. The electron injection layer is used to promote electron injection and may be made of tris(8-hydroxyquinoline)aluminum (Alq3), PBD, TAZ, spiro-PBD, BAlq or SAlq, but the present disclosure is not limited thereto. In addition, the electron injection layer may be a metal halide and may include one or more materials selected from the group consisting of MgF2, LiF, NaF, KF, RbF, CsF, FrF, LiI, NaI, KI, RbI, CsI, FrI and CaF2, but the present disclosure is not limited thereto. In addition, the electron injection layer may include lanthanum-based materials such as Yb, Sm, Eu, etc. In an embodiment, the electron injection layer may include both metal halide materials and lanthanum-based materials, such as RbI:Yb, KI:Yb, etc. When the electron injection layer includes both the metal halide material and the lanthanum-based material, the electron injection layer may be formed by co-deposition of the metal halide material and the lanthanum-based material. In some embodiments, the electron injection layer may be positioned between the third electron transport layer ETL3 and the cathode electrode CE, between the second charge generation layer CGL2 and the second stack ST2, and between the first charge generation layer CGL1 and the first stack ST1.

[0198] In addition to the above structure, the light emitting layer OL may have a modified structure. For example, the light emitting layer OL may be deformed into Figure 12 The light-emitting layer OLa shown in FIG. Figure 11 The structure shown in Figure 12 The light emitting layer OLa shown in FIG may further include a fourth stack ST4 on the third stack ST3 , and may further include a third charge generation layer CGL3 positioned between the third stack ST3 and the fourth stack ST4 .

[0199] The fourth stack ST4 may include a fourth light emitting layer EML4, and may further include a fourth hole transport layer HTL4 and a fourth electron transport layer ETL4.

[0200] Each of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 included in the light-emitting layer OLa may emit light of a third color, for example, blue light. At least one of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 and at least another one of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 may emit blue light having different peak wavelength ranges.

[0201] In an embodiment, at least one of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 may emit green light, and at least another one of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 may emit blue light. For example, any one of the first light-emitting layer EML1, the second light-emitting layer EML2, the third light-emitting layer EML3, and the fourth light-emitting layer EML4 may be a green light-emitting layer, and the remaining three light-emitting layers may be blue light-emitting layers.

[0202] In an embodiment, the fourth light emitting layer EML4 may be a green light emitting layer, and all of the first light emitting layer EML1 , the second light emitting layer EML2 , and the third light emitting layer EML3 may be blue light emitting layers.

[0203] The fourth hole transport layer HTL4 may be positioned on the second charge generation layer CGL2. The fourth hole transport layer HTL4 may be made of the same material as the first hole transport layer HTL1, or may include one or more materials selected from the examples of the materials included in the first hole transport layer HTL1. The fourth hole transport layer HTL4 may be formed as a single layer or multiple layers. When the fourth hole transport layer HTL4 is formed of multiple layers, each layer may include a different material.

[0204] The third electron blocking layer BIL3 may be positioned on the third hole transport layer HTL3 and may be positioned between the third hole transport layer HTL3 and the third light emitting layer EML3. The third electron blocking layer BIL3 may be formed of the same material and the same structure as the first electron blocking layer BIL1, or may include one or more materials selected from the examples of the materials included in the first electron blocking layer BIL1. In some other embodiments, the third electron blocking layer BIL3 may be omitted.

[0205] The fourth electron transport layer ETL4 may be positioned on the fourth light-emitting layer EML4 and between the fourth light-emitting layer EML4 and the cathode electrode CE. The fourth electron transport layer ETL4 may be formed of the same material and the same structure as the first electron transport layer ETL1, or may include one or more materials selected from the examples of the materials included in the first electron transport layer ETL1. The fourth electron transport layer ETL4 may be formed as a single layer or multiple layers. When the fourth electron transport layer ETL4 is formed as multiple layers, each layer may include a different material.

[0206] The third charge generation layer CGL3 may have the same structure as the first charge generation layer CGL1. For example, the third charge generation layer CGL3 may include an n-type charge generation layer CGL31 disposed closer to the second stack ST2 and a p-type charge generation layer CGL32 disposed closer to the cathode electrode CE. The p-type charge generation layer CGL32 may be disposed on the n-type charge generation layer CGL31.

[0207] Although not shown in the drawings, an electron injection layer may be further positioned between the fourth stack ST4 and the cathode electrode CE. In addition, a hole injection layer may be further positioned between the fourth stack ST4 and the third charge generation layer CGL3.

[0208] In some embodiments, Figure 11 The light emitting layer OL shown in FIG Figure 12 The light-emitting layers OLa shown in FIG and FIG may both not include a red light-emitting layer and therefore may not emit light of the first color, for example, red light. That is, the emitted light LE may not include a light component having a peak wavelength of 610 nm to about 650 nm, and the emitted light LE may only include a light component having a peak wavelength of 440 nm to 550 nm.

[0209] like Figure 13 As shown in FIG, the dam member DM may be positioned on the passivation layer 117 in the non-display area NDA.

[0210] The dam member DM may be positioned relatively further outward than the second driving voltage line VSL. Figure 13 As shown in FIG, the second driving voltage line VSL may be positioned between the dam member DM and the display area DA.

[0211] In some embodiments, the dam member DM may include a plurality of dams. For example, the dam member DM may include a first dam D1 and a second dam D2.

[0212] The first dam D1 may partially overlap the second driving voltage line VSL and may be spaced apart from the via layer 130 with the second driving voltage line VSL interposed therebetween. In some embodiments, the first dam D1 may include a first lower dam pattern D11 positioned on the passivation layer 117 and a first upper dam pattern D12 positioned on the first lower dam pattern D11.

[0213] The second dam D2 may be positioned further outward than the first dam D1 and may be spaced apart from the first dam D1. In some embodiments, the second dam D2 may include a second lower dam pattern D21 positioned on the passivation layer 117 and a second upper dam pattern D22 positioned on the second lower dam pattern D21.

[0214] In some embodiments, the first and second lower dam patterns D11 and D21 may be made of the same material as the via layer 130 and may be formed simultaneously with the via layer 130 .

[0215] In some embodiments, the first upper dam pattern D12 and the second upper dam pattern D22 may be made of the same material as the pixel defining layer 150 and may be formed simultaneously with the pixel defining layer 150 .

[0216] In some embodiments, the heights of the first dam D1 and the second dam D2 can be different. For example, the height of the second dam D2 can be higher than that of the first dam D1. That is, the height of the dam included in the dam member DM can gradually increase as the distance from the display area DA increases. Therefore, it is possible to effectively prevent the organic material from overflowing during the process of forming the organic layer 173 included in the encapsulation layer 170, which will be described later.

[0217] like Figure 10 and Figure 13 As shown in , the capping layer 160 may be positioned on the cathode electrode CE. The capping layer 160 may be commonly disposed in the first emission area LA1, the second emission area LA2, the third emission area LA3, and the non-emission area NLA, and may improve viewing angle characteristics and enhance external light emitting efficiency.

[0218] The capping layer 160 may include at least one of an inorganic material and an organic material having a light-transmitting property. That is, the capping layer 160 may be formed of an inorganic layer, an organic layer, or an organic layer including inorganic particles. For example, the capping layer 160 may include a triamine derivative, a carbazole biphenyl derivative, an aromatic diamine derivative, a quinoline aluminum complex (Alq3), and the like.

[0219] In addition, the capping layer 160 may be made of a mixture of a high-refractive material and a low-refractive material. In an embodiment, the capping layer 160 may include two layers having different refractive indices, such as a high-refractive layer and a low-refractive layer.

[0220] In some embodiments, the capping layer 160 may completely cover the cathode electrode CE. Figure 13 As shown in , the end of the capping layer 160 may be positioned relatively more outward than the end of the cathode electrode CE, and the end of the cathode electrode CE may be completely covered by the capping layer 160 .

[0221] The encapsulation layer 170 may be disposed on the capping layer 160. The encapsulation layer 170 protects components such as the light-emitting elements ED1, ED2, and ED3 positioned below the encapsulation layer 170 from foreign matter such as moisture. The encapsulation layer 170 is commonly disposed in the first emission area LA1, the second emission area LA2, the third emission area LA3, and the non-emission area NLA. In some embodiments, the encapsulation layer 170 may directly cover the cathode electrode CE. In some embodiments, a capping layer 160 covering the cathode electrode CE may further be disposed between the encapsulation layer 170 and the cathode electrode CE. In this case, the encapsulation layer 170 may directly cover the capping layer 160. The encapsulation layer 170 may be a thin film encapsulation layer.

[0222] In some embodiments, the encapsulation layer 170 may include a lower inorganic layer 171 , an organic layer 173 , and an upper inorganic layer 175 sequentially stacked on the capping layer 160 .

[0223] In some embodiments, the lower inorganic layer 171 may cover the first, second, and third light emitting elements ED1, ED2, and ED3 in the display area DA. The lower inorganic layer 171 may cover the dam member DM in the non-display area NDA and may extend outside the dam member DM.

[0224] In some embodiments, the lower inorganic layer 171 may completely cover the capping layer 160. In some embodiments, an end portion of the lower inorganic layer 171 may be relatively more positioned outward than an end portion of the capping layer 160, and an end portion of the capping layer 160 may be completely covered by the lower inorganic layer 171.

[0225] The lower inorganic layer 171 may include a plurality of stacked layers. The organic layer 173 may be positioned on the lower inorganic layer 171. The organic layer 173 may cover the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 in the display area DA. In some embodiments, a portion of the organic layer 173 may be positioned in the non-display area NDA and may not be positioned further outward than the dam member DM. Although a portion of the organic layer 173 is shown as being positioned further inward than the first dam D1, the present disclosure is not limited thereto. In some other embodiments, a portion of the organic layer 173 may be accommodated in the space between the first dam D1 and the second dam D2, and an end portion of the organic layer 173 may be positioned in the region between the first dam D1 and the second dam D2.

[0226] The upper inorganic layer 175 may be positioned on the organic layer 173. The upper inorganic layer 175 may cover the organic layer 173. In some embodiments, the upper inorganic layer 175 may be in direct contact with the lower inorganic layer 171 in the non-display area NDA to form an inorganic-inorganic junction. In some embodiments, the end of the upper inorganic layer 175 and the end of the lower inorganic layer 171 may be substantially aligned. The upper inorganic layer 175 may include a plurality of stacked layers.

[0227] In some embodiments, each of the lower inorganic layer 171 and the upper inorganic layer 175 can be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride (SiON), lithium fluoride, etc.

[0228] In some embodiments, the organic layer 173 may be formed of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, perylene resin, or the like.

[0229] In the following, reference will be made to Figure 14 and Figure 15 The aforementioned dummy line DML is described in more detail.

[0230] Figure 14 is a plan view of a dummy line DML in a base substrate including a display panel 100 and peripheral components according to an embodiment.

[0231] First, the display panel 100 of the display device 1 can be manufactured by cutting (or separating) a base substrate (or mother substrate) into unit cells. For example, by cutting the base substrate along the scribe lines SCL, a plurality of display panels 100 can be manufactured in unit cells. Figure 14 FIG is a diagram showing a base substrate before a scribing process. Figure 14 The upper portion of the scribing line SCL corresponds to the display panel 100, and the lower portion corresponds to the dummy panel DMP that is removed after the scribing process. The display panel 100 may include the display area DA and the non-display area NDA described above. In other words, the portion above the scribing line SCL corresponds to the display panel 100 of the display device 1 described above.

[0232] A first upper voltage line VDLb may be provided on the display panel 100 and the dummy panel DMP.

[0233] The second driving voltage line VSL may be provided on the display panel 100 and the dummy panel DMP.

[0234] The data lines DL1, DL2, and DL3 may be disposed on the display panel 100 and the dummy panel DMP. The data lines DL1, DL2, and DL3 may overlap the first upper voltage line VDLb and the second driving voltage line VSL on the display panel 100.

[0235] The initialization voltage line VIL may be provided on the display panel 100 and the dummy panel DMP. The initialization voltage line VIL may overlap the first upper voltage line VDLb and the second driving voltage line VSL on the display panel 100.

[0236] The dummy line DML may be provided on the display panel 100 and the dummy panel DMP. The dummy line DML may overlap with the first upper voltage line VDLb and the second drive voltage line VSL on the display panel 100. The dummy line DML may have a curved shape. The dummy line DML may be provided adjacent to the initialization voltage line VIL.

[0237] A first voltage transmission line VTL1 may be provided on the dummy panel DMP. The first voltage transmission line VTL1 may transmit a first driving voltage. The first voltage transmission line VTL1 may overlap with the first upper voltage line VDLb, the second driving voltage line VSL, and the dummy line DML on the dummy panel DMP. The first voltage transmission line VTL1 and the first upper voltage line VDLb may be connected to each other on the dummy panel DMP. For example, the first voltage transmission line VTL1 and the first upper voltage line VDLb may be connected to each other at the intersection of the first voltage transmission line VTL1 and the first upper voltage line VDLb. In some embodiments, the first voltage transmission line VTL1 and the dummy line DML may be connected to each other on the dummy panel DMP. For example, the first voltage transmission line VTL1 and the dummy line DML may be connected to each other at the intersection of the first voltage transmission line VTL1 and the dummy line DML. As another example, the first voltage transmission line VTL1 may not be connected to the dummy line DML.

[0238] A second voltage transmission line VTL2 may be provided on the dummy panel DMP. The second voltage transmission line VTL2 may transmit a second driving voltage. The second voltage transmission line VTL2 may overlap with the second driving voltage line VSL on the dummy panel DMP. The second voltage transmission line VTL2 and the second driving voltage line VSL may be connected to each other on the dummy panel DMP. For example, the second voltage transmission line VTL2 and the second driving voltage line VSL may be connected to each other at an intersection of the second voltage transmission line VTL2 and the second driving voltage line VSL.

[0239] The third voltage transmission line VTL3 may be provided on the dummy panel DMP. The third voltage transmission line VTL3 may transmit an initialization voltage. The third voltage transmission line VTL3 may overlap the first upper voltage line VDLb, the second driving voltage line VSL, and the dummy line DML on the dummy panel DMP.

[0240] The gate transmission line GTL may be disposed on the dummy panel DMP. The gate transmission line GTL may overlap the first upper voltage line VDLb, the second driving voltage line VSL, and the dummy line DML on the dummy panel DMP.

[0241] A test transistor TR may be provided on the dummy panel DMP. A gate electrode of the test transistor TR may be connected to the gate transmission line GTL, a source electrode thereof may be connected to the third voltage transmission line VTL3, and a drain electrode thereof may be connected to the initialization voltage line VIL via the inspection pad electrode PT. The test transistor TR may be turned on in response to a gate signal from the gate transmission line GTL to connect the inspection pad electrode PT and the third voltage transmission line VTL3 to each other.

[0242] The first data transmission line DTL1 may be provided on the dummy panel DMP. The first data transmission line DTL1 may overlap with the first upper voltage line VDLb, the second drive voltage line VSL, the initialization voltage line VIL, the dummy line DML, and the first data line DL1 on the dummy panel DMP. The first data transmission line DTL1 and the first data line DL1 may be connected to each other on the dummy panel DMP. For example, the first data transmission line DTL1 and the first data line DL1 may be connected to each other at the intersection of the first data transmission line DTL1 and the first data line DL1. For example, the first data transmission line DTL1 may transmit the first data voltage required for light emission of a pixel providing red light.

[0243] A second data transmission line DTL2 may be provided on the dummy panel DMP. The second data transmission line DTL2 may overlap with the first upper voltage line VDLb, the second drive voltage line VSL, the initialization voltage line VIL, the dummy line DML, the first data line DL1, the second data line DL2, and the third data line DL3 on the dummy panel DMP. The second data transmission line DTL2 and the second data line DL2 may be connected to each other on the dummy panel DMP. For example, the second data transmission line DTL2 and the second data line DL2 may be connected to each other at the intersection of the second data transmission line DTL2 and the second data line DL2. For example, the second data transmission line DTL2 may transmit a second data voltage required for light emission of a pixel providing green light.

[0244] A third data transmission line DTL3 may be provided on the dummy panel DMP. The third data transmission line DTL3 may overlap with the first upper voltage line VDLb, the second drive voltage line VSL, the initialization voltage line VIL, the dummy line DML, the first data line DL1, and the third data line DL3 on the dummy panel DMP. The third data transmission line DTL3 and the third data line DL3 may be connected to each other on the dummy panel DMP. For example, the third data transmission line DTL3 and the third data line DL3 may be connected to each other at the intersection of the third data transmission line DTL3 and the third data line DL3. For example, the third data transmission line DTL3 may transmit a third data voltage required for light emission of a pixel providing blue light.

[0245] According to some embodiments, the first data line DL1 may include a signal line disposed in the display area DA and a link line (or connection line) disposed in the fan-out area of ​​the non-display area NDA. Here, the signal line of the first data line DL1 may be connected to the link line of the first data line DL1. Figure 14 The first data line DL1 shown in FIG. 5 may be, for example, a link line of the first data line DL1 . In addition, the second data line DL2 and the third data line DL3 may also include signal lines and link lines similar to those of the first data line DL1 . Figure 14 The second data line DL2 shown in FIG may be, for example, a link line of the second data line DL2. Figure 14 The third data line DL3 shown in FIG. 5 may be, for example, a link line of the third data line DL3 .

[0246] Static electricity may be generated when various processes are performed on the base substrate, and the static electricity may be discharged to the outside through the turned-on test transistor TR. For example, when static electricity is generated in the initialization voltage line VIL during the process, the static electricity in the initialization voltage line VIL may be discharged to the third voltage transmission line VTL3 through the turned-on test transistor TR.

[0247] In addition, during the inspection process, the current of each pixel is detected by the inspection pad electrode PT and the initialization voltage line VIL, and the detected current can be measured to verify whether each pixel is defective. For inspection, the aforementioned gate signal, the first driving voltage, the second driving voltage, the initialization voltage, the first data voltage, the second data voltage, and the third data voltage can be applied to the gate transmission line GTL, the first voltage transmission line VTL1, the second voltage transmission line VTL2, the third voltage transmission line VTL3, the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3, respectively.

[0248] When static electricity flows into the first upper voltage line VDLb, charge may accumulate in the first upper voltage line VDLb due to static electricity. Specifically, the charge of the first upper voltage line VDLb may be concentratedly accumulated in the overlapping area OVA of the first upper voltage line VDLb and the initialization voltage line VIL. For example, a large amount of charge may be accumulated in the overlapping area OVA of the first upper voltage line VDLb and the initialization voltage line VIL through the parasitic capacitance formed in the overlapping area OVA. In this case, the insulating layer (for example, the buffer layer 111 and the gate insulating layer 115) between the first upper voltage line VDLb and the initialization voltage line VIL may be damaged or destroyed. In particular, damage or destruction of the insulating layer may occur in the step portion of the insulating layer. In this case, there may be a problem of short circuit between the first drive voltage line VDL (for example, the first upper voltage line VDLb) and the initialization voltage line VIL.

[0249] According to some embodiments, the dummy line DML can be set to overlap with the first upper voltage line VDLb so as to prevent a large amount of charge from accumulating in the overlapping area OVA of the first upper voltage line VDLb and the initialization voltage line VIL. Through the dummy line DML, the charge of the first upper voltage line VDLb can be dispersed and not concentrated in the overlapping area OVA of the first upper voltage line VDLb and the initialization voltage line VIL. In other words, the charge of the first upper voltage line VDLb can be dispersed to both the initialization voltage line VIL and the dummy line DML, and accumulated in both the initialization voltage line VIL and the dummy line DML. Therefore, a short circuit between the first upper voltage line VDLb and the initialization voltage line VIL can be prevented by the dummy line DML. This charge distribution principle will be referred to in detail later. Figure 16 and Figure 17 Describe in more detail.

[0250] During the manufacturing process of the display device 1 before the dummy panel DMP is removed, the dummy line DML can remain connected to the first voltage transmission line VTL1. Therefore, during the manufacturing process of the display device 1, the dummy line DML can be at the same potential as the first voltage transmission line VTL1. For example, the dummy line DML receives the first drive voltage from the first voltage transmission line VTL1, so that the voltage of the dummy line DML and the voltage of the first voltage transmission line VTL1 can be at the same potential. Therefore, it is possible to prevent charges generated by static electricity from concentrating in specific areas during the manufacturing process of the display device 1.

[0251] Figure 15 Among them Figure 14 FIG. 1 is a plan view of the display device 1 with the dummy panel DMP removed from the base substrate.

[0252] When the dummy panel DMP is removed from the base substrate through the aforementioned scribing process, a portion of the first upper voltage line VDLb, a portion of the second driving voltage line VSL, a portion of the first data line DL1, a portion of the initialization voltage line VIL, a portion of the second data line DL2, a portion of the third data line DL3, a portion of the dummy line DML, the first data transmission line DTL1, the second data transmission line DTL2, the third data transmission line DTL3, the gate transmission line GTL, the first voltage transmission line VTL1, the second voltage transmission line VTL2, the third voltage transmission line VTL3, the inspection pad electrode PT, and the test transistor TR on the dummy panel DMP may be as shown. Figure 15 shown in is removed.

[0253] Therefore, if Figure 15 As shown in , a portion of the first upper voltage line VDLb, a portion of the second driving voltage line VSL, a portion of the first data line DL1, a portion of the initialization voltage line VIL, a portion of the second data line DL2, a portion of the third data line DL3, and a portion of the dummy line DML can be set on the display panel 100.

[0254] According to some embodiments, Figure 15 As shown in , the dummy line DML may be maintained in a floating state. For example, the dummy line DML may be provided in the non-display area NDA of the display panel 100 in a floating state in which the dummy line DML is not directly connected to any signal line.

[0255] According to some embodiments, Figure 15 As shown in FIG, one end EG1 of the dummy line DML may be disposed to correspond to one end EG2 (or edge) of the first substrate 110. For example, one end EG1 of the dummy line DML may be disposed to coincide with one end EG2 of the first substrate 110. This is due to the fact that the dummy line DML and the first substrate 110 are cut together along the scribe line SCL.

[0256] According to some embodiments, one end EG1 of the dummy line DML may have a carbonized region. The carbonized region may be black. For example, when a laser is used in the scribing process, the portion of the dummy line DML cut by the laser along the scribing line SCL (e.g., one end EG1 of the dummy line DML) may be carbonized by the laser irradiation.

[0257] like Figure 15 As shown in FIG, even after the removal process of the dummy panel DMP, the dummy line DML still overlaps the first upper voltage line VDLb. Therefore, as described above, it is possible to prevent the insulation layer from being damaged and the short circuit between the first upper voltage line VDLb and the initialization voltage line VIL caused by charge accumulation due to static electricity.

[0258] Figure 16 is used to describe the Figure 14 Diagram of the charge distribution caused by the imaginary line DML.

[0259] like Figure 16 As shown in FIG, the dummy line DML and the first upper voltage line VDLb can be connected to each other via the first voltage transmission line VTL1. Therefore, there may be an effect of increasing the area of ​​the first upper voltage line VDLb. Therefore, the charge accumulated in the first upper voltage line VDLb due to static electricity can be dispersed, thereby reducing the charge density. Therefore, the aforementioned problems caused by static electricity (for example, a short circuit between the first upper voltage line VDLb and the initialization voltage line VIL) can be prevented.

[0260] like Figure 16 As shown in FIG, charges generated by static electricity of the first upper voltage line VDLb may be discharged to the dummy line DML through the first voltage transmission line VTL1. Figure 16 The arrows in the figure represent the paths of charge movement.

[0261] exist Figure 16 , the first resistor R1 refers to the resistance between the first upper voltage line VDLb and the dummy line DML connected by the first voltage transmission line VTL1, the second resistor R2 refers to the resistance between the first upper voltage line VDLb and the initialization voltage line VIL, and the capacitor Cp refers to the capacitance between the first upper voltage line VDLb and the initialization voltage line VIL.

[0262] Figure 17 is used to describe the Figure 15 Diagram of the charge distribution caused by the imaginary line DML.

[0263] like Figure 17 As shown in FIG, a first resistor R1 and a first capacitor Cp1 can be formed between the first upper voltage line VDLb and the floating dummy line DML, and a second resistor R2 and a second capacitor Cp2 can be formed between the first upper voltage line VDLb and the initialization voltage line VIL. By floating the dummy line DML, the charge of the first upper voltage line VDLb can be dispersed rather than concentrated in the overlapping area OVA of the first upper voltage line VDLb and the initialization voltage line VIL. In other words, the charge of the first upper voltage line VDLb can be dispersed to both the first capacitor Cp1 and the second capacitor Cp2, and accumulated in both the first capacitor Cp1 and the second capacitor Cp2. Therefore, a short circuit between the first upper voltage line VDLb and the initialization voltage line VIL can be prevented by the dummy line DML.

[0264] like Figure 17As shown in , charges generated by static electricity of the first upper voltage line VDLb may be dispersed to both the first capacitor Cp1 and the second capacitor Cp2 and accumulated in both the first capacitor Cp1 and the second capacitor Cp2. Figure 17 The arrows in the figure represent the paths of charge movement.

[0265] Figure 18 is a plan view of a dummy line DML in a base substrate including a display panel 100 and peripheral components according to an embodiment. Figure 19 Among them Figure 18 A plan view of a display device with the dummy panel DMP removed from the base substrate.

[0266] Figure 18 and Figure 19 The display device and the aforementioned Figure 14 and Figure 15 The display device 1 is different in that it includes two dummy lines DML1 and DML2. The following description focuses on the difference.

[0267] like Figure 18 and Figure 19 As shown in , the display device may include a first dummy line DML1 and a second dummy line DML2 .

[0268] Since the first dummy line DML1 is Figure 14 and Figure 15 The imaginary line DML shown in is the same, so use Figure 14 and Figure 15 The description of the dummy line DML shown in FIG. 1 replaces the description of the first dummy line DML1 .

[0269] The second dummy line DML2 may be disposed adjacent to the first dummy line DML1. The second dummy line DML2 may be disposed parallel to the first dummy line DML1. Similar to the first dummy line DML1, the second dummy line DML2 may overlap the first upper voltage line VDLb and the second driving voltage line VSL on the display panel 100.

[0270] The first dummy line DML1 and the second dummy line DML2 may not be connected to each other. However, when the first dummy line DML1 and the second dummy line DML2 are connected to the first upper voltage line VDLb via the damaged insulating layers 111 and 115, the first dummy line DML1 may be indirectly connected to the second dummy line DML2 via the first upper voltage line VDLb.

[0271] Therefore, more charges of the first upper voltage line VDLb can be dispersed through the plurality of dummy lines DML1 and DML2. Therefore, damage and destruction of the insulating layer due to static electricity can be more effectively prevented.

[0272] According to some embodiments, Figure 19 As shown in FIG, one end EG1′ of the second dummy line DML2 may be disposed to correspond to one end EG2 (or edge) of the first substrate 110. For example, one end EG1′ of the second dummy line DML2 may be disposed to coincide with one end EG2 of the first substrate 110. This is due to the fact that the second dummy line DML2 and the first substrate 110 are cut together along the scribe line SCL.

[0273] According to some embodiments, one end EG1' of the second dummy line DML2 may have a carbonized region. The carbonized region may be black. For example, when a laser is used in the scribing process, the portion of the dummy line cut by the laser along the scribing line SCL (e.g., one end EG1' of the second dummy line DML2) may be carbonized by the laser irradiation.

[0274] According to some embodiments, a display device may include three or more dummy lines.

[0275] Figure 20 is a diagram showing the result of a simulation to which the configuration of the display device according to the embodiment is applied.

[0276] like Figure 20 As shown in FIG, the first dummy line DML1 and the second dummy line DML2 may overlap the first driving voltage line VDL (eg, a first upper voltage line VDLb of the first driving voltage line VDL).

[0277] In this case, the intensity of the electric field in the first region A of the first upper voltage line VDLb is approximately 1.4 MV / m, and the intensity of the electric field in the second region B between the first upper voltage line VDLb and the second driving voltage line VSL is approximately 1.3 MV / m. For example, these values ​​can be significantly lower than those in the corresponding overlapping regions A and B in a comparative disclosure that does not include the dummy line DML. For example, in the comparative disclosure, the intensity of the electric field in the first region A is 86 MV / m, and the intensity of the electric field in the second region B is 33 MV / m.

[0278] Figure 21 and Figure 22 is a plan view of a display device according to an embodiment.

[0279] Figure 21 and Figure 22 Display device and Figure 14 The display device 1 is different from the display device 1 in that the dummy line DML and the inspection pad electrode PT are provided. The following description focuses on the differences.

[0280] like Figure 21As shown in , one common inspection pad electrode CPT can be commonly connected to each of the drain terminals of the test transistor TR on the dummy panel DMP. In this case, the area of ​​the common inspection pad electrode CPT can be increased. Therefore, static electricity generated in the initialization voltage line VIL can be effectively discharged.

[0281] To determine whether each pixel is defective, the test pad electrodes PT need to be separated from each other and connected to the corresponding test transistors TR. Therefore, after removing static electricity, the common test pad electrode CPT can be separated into multiple test pad electrodes PT. For example, during the aforementioned patterning step of the anode electrode (e.g., the first anode electrode AE1), the common test pad electrode CPT can be etched and separated into the multiple test pad electrodes PT. In other words, the anode electrodes AE1, AE3, and AE3 and the multiple test pad electrodes PT can be formed together through the same patterning process (e.g., photolithography and etching).

[0282] It will be understood by those skilled in the art that the present disclosure may be implemented in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above exemplary embodiments are exemplary and not restrictive in all aspects. It should be understood that the scope of the present disclosure is defined by the claims rather than the above detailed description, and all modifications and variations derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device comprising: A substrate having a display area and a non-display area; Pixels are arranged in the display area; a first driving voltage line connected to the pixel in the display area and extending to the non-display area; an initialization voltage line connected to the pixel in the display area, extending to the non-display area, and overlapping with the first driving voltage line in the non-display area; as well as The dummy line is disposed in the non-display area and overlaps with the first driving voltage line.

2. The display device according to claim 1, wherein The dummy line has a floating state.

3. The display device according to claim 1, wherein The dummy line is disposed on the same layer as the initialization voltage line.

4. The display device according to claim 1, wherein The first driving voltage line includes: a first lower voltage line disposed on the substrate and extending in a first direction; and A first upper voltage line is connected to the first lower voltage line on the first lower voltage line and extends in a second direction intersecting the first direction.

5. The display device according to claim 4, wherein The dummy line overlaps with the first upper voltage line. The display device according to claim 4 , wherein: The dummy line is connected to the first upper voltage line.

7. The display device according to claim 4, wherein The dummy line is disposed on the same layer as the first lower voltage line.

8. The display device according to claim 4, further comprising an insulating layer between the first lower voltage line and the first upper voltage line, in, The dummy line is disposed between the substrate and the insulating layer.

9. The display device according to claim 1, wherein The dummy line is disposed adjacent to the initialization voltage line.

10. The display device according to claim 1, wherein One end portion of the dummy line is disposed at one end portion of the substrate.

11. The display device according to claim 10, wherein: The one end portion of the imaginary line includes a carbonized region.

12. The display device according to claim 1, wherein The dummy line has a width greater than that of the initialization voltage line.

13. The display device according to claim 1, wherein The dummy lines are arranged into a plurality of dummy lines.

14. The display device according to claim 13, wherein: The plurality of dummy lines each overlap with the first driving voltage line, and The plurality of dummy lines are not connected to each other. 15 . The display device of claim 1 , further comprising a second driving voltage line overlapping the dummy line and the initialization voltage line in the non-display area.

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