Memory device, operating method thereof, and memory system

Abstract

Embodiments of the present disclosure provide a memory device, an operating method thereof, and a memory system, the memory device including: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit is configured to perform a programming operation of a target state on a target memory cell in the plurality of memory cells; verification operation is conducted on the target storage unit subjected to the programming operation in the target state, the verification operation comprises first verification operation and second verification operation, and the voltage corresponding to the second verification operation is larger than the voltage corresponding to the first verification operation; in a verification operation process, recording a failure bit count of the first verification operation; when it is determined that the failure bit count is smaller than or equal to the preset value, only the second verification operation is executed in the next verification operation of the programming operation of the target state.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device, an operating method thereof, and a memory system. Background Art

[0002] Memory devices are used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND Flash memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as the requirements for memory devices continue to increase, many problems still exist when performing programming operations on memory devices. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory device, an operating method thereof, and a memory system.

[0005] In a first aspect, an embodiment of the present disclosure provides a memory device, comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit being configured to: perform a target state programming operation on a target memory cell among the plurality of memory cells; perform a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation comprising a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only executing the second verification operation in the next verification operation of the target state programming operation.

[0006] In an optional embodiment, the peripheral circuit is further configured to: when it is determined that the fail bit count is greater than the preset value, perform the first verification operation and the second verification operation in a next verification operation of the program operation of the target state.

[0007] In an optional embodiment, the first verification operation includes a first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; and when it is determined that the first fail bit count is less than or equal to the first preset value, only perform the second verification operation in the next verification operation of the programming operation of the target state.

[0008] In an optional embodiment, the first verification operation includes a first sub-verification operation and a second sub-verification operation, and the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to the first preset value, only perform the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state; or, record a second fail bit count of the second sub-verification operation; when it is determined that the second fail bit count is less than or equal to the second preset value, only perform the second verification operation in the next verification operation of the programming operation of the target state.

[0009] In an optional embodiment, the first verification operation includes a first sub-verification operation, a second sub-verification operation and a third sub-verification operation, the voltage corresponding to the third sub-verification operation is greater than the voltage corresponding to the second sub-verification operation, and the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to the first preset value, only the second sub-verification operation, the third sub-verification operation and the second verification operation are executed in the next verification operation of the programming operation of the target state; or, record a second fail bit count of the second sub-verification operation; when it is determined that the second fail bit count is less than or equal to the second preset value, only the third sub-verification operation and the second verification operation are executed in the next verification operation of the programming operation of the target state; or, record a third fail bit count of the third sub-verification operation; when it is determined that the third fail bit count is less than or equal to the third preset value, only the second verification operation is executed in the next verification operation of the programming operation of the target state.

[0010] In an optional embodiment, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails to pass the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails to pass the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, and the second bit line voltage is less than the third bit line voltage.

[0011] In an optional embodiment, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second sub-verification operation; apply a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

[0012] In an optional embodiment, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that has not passed the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the first sub-verification operation but has not passed the second sub-verification operation; apply a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second sub-verification operation but has not passed the third sub-verification operation; apply a fifth bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the third sub-verification operation but has not passed the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second verification operation; wherein, the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory system, comprising: the memory device as described in the first aspect; and a memory controller; the memory controller is coupled to the memory device and is used to control the memory device.

[0014] In a third aspect, an embodiment of the present disclosure provides an operating method for a memory device, wherein the memory device comprises: a memory cell array comprising a plurality of memory cells; the operating method comprises: performing a target state programming operation on a target memory cell among the plurality of memory cells; performing a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation comprising a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only executing the second verification operation in the next verification operation of the target state programming operation.

[0015] In an optional embodiment, the method further includes: when it is determined that the fail bit count is greater than the preset value, performing the first verification operation and the second verification operation in a next verification operation of the program operation of the target state.

[0016] In an optional embodiment, the first verification operation includes a first sub-verification operation; recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state, including: recording a first fail bit count of the first sub-verification operation; and when it is determined that the first fail bit count is less than or equal to the first preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state.

[0017] In an optional embodiment, the first verification operation includes a first sub-verification operation and a second sub-verification operation, the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state, including: recording a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to the first preset value, only performing the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state; or, recording a second fail bit count of the second coarse verification operation; when it is determined that the second fail bit count is less than or equal to the second preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state.

[0018] In an optional embodiment, the first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, the voltage corresponding to the third sub-verification operation is greater than the voltage corresponding to the second sub-verification operation, and the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state, including: recording a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to the first preset value, only performing the second sub-verification operation, the third sub-verification operation, and the second verification operation in the next verification operation of the programming operation of the target state; or, recording a second fail bit count of the second sub-verification operation; when it is determined that the second fail bit count is less than or equal to the second preset value, only performing the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state; or, recording a third fail bit count of the third sub-verification operation; and when it is determined that the third fail bit count is less than or equal to the third preset value, only performing the second verification operation in the next verification operation of the programming operation of the target state.

[0019] In an optional embodiment, the method further includes: applying a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails to pass the first sub-verification operation; applying a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails to pass the second verification operation; and applying a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, and the second bit line voltage is less than the third bit line voltage.

[0020] In an optional embodiment, the method further includes: applying a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that has not passed the first sub-verification operation; applying a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the first sub-verification operation but has not passed the second sub-verification operation; applying a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second sub-verification operation but has not passed the second verification operation; applying a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

[0021] In an optional embodiment, the method further includes: applying a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that has not passed the first sub-verification operation; applying a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the first sub-verification operation but has not passed the second sub-verification operation; applying a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second sub-verification operation but has not passed the third sub-verification operation; applying a fifth bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the third sub-verification operation but has not passed the second verification operation; applying a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that has passed the second verification operation; wherein, the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

[0022] The embodiments of the present disclosure provide a memory device and an operation method thereof, and a memory system, wherein the memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit being configured to: perform a target state programming operation on a target memory cell among the plurality of memory cells; perform a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation including a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when determining that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the target state programming operation. Based on this, in the embodiments of the present disclosure, whether the first verification operation needs to be performed can be determined based on the fail bit count of the first verification operation of the target memory cell, thereby reducing the number of unnecessary verification operations, thereby improving programming efficiency and shortening programming verification time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure is provided;

[0024] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0025] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0026] Figure 3A schematic circuit diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0027] Figure 4 A schematic cross-sectional view of a memory cell array including NAND memory strings provided in one embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits provided in accordance with an embodiment of the present disclosure;

[0029] Figure 6 The threshold voltage distribution of the memory cell provided by an embodiment of the present disclosure Figure 1 ;

[0030] Figure 7 A second diagram of the threshold voltage distribution of a memory cell provided in an embodiment of the present disclosure;

[0031] Figure 8 The threshold voltage distribution of the memory cell provided by an embodiment of the present disclosure Figure 3 ;

[0032] Figure 9 A schematic diagram of an implementation flow of an operating method of a memory device provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0034] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0040] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0041] Figure 1 FIG1 shows a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown in FIG, system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0042] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as solid state drives (SSDs) or embedded Multi Media Cards (eMMCs), which are used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0043] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Drive Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire interface protocol, etc.

[0044] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card (Compact Flash), a Smart Media (SM, Smart Media) card, a memory stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro), an SD card (Secure Digital Card) (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0045] Figure 3 FIG. 1 shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit according to an embodiment of the present disclosure. The memory device 300 may be Figure 1 3. An example of a memory device 104 in FIG. Memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to memory cell array 301. Memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0046] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a tri-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for an erased state.

[0047] like Figure 3 As shown in FIG, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselect voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselect voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0048] like Figure 3 As shown in FIG, NAND memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-memory block level, at the quarter-memory block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic unit of data for programming operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by the word lines 318 in a memory block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320 and a gate line coupling the control gates.

[0049] Figure 4 FIG. 3 is a cross-sectional view of an exemplary memory cell array 301 including a NAND memory string 308 according to an embodiment of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 401.

[0050] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0051] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0052] In some embodiments, NAND memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0053] Return Reference Figure 3, the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0054] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated by the voltage generator 510.

[0055] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0056] The control logic 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes, Operation Codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0057] Typically, incremental step-pulse programming (ISPP) can be used to program NAND memories. For NAND memories, programming operations are performed on a page basis, with each page comprising multiple memory cells. Specifically, when performing a target state programming operation, a first programming pulse (programming voltage) is first applied to the memory cells (target memory cells) of a selected memory page (target memory page) in the memory. A verification operation is then performed on the target memory cells to check whether the threshold voltages of the target memory cells in the selected memory page have reached the target threshold voltage. If the number of target memory cells that have not been programmed to the target threshold voltage is greater than the allowable range, a second programming pulse with a higher voltage is reapplied, and a verification operation is performed again after the second programming pulse is applied. The above process of applying programming pulses and performing verification operations is repeated until the number of target memory cells that have not been programmed to the target threshold voltage is within the allowable range, at which point programming of the entire memory page is completed.

[0058] To facilitate evaluation of the number of target memory cells in a memory page that were not programmed to the target threshold voltage after a programming pulse was applied to the memory page, the Failed Bit Count (FBC) is introduced. The FBC is the number of bits in the memory page that were not programmed to the target threshold voltage. In practical applications, during verification operations, the FBC can be used to determine whether verification has passed.

[0059] It should be noted that the target threshold voltage is used to determine whether the target memory cell has reached the target state. Specifically, when the threshold voltage of the target memory cell is greater than the target threshold voltage, the target memory cell has reached the target state. When the threshold voltage of the target memory cell is less than or equal to the target threshold voltage, the target memory cell has not reached the target state.

[0060] During the different programming stages of an ISPP programming operation, different bitline voltages are applied to the bitlines of different target memory cells to optimize the threshold voltage distribution and ensure that the thresholds of the programmed cells are more concentrated in the threshold voltage region of the corresponding data state. This is known as a bitline forcing operation. This allows for different programming results, even if the gates of target memory cells on different bitlines (applied via wordlines) have the same programming voltage Vpgm. Target memory cells with currently large threshold voltage differences will have their threshold voltage differences reduced after programming, and will be closer to the ideal threshold voltage region.

[0061] The present disclosure does not limit the number of bits stored in each memory cell. The present disclosure is explained by taking a TLC with a storage bit number of 3 as an example. The TLC has 8 states (LV0-LV7), where LV0 is an erased state and LV1-LV7 are programming states. Here, the target state can be any of the 7 programming states. As mentioned above, the above-mentioned programming method requires multiple application of programming pulses, and after each application of the programming pulse, at least two verification operations are required to verify the programming results of the target memory cell to determine the target memory cell that needs to undergo a bit line forced operation. Therefore, the programming verification time is relatively long.

[0062] Based on this, in order to improve programming efficiency and shorten programming verification time, the embodiments of the present disclosure provide a memory device and an operating method thereof. The memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit being configured to: perform a target state programming operation on a target memory cell among the plurality of memory cells; perform a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation including a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to a preset value, performing only the second verification operation in the next verification operation of the target state programming operation.

[0063] In some embodiments, the peripheral circuit is further configured to: when it is determined that the fail bit count is greater than a preset value, perform the first verification operation and the second verification operation in a next verification operation of the program operation of the target state.

[0064] In the embodiment of the present disclosure, for the programming operation of the target state, a verification operation needs to be performed on the target memory cell each time a programming pulse (programming voltage) is applied. During the verification operation, the fail bit count of the first verification operation is recorded to count the number of memory cells that failed the first verification operation. When the fail bit count of the first verification operation is less than or equal to the preset value, in the next verification operation of the programming operation of the target state, the first verification operation is not performed, and only the second verification operation is performed; when the fail bit count of the first verification operation is greater than the preset value, in the next verification operation of the programming operation of the target state, the first verification operation and the second verification operation are continued to be performed. Here, the preset value can be set with reference to the preset FBC. The preset FBC is the maximum number of memory cells that the memory device allows in the target storage page that do not reach the target state. In a specific example, the preset value can be 10.

[0065] Figure 6 The threshold voltage distribution of the memory cell provided by an embodiment of the present disclosure Figure 1 . Reference Figure 6In an example embodiment of the present disclosure, a memory cell having a threshold voltage greater than the program verification voltage Vvfy may be an inhibiting cell. Further programming of a memory cell that has reached a target state (i.e., a target threshold voltage) can be inhibited by applying a program inhibit bitline voltage Vinh (e.g., power supply voltage VDD) to the bitline corresponding to the inhibiting cell. Furthermore, a memory cell having a threshold voltage level less than the program verification voltage Vvfy may be a programming cell (PGMCell). Here, the program verification voltage Vvfy is the voltage corresponding to the second verification operation. In other words, the memory cell in the target memory cell that passes the second verification operation is an inhibiting cell. The first verification operation includes a first sub-verification operation, and the voltage corresponding to the first sub-verification operation is the first forced sensing voltage Vfc1. In other words, the verification voltage used in the first sub-verification operation is the first forced sensing voltage Vfc1. The first forced sensing voltage Vfc1 may be less than the program verification voltage Vvfy. In an example embodiment of the present disclosure, the memory cell in the target memory cell that fails the first sub-verification operation is referred to as a 2BL cell, i.e., the threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. The target memory cells that pass the first sub-verification operation but fail the second verification operation are called 3BL cells, ie, the threshold voltage of the 3BL cells is greater than the first forced sensing voltage Vfc1 and less than the program verification voltage Vvfy.

[0066] In some embodiments, the first verification operation includes a first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; and when it is determined that the first fail bit count is less than or equal to a first preset value, only perform the second verification operation in the next verification operation of the programming operation of the target state.

[0067] In the embodiment of the present disclosure, after applying a programming pulse to the target memory cell, a verification operation is performed on the target memory cell. The verification operation includes a first sub-verification operation and a second sub-verification operation. Figure 6 , performing a first sub-verification operation on the target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell; performing a second verification operation on the target memory cell includes applying a programming verification voltage Vvfy to the target memory cell. After applying the first forced sensing voltage Vfc1 to the target memory cell, the first fail bit count of the first sub-verification operation is recorded to count the number of 2BL cells (memory cells that failed the first sub-verification operation). When the first fail bit count is less than or equal to a first preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation is not performed, and only the second verification operation is performed; when the first fail bit count is greater than the first preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation and the second verification operation continue to be performed. In a specific example, the first preset value can be 10.

[0068] In some embodiments, when the first fail bit count is greater than a first preset value, a bit line force operation may be performed on the 3BL cell during the subsequent programming process. Furthermore, the 2BL cell is a normal programming cell that performs a normal programming operation. It should be noted that a normal programming cell is a memory cell in the programming unit that does not undergo a bit line force operation. Therefore, in some embodiments, a normal programming cell may also be referred to as a programming cell that will not undergo a force operation.

[0069] In some embodiments, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, and the second bit line voltage is less than the third bit line voltage.

[0070] In the disclosed embodiment, a first bitline voltage is applied to the bitline coupled to the 2BL cell; a second bitline voltage is applied to the bitline coupled to the 3BL cell; and a third bitline voltage is applied to the bitline coupled to the inhibit cell. The first bitline voltage is less than the second bitline voltage, and the second bitline voltage is less than the third bitline voltage. Here, the first bitline voltage is a normal programming bitline voltage Vprog (e.g., ground voltage Vgnd), the third bitline voltage is a program inhibit bitline voltage Vinh (e.g., power supply voltage VDD), and the second bitline voltage is a forced programming bitline voltage that is greater than the normal programming bitline voltage Vprog and less than the program inhibit bitline voltage Vinh.

[0071] It should be noted that when the first fail bit count is less than or equal to the first preset value (ie, the first sub-verification operation is not performed), a second bit line voltage is applied to the bit line coupled to the target memory cell that fails the second verification operation.

[0072] In the disclosed embodiment, when the first fail bit count is less than or equal to a first preset value (i.e., when the first sub-verification operation is not performed), the memory cell (2BL cell) that failed the first sub-verification operation is treated as a 3BL cell in the subsequent programming process. In other words, the same bit line forcing operation as the 3BL cell is performed on the 2BL cell in the subsequent programming process. In one specific example, a second bit line voltage is applied to the bit lines coupled to both the 2BL cell and the 3BL cell in the subsequent programming process.

[0073] Figure 7 The second diagram of the threshold voltage distribution of the memory cell provided in one embodiment of the present disclosure. Figure 7In an example embodiment of the present disclosure, a memory cell having a threshold voltage greater than the program verification voltage Vvfy may be a prohibited cell. In addition, a memory cell having a threshold voltage level less than the program verification voltage Vvfy may be a program cell. Here, the program verification voltage Vvfy is the voltage corresponding to the second verification operation. The first verification operation includes a first sub-verification operation and a second sub-verification operation, and the voltage corresponding to the first sub-verification operation is the first forced sensing voltage Vfc1. The voltage corresponding to the second sub-verification operation is the second forced sensing voltage Vfc2. In other words, the verification voltage used in the second sub-verification operation is the second forced sensing voltage Vfc2. The first forced sensing voltage Vfc1 may be less than the second forced sensing voltage Vfc2, and both the first forced sensing voltage Vfc1 and the second forced sensing voltage Vfc2 are less than the program verification voltage Vvfy. In an example embodiment of the present disclosure, a memory cell in the target memory cell that fails the first sub-verification operation is referred to as a 2BL cell, that is, the threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. Target memory cells that pass the first sub-verification operation but fail the second sub-verification operation are referred to as 3BL cells, i.e., the threshold voltage of the 3BL cells is greater than the first forced sensing voltage Vfc1 and less than the second forced sensing voltage Vfc2. Target memory cells that pass the second sub-verification operation but fail the second verification operation are referred to as 4BL cells, i.e., the threshold voltage of the 4BL cells is greater than the second forced sensing voltage Vfc2 and less than the program verification voltage Vvfy.

[0074] In some embodiments, the first verification operation includes a first sub-verification operation and a second sub-verification operation, and the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to a first preset value, only perform the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state; or, record a second fail bit count of the second sub-verification operation; when it is determined that the second fail bit count is less than or equal to a second preset value, only perform the second verification operation in the next verification operation of the programming operation of the target state.

[0075] In the embodiment of the present disclosure, after applying a programming pulse to the target memory cell, a verification operation is performed on the target memory cell. The verification operation includes a first sub-verification operation, a second sub-verification operation, and a second verification operation. Figure 7 , performing a first sub-verification operation on the target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell; performing a second sub-verification operation on the target memory cell includes applying a second forced sensing voltage Vfc2 to the target memory cell; performing a second verification operation on the target memory cell includes applying a programming verification voltage Vvfy to the target memory cell.

[0076] In some embodiments, after applying a first forced sensing voltage Vfc1 to a target memory cell, a first fail bit count of the first sub-verification operation is recorded to count the number of 2BL cells (memory cells that failed the first sub-verification operation). When the first fail bit count is less than or equal to a first preset value, the first sub-verification operation is not performed in the next verification operation of the target state programming operation, and only the second sub-verification operation and the second verification operation are performed. When the first fail bit count is greater than the first preset value, the first sub-verification operation, the second sub-verification operation, and the second verification operation are continued in the next verification operation of the target state programming operation.

[0077] In other embodiments, after applying the second forced sensing voltage Vfc2 to the target memory cell, a second fail bit count of the second sub-verification operation is recorded to count the number of 2BL cells and 3BL cells (memory cells that failed the second sub-verification operation). When the second fail bit count is less than or equal to a second preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation and the second sub-verification operation are not performed, and only the second verification operation is performed; when the second fail bit count is greater than the second preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation, the second sub-verification operation, and the second verification operation are continued to be performed.

[0078] In some embodiments, the first preset value and the second preset value may be the same. In other embodiments, the second preset value may be greater than the first preset value. In a specific example, the first preset value may be 10 and the second preset value may be 20.

[0079] In some embodiments, when the first fail bit count is greater than a first preset value, a bit line force operation may be performed on the 3BL cell and the 4BL cell during the subsequent programming process. The bit line force operation in the disclosed embodiments includes a first bit line force operation and a second bit line force operation. The 3BL cell may be the memory cell to be subjected to the first bit line force operation, and the 4BL cell may be the memory cell to be subjected to the second bit line force operation.

[0080] In some embodiments, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second sub-verification operation; apply a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

[0081] In the disclosed embodiment, a first bitline voltage is applied to the bitline coupled to the 2BL cell; a second bitline voltage is applied to the bitline coupled to the 3BL cell; a fourth bitline voltage is applied to the bitline coupled to the 4BL cell; and a third bitline voltage is applied to the bitline coupled to the inhibit cell. The first bitline voltage is less than the second bitline voltage, the second bitline voltage is less than the fourth bitline voltage, and the fourth bitline voltage is less than the third bitline voltage. Here, the first bitline voltage is a normal programming bitline voltage Vprog (e.g., ground voltage Vgnd), the third bitline voltage is an inhibit programming bitline voltage Vinh (e.g., power supply voltage VDD), and both the second and fourth bitline voltages are forced programming bitline voltages greater than the normal programming bitline voltage Vprog and less than the inhibit programming bitline voltage Vinh. In a specific example, the second bitline voltage is the forced programming bitline voltage applied during a first bitline force operation, and the fourth bitline voltage is the forced programming bitline voltage applied during a second bitline force operation.

[0082] It should be noted that, when the first fail bit count is less than or equal to a first preset value (i.e., the first sub-verification operation is not performed), a second bit line voltage is applied to the bit line coupled to the target memory cell that fails the second sub-verification operation. When the second fail bit count is less than or equal to a second preset value (i.e., the first sub-verification operation and the second sub-verification operation are not performed), a fourth bit line voltage is applied to the bit line coupled to the target memory cell that fails the second verification operation.

[0083] In an embodiment of the present disclosure, when the first fail bit count is less than or equal to the first preset value (i.e., when the first sub-verification operation is not performed), the 2BL unit is processed as a 3BL unit in the next programming process. In other words, the same first bit line forced operation as the 3BL unit is performed on the 2BL unit in the next programming process. In a specific example, a second bit line voltage is applied to the bit lines coupled to the 2BL unit and the 3BL unit in the next programming process. When the second fail bit count is less than or equal to the second preset value (i.e., when the first sub-verification operation and the second sub-verification operation are not performed), the storage cells (2BL unit and 3BL unit) that have not passed the second sub-verification operation are processed as 4BL units in the next programming process. In other words, the same second bit line forced operation as the 4BL unit is performed on the 2BL unit and the 3BL unit in the next programming process. In a specific example, a fourth bit line voltage is applied to the bit lines coupled to the 2BL unit, the 3BL unit, and the 4BL unit in the next programming process.

[0084] Figure 8 The threshold voltage distribution of the memory cell provided by an embodiment of the present disclosure Figure 3 . Reference Figure 8 In an example embodiment of the present disclosure, a memory cell having a threshold voltage greater than a program verification voltage Vvfy may be an inhibited cell. Furthermore, a memory cell having a threshold voltage level less than a program verification voltage Vvfy may be a program cell. Here, the program verification voltage Vvfy is the voltage corresponding to the second verification operation. The first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation. The voltage corresponding to the first sub-verification operation is the first forced sensing voltage Vfc1. The voltage corresponding to the second sub-verification operation is the second forced sensing voltage Vfc2. The voltage corresponding to the third sub-verification operation is the third forced sensing voltage Vfc3. In other words, the verification voltage used in the third sub-verification operation is the third forced sensing voltage Vfc3. The first forced sensing voltage Vfc1 may be less than the second forced sensing voltage Vfc2, and the second forced sensing voltage Vfc2 may be less than the third forced sensing voltage Vfc3. Furthermore, the first forced sensing voltage Vfc1, the second forced sensing voltage Vfc2, and the third forced sensing voltage Vfc3 are all less than the program verification voltage Vvfy. In an example embodiment of the present disclosure, a target memory cell that fails the first sub-verification operation is referred to as a 2BL cell, i.e., the threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. A target memory cell that passes the first sub-verification operation but fails the second sub-verification operation is referred to as a 3BL cell, i.e., the threshold voltage of the 3BL cell is greater than the first forced sensing voltage Vfc1 and less than the second forced sensing voltage Vfc2. A target memory cell that passes the second sub-verification operation but fails the third sub-verification operation is referred to as a 4BL cell, i.e., the threshold voltage of the 4BL cell is greater than the second forced sensing voltage Vfc2 and less than the third forced sensing voltage Vfc3. A target memory cell that passes the third sub-verification operation but fails the second verification operation is referred to as a 5BL cell, i.e., the threshold voltage of the 5BL cell is greater than the third forced sensing voltage Vfc3 and less than the program verification voltage Vvfy.

[0085] In some embodiments, the first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, the voltage corresponding to the third sub-verification operation is greater than the voltage corresponding to the second sub-verification operation, and the voltage corresponding to the second sub-verification operation is greater than the voltage corresponding to the first sub-verification operation; the peripheral circuit is configured to: record a first fail bit count of the first sub-verification operation; when it is determined that the first fail bit count is less than or equal to a first preset value, in the next verification operation of the programming operation of the target state, only the second sub-verification operation, the third sub-verification operation, and the second verification operation are executed; or, record the second fail bit count of the second sub-verification operation; when it is determined that the second fail bit count is less than or equal to the second preset value, in the next verification operation of the programming operation of the target state, only the third sub-verification operation and the second verification operation are executed; or, record the third fail bit count of the third sub-verification operation; when it is determined that the third fail bit count is less than or equal to the third preset value, in the next verification operation of the programming operation of the target state, only the second verification operation is executed.

[0086] In the embodiment of the present disclosure, after applying a programming pulse to the target memory cell, a verification operation is performed on the target memory cell. The verification operation includes a first sub-verification operation, a second sub-verification operation, a third sub-verification operation, and a second verification operation. Figure 8 , performing a first sub-verification operation on the target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell; performing a second sub-verification operation on the target memory cell includes applying a second forced sensing voltage Vfc2 to the target memory cell; performing a third sub-verification operation on the target memory cell includes applying a third forced sensing voltage Vfc3 to the target memory cell; performing a second verification operation on the target memory cell includes applying a programming verification voltage Vvfy to the target memory cell.

[0087] In some embodiments, after applying a first forced sensing voltage Vfc1 to a target memory cell, a first fail bit count of the first sub-verification operation is recorded to count the number of 2BL cells (memory cells that failed the first sub-verification operation). When the first fail bit count is less than or equal to a first preset value, the first sub-verification operation is not performed in the next verification operation of the target state programming operation, and only the second sub-verification operation, the third sub-verification operation, and the second verification operation are performed. When the first fail bit count is greater than the first preset value, the first sub-verification operation, the second sub-verification operation, the third sub-verification operation, and the second verification operation are continued in the next verification operation of the target state programming operation.

[0088] In other embodiments, after applying the second forced sensing voltage Vfc2 to the target memory cell, a second fail bit count of the second sub-verification operation is recorded to count the number of 2BL cells and 3BL cells (memory cells that failed the second sub-verification operation). When the second fail bit count is less than or equal to a second preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation and the second sub-verification operation are not performed, and only the third sub-verification operation and the second verification operation are performed; when the second fail bit count is greater than the second preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation, the second sub-verification operation, the third sub-verification operation, and the second verification operation are continued to be performed.

[0089] In some further embodiments, after applying a third forced sensing voltage Vfc3 to the target memory cells, a third fail bit count of the third sub-verification operation is recorded to count the number of 2BL cells, 3BL cells, and 4BL cells (memory cells that failed the third sub-verification operation). When the third fail bit count is less than or equal to a third preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation, the second sub-verification operation, and the third sub-verification operation are not performed, and only the second verification operation is performed. When the third fail bit count is greater than the third preset value, in the next verification operation of the programming operation of the target state, the first sub-verification operation, the second sub-verification operation, the third sub-verification operation, and the second verification operation are continued to be performed.

[0090] In some embodiments, the first preset value, the second preset value, and the third preset value may be the same. In other embodiments, the second preset value may be greater than the first preset value, and the third preset value may be greater than the second preset value. In a specific example, the first preset value may be 10, the second preset value may be 20, and the third preset value may be 30.

[0091] In some embodiments, when the first fail bit count is greater than a first preset value, a bit line force operation may be performed on the 3BL cell, the 4BL cell, and the 5BL cell during the subsequent programming process. The bit line force operation in the disclosed embodiments includes a first bit line force operation, a second bit line force operation, and a third bit line force operation. The 3BL cell may be the memory cell to be subjected to the first bit line force operation, the 4BL cell may be the memory cell to be subjected to the second bit line force operation, and the 5BL cell may be the memory cell to be subjected to the third bit line force operation.

[0092] In some embodiments, the peripheral circuit is further configured to: apply a first bit line voltage to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; apply a second bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second sub-verification operation; apply a fourth bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the third sub-verification operation; apply a fifth bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the third sub-verification operation but fails the second verification operation; apply a third bit line voltage to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

[0093] In the disclosed embodiment, a first bitline voltage is applied to the bitline coupled to the 2BL cell; a second bitline voltage is applied to the bitline coupled to the 3BL cell; a fourth bitline voltage is applied to the bitline coupled to the 4BL cell; a fifth bitline voltage is applied to the bitline coupled to the 5BL cell; and a third bitline voltage is applied to the bitline coupled to the inhibit cell. The first bitline voltage is less than the second bitline voltage, the second bitline voltage is less than the fourth bitline voltage, the fourth bitline voltage is less than the fifth bitline voltage, and the fifth bitline voltage is less than the third bitline voltage. Here, the first bitline voltage is a normal programming bitline voltage Vprog (e.g., ground voltage Vgnd), the third bitline voltage is an inhibit programming bitline voltage Vinh (e.g., power supply voltage VDD), and the second, fourth, and fifth bitline voltages are all forced programming bitline voltages that are greater than the normal programming bitline voltage Vprog and less than the inhibit programming bitline voltage Vinh. In a specific example, the second bit line voltage is a forced programming bit line voltage applied during a first bit line forced operation, the fourth bit line voltage is a forced programming bit line voltage applied during a second bit line forced operation, and the fifth bit line voltage is a forced programming bit line voltage applied during a third bit line forced operation. The first, second, fourth, fifth, and third bit line voltages are all voltages applied to the bit lines during the programming process.

[0094] It should be noted that when the first fail bit count is less than or equal to the first preset value (i.e., when the first sub-verification operation is not performed), a second bit line voltage is applied to the bit line coupled to the target memory cell that fails the second sub-verification operation. When the second fail bit count is less than or equal to the second preset value (i.e., when the first sub-verification operation and the second sub-verification operation are not performed), a fourth bit line voltage is applied to the bit line coupled to the target memory cell that fails the third sub-verification operation. When the third fail bit count is less than or equal to the third preset value (i.e., when the first sub-verification operation, the second sub-verification operation, and the third sub-verification operation are not performed), a fifth bit line voltage is applied to the bit line coupled to the target memory cell that fails the second verification operation.

[0095] In an embodiment of the present disclosure, when the first fail bit count is less than or equal to the first preset value (i.e., when the first sub-verification operation is not performed), the 2BL unit is processed as a 3BL unit in the next programming process. In other words, the same first bit line forced operation as the 3BL unit is performed on the 2BL unit in the next programming process. In a specific example, a second bit line voltage is applied to the bit lines coupled to the 2BL unit and the 3BL unit in the next programming process. When the second fail bit count is less than or equal to the second preset value (i.e., when the first sub-verification operation and the second sub-verification operation are not performed), the storage cells (2BL unit and 3BL unit) that have not passed the second sub-verification operation are processed as 4BL units in the next programming process. In other words, the same second bit line forced operation as the 4BL unit is performed on the 2BL unit and the 3BL unit in the next programming process. In a specific example, a fourth bit line voltage is applied to the bit lines coupled to the 2BL unit, the 3BL unit, and the 4BL unit in the next programming process. When the third fail bit count is less than or equal to a third preset value (i.e., the first, second, and third sub-verification operations are not performed), the memory cells that failed the third sub-verification operation (the 2BL cell, the 3BL cell, and the 4BL cell) are treated as 5BL cells in the subsequent programming process. In other words, the same third bit line forcing operation as that of the 5BL cell is performed on the 2BL cell, the 3BL cell, and the 4BL cell in the subsequent programming process. In a specific example, a fifth bit line voltage is applied to the bit lines coupled to the 2BL cell, the 3BL cell, the 4BL cell, and the 5BL cell in the subsequent programming process.

[0096] Based on this, in the embodiment of the present disclosure, whether the first verification operation needs to be performed can be determined based on the fail bit count of the first verification operation of the target storage unit, thereby reducing the number of unnecessary verification operations, thereby improving programming efficiency and shortening programming verification time.

[0097] The present disclosure also provides a memory system, comprising:

[0098] One or more memory devices as described in any of the above embodiments; and

[0099] A memory controller is coupled to the memory device and controls the memory device.

[0100] Here, the specific structure and composition of the memory system can be referred to the aforementioned Figure 1 、 Figure 2a 、 Figure 2b For the sake of brevity, the relevant structure and composition of the memory system in [1] are not described here.

[0101] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0102] Based on the above memory device, the embodiment of the present disclosure further provides an operating method of the memory device, the memory device comprising: a memory cell array comprising a plurality of memory cells; Figure 9 As shown, the operation method includes:

[0103] Step 701: performing a target state programming operation on a target memory cell among the plurality of memory cells;

[0104] Step 702: performing a verification operation on the target memory cell that has undergone the programming operation in the target state, the verification operation including a first verification operation and a second verification operation, wherein a voltage corresponding to the second verification operation is greater than a voltage corresponding to the first verification operation;

[0105] Step 703: During the verification operation, record the failed bit count of the first verification operation;

[0106] Step 704: When it is determined that the fail bit count is less than or equal to the preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

[0107] In some embodiments, the method further comprises:

[0108] When it is determined that the fail bit count is greater than the preset value, the first verification operation and the second verification operation are performed in a next verification operation of the program operation of the target state.

[0109] In some embodiments, the first verification operation includes a first sub-verification operation; recording a fail bit count of the first verification operation; and when determining that the fail bit count is less than or equal to the preset value, performing only the second verification operation in a next verification operation of the target state programming operation, including:

[0110] Recording a first failure bit count of the first sub-verification operation;

[0111] When it is determined that the first fail bit count is less than or equal to the first preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

[0112] In some embodiments, the first verification operation includes a first sub-verification operation and a second sub-verification operation, a voltage corresponding to the second sub-verification operation is greater than a voltage corresponding to the first sub-verification operation; recording a fail bit count of the first verification operation; and when determining that the fail bit count is less than or equal to the preset value, performing only the second verification operation in a next verification operation of the target state programming operation, including:

[0113] recording a first fail bit count of the first sub-verification operation; and performing only the second sub-verification operation and the second verification operation in a next verification operation of the program operation of the target state when it is determined that the first fail bit count is less than or equal to the first preset value;

[0114] Alternatively, a second fail bit count of the second coarse verification operation is recorded; and when it is determined that the second fail bit count is less than or equal to the second preset value, only the second verification operation is performed in a next verification operation of the target state programming operation.

[0115] In some embodiments, the first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, a voltage corresponding to the third sub-verification operation is greater than a voltage corresponding to the second sub-verification operation, and a voltage corresponding to the second sub-verification operation is greater than a voltage corresponding to the first sub-verification operation; recording a fail bit count of the first verification operation; and when determining that the fail bit count is less than or equal to a preset value, performing only the second verification operation in a next verification operation of a programming operation of the target state, including:

[0116] recording a first fail bit count of the first sub-verification operation; and when determining that the first fail bit count is less than or equal to the first preset value, performing only the second sub-verification operation, the third sub-verification operation, and the second verification operation in a next verification operation of the target state;

[0117] Alternatively, recording a second fail bit count of the second sub-verification operation; and when determining that the second fail bit count is less than or equal to the second preset value, performing only the third sub-verification operation and the second verification operation in a next verification operation of the program operation of the target state;

[0118] Alternatively, a third fail bit count of the third sub-verification operation is recorded; and when it is determined that the third fail bit count is less than or equal to the third preset value, only the second verification operation is performed in a next verification operation of the programming operation of the target state.

[0119] In some embodiments, the method further comprises:

[0120] A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second verification operation; and a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, and the second bit line voltage is less than the third bit line voltage.

[0121] In some embodiments, the method further comprises:

[0122] A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second sub-verification operation; a fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

[0123] In some embodiments, the method further comprises:

[0124] A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that does not pass the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but does not pass the second sub-verification operation; a fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but does not pass the third sub-verification operation; a fifth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the third sub-verification operation but does not pass the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein, the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

[0125] The embodiments of the present disclosure provide a memory device and an operation method thereof, and a memory system, wherein the memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit being configured to: perform a target state programming operation on a target memory cell among the plurality of memory cells; perform a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation including a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when determining that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the target state programming operation. Based on this, in the embodiments of the present disclosure, whether the first verification operation needs to be performed can be determined based on the fail bit count of the first verification operation of the target memory cell, thereby reducing the number of unnecessary verification operations, thereby improving programming efficiency and shortening programming verification time.

[0126] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0127] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A memory device, characterized in that: The memory device comprises: a memory cell array comprising a plurality of memory cells; A peripheral circuit is coupled to the memory cell array; the peripheral circuit is configured to: performing a target state programming operation on a target memory cell among the plurality of memory cells; performing a verification operation on a target memory cell that has undergone a programming operation in the target state, the verification operation including a first verification operation and a second verification operation, wherein a voltage corresponding to the second verification operation is greater than a voltage corresponding to the first verification operation; During the verification operation, recording a failure bit count of the first verification operation; When it is determined that the fail bit count is less than or equal to the preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

2. The memory device according to claim 1, wherein The peripheral circuit is further configured to: When it is determined that the fail bit count is greater than the preset value, the first verification operation and the second verification operation are performed in a next verification operation of the program operation of the target state.

3. The memory device according to claim 1, wherein The first verification operation includes a first sub-verification operation; the peripheral circuit is configured to: Recording a first failure bit count of the first sub-verification operation; When it is determined that the first fail bit count is less than or equal to the first preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

4. The memory device according to claim 1, wherein: The first verification operation includes a first sub-verification operation and a second sub-verification operation, wherein a voltage corresponding to the second sub-verification operation is greater than a voltage corresponding to the first sub-verification operation; and the peripheral circuit is configured as follows: recording a first fail bit count of the first sub-verification operation; and performing only the second sub-verification operation and the second verification operation in a next verification operation of the program operation of the target state when it is determined that the first fail bit count is less than or equal to the first preset value; Alternatively, recording a second failure bit count of the second sub-verification operation; When it is determined that the second fail bit count is less than or equal to the second preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

5. The memory device according to claim 1, wherein The first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, wherein a voltage corresponding to the third sub-verification operation is greater than a voltage corresponding to the second sub-verification operation, and a voltage corresponding to the second sub-verification operation is greater than a voltage corresponding to the first sub-verification operation; and the peripheral circuit is configured as follows: recording a first fail bit count of the first sub-verification operation; and when determining that the first fail bit count is less than or equal to the first preset value, performing only the second sub-verification operation, the third sub-verification operation, and the second verification operation in a next verification operation of the target state; Alternatively, recording a second failure bit count of the second sub-verification operation; When it is determined that the second fail bit count is less than or equal to the second preset value, in a next verification operation of the program operation of the target state, only the third sub-verification operation and the second verification operation are performed; Alternatively, recording a third failure bit count of the third sub-verification operation; When it is determined that the third fail bit count is less than or equal to the third preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state. The memory device according to claim 3 , wherein: The peripheral circuit is further configured to: Applying a first bit line voltage to a bit line coupled to the target memory cell that fails the first sub-verification operation; applying a second bit line voltage to a bit line coupled to the target memory cell that passes the first sub-verification operation but fails the second verification operation; A third bit line voltage is applied to a bit line coupled to the target memory cell that passes the second verification operation; wherein the first bit line voltage is lower than the second bit line voltage, and the second bit line voltage is lower than the third bit line voltage.

7. The memory device according to claim 4, wherein: The peripheral circuit is further configured to: Applying a first bit line voltage to a bit line coupled to a memory cell that fails the first sub-verification operation among the target memory cells; applying a second bit line voltage to a bit line coupled to a memory cell that passes the first sub-verification operation but fails the second sub-verification operation among the target memory cells; A fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

8. The memory device according to claim 5, wherein: The peripheral circuit is further configured to: applying a first bit line voltage to a bit line coupled to the target memory cell that fails the first sub-verification operation; applying a second bit line voltage to a bit line coupled to the target memory cell that passes the first sub-verification operation but fails to pass the second sub-verification operation; A fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails to pass the third sub-verification operation; a fifth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the third sub-verification operation but fails to pass the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

9. A memory system, characterized in that: include: The memory device according to any one of claims 1 to 8; as well as Memory controller; The memory controller is coupled to the memory device and is used to control the memory device.

10. A method for operating a memory device, characterized in that: The memory device comprises: a memory cell array comprising a plurality of memory cells; the operating method comprises: performing a target state programming operation on a target memory cell among the plurality of memory cells; performing a verification operation on a target memory cell that has undergone a programming operation in the target state, the verification operation including a first verification operation and a second verification operation, wherein a voltage corresponding to the second verification operation is greater than a voltage corresponding to the first verification operation; During the verification operation, recording a failure bit count of the first verification operation; When it is determined that the fail bit count is less than or equal to the preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

11. The method for operating a memory device according to claim 10, wherein: The method further comprises: When it is determined that the fail bit count is greater than the preset value, the first verification operation and the second verification operation are performed in a next verification operation of the program operation of the target state.

12. The method for operating a memory device according to claim 10, wherein the first verification operation comprises a first sub-verification operation; and recording a fail bit count of the first verification operation. When it is determined that the fail bit count is less than or equal to the preset value, performing only the second verification operation in a next verification operation of the program operation of the target state includes: Recording a first failure bit count of the first sub-verification operation; When it is determined that the first fail bit count is less than or equal to the first preset value, only the second verification operation is performed in a next verification operation of the program operation of the target state.

13. The method for operating a memory device according to claim 10 , wherein the first verification operation comprises a first sub-verification operation and a second sub-verification operation, the voltage corresponding to the second sub-verification operation being greater than the voltage corresponding to the first sub-verification operation; and recording a count of failed bits in the first verification operation; When it is determined that the fail bit count is less than or equal to the preset value, performing only the second verification operation in a next verification operation of the program operation of the target state includes: recording a first fail bit count of the first sub-verification operation; and performing only the second sub-verification operation and the second verification operation in a next verification operation of the program operation of the target state when it is determined that the first fail bit count is less than or equal to the first preset value; Alternatively, a second fail bit count of the second coarse verification operation is recorded; and when it is determined that the second fail bit count is less than or equal to the second preset value, only the second verification operation is performed in a next verification operation of the target state programming operation.

14. The method for operating a memory device according to claim 10 , wherein the first verification operation comprises a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, a voltage corresponding to the third sub-verification operation is greater than a voltage corresponding to the second sub-verification operation, and a voltage corresponding to the second sub-verification operation is greater than a voltage corresponding to the first sub-verification operation; and recording a count of failed bits of the first verification operation; When it is determined that the fail bit count is less than or equal to the preset value, performing only the second verification operation in a next verification operation of the program operation of the target state includes: recording a first fail bit count of the first sub-verification operation; and when determining that the first fail bit count is less than or equal to the first preset value, performing only the second sub-verification operation, the third sub-verification operation, and the second verification operation in a next verification operation of the target state; Alternatively, recording a second fail bit count of the second sub-verification operation; and when determining that the second fail bit count is less than or equal to the second preset value, performing only the third sub-verification operation and the second verification operation in a next verification operation of the target state; Alternatively, a third fail bit count of the third sub-verification operation is recorded; and when it is determined that the third fail bit count is less than or equal to the third preset value, only the second verification operation is performed in a next verification operation of the target state programming operation.

15. The method for operating a memory device according to claim 12, wherein: The method further comprises: A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second verification operation; and a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, and the second bit line voltage is less than the third bit line voltage.

16. The method for operating a memory device according to claim 13, wherein: The method further comprises: A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that fails the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but fails the second sub-verification operation; a fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but fails the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

17. The method for operating a memory device according to claim 14, wherein: The method further comprises: A first bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that does not pass the first sub-verification operation; a second bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the first sub-verification operation but does not pass the second sub-verification operation; a fourth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second sub-verification operation but does not pass the third sub-verification operation; a fifth bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the third sub-verification operation but does not pass the second verification operation; a third bit line voltage is applied to the bit line coupled to the memory cell in the target memory cell that passes the second verification operation; wherein, the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

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