Peripheral circuit of memory and memory

Abstract

The invention discloses a peripheral circuit of a memory and the memory. The memory comprises a plurality of memory cells. The peripheral circuit includes a bit line decoder, and the bit line decoder includes a plurality of gate units. Each gating unit comprises a first end coupled with a bit line of any memory unit, a second end used for outputting a read signal of the selected memory unit, and a third end coupled between the first end and the second end and coupled with a local bit line of the memory. In the process of performing reading operation on the selected storage unit, the first end and the third end are kept to be conducted, and after the second end and the third end are disconnected for preset time, the second end and the third end are conducted. According to the invention, the voltage offset after charge sharing of the second end and the third end is increased, an obvious voltage difference between a read signal and a reference signal can be formed, the discrimination margin of the comparator is enhanced, and the accuracy and stability of the read operation of the memory are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and in particular to a peripheral circuit of a memory and a memory. Background Art

[0002] In memory, data reading usually relies on charge sharing between the bit line (BL) and the data line (DL) to determine the state of the memory cell. Specifically, the current mainstream default reading method usually includes the following steps: first, the selected bit line is disconnected from the data line, and then reconnected through control logic, thereby enabling charge sharing between the bit line and the data line. The shared voltage value will be input into the comparator, compared with the preset reference voltage, and the reading result will be output after comparison and amplification.

[0003] However, when performing a read operation on a memory cell, the deviation of parasitic capacitance during the manufacturing process may result in insufficient voltage difference after charge sharing, thereby affecting the discrimination effect of the comparator amplifier and reducing the reading accuracy and stability. Summary of the Invention

[0004] In view of the above-mentioned defects of the prior art, the technical problem to be solved by this application is how to improve the accuracy and stability of memory reading operations.

[0005] In order to solve at least one of the above-mentioned technical problems, the present application discloses a peripheral circuit of a memory and a memory.

[0006] According to one aspect of the present application, a peripheral circuit of a memory is provided, wherein the memory includes a memory array, the memory array includes a plurality of memory cells, and the peripheral circuit of the memory includes:

[0007] A bit line decoder comprising:

[0008] A plurality of gating units, each of the gating units comprising:

[0009] A first terminal coupled to a bit line of any of the memory cells;

[0010] The second terminal is used to output a read signal of the selected storage unit;

[0011] a third terminal coupled between the first terminal and the second terminal and coupled to a local bit line of the memory;

[0012] Each of the gating units is configured to:

[0013] During a read operation on the selected memory cell, the first terminal and the third terminal are kept conductive, and after the second terminal and the third terminal are disconnected for a preset time, the second terminal and the third terminal are conductively connected.

[0014] Optionally, each of the gating units includes:

[0015] a first line switch connected between the second end and the third end;

[0016] The first bit line switch is configured to be turned on after being turned off for a preset time during a reading operation on a selected memory cell.

[0017] Optionally, each of the gating units includes:

[0018] a second bit line switch connected between the first terminal and the third terminal;

[0019] The second bit line switch is configured to be continuously turned on during a read operation on a selected memory cell.

[0020] Optionally, the first bit line switch further includes a first control terminal, which is used to receive a first control signal to control the first bit line switch to be turned on or off; the second bit line switch further includes a second control terminal, which is used to receive a second control signal to control the second bit line switch to be turned on or off.

[0021] Optionally, the second bit line switch is a transistor, and the gate terminal of the transistor is the second control terminal;

[0022] During a read operation on the selected memory cell, the magnitude of the second control signal is positively correlated or negatively correlated with the magnitude of the current between the first terminal and the third terminal.

[0023] Optionally, the system further includes: a signal controller configured to:

[0024] During a read operation on a selected memory cell, a first control signal is provided to the first control terminal, and a second control signal is provided to the second control terminal. The first control signal is used to control the first bit line switch to be turned on after being turned off for a preset time, and the second control signal is used to control the second bit line switch to be continuously turned on.

[0025] Optionally, each of the selection units further includes: a first control switch, one end of which is connected to the first control end, and the other end is used to receive a first control signal, and the first control switch is configured to: during a reading operation on a selected storage unit, turn off for a preset time and then turn on.

[0026] Optionally, the system further includes: a signal controller configured to:

[0027] During a read operation on a selected memory cell, a first control signal is provided to the first control terminal, a second control signal is provided to the second control terminal, and a first switch signal is provided to the first control switch. The first control signal is used to control the first bit line switch to be continuously turned on, the second control signal is used to control the second bit line switch to be continuously turned on, and the first switch signal is used to control the first control switch to be turned on after being turned off for a preset time.

[0028] Optionally, the device further comprises: a comparator having a first input terminal, a second input terminal and an output terminal;

[0029] The first input terminal is used to input a reference signal;

[0030] The second input terminal is coupled to the second terminal and is used to receive the read signal;

[0031] The output end is used to output a comparison result between the reference signal and the read signal.

[0032] According to a second aspect of the present application, a memory is provided, the memory comprising:

[0033] a storage array comprising a plurality of storage units;

[0034] The peripheral circuit as described in any one of the above items is coupled to the storage unit.

[0035] The peripheral circuit of the memory disclosed in the embodiments of the present application can improve the accuracy and stability of the memory reading operation.

[0036] Specifically, the present application introduces a three-terminal structure in the selection unit, and adopts a time-sharing conduction control method in the process of performing a read operation on the selected memory cell. First, the first terminal and the third terminal are connected, and the third terminal and the second terminal are temporarily closed, so that the bit line of the memory cell is connected to the local bit line; then the second terminal and the third terminal are connected, so that the second terminal outputs a read signal. In the process of charge sharing between the second terminal and the third terminal, in addition to the original parasitic capacitance, the parasitic capacitance of the local bit line is also introduced on the bit line side of the memory cell, thereby effectively increasing the equivalent parasitic capacitance of the bit line. As a result, the voltage offset after the second terminal and the third terminal share the charge is increased, which helps to form a significant voltage difference between the read signal and the reference signal, enhances the judgment margin of the comparator, and improves the accuracy and stability of the memory read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of the structure corresponding to the memory provided in the embodiment of the present application;

[0039] Figure 2 A circuit for a peripheral circuit of a memory provided in an embodiment of the present application Figure 1 ;

[0040] Figure 3 A circuit for a peripheral circuit of a memory provided in an embodiment of the present application Figure 2 ;

[0041] Figure 4 A read signal simulation diagram of the peripheral circuit of the memory provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of voltage waveforms of the peripheral circuit of the memory provided in an embodiment of the present application during data reading;

[0043] Figure 6 This is a diagram showing how the current on the bit line changes with time.

[0044] Description of reference numerals:

[0045] 1. Storage array;

[0046] 2. Peripheral circuit; 3. Bit line decoder; 4. Signal controller; 5. Memory cell; 6. Selected memory cell;

[0047] 21. Selection unit; 211. First terminal; 212. Second terminal; 213. Third terminal; 22. Comparator; 221. First input terminal; 222. Second input terminal; 223. Output terminal.

[0048] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the embodiments described are part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0052] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0053] The term "and / or" as used herein describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of A alone, the simultaneous existence of A and B, and the existence of B alone. Furthermore, the term "at least one" as used herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0054] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0055] As described in the background art, when performing a read operation on a memory cell, parasitic capacitance deviations during the manufacturing process may result in insufficient voltage difference after charge sharing, thereby affecting the discrimination effect of the comparator and reducing the accuracy and stability of the reading.

[0056] In a first embodiment, a memory includes a memory array, which includes a plurality of memory cells. The peripheral circuitry of the memory provided in the first embodiment includes a bitline decoder and a comparator. The bitline decoder includes a plurality of gating units, each of which includes a first end and a second end. The first end is coupled to the bitline of any memory cell, and the second end is coupled to a data line for outputting a read signal from the selected memory cell. The comparator has a first input, a second input, and an output. The first input is coupled to the second end of the gating unit for receiving a read signal from the selected memory cell. The second input is coupled to the second end of the gating unit for receiving a read signal from the selected memory cell, and the output is configured to output a comparison result between the reference signal and the read signal.

[0057] In the first embodiment, when performing a read operation on a selected memory cell, the connection between the first end of the selection unit and the second end of the selection unit is first disconnected. After maintaining the disconnected state for a preset time, the first end and the second end of the selection unit are connected so that the second end outputs a read signal corresponding to the memory cell.

[0058] However, due to process errors and fluctuations in device parameters during actual chip manufacturing, the parasitic capacitance of the bit line and data line may deviate from the designed value. For example, the parasitic capacitance of the bit line may be smaller than expected, while the parasitic capacitance of the data line may be larger than expected. In this case, when the connection between the first end and the second end is disconnected and then reconnected, the bit line and the data line will share charge after being reconnected. Ultimately, the voltage on the data line may be closer to the voltage of the reference signal, that is, the voltage of the read signal output by the second end may be too close to the voltage of the reference signal. If the voltage difference between the two is lower than the minimum resolution threshold of the comparator, the comparison result will be inaccurate, thereby reducing the reading accuracy and stability of the memory.

[0059] Therefore, in order to improve the reading accuracy and stability of the memory, the second embodiment provides a peripheral circuit of the memory.

[0060] Figure 1 is a schematic diagram of the structure corresponding to the memory provided in the embodiment of the present application, such as Figure 1 As shown, the memory includes a memory array 1 and a peripheral circuit 2 , and the peripheral circuit 2 is coupled to the memory array 1 .

[0061] The memory array 1 corresponds to at least a portion of a phase change memory and includes a plurality of word lines WL (wordlines), a plurality of bit lines BL (bit lines) and a plurality of memory cells 5. The memory cells 5 are located at the intersections of the word lines WL and the bit lines BL. Binary data can be written into the memory cells 5 or read from the memory cells 5.

[0062] The memory cell 5 includes a crystalline state and an amorphous state, and corresponds to different voltage thresholds. By applying different forms of heat to the memory cell 5, its crystalline and amorphous states can be converted. The crystalline state is defined as 1, and the corresponding threshold voltage is lower, and the amorphous state is defined as 0, and the corresponding threshold voltage is higher. The programming operation of writing "1" to the memory cell 5 is defined as a set operation, and the programming operation of writing "0" to the memory cell 5 is defined as a reset operation. By applying a pressure greater than the threshold voltage of the set state and less than the reset state to the selected memory cell 6, the memory cell 5 in the crystalline state can be opened, but the memory cell 5 in the amorphous state cannot be opened, and the state of the memory cell 5 can be read.

[0063] Figure 2 A circuit for a peripheral circuit of a memory provided in an embodiment of the present application Figure 1 ,like Figure 2 As shown, a peripheral circuit of a memory disclosed in the second embodiment of the present application includes a bit line decoder 3. The bit line decoder 3 includes a plurality of selection units 21, each of which includes a first end 211, a second end 212, and a third end 213. The first end 211 is coupled to the bit line BL of any memory cell 5; the second end 212 is used to output a read signal of the selected memory cell 6; the third end 213 is coupled between the first end 211 and the second end 212, and is coupled to the local bit line LBL of the memory. That is, the side of the first end 211 facing away from the second end 212 is coupled to the bit line BL of any memory cell 5, the local bit line LBL is coupled between the first end 211 and the second end 212, the side of the second end 212 facing away from the first end 211 is coupled to the first data line DL0, and the third end 213 is located between the first end 211 and the second end 212 and is coupled to the local bit line LBL.

[0064] During the reading operation on the selected storage cell 6, each selection unit 21 is configured to: maintain conduction between the first end 211 and the third end 213, and after disconnecting the second end 212 and the third end 213 for a preset time, connect the second end 212 and the third end 213.

[0065] The present application introduces a three-terminal structure into the selection unit 21 and adopts a time-sharing conduction control method during the reading operation of the selected memory cell 6. First, the first terminal 211 and the third terminal 213 are connected, while the third terminal 213 and the second terminal 212 are temporarily disconnected, so that the bit line BL of the selected memory cell 6 is connected to the local bit line LBL. Then, the second terminal 212 and the third terminal 213 are connected, so that the second terminal 212 outputs a read signal. During the charge sharing process between the second terminal 212 and the third terminal 213, the parasitic capacitance of the local bit line LBL is introduced on the bit line side of the selected memory cell 6 in addition to the original parasitic capacitance, thereby effectively increasing the equivalent parasitic capacitance on the bit line side. As a result, the voltage offset after the charge sharing between the second terminal 212 and the third terminal 213 is increased, which helps to form a significant voltage difference between the read signal and the reference signal, enhances the judgment margin of the comparator 22, and improves the accuracy and stability of the memory read operation.

[0066] Continue to refer to Figure 2 The bit line decoder 3 of the peripheral circuit of the memory disclosed in the second embodiment of the present application further includes a comparator 22. The comparator 22 has a first input terminal 221, a second input terminal 222, and an output terminal 223. The first input terminal 221 is coupled to the second data line DL1 for inputting a reference signal. The second input terminal 222 is coupled to the second terminal 212 via the first data line DL0 for receiving a read signal. The comparator 22 compares the reference signal with the read signal and outputs the comparison result of the reference signal and the read signal through the output terminal 223.

[0067] like Figure 4 As shown, when the selected memory cell 6 is read, if the selected memory cell 6 is in the set state (indicating "read 1"), the bit line side voltage of the selected memory cell 6 is V BL-set If the selected memory cell 6 is in the reset state (indicating "read 0"), the bit line voltage of the selected memory cell 6 is V BL-reset Before the selected memory cell 6 is read, the second terminal 212 is coupled to the data line DL0, and the voltage at the second terminal 212 is V DL0 In the first embodiment, after reading the selected memory cell 6 in the set state, the voltage of the read signal outputted by the second terminal 212 is V DL0-set After reading the selected memory cell 6 in the reset state, the voltage of the read signal output by the second terminal 212 is V DL0-reset In the second embodiment, after reading the selected memory cell 6 in the set state, the voltage of the read signal outputted by the second terminal 212 is V DL0-set’ After reading the selected memory cell 6 in the reset state, the voltage of the read signal output by the second terminal 212 is VDL0-reset’ . Figure 4 The “first margin” and “second margin” shown in the figure represent the voltage of the read signal and the voltage of the reference signal V in the first embodiment and the second embodiment respectively. DL1-ref Through the improvement in the second embodiment, it can be seen that the second margin is greater than the first margin, which improves the read judgment margin of the memory.

[0068] Further, refer to Figure 5 , Figure 5 This is a schematic diagram of voltage waveforms during data reading in the peripheral circuits of the memory provided by an embodiment of the present application. The diagram illustrates the difference in voltage read margin between Embodiment 1 and Embodiment 2 after a read operation on a selected memory cell 6. Specifically, Curve E represents the voltage waveform at the second terminal 212; Curve F represents the voltage waveform at the first terminal 211; and Curve G represents the voltage waveform at the first input terminal 221. The first interval represents the voltage states of each terminal after reading the selected memory cell 6. ΔV represents the voltage difference between the second terminal 212 and the first input terminal 221. The voltage at the first input terminal 221 represents the reference voltage.

[0069] Specifically, Figure 5 In Figure a, Figure b, Figure c, and Figure d, the vertical axes all represent voltage, and the horizontal axes all represent time. The vertical axis scales of Figure a, Figure b, Figure c, and Figure d are consistent, and the horizontal axis scales of Figure a, Figure b, Figure c, and Figure d are consistent. Figure 5 Figures a and b in the figure both perform read operations on the selected storage unit 6 in the set state. Figure a completes the read 1 operation through Example 1, and Figure b completes the read 1 operation through Example 2. It can be clearly found that in the first interval, ΔV2 of Example 2 is greater than ΔV1 of Example 1. Figure 5 Figures c and d in the figure both perform a read 0 operation on the selected storage cell 6 in the reset state. Figure c completes the read 0 operation through Example 1, and Figure d completes the read operation through Example 2. It can be clearly found that in the first interval, ΔV4 of Example 2 is greater than ΔV3 of Example 1.

[0070] From the above comparison, it can be seen that, through the improvement of the structure and control strategy, the second embodiment effectively widens the voltage difference between the read signal and the reference signal when "reading 1" and "reading 0", that is, increases the judgment margin of the comparator, thereby improving the reading accuracy and stability of the memory in the presence of parasitic capacitance deviation.

[0071] Reference Figure 2In the second embodiment, each selection unit 21 further includes: a first bit line switch SW1. The first bit line switch SW1 is connected between the second terminal 212 and the third terminal 213. The second embodiment achieves precise control of the read path by controlling the on and off of the first bit line switch SW1, thereby optimizing the charge sharing process and improving the voltage difference of the read signal. Specifically, the first bit line switch SW1 is configured to: during the reading operation of the selected memory cell 6, it is turned off for a preset time and then turned on, thereby ensuring that before the charge sharing between the second terminal 212 and the third terminal 213, only the bit line BL of the selected memory cell 6 is connected to the local bit line LBL, so that the parasitic capacitance of the local bit line LBL is introduced to the bit line side, effectively increasing the equivalent parasitic capacitance on the bit line side, and improving the voltage offset and comparison judgment margin.

[0072] In the second embodiment, the first-line switch SW1 has a first control terminal configured to receive a first control signal to control the first-line switch SW1 to be turned on and off. The memory peripheral circuit 2 further includes a signal controller 4 that, during a read operation on a selected memory cell 6, provides a first control signal to the first control terminal. The first control signal is configured to control the first-line switch SW1 to be turned on after being turned off for a predetermined time.

[0073] It is worth noting that the first-line switch SW1 may include, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar junction transistor (BJT), or other semiconductor switching devices capable of implementing on / off control functions. When the first-line switch SW1 is a PMOS transistor or an NMOS transistor, the gate terminals of the PMOS transistor and the NMOS transistor form the first control terminal of the first-line switch SW1. When the first-line switch SW1 is a bipolar junction transistor (BJT), the base terminal of the bipolar junction transistor (BJT) serves as the first control terminal of the first-line switch SW1.

[0074] Continue to refer to Figure 2 In some other embodiments, each selection unit 21 further includes: a second bit line switch SW2. The second bit line switch SW2 is connected between the first terminal 211 and the third terminal 213. In this embodiment, by controlling the conduction and cutoff of the second bit line switch SW2, precise control of the read path is achieved, thereby optimizing the charge sharing process and improving the voltage difference of the read signal. Specifically, the second bit line switch SW2 is configured to be continuously turned on during the read operation of the selected memory cell 6. This ensures that before the charge sharing between the second terminal 212 and the third terminal 213 is carried out, the bit line BL of the selected memory cell 6 is turned on with the local bit line LBL, so as to introduce the parasitic capacitance of the local bit line LBL on the bit line side, increase the equivalent parasitic capacitance on the bit line side, and improve the voltage offset and comparison judgment margin.

[0075] In this embodiment, the second bit line switch SW2 has a second control terminal for receiving a second control signal to control the second bit line switch SW2 to be turned on and off. During a read operation on a selected memory cell 6, the signal controller 4 also provides a second control signal to the second control terminal for controlling the second bit line switch SW2 to be continuously turned on.

[0076] It is worth noting that the second bit line switch SW2 may include, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar junction transistor (BJT), or other semiconductor switching devices capable of implementing on / off control functions. When the second bit line switch is a PMOS transistor or an NMOS transistor, the gate terminals of the PMOS transistor and the NMOS transistor form the second control terminal of the second bit line switch SW2. When the second bit line switch is a bipolar junction transistor (BJT), the base terminal of the bipolar junction transistor (BJT) serves as the second control terminal of the second bit line switch SW2.

[0077] When performing a read operation on the selected memory cell 6, the equivalent parasitic capacitance on the bit line side increases, and the voltage drop rate on the bit line side will slow down, resulting in a longer read process. If the voltage change on the bit line side is too slow or unclear, it may cause the unselected memory cells 5 to discharge, thereby affecting their state and resulting in erroneous read results. To avoid the above problems, in this embodiment, the second bit line switch SW2 is a transistor (which can be a PMOS transistor or an NMOS transistor). When the second bit line switch SW2 is an NMOS transistor, during the read operation on the selected memory cell 6, the magnitude of the second control signal is positively correlated with the magnitude of the current between the first terminal 211 and the third terminal 213. Specifically, when the second control signal is large, the conduction capability of the second bit line switch SW2 is strong, and the current between the first terminal 211 and the third terminal 213 is large. When the second control signal is small, the conduction capability of the second bit line switch SW2 is weak, and the current between the first terminal 211 and the third terminal 213 is small. When the second bit line switch SW2 is a PMOS transistor, during the reading operation on the selected memory cell 6 , the magnitude of the second control signal is negatively correlated with the magnitude of the current between the first terminal 211 and the third terminal 213 .

[0078] By setting the second bit line switch SW2 as a transistor, a suitable second control signal can be selected based on the size of the equivalent parasitic capacitance. By controlling the size of the second control signal, the conduction time of the second bit line switch SW2 can be controlled, thereby reducing read interference and improving the read discrimination margin of the memory.

[0079] Taking the second bit line switch SW2 as an NMOS transistor as an example, refer to Figure 6 , Figure 6This is a diagram showing how the current on the bit line changes with time. Figure 6 The ordinate represents the current value on the bit line side, and the abscissa represents time. Specifically, curve A shows how the bit line side current changes with time in the first case; curve B shows how the bit line side current changes with time in the second case; curve C shows how the bit line side current changes with time in the third case; and curve D shows how the bit line side current changes with time in the fourth case.

[0080] Case 1: The reading method is to keep the first bit line switch SW1 turned on when performing a read operation on the selected read unit, and the second bit line switch SW2 is turned on after being turned off for a preset time (this reading method does not change the equivalent parasitic capacitance on the bit line side). Case 2: The reading method is the reading method of this embodiment, specifically, when performing a read operation on the selected storage unit 6, keep the second bit line switch SW2 turned on, and the first bit line switch SW1 is turned on after being turned off for a preset time. Case 3: The reading method is the same as the reading method of Case 2. Case 4: The reading method is the same as the reading method of Case 2. Among them, the voltage value of the second control signal in Case 2 is less than the voltage value of the second control signal in Case 3, the voltage value of the second control signal in Case 3 is less than the voltage value of the second control signal in Case 4, and the voltage value of the second control signal in Case 4 is equal to the voltage value of the second control signal in Case 1.

[0081] pass Figure 6 It can be clearly concluded from curves A and D that, when the voltage values ​​of the second control signal are equal, the turn-on time of the second bit line switch SW2 in the reading method disclosed in this embodiment (when performing a read operation on the selected read unit, the second bit line switch SW2 is kept turned on, and the first bit line switch SW1 is turned on after being disconnected for a preset time) is greater than the turn-on time of the second bit line switch SW2 in another reading method (when performing a read operation on the selected read unit, the first bit line switch SW1 is kept turned on, and the second bit line switch SW2 is turned on after being disconnected for a preset time). The embodiment of the present application indeed increases the equivalent parasitic capacitance on the bit line side, and can effectively improve the read discrimination margin of the memory, thereby improving the accuracy and stability of the memory read operation.

[0082] pass Figure 6 It can be clearly seen from curves B, C, and D that when the read operation is performed on the selected read unit using the read method disclosed in this embodiment, the conduction time of the second bit line switch SW2 can be controlled by changing the size of the second control signal to reduce read interference, thereby further improving the accuracy and stability of the memory read operation.

[0083] Figure 3 A circuit for a peripheral circuit of a memory provided in an embodiment of the present application Figure 2 ,like Figure 3 As shown, the third embodiment of the present application also discloses a peripheral circuit for a memory. Unlike the above embodiments, the decoder 3 further includes a first control switch SW3. One end of the first control switch SW3 is connected to the first control end, and the other end is used to receive a first control signal. The signal controller 4 is configured to provide a first control signal to the first control end, a second control signal to the second control end, and a first switching signal to the first control switch SW3 during a read operation on a selected memory cell 6. The first control signal is used to control the first bitline switch SW1 to be continuously conductive, the second control signal is used to control the second bitline switch SW2 to be continuously conductive, and the first switching signal is used to control the first control switch SW3 to be conductive after being off for a preset time. The first control switch SW3 is configured to be conductive after being off for a preset time during a read operation on the selected memory cell 6. In the third embodiment, the first bitline switch SW1 is controlled to be conductive after being off for a preset time by controlling the first control switch SW3 to be on and off.

[0084] The present application also discloses a memory, which includes:

[0085] a storage array comprising a plurality of storage units;

[0086] The peripheral circuit as described in any one of the above items is coupled to the memory unit.

[0087] The present application also discloses a method for operating the memory as described above, including:

[0088] Perform a read operation on the selected storage unit, including:

[0089] Maintaining conduction between the first end and the third end, and disconnecting the second end and the third end;

[0090] After the second terminal and the third terminal are disconnected for a preset time, the second terminal and the third terminal are connected to enable the second terminal to output a read signal.

[0091] The above are only optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A peripheral circuit of a memory, wherein the memory comprises a memory array, the memory array comprises a plurality of memory cells, characterized in that: The peripheral circuit includes: A bit line decoder comprising: A plurality of gating units, each of the gating units comprising: A first terminal coupled to a bit line of any of the memory cells; The second terminal is used to output a read signal of the selected storage unit; a third terminal coupled between the first terminal and the second terminal and coupled to a local bit line of the memory; Each of the gating units is configured to: During a read operation on the selected memory cell, the first terminal and the third terminal are kept conductive, and after the second terminal and the third terminal are disconnected for a preset time, the second terminal and the third terminal are conductively connected.

2. The peripheral circuit of the memory according to claim 1, wherein: Each of the gating units comprises: a first line switch connected between the second end and the third end; The first bit line switch is configured to be turned on after being turned off for a preset time during a reading operation on a selected memory cell.

3. The peripheral circuit of the memory according to claim 2, wherein: Each of the gating units comprises: a second bit line switch connected between the first terminal and the third terminal; The second bit line switch is configured to be continuously turned on during a read operation on a selected memory cell.

4. The peripheral circuit of the memory according to claim 3, wherein: The first bit line switch further includes a first control terminal, which is used to receive a first control signal to control the first bit line switch to be turned on or off; the second bit line switch further includes a second control terminal, which is used to receive a second control signal to control the second bit line switch to be turned on or off.

5. The peripheral circuit of the memory according to claim 4, wherein: The second bit line switch is a transistor, and the gate terminal of the transistor is the second control terminal; During a read operation on the selected memory cell, the magnitude of the second control signal is positively correlated or negatively correlated with the magnitude of the current between the first terminal and the third terminal.

6. The peripheral circuit of the memory according to claim 4, wherein: Also includes: The signal controller is configured to: During a read operation on a selected memory cell, a first control signal is provided to the first control terminal, and a second control signal is provided to the second control terminal. The first control signal is used to control the first bit line switch to be turned on after being turned off for a preset time, and the second control signal is used to control the second bit line switch to be continuously turned on.

7. The peripheral circuit of the memory according to claim 4, wherein: Each of the selection units further includes: a first control switch, one end of which is connected to the first control end, and the other end is used to receive a first control signal, and the first control switch is configured to: during a reading operation on a selected storage unit, be turned off for a preset time and then turned on.

8. The peripheral circuit of the memory according to claim 7, wherein: Also includes: The signal controller is configured to: During a read operation on a selected memory cell, a first control signal is provided to the first control terminal, a second control signal is provided to the second control terminal, and a first switch signal is provided to the first control switch. The first control signal is used to control the first bit line switch to be continuously turned on, the second control signal is used to control the second bit line switch to be continuously turned on, and the first switch signal is used to control the first control switch to be turned on after being turned off for a preset time.

9. The peripheral circuit of the memory according to claim 1, wherein: The bit line decoder further includes: a comparator having a first input terminal, a second input terminal, and an output terminal; The first input terminal is used to input a reference signal; The second input terminal is coupled to the second terminal and is used to receive the read signal; The output end is used to output a comparison result between the reference signal and the read signal.

10. A memory, characterized in that: The memory includes: a storage array comprising a plurality of storage units; The peripheral circuit according to any one of claims 1 to 9, coupled to the memory unit.

Images