Memory and operation method of memory

Abstract

The invention discloses a memory and an operation method of the memory, the memory comprises a memory array and a peripheral circuit, and the peripheral circuit comprises a plurality of gating switch units and a plurality of discharging switch units; one end of each gating switch unit is connected with the bit line end of the storage unit structure, and the gating switch units are configured to control the operation state of the storage unit structure and are continuously switched on or switched off after being switched on for a part of time in the process of performing discharging operation on the selected storage unit structure; each discharging switch unit is connected with the other end of the gating switch unit, and the discharging switch units are configured to provide reset voltage signals for the other end of the gating switch unit connected with the selected storage unit structure in the discharging operation process. According to the technical characteristics, in the discharging operation process, the gating switch unit is set to be continuously switched on or switched off after being switched on for a part of time, and the reliability of the reading process can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of phase change memory, and in particular to a memory and a method for operating the memory. Background Art

[0002] Phase Change Memory (PCM) is a type of non-volatile memory that uses resistance differences in a phase-change material to represent data states. During data reads, the storage state of a memory cell is typically determined by charge sharing between the bit line (BL) and the data line (DL).

[0003] In the related art, the reading of the memory cell structure cell is easily affected by factors such as BL leakage current and parasitic capacitance corresponding to the BL, thereby causing inaccurate reading of the memory cell structure cell state. Summary of the Invention

[0004] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present application is how to improve the reliability of the reading process of the storage unit structure.

[0005] In order to solve at least one of the above-mentioned technical problems, the present application discloses a memory and a method for operating the memory.

[0006] According to one aspect of the present application, a memory is provided, comprising a memory array and a peripheral circuit, wherein the memory array comprises a plurality of memory cell structures, the peripheral circuit is electrically connected to the memory cell structures, and the peripheral circuit comprises:

[0007] A plurality of gate switch units, each gate switch unit including a first end and a second end, the first end being connected to a bit line end of any memory cell structure, the gate switch unit being configured as follows:

[0008] Controlling the operational state of the storage unit structure;

[0009] During the discharge operation of the selected memory cell structure, the memory cell is continuously turned on or turned off after a portion of the time;

[0010] A plurality of discharge switch units, each of which is connected to the second end of any one of the selection switch units, and the discharge switch unit is configured to: during a discharge operation on a selected memory cell structure, provide a reset voltage signal to the second end of the selection switch unit connected to the selected memory cell structure.

[0011] Optionally, the gate switch unit includes:

[0012] a first bit line switch having a third terminal and a fourth terminal, the third terminal being connected to the bit line terminal of the memory cell structure, and the fourth terminal being connected to the local bit line of the memory array;

[0013] The second bit line switch has a fifth terminal and a sixth terminal, wherein the fifth terminal is connected to the fourth terminal of the first bit line switch, and the sixth terminal is connected to the discharge switch unit.

[0014] Optionally, the first bit line switch is configured to: remain on during a discharge operation and a read operation on the selected memory cell structure;

[0015] The second bit line switch is configured to be turned off after being turned on for a portion of the time during a discharge operation on a selected memory cell structure, and to be turned on after being turned off for a portion of the time during a read operation.

[0016] Optionally, the first bit line switch is configured to: be turned on for a portion of time during a discharge operation on the selected memory cell structure and then be turned off, and be turned on for a portion of time during a read operation;

[0017] The second bit line switch is configured to be continuously turned on during a discharge operation and a read operation on the selected memory cell structure.

[0018] Optionally, the discharge switch unit includes:

[0019] A voltage switch, one end of which is connected to the second end of the selection switch unit, and the other end of which is connected to the negative voltage signal. The voltage switch is configured to: during the discharge operation of the selected memory cell structure, the voltage switch is turned on to provide a reset voltage signal to the second end of the selection switch unit.

[0020] Optionally, the peripheral circuit further includes a balancing switch,

[0021] The balancing switch has a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively connected to the second terminals of two adjacent gate switch units;

[0022] The equalizing switch is configured such that: the seventh terminal is connected to the selected memory cell structure, and during the process of performing a discharge operation on the selected memory cell structure, a reference voltage is obtained at the eighth terminal.

[0023] Optionally, the peripheral circuit further includes:

[0024] The signal control structure is configured as follows:

[0025] Performing an initialization operation, during which the gate switch unit is controlled to be turned on;

[0026] After the initialization operation, a discharge operation is performed. During the discharge operation phase, the discharge switch unit is controlled to be turned on, and the gate switch unit is controlled to be turned on for a certain period of time and then turned off.

[0027] A reading operation is performed after the discharge operation. During the reading operation phase, the selected memory cell structure remains turned on, and the discharge switch unit is turned off after being turned on for a period of time.

[0028] According to a second aspect of the present application, there is provided a method for operating a memory as described in any one of the above items, comprising:

[0029] Performing an initialization operation to turn on the gate switch unit to control the operation state of the memory cell structure;

[0030] After the initialization operation, a discharge operation is performed, and the discharge switch unit is turned on to provide a reset voltage signal to the second end of the gate switch unit; wherein the gate switch unit is turned off after being turned on for a part of the time;

[0031] After the discharge operation, a read operation is performed to turn on the selected memory cell structure.

[0032] Optionally, the discharge operation includes a first operation stage, a second operation stage, and a third operation stage; the peripheral circuit further includes a balancing switch;

[0033] The discharge operation includes:

[0034] In the first operation phase, the balancing switch is turned on to generate a reference voltage at the eighth terminal of the balancing switch; and the balancing switch is continuously turned on in the second operation phase and the third operation phase.

[0035] Optionally, the discharge operation includes a first operation phase, a second operation phase, and a third operation phase; the gate switch unit includes a first bit line switch and a second bit line switch;

[0036] The discharge operation also includes:

[0037] In a first operation phase, the first bit line switch and the second bit line switch are turned on;

[0038] In the second operation phase, one of the first bit line switch and the second bit line switch is turned off, and the other continues to be turned on;

[0039] In the third operation phase, the first bit line switch and the second bit line switch maintain the same on or off state as in the second operation phase.

[0040] The memory disclosed in the embodiments of the present application can improve the reliability of the reading process of the memory cell structure by adjusting the timing control method of each switch of the peripheral circuit.

[0041] Specifically, a selection switch unit is set in the peripheral circuit, and by controlling some selection switch units to be continuously turned on and some selection switch units to be turned off after being turned on for a part of the time during the discharge operation of the selected memory cell structure, the reading time of the selected memory cell structure can be optimized, so that the reading voltage is closer to the intrinsic reading voltage, thereby improving the reliability of the reading process.

[0042] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0045] Figure 1 A schematic structural diagram corresponding to a memory provided for an exemplary embodiment of the present disclosure;

[0046] Figure 2 A circuit diagram corresponding to a peripheral circuit of a memory provided for an exemplary embodiment of the present disclosure;

[0047] Figure 3 A first voltage change timing diagram provided for an exemplary embodiment of the present disclosure;

[0048] Figure 4 A first switch control timing diagram provided for an exemplary embodiment of the present disclosure;

[0049] Figure 5 A second voltage change timing diagram provided for an exemplary embodiment of the present disclosure;

[0050] Figure 6 A second switch control timing diagram provided for an exemplary embodiment of the present disclosure;

[0051] Figure 7 A flowchart corresponding to a memory operation method provided by an exemplary embodiment of the present disclosure is provided.

[0052] Description of reference numerals:

[0053] 1-memory array, 2-peripheral circuit, 3-word line unit, 4-circuit control structure, 5-signal control structure, 6-memory cell structure, 7-selected memory cell structure;

[0054] 10-select switch unit, 11-local bit line, 20-discharge switch unit, 30-compensation capacitor, 40-comparator;

[0055] S0-balance switch, S1-initialization switch, S2-voltage switch, S3-first bit line switch, S4-second bit line switch;

[0056] Vneg-negative voltage signal, Vref-reference voltage, Vss-initialization signal. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the embodiments described are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0058] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0059] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0060] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0061] The term "and / or" as used herein describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of A alone, the simultaneous existence of A and B, and the existence of B alone. Furthermore, the term "at least one" as used herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0062] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0063] As described in the background art, the reading process of a memory cell structure is easily affected by factors such as BL leakage current and parasitic capacitance corresponding to the BL.

[0064] Figure 1 Schematic diagram of a memory structure embodiment, such as Figure 1 As described above, the memory includes a memory array 1 and a peripheral circuit 2 , wherein the memory array 1 has a plurality of memory cell structures 6 , and the peripheral circuit 2 is connected to the memory array 1 .

[0065] In some embodiments, the memory array 1 corresponds to at least a portion of a phase change memory and includes a plurality of WLs (wordlines), a plurality of bit lines, and a plurality of memory cell structures 6. The memory cell structures 6 are located at the intersections of the WLs and the BLs. Binary data can be written into the memory cell structures 6 or read from the memory cell structures 6.

[0066] The memory cell structure 6 may include a crystalline state and an amorphous state, and correspond to different voltage thresholds. The conversion between the crystalline state and the amorphous state is achieved by applying different forms of heat to the memory cell structure 6. The crystalline state is defined as 1, and the corresponding threshold voltage is lower, and the amorphous state is defined as 0, and the corresponding threshold voltage is higher. The programming operation of writing "1" to the memory cell structure 6 is defined as a set operation, and the programming operation of writing "0" to the memory cell structure 6 is defined as a reset operation. By applying a pressure greater than the threshold voltage of the set state and less than the reset state to the selected memory cell structure 7, the memory cell structure 6 in the crystalline state can be opened, but the memory cell structure 6 in the amorphous state cannot be opened, and the state of the memory cell structure 6 can be read. Among them, the voltage threshold corresponding to each memory cell structure 6 itself is the intrinsic read voltage corresponding to the BL voltage when the selected memory cell structure is read.

[0067] The peripheral circuit 2 includes a word line unit 3, a circuit control structure 4, and a signal control structure 5. The word line unit 3 is configured to determine a target WL corresponding to a target memory cell structure. The signal control structure 5 is configured to perform operations associated with the circuit control structure 4, such as controlling the conduction or disconnection of switches corresponding to various components of the circuit control structure 4 during a read operation of a memory cell structure 6.

[0068] In the embodiment, when reading any memory cell structure 6 in the memory array 1, the BL voltage may rise prematurely due to the BL leakage sensitivity, resulting in an inaccurate read voltage when reading the memory cell structure cell, or the BL capacitance sensitivity may affect the charge sharing effect between the BL and DL, thereby resulting in an inaccurate read state of the memory cell structure cell.

[0069] In order to solve the technical problems existing in the above-mentioned embodiments, the technical solution of the present application proposes a peripheral circuit of a memory, which optimizes the reading time of the selected memory cell structure by controlling some selection switch units to be continuously turned on and some selection switch units to be turned off after being turned on for a part of the time during the discharge operation of the selected memory cell structure, so that the reading voltage is closer to the intrinsic reading voltage, thereby improving the reliability of the reading process.

[0070] Figure 2 A circuit diagram corresponding to the peripheral circuit of the memory provided by the exemplary embodiment of the present disclosure is shown in FIG. Figure 1 and Figure 2 As shown, the peripheral circuit 2 of the memory includes a circuit control structure 4 .

[0071] The circuit control structure 4 includes:

[0072] A plurality of gate switch units 10, each gate switch unit 10 includes a first end and a second end, the first end is connected to a bit line end of any memory cell structure 6, and the gate switch unit 10 is configured as follows:

[0073] Controlling the operating state of the memory cell structure 6;

[0074] During the discharge operation of the selected memory cell structure 7, the memory cell structure 7 is continuously turned on or turned on for a portion of the time and then turned off;

[0075] Multiple discharge switch units 20, each discharge switch unit 20 is connected to the second end of any selection switch unit 10, and the discharge switch unit 20 is configured to: during the discharge operation on the selected memory cell structure 7, provide a reset voltage signal to the second end of the selection switch unit 10 connected to the selected memory cell structure 7.

[0076] In some embodiments, the peripheral circuit 2 includes a circuit control structure 4, a word line unit 3, and a signal control structure 5. The circuit control structure 4 is configured to select and read a target memory cell structure from a plurality of memory cell structures 6 in the memory array 1 to determine the storage state of the target memory cell structure. The components of the circuit control structure 4 can be equivalent to the following: Figure 2 The circuit control structure 4 includes a plurality of gate switch units 10 and a plurality of discharge switch units 20. The first end of each gate switch unit 10 is connected to a storage cell structure 6, and the second end is connected to a discharge switch unit 20. That is, each storage cell structure 6 corresponds to a gate switch unit 10 and a discharge switch unit 20.

[0077] When the select switch unit 10 is turned on, the corresponding memory cell structure 6 can be considered as the selected memory cell structure 7, that is, the target memory cell structure mentioned above. When binary data needs to be read from the selected memory cell structure 7, the corresponding operation state is read. When binary data needs to be written to the selected memory cell structure 7, the corresponding operation state is write. In this application, the operation state of the selected memory cell structure 7 is read as an example.

[0078] In some embodiments, as Figure 2 As shown, the gate switch unit 10 includes:

[0079] a first bit line switch S3 having a third terminal and a fourth terminal, wherein the third terminal is connected to the bit line terminal of the memory cell structure 6 and the fourth terminal is connected to the local bit line 11 of the memory array 1;

[0080] The second bit line switch S4 has a fifth terminal and a sixth terminal. The fifth terminal is connected to the fourth terminal of the first bit line switch S3 , and the sixth terminal is connected to the discharge switch unit 20 .

[0081] In some embodiments, the gate switch unit 10 includes a first bit line switch S3 connected to a bit line terminal of any memory cell structure 6, and a second bit line switch S4 connected to the first bit line switch S3 and the discharge switch unit 20. The third terminal of the first bit line switch S3 is the first terminal of the gate switch unit 10, and the sixth terminal of the second bit line switch S4 is the second terminal of the gate switch unit 10.

[0082] Figure 3 A first voltage change timing diagram is provided for an exemplary embodiment of the present disclosure. Figure 4 A first switch control timing diagram is provided for an exemplary embodiment of the present disclosure. Figure 3 The voltages in Figure 4 The on or off state of each switch in the circuit changes. Figure 3 and Figure 4As shown, in some embodiments, the first bit line switch S3 is configured to: be continuously turned on during the discharge operation and the read operation on the selected memory cell structure 7;

[0083] The second bit line switch S4 is configured to be turned off after being turned on for a portion of time during a discharge operation on the selected memory cell structure 7 , and to be turned on after being turned off for a portion of time during a read operation.

[0084] In some embodiments, as Figure 3 and Figure 4 As shown, the first bit line switch S3 and the second bit line switch S4 are simultaneously turned on during the initialization operation. The first bit line switch S3 remains on throughout the entire reading process of the selected memory cell structure 7. That is, the first bit line switch S3 is turned on during the initialization operation and remains on until the reading of the selected memory cell structure 7 is completed, and then turns off. The second bit line switch S4 is turned on during the initialization operation, turns off after a portion of the on time during the discharge operation phase, and turns on after a portion of the off time during the read operation phase.

[0085] In some embodiments, the first bitline switch S3 and the second bitline switch S4 are simultaneously turned on during the initialization operation phase. The second bitline switch S4 is configured to be turned on for a portion of the time, then turned off, and then turned on for a portion of the time, during the entire reading process of the selected memory cell structure 7. The continuous conduction of the first bitline switch S3 facilitates accurate control and level recovery of the BL voltage. The timely turning off of the second bitline switch S4 after turning on during the discharge phase can prevent voltage overdischarge and path interference, reducing voltage noise. Furthermore, the first turning off and then turning on during the reading process can avoid interference with the charge sharing process in the early stages of the reading process, effectively improving the voltage stability, discrimination accuracy, and anti-interference capability of the memory during the reading process, and to a certain extent reducing overall power consumption.

[0086] In some embodiments, a discharge switch unit 20 is provided to be connected to the gate switch unit 10 , and the discharge switch unit 20 is turned on after the gate switch unit 10 is turned on, so as to provide a DC signal to the gate switch unit 10 .

[0087] Specifically, such as Figure 2 As shown, the discharge switch unit 20 includes:

[0088] The voltage switch S2 has one end connected to the second end of the selection switch unit 10 and the other end connected to the negative voltage signal Vneg. The voltage switch S2 is configured as follows: during the discharge operation of the selected memory cell structure 7, the voltage switch S2 is turned on to provide a reset voltage signal to the second end of the selection switch unit 10.

[0089] In some embodiments, the discharge switch unit 20 includes a voltage switch S2, one end of the voltage switch S2 is connected to the sixth end of the second bit line switch S4, and the other end is connected to the negative voltage signal Vneg. Figure 3 as well as Figure 4 The voltage switch S2 is turned on in phase p3 and remains on until phase p6, and is turned off in phase p7. The voltage switch S2 provides a reset voltage signal to the first bit line switch S3 and the second bit line switch S4, causing the BL voltage and the LBL voltage to change from 0V to the voltage corresponding to the reset voltage signal. The voltage value of the reset voltage signal is equal to the voltage value of the negative voltage signal Vneg.

[0090] During the discharge phase, voltage switch S2 conducts, rapidly adjusting the BL and LBL voltages to the reset voltage signal. This effectively achieves deep discharge and voltage reset at the node, thereby improving node voltage consistency and initialization stability, and enhancing the reliability and accuracy of memory read operations. This also shortens preprocessing time and improves overall read efficiency.

[0091] Please continue reading Figure 2 The circuit control structure 4 further includes an initialization switch S1, one end of the initialization switch S1 is connected to the second end of the gate switch unit 10, and the other end is grounded. The initialization switch S1 is configured as follows:

[0092] When the selected memory cell structure 7 is initialized, the initialization switch S1 is turned off to provide the initialization signal Vss to the second end of the gate switch unit 10 .

[0093] In some embodiments, please refer to Figure 3 and Figure 4 Before the selected storage unit structure 7 is initialized, that is, no operation is performed on the selected storage unit structure 7, the corresponding Figure 3 and Figure 4 The p1 phase is a non-operation phase, during which the initialization switch S1 is turned on and the other switches in the circuit control structure 4 are turned off, so that the BL voltage and the LBL voltage are maintained at the voltage value of the initialization signal Vss, that is, the BL voltage and the LBL voltage are maintained at 0V.

[0094] When the selected memory cell structure 7 is initialized, corresponding to the p2 phase, the initialization switch S1 is turned off, and the first bit line switch S3 and the second bit line switch S4 are turned on.

[0095] Please continue reading Figure 2 The circuit control structure 4 further includes a balancing switch S0, the balancing switch S0 having a seventh terminal and an eighth terminal, the seventh terminal and the eighth terminal being respectively connected to the second terminals of two adjacent gate switch units 10;

[0096] The equalizing switch S0 is configured as follows: a seventh terminal is connected to the selected memory cell structure 7 , and a reference voltage Vref is obtained at an eighth terminal during a discharge operation on the selected memory cell structure 7 .

[0097] In some embodiments, the balancing switch S0 is connected to the second ends of two adjacent gate switch units 10, that is, connected to the sixth ends of the second bit line switches S4 of the two adjacent gate switch units 10. One end of the balancing switch S0 is connected to the selected memory cell structure 7 through the gate switch unit 10, and the other end is connected to the unselected memory cell structure 7 through the gate switch unit 10.

[0098] In some embodiments, the balancing switch S0 includes a seventh terminal and an eighth terminal, wherein the seventh terminal is connected to the selected memory cell structure 7, and the eighth terminal is connected to the unselected memory cell structure 7. The seventh terminal corresponds to a DL voltage, and the eighth terminal corresponds to an Unsel DL voltage. During the p8-p9 phase corresponding to the read operation, the Unsel DL voltage has a voltage value equal to the reference voltage Vref.

[0099] Please continue reading Figure 2 , the circuit control structure 4 further includes a compensation capacitor 30, one end of the compensation capacitor 30 is connected to the eighth end of the balancing switch S0, and the other end is connected to the discharge switch unit 20;

[0100] The compensation capacitor 30 is configured to adjust the voltage value of the reference voltage Vref by adjusting the capacitance value of the compensation capacitor 30 .

[0101] In some embodiments, one end of the compensation capacitor 30 is connected to the eighth end of the balancing switch S0 corresponding to the selected memory cell structure 7 , and the other end is connected to the discharge switch unit 20 corresponding to the unselected memory cell structure 7 .

[0102] In some embodiments, the first bitline switch S3 corresponds to a first parasitic capacitor, the second bitline switch S4 corresponds to a second parasitic capacitor, and the third terminal of the equalizing switch S0 corresponds to a third parasitic capacitor. The capacitance value during the discharge process may include the sum of the capacitance values ​​of the first parasitic capacitor, the second parasitic capacitor, the third parasitic capacitor, and the compensation capacitor 30.

[0103] In some embodiments, the voltage value of the reference voltage Vref is negatively correlated with the on-time of the balancing switch S0 and positively correlated with the capacitance value during the discharge process. Therefore, a compensation capacitor 30 is introduced at the fourth terminal of the balancing switch S0. By adjusting the capacitance value of the compensation capacitor 30, the voltage value of the reference voltage Vref can be adjusted. Furthermore, the voltage value of the reference voltage Vref can also be adjusted by adjusting the on-time of the balancing switch S0.

[0104] In some embodiments, the word line unit 3 further includes a word line switch, the specific location of which is Figure 2 It is not shown in the figure, but it is clear that one end of the memory cell structure 7 is connected to the word line corresponding to the selected memory cell structure 7, and the memory cell structure 7 is connected to the word line corresponding to the selected memory cell structure 7. Figure 3 as well as Figure 4 It can be seen that the WL switch is turned on in the p5 stage, continues to be turned on until the p7 stage, and is turned off in the p8 stage, so that the WL voltage increases in the p5 stage and decreases in the p8 stage.

[0105] like Figure 3 and Figure 4 As shown, in the p8 phase, the WL voltage drops, and the second bit line switch S4 is turned on again. The balancing switch S0 has been turned off. After the second bit line switch S4 is turned on, charge sharing between BL, LBL and DL can be achieved to achieve a new voltage balance. In this process, the following conditions are met:

[0106]

[0107] In a specific embodiment, assuming C bl :C lbl :C dl =1:1:2, and for the selected memory cell structure 7, when the "1" state operation is performed, V bl =V lbl =-500mV, when storing "0" state, V bl =V lbl =-2.2V,V dl =-2.5V.

[0108] According to the above formula, when storing the "1" state operation, When performing a "0" state storage operation Assume V ref =-1.925V, then the reading window voltage is 425mV.

[0109] In another specific embodiment, when the second bit line switch S4 is turned off, it is still assumed that C bl :C lbl :C dl =1:1:2, and for the selected memory cell structure 7, when the "1" state operation is performed, V bl =-500mV, when storing "0" state, V bl =-2V,V lbl =V dl =-2.5V.

[0110] According to the above formula, when storing the "1" state operation, When performing a "0" state storage operation Assume V ref=-2.1875V, then the reading window voltage is 187mV.

[0111] As can be seen, during a read operation, electrical connections are established between BL, LBL, and DL during the WL voltage drop phase, forming a complete charge-sharing path. This allows for a significant voltage difference between BL and DL corresponding to the data state of the memory cell structure 6, thereby expanding the read window voltage. When the second bit line switch S4 is turned on, a larger read voltage difference is achieved between the memory cell structures 6 storing "1" and "0," improving the discrimination margin, thereby enhancing the accuracy and reliability of the read operation and reducing the false positive rate.

[0112] Please continue reading Figure 2 The circuit control structure 4 further includes: a comparator 40 , wherein the input terminals of the comparator 40 are respectively connected to the seventh terminal and the eighth terminal of the balancing switch S0 , and the output terminal of the comparator 40 outputs a read signal.

[0113] In some embodiments, the circuit control structure 4 also includes a comparator 40 connected to both ends of the balancing switch S0. The comparator 40 obtains and compares the DL voltage and the UnselDL voltage, and outputs the comparison result as a read signal corresponding to the selected storage cell structure 7. The read signal represents the storage state corresponding to the selected storage cell structure 7.

[0114] In some embodiments, the seventh terminal of the balancing switch S0 is connected to the sixth terminal of the second bit line switch S4, and when the selected memory cell structure 7 is turned on, the voltage values ​​of the DL voltage, the BL voltage, and the LBL voltage are equal and change synchronously. The eighth terminal of the balancing switch S0 corresponds to the Unsel DL voltage, and the voltage value of the Unsel DL voltage is equal to the reference voltage Vref during the read operation. Therefore, the comparator 40 connected to the two ends of the balancing switch S0 can obtain the DL voltage and the Unsel DL voltage respectively. By comparing the DL voltage and the Unsel DL voltage, the relationship between the BL voltage and the reference voltage Vref can be determined, and then a read signal is output to determine the storage state corresponding to the selected memory cell structure 7. The storage state includes a "0" state and a "1" state.

[0115] Please continue reading Figure 3 , it can be seen that when the selected memory cell structure 7 is in the "0" state, the voltage value of the BL voltage remains unchanged at the reset voltage signal and is less than the voltage value of the reference voltage Vref. When the selected memory cell structure 7 is in the "1" state, the voltage value of the BL voltage increases from the reset voltage signal and is greater than the voltage value of the reference voltage Vref.

[0116] Figure 3In the voltage change timing diagram shown, due to the voltage difference between WL and BL, the subthreshold conduction current corresponding to the selected memory cell structure 7 is affected in a non-ideal state. Therefore, when the selected memory cell structure 7 is in the "0" state, the BL voltage will still partially charge up. The smaller the BL capacitance, the greater the corresponding BL voltage charge. If this is considered an ideal state, the BL voltage will not charge up and will remain stable at the reset voltage signal.

[0117] See also Figure 1 The peripheral circuit 2 of the memory further includes a signal control structure 5 configured as follows:

[0118] Performing an initialization operation, during which the gate switch unit 10 is controlled to be turned on;

[0119] After the initialization operation, a discharge operation is performed. In the discharge operation phase, the discharge switch unit 20 is controlled to be turned on, and the gate switch unit 10 is controlled to be turned on for a period of time and then turned off.

[0120] The reading operation is performed after the discharge operation. During the reading operation phase, the selected memory cell structure 7 remains turned on, and the discharge switch unit 20 is turned on for a portion of time and then turned off.

[0121] In some embodiments, the signal control structure 5 is configured to control the on and off of each switch. Figure 3 as well as Figure 4 , Figure 3 as well as Figure 4 In the figure, the p1 stage corresponds to the non-operation stage, the p2 stage corresponds to the initialization operation stage, the p3 stage, the p4 stage and the p5 stage correspond to the discharge operation stage, and the p6 stage to the p9 stage correspond to the read operation stage.

[0122] according to Figure 4 As can be seen, under the control of signal control structure 5, initialization switch S1 is turned on in phase p1, turned off in phase p2, and remains turned off until the end of the read process. First bit line switch S3 and second bit line switch S4 are turned on in phase p2, and first bit line switch S3 remains turned on until the end of the read process. Second bit line switch S4 remains turned on until phase p3 of the discharge operation phase, turns off in phase p4, remains turned off until phase p7 of the read operation phase, and turns off in phase p8. Voltage switch S2 and equalization switch S0 are turned on in phase p3, remain turned on until phase p6, and turn off in phase p7. WL switch is turned on in phase p5, remains turned on until phase p7, and turns off in phase p8, causing the WL voltage to increase in phase p5 and decrease in phase p8.

[0123] Another circuit timing control method according to an embodiment of the present application is as follows: Figure 5 as well as Figure 6As shown, the first line switch S3 is configured to be turned off after being turned on for a portion of the time during the discharge operation of the selected memory cell structure 7, and turned on after being turned off for a portion of the time during the read operation;

[0124] The second bit line switch S4 is configured to be continuously turned on during the discharge operation and the read operation on the selected memory cell structure 7 .

[0125] In this embodiment, the coupling relationship between the initialization switch S1, the voltage switch S2, the equalization switch S0, the first bit line switch S3 and the second bit line switch S4 of the circuit control structure 4 is the same as Figure 3 and Figure 4 The corresponding embodiments are the same as those in the previous embodiment, and the configuration and functions of the initialization switch S1, voltage switch S2, and equalization switch S0 are also the same as those in the previous embodiment. In this embodiment, the configuration and functions of the first bit line switch S3 and the second bit line switch S4 are changed. These changes will be described below, and other structures will not be repeated here.

[0126] In some embodiments, as Figure 3 and Figure 4 As shown, the first bit line switch S3 and the second bit line switch S4 are simultaneously turned on during the initialization operation. The second bit line switch S4 remains on throughout the entire reading process of the selected memory cell structure 7. That is, the second bit line switch S4 is turned on during the initialization operation and remains on until the reading of the selected memory cell structure 7 is completed, and then turns off. The first bit line switch S3 is turned on during the initialization operation, turns off after a portion of the on time during the discharge operation phase, and turns on after a portion of the off time during the read operation phase.

[0127] In this embodiment, the configuration and function settings of the first bit line switch S3 and the second bit line switch S4 can also achieve the same technical effects as the previous embodiment.

[0128] Accordingly, the technical solution of the present application further provides a memory, comprising:

[0129] A memory array 1 including a plurality of memory cell structures 6;

[0130] like Figure 2 The peripheral circuit 2 shown is connected to the memory array 1. In the process of reading the memory cell structure 6, the signal control structure 5 controls the circuit control structure 4 to obtain the following Figure 3 and Figure 4 The timing changes shown.

[0131] Correspondingly, the technical solution of this application also discloses a method for operating a memory, such as Figure 7 Shown, including:

[0132] S10: In the non-operation phase p1, the initialization switch S1 is turned on to provide the initialization signal Vss to the first bit line switch S3, the second bit line switch S4 and the seventh terminal of the equalization switch S0;

[0133] In some embodiments, the non-operation phase may correspond to a phase in which the selected memory cell structure 7 is not read, or may correspond to a state in which the memory cell structure 6 is not selected. Figure 3 as well as Figure 4 At this time, the initialization switch S1 is turned on, and the other switches are turned off. The BL voltage, DL voltage, LBL voltage and Unsel DL voltage are all 0V.

[0134] S20: Initialization phase p2, turning on the first bit line switch S3 and the second bit line switch S4 to control the operation state of the memory cell structure 6;

[0135] In some embodiments, see Figure 3 as well as Figure 4 During the initialization operation phase, the first bit line switch S3 and the second bit line switch S4 are turned on, making the memory cell structure 6 the selected memory cell structure 7. At this time, since the other switches are still in the off state, the BL voltage, the DL voltage, the LBL voltage, and the Unsel DL voltage remain at 0V.

[0136] S30: Discharging operation phase p3, turning on the voltage switch S2 to provide a reset voltage signal to the second terminal of the gate switch unit 10; and turning on the balancing switch S0 to generate a reference voltage Vref at the eighth terminal of the balancing switch S0;

[0137] S40: Discharging operation phase p4, turning off the second bit line switch S4;

[0138] S50: Discharge operation phase p5, the WL switch is turned on to increase the WL voltage;

[0139] In some embodiments, see Figure 3 as well as Figure 4 , a discharge operation is performed after the initialization operation.

[0140] In phase p3 , ie, the first operation phase of the discharge operation, the voltage switch S2 is turned on and provides a reset voltage signal, so that the BL voltage, the DL voltage, and the LBL voltage change from 0V to a voltage value Vneg corresponding to the reset voltage signal.

[0141] In phase p3, the balancing switch S0 is turned on, and the seventh and eighth terminals of the balancing switch S0 are connected, making the balancing switch S0 equivalent to a finite resistor and generating a reference voltage Vref, and making the voltage value of the Unsel DL voltage at the eighth terminal equal to the voltage value of the reference voltage Vref.

[0142] During phase p4, the second operating phase of the discharge operation, the second bit line switch S4 is turned off, reducing the parasitic capacitance connected to the BL, improving voltage accuracy during the read phase, and reducing noise interference and leakage errors. At this time, the first bit line switch S3 remains on.

[0143] In phase p5, the third phase of the discharge operation, after the BL, DL, and LBL voltages change in phase p3 and remain stable through phase p4, the WL switch turns on, increasing the WL voltage and simultaneously charging the BL voltage. When the WL voltage reaches a voltage difference between the WL and BL voltages equal to the threshold voltage corresponding to the "1" state of the selected memory cell structure 7, the selected memory cell structure 7 turns on. At this point, the first bitline switch S3 remains on, and the second bitline switch S4 remains off.

[0144] S60: Read operation phase p6-p7, the selected memory cell structure 7 is turned on, and the WL switch and the first bit line switch S3 are continuously turned on; and the voltage switch S2 and the equalization switch S0 are turned on in phase p6 and turned off in phase p7;

[0145] In some embodiments, the voltage difference between the WL voltage and the BL voltage remains stable after the p5 stage and reaches the threshold voltage corresponding to the "1" state of the selected memory cell structure 7. Therefore, the selected memory cell structure 7 is turned on in the p6 stage, and the selected memory cell structure 7 remains turned on.

[0146] In some embodiments, the voltage switch S2 and the balancing switch S0 are turned off in the p6 stage, and the voltage switch S2 and the balancing switch S0 are turned off in the p7 stage, which can improve voltage stability and reduce perception errors or drifts caused by premature path disconnection, thereby improving the judgment accuracy and reliability of memory read operations.

[0147] S70: Read operation phase p8-p9, the selected memory cell structure 7 remains turned on, the WL switch is turned off, and the first bit line switch S3 and the second bit line switch S4 are turned on.

[0148] In some embodiments, in stage p8, after reading is completed, the WL switch is turned off and the WL voltage gradually decreases; in stage p9, the BL voltage, the DL voltage, the LBL voltage and the Unsel DL voltage return to 0V.

[0149] The above-described memory operation method can improve read accuracy and expand the voltage window while reducing power consumption. By turning off the second bitline switch S4, unnecessary charge-sharing paths can be effectively isolated, reducing voltage crosstalk. Delaying the turning off of the voltage switch S2 and the equalization switch S0 during the p6-p7 phase ensures the integrity of the charge-sharing paths and the stability of the reference levels of the memory cell structure 6 during the read operation, thereby creating a larger read window and enhancing the accuracy of determining the state of the memory cell structure 6.

[0150] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0151] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0152] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0153] The above are only preferred embodiments of the present application and are not intended to limit the present application in any form. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application shall still fall within the scope of the technical solution of the present application. The selection of terms used in this article is intended to best explain the principles, practical applications, or technical improvements of each embodiment in the market, or to enable other ordinary technicians in this technical field to understand the embodiments disclosed herein.

Claims

1. A memory comprising a memory array and a peripheral circuit, wherein the memory array comprises a plurality of memory cell structures, and the peripheral circuit is electrically connected to the memory cell structures, characterized in that: The peripheral circuit includes: A plurality of gate switch units, each of the gate switch units including a first end and a second end, the first end being connected to a bit line end of any of the memory cell structures, the gate switch units being configured as follows: controlling an operating state of the storage unit structure; During the discharge operation of the selected memory cell structure, the memory cell is continuously turned on or turned off after a portion of the time; a plurality of discharge switch units, each of which is connected to the second end of any one of the selection switch units, and the discharge switch unit is configured to: during a discharge operation on the selected memory cell structure, provide a reset voltage signal to the second end of the selection switch unit connected to the selected memory cell structure.

2. The memory according to claim 1, wherein The gate switch unit includes: a first bit line switch having a third terminal and a fourth terminal, the third terminal being connected to the bit line terminal of the memory cell structure, and the fourth terminal being connected to the local bit line of the memory array; The second bit line switch has a fifth terminal and a sixth terminal, wherein the fifth terminal is connected to the fourth terminal of the first bit line switch, and the sixth terminal is connected to the discharge switch unit.

3. The memory according to claim 2, wherein: The first bit line switch is configured to: be continuously turned on during a discharge operation and a read operation on the selected memory cell structure; The second bit line switch is configured to be turned off after being turned on for a portion of time during a discharge operation on the selected memory cell structure, and to be turned on after being turned off for a portion of time during a read operation.

4. The memory according to claim 2, wherein: The first bit line switch is configured to: be turned on for a portion of time during a discharge operation on the selected memory cell structure and then be turned off, and be turned on for a portion of time during a read operation; The second bit line switch is configured to be continuously turned on during a discharge operation and a read operation on the selected memory cell structure.

5. The memory according to claim 1, wherein: The discharge switch unit includes: a voltage switch, one end of which is connected to the second end of the selection switch unit, and the other end of which is connected to a negative voltage signal, wherein the voltage switch is configured to be turned on to provide the reset voltage signal to the second end of the selection switch unit during a discharge operation on the selected memory cell structure. The memory according to claim 1 , wherein: The peripheral circuit further includes a balancing switch, The balancing switch has a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively connected to the second terminals of two adjacent gate switch units; The equalizing switch is configured such that: the seventh terminal is connected to the selected memory cell structure, and a reference voltage is obtained at the eighth terminal during a discharge operation on the selected memory cell structure.

7. The memory according to claim 1, wherein: The peripheral circuit further includes: The signal control structure is configured as follows: Performing an initialization operation, during which the gate switch unit is controlled to be turned on; After the initialization operation, a discharge operation is performed. During the discharge operation phase, the discharge switch unit is controlled to be turned on, and the gate switch unit is controlled to be turned off after being turned on for a certain period of time. A reading operation is performed after the discharge operation. During the reading operation phase, the selected memory cell structure remains turned on, and the discharge switch unit is turned on for a portion of the time and then turned off.

8. A method for operating a memory according to any one of claims 1 to 7, characterized in that: include: Performing an initialization operation to turn on the gate switch unit to control the operation state of the memory cell structure; After the initialization operation, a discharge operation is performed, and the discharge switch unit is turned on to provide a reset voltage signal to the second end of the gate switch unit; wherein the gate switch unit is turned off after being turned on for a part of the time; A read operation is performed after the discharge operation to turn on the selected memory cell structure.

9. The memory operating method according to claim 8, characterized in that: The discharge operation includes a first operation stage, a second operation stage and a third operation stage; the peripheral circuit further includes a balancing switch; The discharging operation includes: In the first operation phase, the balancing switch is turned on to generate a reference voltage at the eighth terminal of the balancing switch; and the balancing switch is continuously turned on in the second operation phase and the third operation phase.

10. The memory operating method according to claim 8, wherein: The discharge operation includes a first operation phase, a second operation phase and a third operation phase; the gate switch unit includes a first bit line switch and a second bit line switch; The discharging operation further includes: In the first operation phase, the first bit line switch and the second bit line switch are turned on; In the second operation phase, one of the first bit line switch and the second bit line switch is turned off, and the other continues to be turned on; In the third operation phase, the first bit line switch and the second bit line switch maintain the same on or off state as in the second operation phase.

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